Self-aligned gratings for tight pitch interconnects and fabrication methods

Abstract

To provide self-aligned gratings for tight-pitch interconnects and methods of fabrication.SOLUTION: An integrated circuit interconnect structure 100 includes a first metallization level 101 including a first metal line 102 having a first sidewall 102A and a second sidewall 102B extending a length in a first direction. A second metal line 106 is adjacent to the first metal line. A dielectric 110 is between the first metal line and the second metal line. A second metallization level 111 is above the first metallization level, and includes a third metal line 114 extending in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via 118 is between the first metal line and the third metal line, and does not extend beyond the first sidewall or beyond the second sidewall.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] Scaling of transistors requires precise alignment between various elements of interconnect circuitry to avoid shorts or to prevent miswiring. The limitations in alignment using traditional lithographic methods can be overcome by utilizing self-assembly methods and self-alignment between structures such as interconnect line segments and vias within a single die and within a wafer.

[0002] It is with respect to these and other considerations that the improvements of the present invention are needed. Such improvements can be important with the increasing demand for the manufacture of high density, high performance transistors. [Brief description of the drawings]

[0003] [Figure 1A] 1 illustrates an isometric view of an integrated circuit interconnect structure according to one embodiment of the present disclosure. [Figure 1B] 1B shows a cross-sectional view of the integrated circuit interconnect structure in FIG. 1A. [Figure 1C] 1 shows a cross-sectional view of an integrated circuit interconnect structure. [Figure 1D] 1 shows a cross-sectional view of an integrated circuit interconnect structure. [Figure 1E] 1 shows a cross-sectional view of an integrated circuit interconnect structure. [Diagram 2] 1 illustrates a flow diagram of a method for fabricating an integrated circuit interconnect structure according to one embodiment of the present disclosure. [Figure 3A] 1 illustrates a cross-sectional view of a number of metal lines formed on a substrate. [Figure 3B] 3B illustrates the structure of FIG. 3A after a process to form a first set of polymer lines, where each polymer line is directly above each of the multiple metal lines. [Figure 3C]A cross-sectional view of the structure of Figure 3B is shown after a process of forming a second dielectric on the first dielectric adjacent to the second set of polymer lines, after forming a first dielectric adjacent to the first set of polymer lines, and after forming a second set of polymer lines (where each polymer line in the second set of polymer lines is directly above each of the polymer lines in the first set of polymer lines). [Figure 3D] 3D shows a cross-sectional view of the structure of FIG. 3C after removing the first and second sets of polymer lines. [Figure 3E] 3D after forming a third dielectric adjacent to the first dielectric. [Figure 4A] 3E after forming a sacrificial patterning layer adjacent to the second dielectric and a mask over the sacrificial layer. [Figure 4B] 4B shows a cross-sectional view perpendicular to line AA' in FIG. 4A. [Figure 5A] 4C shows a cross-sectional view of the structure of FIG. 4B after a process of etching the portions of the second dielectric exposed by the mask. [Figure 5B] 5B illustrates a cross-sectional view of the structure of FIG. 5A after depositing a fourth dielectric on the third dielectric adjacent to portions of the second dielectric. [Figure 6A] 5C shows an isometric view of the structure of FIG. 5B after a process of planarizing the fourth dielectric, the sacrificial layer, and the second dielectric. [Figure 6B] 6B shows a cross-sectional view through line A-A' of the structure of FIG. 6A after a process of planarizing the sacrificial layer and the second dielectric. [Figure 7] (A) shows an isometric view of the structure of FIG. 6A after a process of removing the sacrificial layer and recessing portions of the third dielectric. (B) shows a cross-sectional view through line A-A' of the structure of FIG. 7(A) after a process of removing the sacrificial layer and recessing portions of the third dielectric. (C) shows an enlarged isometric view of a portion of the structure of FIG. 7(A) after a process of planarizing the sacrificial layer and the second dielectric, illustrating the curved surfaces due to the etching process. [Figure 8A] 7(A) shows an isometric view of the structure of FIG. 7(A) after formation of a sacrificial material and after processes of planarization and mask formation on the sacrificial material, the second dielectric and the fourth dielectric. [Figure 8B] 8B shows a cross-sectional view through line A-A' of the structure of FIG. 8A after formation of the sacrificial material and after processes of planarization and mask formation on the sacrificial material, the second dielectric and the fourth dielectric. [Figure 9A] 8C shows a cross-sectional view of the structure of FIG. 8B after removal of the sacrificial material and etching of the third dielectric material from areas not covered by the mask. [Figure 9B] 9B illustrates a cross-sectional view of the structure in FIG. 9A after forming a second sacrificial material over the exposed portions of the metal lines, planarizing the second sacrificial material, and forming a masking layer and a mask over the masking layer. [Figure 9C] 9C shows a cross-sectional view of the structure of FIG. 9B after a process that etches the masking layer and portions of the second dielectric that are not covered by the mask. [Figure 9D] 9C after a process that removes the masking layer and etches portions of the first dielectric selectively to the second dielectric and the third sacrificial material. [Figure 9E] 9D after a process of removing the third sacrificial material. [Figure 10A] 10B shows an isometric view of the structure of FIG. 10A after blanket deposition of conductive material. [Figure 10B] A cross-sectional view of the structure in FIG. 9D is shown after blanket deposition of a liner, followed by blanket deposition of a conductive material over the liner. [Figure 11] 10B shows an isometric view of the structure of FIG. 10A after a process for forming conductive vias and metal lines according to one embodiment of the present disclosure. [Figure 12] 1 shows a cross-sectional view of an integrated circuit structure coupled with a transistor. [Figure 13] 1 illustrates a computing device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] An integrated circuit interconnect structure and a method of manufacture are described. In order to provide a thorough understanding of the embodiments of the present disclosure, numerous specific details are described in the following description, such as structural schemes and detailed manufacturing methods. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known features, such as transistor operation and switching operations associated with embedded memories, are not described in great detail so as not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0005] In some instances, in the following description, well-known methods and devices are shown in block diagram form and not in detail to avoid obscuring the disclosure. Throughout this specification, a reference to "an embodiment" or "one embodiment" or "some embodiments" means that a specific feature, structure, function, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases "in an embodiment" or "in an embodiment" or "some embodiments" appearing in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, specific features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment, and specific features, structures, functions, or characteristics related to the two embodiments are not mutually exclusive anywhere.

[0006] As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that as used herein, the term "and / or" refers to and includes any and all possible combinations of one or more of the associated listed items.

[0007] The terms "coupled" and "connected," as well as derivatives thereof, may be used herein to describe a functional or structural relationship between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in physical or electrical contact with each other, either directly or indirectly (with other elements between them), and / or that two or more elements cooperate or interact with each other (e.g., in a causal relationship).

[0008] Terms such as "above," "below," "between," "on," and the like are used herein to refer to the relative location of one component or material to another component or material where such physical relationship is noteworthy. For example, in the context of materials, one material that is disposed above or below another material may be in direct contact or may have one or more intervening materials. Furthermore, one material that is disposed between two materials may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with the second material. In the context of component assemblies, a similar distinction is made. As used throughout this specification and claims, a series of items combined with the terms "at least one of" or "one or more of" may mean any combination of the listed terms.

[0009] As used herein, the term "adjacent" generally refers to the location of something next to (e.g., immediately next to or nearby with one or more intervening things between) or next to (e.g., abutting) another.

[0010] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "one," "one," and "the" include plural. The meanings of "in" and "within" include "in" and "on."

[0011] The term "device" may generally refer to an apparatus depending on the context of the use of the term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and / or passive elements, etc. Generally, a device is a three-dimensional structure having a plane along the xy direction of an x-y-z Cartesian coordinate system and a height along the z direction. The plane of a device may also be the plane of an apparatus that contains the device.

[0012] As used throughout this specification and claims, a series of items joined with the term "at least one of" or "one or more of" may mean any combination of the listed terms. Unless otherwise specified in the express context of use, the terms "substantially equal," "approximately equal," and "approximately equal" mean that the difference between the two items so described is within random variation. In the art, such variation is typically within ±10% of a predetermined target value.

[0013] In this specification and claims, terms such as "left", "right", "front", "back", "top", "bottom", "above", "below", if any, are used for descriptive purposes and not necessarily used to describe permanent relative positions. For example, terms such as "above", "below", "front side", "back side", "top", "bottom", "above", "below" and "above" as used herein refer to the relative position of one component, structure, or material in a device relative to another referenced component, structure, or material. Here, such physical relationships are noteworthy. In this specification, these terms are utilized for descriptive purposes only, primarily within the context of the z-axis of the device, and thus may be relative to the orientation of the device. Thus, in the context of the figures provided herein, a first material "above" a second material may also be "below" the second material if the device is in an upside-down orientation relative to the context of the figures provided. In the context of materials, one material that is disposed above or below another material may be directly adjacent or may have one or more intervening materials. Additionally, a material that is disposed between two materials may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first material "on" a second material is in direct contact with the second material. In the context of component assembly, a similar distinction is made.

[0014] The term "between" may be utilized in the context of the z-axis, x-axis, or y-axis of a device. A material that is between two other materials may contact one or both of those materials, or may be isolated from both of the other two materials by one or more intervening materials. Thus, a material that is "between" two other materials may contact either of the other two materials, or may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or may be isolated from both of the other two devices by one or more intervening devices.

[0015] An integrated circuit interconnect structure is an intervening substrate used to bridge a first substrate to a second substrate. The first substrate may be, for example, an integrated circuit die including one or more transistors. The second substrate may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an integrated circuit interconnect structure is to spread connections to a wider pitch or to reroute connections to different connections. For example, an integrated circuit interconnect structure may couple an integrated circuit die to one or more transistors that may later be coupled to a second substrate. In some embodiments, the first and second substrates are attached to opposite sides of the integrated circuit interconnect structure. In other embodiments, the first and second substrates are attached to the same side of the integrated circuit interconnect structure.

[0016] Scaling of transistors in an integrated circuit die can enable, for example, high density logic and memory applications. However, as transistors are scaled, it becomes difficult to optimize the spacing and connections between transistors and peripheral circuitry. High precision alignment is required to route multiple levels of interconnects (lines and vias). Because patterning is achieved through lithographic means, misalignment in one location propagates evenly across the die. When the pitch between metal lines is reduced to, for example, 40 nm or less, misalignment can result in placement errors that can cause vias to short to the wrong metal line. One means of addressing alignment is to shrink the size of vias and lines relative to each other and relative to the transistor dimensions. However, when transistors are scaled to dimensions below 10 nm, it is much more difficult to further shrink the lines. Furthermore, reducing line widths without engineering materials can, for example, increase electrical line resistance, which is disadvantageous from a power consumption perspective.

[0017] However, this situation can be mitigated by replacing traditional lithography techniques with a combination of guided self-assembly and damascene methods to form integrated circuit interconnect structures that can be coupled to one or more transistors. This combination of methods can enable self-alignment between two or more layers of metal lines, plugs, or conductive vias between two substrates. More importantly, the shape and size of the lines and conductive vias above the lowest level metal lines can also be controlled, such that the conductive vias do not extend beyond the sidewalls of the underlying metal lines, for example. Thus, not only are misalignments and the problems associated with misalignments mitigated, but the feature sizes of the lines, plugs (line ends), or conductive vias can also be predetermined.

[0018] 1A illustrates an isometric view of an integrated circuit interconnect structure 100 according to one embodiment of the present disclosure. In an exemplary embodiment, the integrated circuit interconnect structure 100 includes a first metallization level 101 including a first metal line 102 having a first sidewall 102A and a second sidewall 102B extending a length in an X-direction. The metallization level 101 further includes a second metal line 106 adjacent to the first metal line. A dielectric 110 is between the first metal line 102 and the second metal line 106. The metallization level 101 overlies a substrate 108.

[0019] The integrated circuit interconnect structure 100 further includes a second metallization level 111 over the first metallization level 101. The metallization level 111 includes a third metal line 114 extending a length in the Y-direction over the metal line 102 and the metal line 106. As shown, the metal line 114 has a sidewall 114A that does not extend beyond the first sidewall 102A. In an exemplary embodiment, the metal line 114 has a sidewall 114B that does not extend beyond the sidewall 106B. A conductive via 118 is between the metal line 102 and the metal line 114. As shown, the conductive via 118 does not extend beyond the sidewall 102A or the sidewall 102B.

[0020] The integrated circuit interconnect structure 100 further includes a second conductive via 122 between the metallization level 101 and the metallization level 111. As shown, the second conductive via 122 does not extend beyond the first sidewall 106A or the second sidewall 106B of the second metal line 106. In an exemplary embodiment, the conductive via 122 contacts a portion of the metal line 106 in the X-direction. The metal line 106 has a length (in the X-direction) L M The conductive via 122 has a L M A part of the length L C The metal wire 102 also extends in the X direction by a length L M (not shown), and the conductive via 118 also has L M A part of the length L C extends in the X direction only.

[0021] Metal line 114 may be aligned with vias 122 and 118 along the X-direction. As shown, metal line 114 has a width W MT In some embodiments, W MT L C and in another embodiment, W MT L C To optimize the electrical resistance of the via 122, L C is the width W of the metal wire 114 MT It is preferable that the .lambda.

[0022] 1B is a cross-sectional view taken in a plane (along line A-A') of integrated circuit interconnect structure 100 in FIG. 1A. In general, the lateral width and spacing between metal lines 102 and 106 may be indicative of the directed self-assembly process utilized to fabricate integrated circuit interconnect structure 100. As shown, metal line 102 has a lateral width W M1 and the metal line 106 has a lateral width W M2 W M1 W M2 In an exemplary embodiment, W M1 W M2 Equivalent to W M1can be in the range of 5 nm to 50 nm. M2 can be in the range of 5 nm to 50 nm. In an exemplary embodiment, W M1 and W M2 can vary from each other by up to 10%.

[0023] Parameters such as the spacing between interconnects associated with transistors or other circuit elements, and / or the directed self-assembly process utilized may determine the spacing S1 between metal lines 102 and 106. In some embodiments, S1 is between 5 nm and 50 nm. In an exemplary embodiment, S1 is W M1 and W M2 The range is between 0 and 10% of

[0024] Conductive vias 118 and 122 each have a lateral width (in the Y direction) that correlates to the lateral width of metal lines 102 and 106. Generally, the lateral widths of conductive vias 118 and 122 are at most equal to the lateral widths of metal lines 102 and 106, respectively. As shown in FIG. 1B, conductive via 118 has a lateral width W V1 and conductive via 122 has a lateral width W V2 As explained above and shown in FIG. V1 W M1 is essentially equal to W V2 W M2 is essentially equal to

[0025] The second dielectric 124 includes a dielectric portion 124A over the dielectric 110 and between the conductive vias 118 and 122. As shown, the dielectric portion 124A has a width substantially equal to the width (along the Y direction) of the dielectric 110. The dielectric 110 between the conductive vias 118 and 122 also has a width substantially equal to the spacing S1.

[0026] 1A , in an exemplary embodiment, metallization level 111 further includes metal line 126 extending in a length in the Y-direction over metal line 130 and metal line 134, where metal line 130 and metal line 134 are in first metallization level 101. As shown, metal line 130 has sidewalls 130A and 130B and extends in a length in the X-direction, and metal line 134 also has sidewalls 134A and 134B and extends in a length in the X-direction.

[0027] 1B, metal line 126 extends laterally in the Y direction from above sidewall 134A to sidewall 130B. As shown, metal line 126 has a first portion 126A, a second portion 126B, and a third portion 126C between first portion 126A and second portion 126B (here, metal line portions 126A, 126B, or 126C). Different metal line portions 126A, 126B, or 126C may have different lateral thicknesses (Y direction) and different vertical thicknesses (Z direction). The different thicknesses may be indicative of the processing technique utilized to form metal line 126.

[0028] Each of metal line portions 126A and 126B has a width W M5 and W M6 and a width (in the Y direction) W M3 and W M4 It should be understood that in some embodiments, as shown, W M3 , W M4 , W M5 and W M6 are practically identical. M5 may be in the range of 5 nm to 50 nm, and W M6 In some embodiments, W may range from 5 nm to 50 nm. M1 , W M2 , W M5 , W M6 Each of W is in the range of 5 nm to 50 nm. M5 and W M6 can vary from each other by up to 10%.

[0029] In some examples, metal line portion 126A has a sidewall 126D that is substantially aligned with sidewall 134A, and metal line portion 126B has a sidewall 126E that is substantially aligned with sidewall 130B. As shown, metal line portion 126A does not extend beyond sidewall 134B, and metal line portion 126B does not extend beyond sidewall 130A. As shown, metal line portion 126C does not extend over metal line 130 or metal line 134. Metal line portion 126C has a lateral width W that is substantially equal to the spacing S2 between metal lines 130 and 134. C W C can range from 5 nm to 50 nm. In some examples, metal line portion 126C is located just above the midpoint between sidewalls 130A and 134B (lateral width W C In an exemplary embodiment, S2 has a center point along W M5 and W M6 The range is 0 to 10%.

[0030] In some examples, such as the example shown, the metal line 126 has a vertical thickness (in the Z direction relative to the top surface 126G) that varies along the Y direction. The metal line portions 126A and 126B each have a vertical thickness T A and T B In some examples, T A and T B As shown, the metal line portion 126C has a longitudinal thickness T C In some examples, T A and T B is T C In another example, as shown, T C is T A and / or T B In some embodiments, T C is T A and / or T B Increasing the Z-direction vertical thickness of metal line portion 126C may provide electrical benefits through an overall increase in the electrical conductivity of metal line 126.

[0031] Referring to metal line 114, there is no variation in vertical thickness (relative to top surface 114C) along the Y direction. In the exemplary embodiment, metal line 114 has a bottom surface 114D that is substantially coplanar with bottom surface 126H of metal line portion 126C. In addition, top surface 114C of metal line 114 is substantially coplanar with top surface 126G of metal line 126.

[0032] Dielectric 124 has dielectric portion 124B over dielectric portion 110A. As shown, dielectric portion 124B occupies the space between metal line portion 126B and metal line 114. Dielectric portion 124B has a lateral width W D In an exemplary embodiment, W D does not vary along the Z direction and is substantially equal to the spacing S3 between metal line 102 and metal line 130.

[0033] The dielectric 124 also includes metal line portions 126A, 126B, and 126C, and a dielectric portion 124C directly between the metal line 134, the metal line 130, and the dielectric 110, respectively. The dielectric portion 124C has a longitudinal thickness T that varies along the Y direction. D In the exemplary embodiment, the dielectric portion 124C has a minimum vertical thickness T D In addition, the dielectric portion 124A between the conductive vias 118 and 122 has a vertical thickness T D has.

[0034] In other embodiments, bottom surface 126H of metal line 126 and bottom surface 114C of metal line 114 may not be planar. FIG. 1C is a cross-sectional view of the structure in FIG. 1B in which bottom surfaces 126H and 114C are substantially curved. The curved surfaces indicate the processing steps utilized to form metal lines 126 and 114. Such curved surfaces may indicate the particular processing techniques utilized, as described further below. In an exemplary embodiment, the lowest portions of surfaces 126H and 114D are substantially flush with top surfaces 126G and 114C, respectively, where top surfaces 126G and 114C are substantially flush.

[0035] In some instances, sidewalls 118B and 118A or sidewalls 122B and 122A are not substantially vertical as shown in Figures 1B or 1C. Figure 1D is a cross-sectional view of a portion of integrated circuit interconnect structure 100 shown in Figure 1B. In some such instances, lateral width W V1 decreases along the Z direction. As shown, the lateral width W V1 decreases from a maximum lateral width at boundary 136 between metal line 114 and conductive via 118 to a minimum lateral width at boundary 138 between metal line 102 and conductive via 118. In an exemplary embodiment, the lateral width W at boundary 136 V1 is the lateral width W of the metal line 102 M1 As shown, sidewalls 118A and 118B are inclined substantially similarly relative to boundary 138. Also, as shown, sidewalls 118A and 118B do not extend beyond sidewalls 102A and 102B, respectively.

[0036] In the embodiment, the lateral width W V2 decreases along the Z direction. As shown, the lateral width W V2 decreases from a maximum lateral width at boundary 140 between metal line 114 and conductive via 122 to a minimum lateral width at boundary 142 between metal line 106 and conductive via 122. In an exemplary embodiment, the lateral width W at boundary 140 V2 is the lateral width W of the metal line 106 M2As shown, sidewalls 122A and 122B are angled substantially similarly relative to boundary 142. Also, as shown, sidewalls 122A and 122B do not extend beyond sidewalls 106A and 106B, respectively. In the exemplary embodiment, sidewalls 122A and 122B are angled substantially similarly relative to sidewalls 118A and 118B, respectively.

[0037] In other embodiments, metal lines 102 and 106 (not shown) may be tapered, with metal lines 102 and 106 having a maximum width at boundaries 138 and 142, respectively. In such an example, the maximum lateral width W V1 is the maximum lateral width W of the metal line 102 at the boundary 138 M1 In a further such example, the maximum lateral width W of conductive via 122 at boundary 140 is substantially equal to V2 is the maximum lateral width W of the metal line 106 at the boundary 142 M2 is essentially equal to

[0038] Horizontal width W at boundaries 138 and 142 V1 and W V2 W M1 and W M2 , dielectric portion 124 contacts portions of metal lines 102 and 106. As shown, dielectric 124 directly contacts a portion of top surface 102C of metal line 102 and directly contacts a portion of top surface 106C of metal line 106.

[0039] 1A , in some examples, metal lines in metallization level 111 have lateral widths that vary in the X-direction. Such variations may be periodic and may be aligned with portions of dielectric 110 in integrated circuit interconnect structure 100. In an exemplary embodiment, metal line 114 has a width W MT As shown, portion 114E is directly above dielectric portion 124A and dielectric 110. As shown, portion 114E has a larger width W MTThe portion of metal line 114 having a . . . is also not overlying metal lines 102 or 106.

[0040] In an embodiment, metal line portion 126C has a width W MT The larger width W (within dashed line 144B) MT Metal line portion 126C also overlies dielectric 110. In some embodiments, metal line portions 114E and 126C have a width W MT It should be understood that the widths W are substantially similar. As shown, the larger width W MT The portions of metal line 126 having a thickness T M , metal line portion 126C still has a width W MT The larger width W (within dashed line 144B) MT may have:

[0041] In some examples, a metal line, such as metal line 146 in metallization level 111, may extend over more than two metal lines in the first metallization level 101. In an exemplary embodiment, metal line 146 has a thickness T that varies along the plane of the metal line in the Y direction relative to a top surface 146A. M 1. Metal line 146 is located in a plane behind the plane of metal line 126, where the two planes are separated along the X-direction. In an exemplary embodiment, the plane of metal line 126 is separated from the plane of metal line 146 by one or more dielectrics. Integrated circuit interconnect structure 100 further includes metal line 148 and metal line 150 on the plane behind the plane of metal line 146.

[0042] In some embodiments, metal line 146 also has portions within dashed lines 144C, 144D, and 144E, where lateral width W MT is larger than other portions of metal line 146. The portions of metal line within dashed lines 144C, 144D, and 144E also correspond to positions above dielectric 110.

[0043] In some embodiments, metal line 148 also has portions within dashed lines 144F and 144G, where lateral width W MT is larger than other portions of metal line 148. The portions of metal line within dashed lines 144F and 144G also correspond to positions above dielectric 110.

[0044] Depending on the layout of integrated circuit interconnect structure 100 , metal lines 146 , 148 and 150 in metallization level 111 may have features of one or more of metal lines 114 and 126 .

[0045] Figure 1E is a cross-sectional view through line B-B' in Figure 1A. As shown, integrated circuit interconnect structure 100 includes metal line 146 that extends over metal lines 102, 106, 130 and 134. Metal line 146 includes metal line portions 146B, 146C and metal line portion 146D between portions 146B and 146C.

[0046] In various examples, different portions of metal line 146 may have different thicknesses relative to top surface 146G. For example, as shown, metal line portions 146B and 146C each have a vertical thickness T1, and metal line portion 146C has a vertical thickness T2. In an embodiment, as shown, T1 is less than T2. ​​The different vertical thicknesses may be the result of a manufacturing process. As illustrated in FIG. 1B, T1 and T2 are each a vertical thickness T A and T C It should be understood that this may be substantially the same as:

[0047] 1E, in an exemplary embodiment, metal line 146 has sidewall 146E and sidewall 146F that extend along the X-direction (into the page as depicted). In some embodiments, sidewall 146E does not extend beyond sidewall 134A, and sidewall 146F does not extend beyond sidewall 106B. As shown, sidewall 146E is substantially aligned with sidewall 134A (in the Y-direction), and sidewall 146F is substantially aligned with sidewall 106B (also in the Y-direction).

[0048] As explained above, the manufacturing process, including the DSA process, may result in different vertical thicknesses (along the Z direction) of portions of metal line 146. The DSA process may result in different metal line portions in metallization level 111 extending over and being aligned with individual metal lines in metallization level 101. For example, metal line portion 146D extends over metal lines 130 and 102, but does not extend over metal lines 134 or 106.

[0049] In some embodiments, metal line 146 may also be coupled to one or more conductive vias that are substantially similar to conductive vias 118 or 122. In an exemplary embodiment, metal line portion 146D contacts conductive via 150 and conductive via 152. As shown, at metallization level 101, each of conductive vias 150 and 152 is separately coupled to metal line 130 and metal line 102, respectively. Conductive vias 150 and 152 are separated from each other in the YZ plane by portions of dielectric 124. Each of conductive vias 150 and 152 includes one or more characteristics of conductive vias 118 and 122, such as length and width (X and Y directions, respectively), height (Z direction), and material composition.

[0050] 1A, in embodiments, each of the metal lines 102, 106, 130, and 134 includes the same material. In some embodiments, the metal lines 102, 106, 130, and 134 include a liner layer and a filler metal on the liner layer. For example, the liner layer can include ruthenium or tantalum, and the filler metal can include tungsten, cobalt, nickel, or copper.

[0051] In embodiments, each of the metal lines 114, 126, 146, 148, and 150 includes the same material. In some embodiments, the metal lines 114, 126, 146, 148, and 150 include a liner layer and a fill metal on the liner layer. For example, the liner layer may include ruthenium or tantalum, and the fill metal may include tungsten, cobalt, nickel, or copper. The metal lines 114, 126, 146, 148, and 150 may include a material that is different from the material of the metal lines 102, 106, 130, and 134.

[0052] The dielectric 110 includes silicon and at least one or more of oxygen, carbon, or nitrogen, such as, for example, SiO2, SiOC, SiOCN, SiN, or SiC.

[0053] In an embodiment, the substrate 108 comprises a suitable semiconductor material, such as, but not limited to, monocrystalline silicon, polycrystalline silicon, silicon on insulator (SOI). In another embodiment, the substrate 108 comprises other semiconductor materials, such as germanium, silicon germanium, or suitable III-N or III-V compounds. In another embodiment, the substrate 108 comprises silicon and at least one or more of oxygen, carbon, or nitrogen, such as, for example, SiO2, SiOC, SiOCN, SiN, or SiC. In some examples, the substrate 108 comprises a material substantially similar to that of the dielectric 110. Logic devices, such as MOSFET transistors and access transistors, may be formed on the substrate 108. Logic devices, such as access transistors, may be integrated with the integrated circuit interconnect structure 100 and memory devices, such as SOT memory devices, to form embedded memories. SOT memory devices and embedded memories, including logic MOSFET transistors, may be combined to form functional integrated circuits, such as systems on chips.

[0054] FIG. 2 illustrates a flow diagram of a method for fabricating an integrated circuit interconnect structure according to one embodiment of the disclosure. Method 200 begins at step 210 by forming a plurality of metal lines above a substrate, where each line is separated by a dielectric. Method 200 continues at step 220, where a stack of polymer structures is selectively formed on each of the plurality of metal lines. The polymer structures have substantially equal heights and lateral widths that correlate with the lateral widths of the metal lines. Method 200 continues at step 230, where a stack of dielectric structures is formed adjacent to the stack of polymer structures. Method 200 continues at step 240, where the stack of polymer structures is removed to form a mesh structure including a first stack of dielectric structures and a second dielectric structure that intersects the first stack of dielectric structures orthogonally. Method 200 continues at step 250, where the dielectric mesh is etched at selected locations to expose the underlying metal lines. The method finally continues at step 260, where a via structure is formed on a portion of the metal lines and the second plurality of metal lines in a direction orthogonal to the direction of the first plurality of metal lines.

[0055] 3A illustrates a cross-sectional view after formation of metal lines 102, 106, 130, and 134 formed above substrate 108. In an embodiment, metal lines 102, 106, 130, and 134 are formed using a damascene process by patterning a plurality of trenches in dielectric 110. The metal lines may have substantially vertical or tapered sidewalls. In an exemplary embodiment, sidewalls 102A, 102B, 106A, 106B, 130A, 130B, 134A, and 134B are substantially vertical to the top surface of substrate 108. In an exemplary embodiment, each of metal lines 106, 130, and 134 has a substantially equal lateral width W M , evenly spaced apart by a spacing S1. In some embodiments, to facilitate the direct self-assembly process described below, W M and S1 are substantially equal to each other.

[0056] FIG. 3B shows the structure of FIG. 3A after a process of selectively forming polymer lines 300 on each of the metal lines 102, 106, 130, and 134. The polymer lines 300 are formed by a directed self-assembly process, where a diblock copolymer is formed on the metal lines 102, 106, 130, and 134 and the dielectric 110. The diblock copolymer includes a first polymer, such as polystyrene (PS) 300, and a second polymer, such as polymethylmethacrylate (PMMA) (inside dashed box 301), adjacent to the PS 300. In one embodiment, a wet chemical process is utilized to selectively remove the polymethylmethacrylate (PMMA) 301 relative to the PS 300. In other embodiments, the PS 300 can be selectively removed relative to the polymethylmethacrylate (PMMA) 301. Removal of the PS 300 can provide more flexibility in material selection above the metal lines 102, 106, 130, and 134, for example.

[0057] As shown, polymer lines 300 are selectively formed on metal lines 134, 130, 102 and 106, where sidewalls 300A and 300B of each polymer line 300 are substantially aligned with sidewalls 102A and 102B, 106A and 106B, 130A and 130B, 134A and 134B, respectively. In an exemplary embodiment, polymer lines 300 do not extend over dielectric 110.

[0058] As shown, the polymer line 300 has a longitudinal thickness T P and width W P T P and W P The ratio of T to T defines the aspect ratio (AR) of the polymer line 300. In an embodiment, the AR of the polymer line is in the range of between 2:1 and 3:1, and T P W P Greater than 300 W for each polymer wire P is the lateral width W of each metal line 102, 106, 130 or 134 M Since the aspect ratio of each polymer line 300 depends on W M It should be understood that the aspect ratio of each metal line may vary depending on the W of the polymer line 300 to reduce the variation in the aspect ratio. M In some embodiments, it is desirable to have a single value of W between each of the metal lines 102, 106, 130, and 134 without significantly affecting the aspect ratio of each of the formed polymer lines 300. M can vary by up to 10%.

[0059] The spacing S1 can also affect the aspect ratio. Since the diblock copolymer contains polymethylmethacrylate (PMMA) 301, the polymethylmethacrylate (PMMA) 301 (T P The aspect ratio of W / S1 depends on the spacing S1 and the aspect ratio of PS 300. S1 and W are set so that the aspect ratio of PS 300 and the aspect ratio of polymethyl methacrylate (PMMA) 301 are substantially equal. M It may be desirable for the ratio of W to be close to 1:1. MThe ratio of S1 to S2 can vary by up to 10%.

[0060] FIG. 3C shows a cross-sectional view of the structure of FIG. 3B after processes to form dielectrics 302, polymer lines 304 on each dielectric 300, and dielectric 306.

[0061] In an embodiment, a dielectric 302 is formed adjacent to each polymer line 300. The dielectric may be formed at a sufficiently low temperature to prevent the polymer lines 300 from collapsing. In some embodiments, the dielectric 302 includes SiO2, SiOC, SiOCN, SiN, SiC. In some embodiments, the dielectric 302 is replaced by a thin hermetic liner 303A formed adjacent to the polymer 300, as shown by the area in dashed line 303C, and a dielectric 303B formed on the hermetic liner 309A. The hermetic liner may help reduce oxidation of the metal lines 102, 106, 130, and 134 and provide a hermetic etch stop. The thin hermetic liner 309A may include SiOCN, Al2O3, or HfO2, and the dielectric 303B includes the material of the single dielectric 302. The dielectric 302 may be deposited to fill the space between each polymer line 300. In another example, the dielectric 302 may be blanket deposited and any excess formed on the polymer 300 may be removed by a planarization process, such as a chemical mechanical polishing (CMP) process.

[0062] When a thicker polymer structure is desired (in the Z direction), a second set of polymer lines may be formed over the first set of polymer lines 300, since the aspect ratio of the polymer lines 300 is determined by the metal lines 102, 106, 130, and 134. A thicker polymer structure may be desired because the metal lines and vias subsequently formed by polymer removal may need to have a minimum thickness to operate effectively. For example, to reduce electrical capacitance, the total polymer thickness T TP It is desirable to increase T TPBy increasing the total polymer thickness T, one or more higher conductive vias can be formed above the metal lines 102, 106, 130 and / or 134. The higher conductive vias can isolate the metal lines 102, 106, 130 or 134, for example, from metal lines that will be formed above the higher conductive vias. As a further example, to reduce line resistance, the total polymer thickness T TP It may be desirable to increase the thickness of the conductive vias to form thicker metal lines over one or more conductive vias formed above the metal lines 102, 106, 130 and / or 134.

[0063] In an exemplary embodiment, a second set of polymer lines 304 is formed on the first set of polymer lines 300. Each polymer line 304 is aligned with each of the polymer lines 300. The method of forming the polymer lines 304 is substantially identical to the process utilized to form the polymer lines 300. The dielectric 302 is exposed after the polymer lines 304 are formed.

[0064] A second dielectric 306 is formed on the dielectric 302. In an embodiment, the dielectric 306 comprises a material different from that of the dielectric 302. The different dielectric material helps enable selective removal and increases tolerances during subsequent lithography and etching steps. The dielectric 306 may be blanket deposited in the spaces between the polymer lines 304 by a plasma enhanced chemical vapor deposition (PECVD) or chemical vapor deposition (CVD) process. In some embodiments, any excess dielectric 306 formed on the polymer lines 304 is removed by a planarization process. In some embodiments, prior to deposition of the dielectric, a thin sealing liner 305A comprising SiOCN, Al2O3, or HfO2 is formed adjacent to the polymer 300. A dielectric 305B may be formed on the sealing liner 305A, as shown by the area within the dashed line 305C. In an embodiment, the dielectric 305B comprises the material of the dielectric 302.

[0065] Depending on the embodiment, the process of forming a dielectric between the polymer lines and forming additional polymer lines on top of a given polymer line may be repeated two to four times.

[0066] FIG. 3D shows a cross-sectional view of the structure of FIG. 3C after removal of the polymer lines 304 and 300. In an embodiment, a wet chemical process is utilized to remove the polymer lines 304 and 300 selectively to the metal lines 102, 106, 130 and 134, the dielectrics 302 and 306. After removal of the polymer lines 300 and 304, a plurality of openings 307 are formed between the stack of dielectrics 306 and 302. The stack of dielectrics 306 and 302 has substantially aligned sidewalls. The lateral width (in the Y direction) of the dielectrics 306 and 302 is substantially equal to the spacing S1. For example, the dielectric 302 is spaced apart from the width W of the dielectric 306. D2 and a width W substantially equal to the spacing S2 between the metal lines 134 and 130. D1 has.

[0067] As shown, sidewalls 306A and 306B of dielectric 306 are substantially perpendicular to the X and Y axes. The perpendicularity of sidewalls 306A and 306B can determine, for example, whether the sidewalls of a metal line to be subsequently formed in opening 307 will align with the sidewalls of metal lines 102, 106.

[0068] FIG. 3E shows a cross-sectional view of the structure of FIG. 3D after forming dielectric 308 adjacent to dielectric 302 on metal lines 102, 106, 130, and 134. In an embodiment, dielectric 308 comprises a material that is the same or substantially the same as the material of dielectric 302. In some such embodiments, the boundary between 302 and 308 may be inconclusive. In other embodiments, some voids may be formed in dielectric 308 adjacent to dielectric 302 depending on the materials of dielectrics 302 and 308 and the spacing between each dielectric 302. Dielectric 308 may be blanket deposited by a CVD or PECVD process in a plurality of openings 307 on dielectric 306, adjacent to dielectric 302, and on metal lines 102, 106, 130, and 134. In an embodiment, dielectric 308 comprises the material of dielectric 302.

[0069] In some embodiments, any excess dielectric 308 formed above the dielectric 306 may be removed by a planarization process. After the planarization process, the dielectric 308 may be recessed by a wet chemical process selective to the dielectric 306. During recessing of the dielectric 308, the width W D2 remains unchanged or substantially unchanged. In embodiments, the recessing process forms a top surface 308A of the dielectric 308 that is flush with the top surface 302A of the dielectric 302. In other embodiments, surfaces 302A and 308A are not coplanar. For example, surface 302A can be above or below surface 308A.

[0070] In some embodiments, as indicated by the area within dashed line 309C, single dielectric 308 is replaced by a thin sealing liner 309A formed adjacent to dielectric 302 and a dielectric 309B formed on sealing liner 309A. Thin sealing liner 309A may include SiOCN, Al2O3, or HfO2, and dielectric 309B includes the material of dielectric 308. Thin sealing liner 309A may or may not be adjacent to dielectric 306. For example, in an exemplary embodiment, thin sealing liner 309A is not adjacent to dielectric 306.

[0071] In an embodiment in which the single dielectric 302 is replaced by a thin sealing liner 303A and a dielectric 303B on the thin sealing liner 303A, as shown, the sealing liner 303A and the sealing liner 309A are directly adjacent to one another.

[0072] 4A shows a cross-sectional view of the structure in FIG. 3E after a sacrificial layer 310 adjacent to and overlying dielectric 306 and a mask 311 over sacrificial layer 310 has been formed. In an embodiment, sacrificial layer 310 includes silicon and one or more of carbon and oxygen. In an exemplary embodiment, sacrificial layer 310 is 100% thicker than dielectric 306 by a height H D In some embodiments, the sacrificial layer 310 may be planarized after deposition. A mask 311 may be formed on the sacrificial layer 310 by a lithographic process.

[0073] Figure 4B shows a cross-sectional view perpendicular to line A-A' in Figure 4A. Mask 311 is designed to form openings 312 that define the lengths of metal lines and conductive vias to be formed later. Dielectrics 306 and 302 form lines in the X direction as shown.

[0074] 5A shows a cross-sectional view of the structure of FIG. 4B after a process that etches the portions of the sacrificial layer 310 and the dielectric 306 exposed by the mask 311. In an embodiment, a plasma etching process is utilized to etch the sacrificial layer 310 and the dielectric 306. In an embodiment, the plasma etching process is sufficiently anisotropic to form sidewalls 306A and 306B in the dielectric 306 that are substantially perpendicular to the top surface 302A. The process of plasma etching removes portions of the dielectric 306 and exposes the top surface 302A of the dielectric 302.

[0075] Figure 5B shows a cross-sectional view of the structure of Figure 5A after deposition of dielectric 314. In an embodiment, mask 311 is removed prior to deposition of dielectric 314. In an embodiment, dielectric 314 is blanket deposited on sacrificial layer 310 in opening 313 adjacent dielectric 306 on uppermost dielectric surface 302A.

[0076] In an embodiment, the dielectric 314 is deposited by a PECVD or CVD process. The dielectric 314 comprises a material different from the material of the dielectric 306 or 302. In an embodiment, the dielectric 314 comprises SiO2, SiOC, SiOCN, SiN, or SiC.

[0077] 6A shows an isometric view of the structure of FIG. 5B after a process of planarizing the dielectric 314, the sacrificial layer 310, and the dielectric 306 to form the mesh structure 315. In an embodiment, the planarization process includes a chemical mechanical polishing (CMP) process. The CMP process forms coplanar or substantially coplanar top surfaces 310A, 306C, and 314A. As shown, the dielectric 314 extends along the Y direction. As shown, each dielectric 306 forms a pillar structure, where each pillar of the dielectric 306 is separated from another pillar of the dielectric 306 in the Y direction by the sacrificial material 310 and separated in the X direction by the dielectric 314.

[0078] Figure 6B shows a cross-sectional view through line A-A' of the structure in Figure 6A. In an exemplary embodiment, the sacrificial layer 310 has a substantially vertical sidewall 310B (relative to the top surface 310A) adjacent the dielectric 306.

[0079] FIG. 7(A) shows an isometric view of the structure of FIG. 6A after a process to remove the sacrificial layer 310 and recess portions of the dielectric 308. In an embodiment, the sacrificial layer 310 is removed by a plasma etching process. The plasma etching process may have a sufficiently low ion energy to not recess the top surfaces 306C and 314A. After removal of the sacrificial layer 310, the dielectric 308 is recessed below the bottom surface 314B that contacts the dielectric 308. In an embodiment, the dielectric 308 is recessed by a plasma etching process that is different from the etching process utilized to remove the sacrificial layer 310. In an exemplary embodiment, the sidewalls 302B and 308A of the dielectric 302 are exposed after the plasma etching process. In an embodiment, as shown, the sidewalls 302B and 308A are substantially vertical. In some examples, the exposed top surface 308B of the dielectric 308 has a concave profile, as shown in the enlarged isometric view of FIG. 7(B). The top surface 308B may be concave, formed by a plasma etching process.

[0080] 7(C) shows a cross-sectional view through line A-A' of the structure in FIG. 7(A) after a process of removing the sacrificial layer 310 to recess portions of the dielectric 308. In an embodiment, the dielectric 308 may have a portion 308C that remains adjacent to the sidewall 302B after the plasma etching process. In another embodiment, the dielectric 308 has a portion 308C with a curved surface 308B that remains adjacent to the sidewall 302B. The remaining portion 308C may change the profile of a conductive via that may be formed above one or more metal lines 102, 106, 130, or 134.

[0081] FIG. 8A shows an isometric view of the structure of FIG. 7(A) after the formation of sacrificial material 316 and after the process of planarization and formation of a mask 318 over the sacrificial material 316, dielectric 306, and dielectric 314.

[0082] In an embodiment, the sacrificial material 316 is the same or substantially the same as the sacrificial material 310 described in connection with FIG. 4A. The sacrificial material 316 may be blanket deposited using a PVD or PECVD process. The sacrificial material 316 is viscous during deposition to fill the vacant space between the dielectric 314 and the dielectric 306 on the dielectric 308. In an embodiment, the sacrificial material 316 may be planarized by a CMP process. The planarization process also removes the top of the dielectric 306 and the dielectric 314.

[0083] Mask 318 may be formed by a lithography process. Mask 318 includes various openings that define locations where conductive vias will be formed in a later step. As shown, mask 318 includes openings 319 that expose sacrificial material portions 316A and 316B. In an exemplary embodiment, after removal of sacrificial material portions 316A and 316B and underlying dielectric 308, conductive vias are formed on portions of metal lines 102 and 106. The lithography process allows for some lithography misalignment between mask 318 and sacrificial material 316. For example, desired portions of sacrificial material portions 316A and 316B can be removed as long as some portions of sacrificial material portions 316A and 316B are exposed. In an exemplary embodiment, mask 318 completely exposes sacrificial material portions 316A and 316B. Mask 318 also includes openings 320, 321, and 322.

[0084] 8B shows a cross-sectional view through line A-A' of the structure in FIG. 8A. As shown, opening 319 partially covers dielectric portion 306D and fully exposes (in the Y direction) sacrificial material portions 316A and 316B. Utilizing a directed self-assembly technique to define the location of sacrificial material 316 is advantageous because mask 318 does not need to be precisely aligned with the sacrificial material portions that are to be removed. However, it is important to ensure that the mask properly covers all sacrificial material portions that do not need to be removed.

[0085] FIG. 9A shows a cross-sectional view of the structure in FIG. 8B after a process of etching the dielectric 308 from areas not covered by the mask 318 after removing the sacrificial material 316. In an embodiment, the sacrificial material portions 316A and 316B are removed by a plasma etching process. The plasma etching process may have a sufficiently low ion energy so as not to recess the tops of the dielectrics 306D and 306E. After removal of the sacrificial material portions 316A and 316B, the dielectric 308 is removed to expose each of the metal lines 102 and 106. In an embodiment, the dielectric 308 is recessed by the plasma etching process. In an exemplary embodiment, after the plasma etching process, the sidewall 302B of the dielectric 302 is exposed. In an embodiment, the substantially vertical profile of the sidewall 302B remains unchanged after the plasma etching process. In embodiments in which dielectric 308 comprises the same material as that of dielectric 302, some portions of dielectric 308 may remain on sidewall 302B and on the top surfaces of metal lines 102C and 106C. In some such embodiments, opening 323 between dielectric portions 306D and 306E may have a width W O Larger width W O It should be understood that if the metal lines in metallization level 101 are of substantially the same width (in the Y direction), then all of the openings 323 will have substantially the same size and shape. After formation of the openings 323, the mask 318 is removed.

[0086] FIG. 9B shows a cross-sectional view of the structure in FIG. 9A after forming a masking layer 328 and a mask 330 over the masking layer 328 after forming a sacrificial material 326 in the openings 323 .

[0087] In an embodiment, the sacrificial material 326 is the same or substantially the same as the sacrificial material 316 described in connection with FIG. 9A. The sacrificial material 326 may be blanket deposited using a PVD or PECVD process. The sacrificial material 326 is viscous during deposition to fill the opening 323. In an embodiment, the sacrificial material 326 may be planarized by a CMP process. The planarization process also removes the top of the dielectric 306 and the sacrificial material 316.

[0088] In an embodiment, a masking layer 328 is deposited over the dielectric 306, the sacrificial material 316, and the sacrificial material 326. In an embodiment, the masking layer 328 may be a photoresist material or alloy that can be removed by a wet chemical process. The mask 330 may be formed by lithographic techniques. The mask 330 is designed to expose selected portions of the dielectric 306 after the masking layer 328 is patterned.

[0089] 9C shows a cross-sectional view of the structure in FIG. 9B after a process of etching the masking layer 328 and the portions of the dielectric 306 not covered by the mask 330. In an embodiment, the masking layer 328 is etched by a plasma etching process. As shown, the mask 330 is designed to allow for the removal of selected portions of the dielectric 306. Thus, the mask 330 may not require precise alignment with respect to the sacrificial materials 326 and 316. Partial exposure of the selected portions of the dielectric 306 by the mask 330 is sufficient.

[0090] After the masking layer 328 is etched, selected portions of the dielectric 306 are removed using a wet chemical etching process. In the figure, dashed lines indicate the dielectric portions 306E and 306F that are etched by the wet chemical etching process. As shown, the etching process is selective to the masking layer 328, the sacrificial layers 316 and 326, and the dielectric 302. As shown, the masking layer 328 does not perfectly align with the dielectric portion 306E. However, because the dielectric portion 306E is predetermined, it occupies a fixed volume that is all removed by the wet chemical etching. The removal of the dielectric portions 306E and 306F forms an opening 332.

[0091] 9D shows a cross-sectional view of the structure in FIG. 9C after a process to remove mask 330, masking layer 328, and etch portions of dielectric 302 selective to dielectric 306 and sacrificial materials 316 and 326. In an embodiment, dielectric 302 is recessed by a plasma etching process. Although it may be desirable to utilize a wet chemical process to etch dielectric 302, portions of dielectric 302 (not shown in the figure, in the X direction below dielectric 314) may also be etched by the wet chemical etch. A directional etch such as a plasma etch is desirable.

[0092] In the exemplary embodiment, the plasma etch recesses surface 302C of dielectric 302 below top surface 308A of dielectric 308. In other embodiments, dielectric surface 302C may be at the same level as surface 308A or at a level above surface 308A. As shown, dielectric 302 has a thickness T D and the dielectric 302 has a thickness T D1 Depending on the amount of recess in the dielectric 302, T D and T D1 The relative difference between the

[0093] In some examples, the plasma etching process forms recesses or curved surfaces 302C, which result in the formation of the curved metal line portions described above in connection with FIG.

[0094] It should be understood that dielectric portion 302D having surface 302C recessed below surface 308A results in the formation of third metal line portion 126C, as described in connection with FIG. 1B. When dielectric 302 is recessed by directional plasma etching (in the negative Z direction), the sidewalls of dielectric 308 are not etched and remain substantially vertical, as shown. In such an example, the lateral width W of dielectric 302 is D is substantially the same as the spacing S2 between metal lines 134 and 130.

[0095] Figure 9E shows an isometric view of the structure in Figure 9D after a process to remove sacrificial materials 316 and 326. In an embodiment, when sacrificial materials 316 and 326 are the same material, a single plasma etch process can remove sacrificial materials 316 and 326.

[0096] After removing the sacrificial materials 316 and 326, various portions of the metal lines 102, 106, 130, and 134 may be exposed depending on the layout of the mask utilized during the manufacturing process. The exposed portions of the metal lines 102, 106, 130, and 134 provide locations where conductive vias will be formed in subsequent steps. As shown, each conductive via formed has a spatial extent in the X-direction of length L V Limited to.

[0097] As shown, some columnar dielectric portions may remain, such as dielectric portion 308D. In an embodiment, dielectric portion 308D provides insulation between two metal lines to be formed later. Also, as shown, surface 302C is at a lower level compared to surface 308A in mesh structure 315 due to the recessing process described in connection with FIG. 9D.

[0098] Openings 334 provide space for conductive vias and metal lines to be formed. Openings 336 provide space for metal lines to be formed in a later step. It should be understood that the shape of openings 334 and 336 shown in Figure 10A is defined by the polymer lines 300 and the spaces between the polymer lines 300 as described in connection with Figure 3B.

[0099] FIG. 10A shows an isometric view of the structure in FIG. 10A after the process of depositing conductive material 338 to form conductive vias 118 and 122, and metal lines 114 and 126.

[0100] It should be understood that conductive vias 118 and 122 and metal line 114 are formed simultaneously by a deposition process. As shown, the boundary of conductive vias 118 and 122 is defined by dashed line 340. Conductive metal 338 deposited in opening 336 between dashed lines 340 and 342 defines metal line 114. Conductive metal 338 deposited in opening 336 defines metal line 126.

[0101] In the exemplary embodiment, metal lines 114, 126 and 146 are not insulated. A subsequent planarization process insulates metal lines 114, 126 and 146 from one another.

[0102] 10B illustrates a cross-sectional view of the structure of FIG. 10A in an embodiment in which the conductive material 338 can include more than one material. For example, the liner layer 338A can be a blanket deposition in the openings 334 and 336 followed by deposition of a fill metal 338B, such as tungsten, cobalt or nickel, on the liner layer 338A.

[0103] In the exemplary embodiment, a liner layer 338A is deposited on the exposed top surfaces 302C and 308A on the sidewalls of dielectric portion 302E at opening 338. A liner layer is also deposited on the sidewalls and on the upper surface of dielectric 306. A liner layer 338A is also deposited on top surface 102C of metal line 102, top surface 106C of metal line 106, surface 302C, and on the sidewalls of dielectric portion 302F at opening 336.

[0104] In an embodiment, the liner layer 338A includes ruthenium or tantalum and the fill metal 338B includes tungsten, cobalt, nickel or copper.

[0105] 11 shows an isometric view of the structure in FIG. 10A after a process of planarization of the conductive material. In an embodiment, the conductive material may be planarized by a CMP process. The CMP process may be utilized to remove excess conductive material from above dielectrics 302, 308, 306, and 314. In an exemplary embodiment, the planarization process continues until dielectrics 306 and 314 are also completely removed, metal line 126 is formed in opening 336, and conductive vias 118 and 122 and metal line 114 are formed in opening 334.

[0106] The process steps described in connection with Figures 3A-10B describe several combinations of steps that result in the structure shown in Figures 11 and 1A. While masks utilized in the manufacturing process define the locations of the various openings that are formed, it should be understood that the metal lines and / or vias that are formed are self-aligned with respect to an axis passing through each metal line 102, 106, 130 or 134. Although the various conductive vias may have vertical or angled sidewalls, due to the self-alignment process described above, there is no misalignment between the conductive vias and metal lines in metallization levels 101 and 111.

[0107] 12 illustrates a cross-sectional view of an integrated circuit structure, such as integrated circuit interconnect structure 100 coupled with a MOS transistor 1200, according to one embodiment of the present disclosure. The integrated circuit interconnect structure 100 includes metal lines 102, 106, 130, and 134 embedded in a dielectric 110 on a plane above the MOS transistor 1200.

[0108] In an embodiment, the transistor 1200 is on a substrate 1201 and has a gate 1202, a source region 1204, and a drain region 1206. In an exemplary embodiment, an insulator 1208 is adjacent to the source region 1204, the drain region 1206, and portions of the substrate 1201. As shown, in some implementations of the disclosure, a pair of sidewall spacers 1210 are on opposite sides of the gate 1202. As shown in FIG. 12, the transistor 1200 further includes a gate contact 1212 above and electrically coupled to the gate 1202, a drain contact 1214 above and electrically coupled to the drain region 1206, and a source contact 1216 above and electrically coupled to the source region 1204. Transistor 1200 also includes gate 1202, source region 1204, drain region 1206, insulator 1208, sidewall spacers 1210, gate contact 1212, contact 1214, and dielectric 1218 adjacent contact 1216. In an exemplary embodiment, conductive interconnect 1222 is directly over and in contact with contact 1216. In other embodiments, there are one or more additional interconnect structures between source region 1204 and conductive interconnect 1222.

[0109] The gate contact 1212 and the contact 1214 are each coupled to an interconnect. In an exemplary embodiment, the gate contact 1212 is coupled to the gate interconnect 1224 and the contact 1214 is coupled to the interconnect 1226. A dielectric 1228 is adjacent to the interconnect 1226, the interconnect 1224, the interconnect 1222, the substrate 1201, the source contact 1216, the gate contact 1212, and the contact 1214.

[0110] In an embodiment, integrated circuit interconnect structure 100 has one or more structural and material characteristics described above in connection with integrated circuit interconnect structure 100 shown in FIG. 1A. In an exemplary embodiment, integrated circuit interconnect structure 100 includes a first metallization level 101 including a metal line 102 having a first sidewall 102A and a second sidewall 102B extending a length in an X-direction. Metallization level 101 is above MOS transistor 1200. Metal line 102 is directly above and coupled to interconnect 1226. Metal line 102 is directly above and coupled to interconnect 1226 and has a length in the X-direction that is less than or equal to the length in the X-direction of interconnect 1226. Metal line 102 is aligned with a width W of interconnect 1226 in the Y-direction. C1 The width W in the Y direction is greater than or equal to M1 may have:

[0111] The integrated circuit interconnect structure 100 further includes a metallization level 111 above the metallization level 101. In the exemplary embodiment, the metallization level 111 includes a metal line 114 that extends in length in the Y direction above the metal line 102 (but does not extend beyond the sidewalls 102A or 102B). A conductive via 118 is between the metallization level 101 and the second metallization level 111. As shown, the conductive via 118 does not extend beyond the sidewalls 102A or 102B.

[0112] In the exemplary embodiment, metallization level 111 further includes metal line 126 extending a length in the Y-direction over metal line 130 and metal line 134, where metal line 130 and metal line 134 are in metallization level 101. As shown, metal line 130 has sidewalls 130A and 130B and extends a length in the X-direction, and metal line 134 also has sidewalls 134A and 134B and extends a length in the X-direction.

[0113] Metal line 130 is directly above and coupled to interconnect 1224 and has a length in the X-direction that is less than or equal to the length in the X-direction of interconnect 1224. Metal line 130 has a width W C2 The width W in the Y direction is greater than or equal to M2 may have:

[0114] Metal line 134 is directly above and coupled to interconnect 1222 and has a length in the X-direction that is less than or equal to the length in the X-direction of interconnect 1222. Metal line 134 is spaced apart from interconnect 1222 by a width W C3 The width W in the Y direction is greater than or equal to M2 may have:

[0115] 1B , etc. As shown, metal line 126 is aligned with metal lines 134 and 130 and interconnects 1222 and 1224. In other embodiments, metal line 126 may be substantially aligned with metal lines 134 and 130 but not substantially aligned with interconnects 1222 and 1224.

[0116] In some embodiments, the single conductive via within dashed line 1230 is between metal line 126 and metal line 134, and is on and directly adjacent to metal line 134. In other embodiments, the single conductive via within dashed line 1232 is between metal line 126 and metal line 130, and is on and directly adjacent to metal line 130. In some such embodiments, the conductive via within dashed line 1230 or within dashed line 1232 is coplanar with conductive via 118.

[0117] In other embodiments, a metal line substantially similar to metal line 126 is on a plane behind the illustrated YZ plane, where the metal line is not in electrical contact with metal line 126. The metal line on the plane behind the illustrated YZ plane may be connected to a single conductive via in dashed line 1230 or to a single conductive via in dashed line 1232, providing an electrical connection to metal line 134 or metal line 130, respectively. A physical (and electrical) connection between the metal lines on the plane behind the YZ plane and metal line 134 or metal line 130 and interconnect 1222 or 1224, respectively, may be possible because metal lines 134 and 130 and interconnect 1222 and 1224 may extend in the X direction (toward the viewer of the page). Although conductive via 118 is shown in the YZ plane of FIG. 12, conductive via 118 may be on a plane behind the illustrated YZ plane in other embodiments. In some such embodiments, the single conductive via within dashed line 1230 or the single conductive via within dashed line 1232 may be on a plane in front of conductive via 118 .

[0118] In embodiments, underlying substrate 1201 represents a surface used to fabricate integrated circuits. Suitable substrates 1201 include materials such as monocrystalline silicon, polycrystalline silicon, silicon on insulator (SOI), as well as substrates formed on other semiconductor materials. In some embodiments, substrate 1201 is the same or substantially the same as substrate 108. Substrate 1201 may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly used in semiconductor substrates.

[0119] In an embodiment, the transistor 1200 associated with the substrate 1201 is a metal oxide semiconductor field effect transistor (MOSFET or simply MOS transistor) fabricated on the substrate 1201. In some embodiments, the transistor 1200 is an access transistor 1200. In various implementations of the present disclosure, the transistor 1200 can be a planar transistor, a non-planar transistor, or a combination of both. Non-planar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, as well as wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0120] In some embodiments, the gate 1202 includes at least two layers, a gate dielectric layer 1202A and a gate electrode 1202B. The gate dielectric layer 1202A can include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiO2) and / or high-k dielectric materials. The high-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum oxide, aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, the gate dielectric layer 1202A may be subjected to an annealing process to improve its quality when high-k materials are used.

[0121] A gate electrode 1202B of an access transistor 1200 in a substrate 1201 is formed on a gate dielectric layer 1202A and may consist of at least one P-type work function metal or an N-type work function metal depending on whether the transistor is a PMOS or NMOS transistor. In some implementations, the gate electrode 1202B may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer.

[0122] For PMOS transistors, metals that may be used for the gate electrode 1202B include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer allows for the formation of a PMOS gate electrode with a work function between about 4.6 eV and about 5.2 eV. For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer allows for the formation of an NMOS gate electrode with a work function between about 3.6 eV and about 4.2 eV.

[0123] In some implementations, the gate electrode may be comprised of a U-shaped structure with a bottom substantially parallel to the top surface of the substrate and two sidewalls substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode 1202B may simply be a flat layer that is substantially parallel to the top surface of the substrate and does not include sidewalls substantially perpendicular to the top surface of the substrate. In further implementations of the present disclosure, the gate electrode may be comprised of a combination of U-shaped and flat, non-U-shaped structures. For example, the gate electrode 1202B may be comprised of one or more U-shaped metal layers formed on one or more planar, non-U-shaped layers.

[0124] The sidewall spacers 1210 may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon doped silicon nitride and silicon oxynitride. The process of forming the sidewall spacers includes deposition and etching process steps. In alternative implementations, multiple pairs of spacers may be used, for example, two, three or four pairs of sidewall spacers may be formed on the opposite side of the gate stack. As shown, the source region 1204 and the drain region 1206 are formed in the substrate adjacent to the gate stack of each MOS transistor. The source region 1204 and the drain region 1206 are typically formed using either an implantation / diffusion process or an etching / deposition process. If the former process is used, dopants such as boron, aluminum, antimony, phosphorus or arsenic may be ion-implanted into the substrate to form the source region 1204 and the drain region 1206. An annealing process that activates the dopants and further diffuses them into the substrate typically follows the ion-implantation process. When using the latter process, the substrate 1201 may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be performed to fill the recesses with a material used to fabricate the source and drain regions 1204 and 1206. In some implementations, the source and drain regions 1204 and 1206 may be fabricated using silicon alloys such as silicon germanium or silicon carbide. In some implementations, the epitaxially grown silicon alloy may be doped in situ with a dopant such as boron, arsenic, or phosphorus. In other embodiments, the source and drain regions 1204 and 1206 may be formed using another semiconductor material or materials, such as germanium or a III-V material or alloy. In other embodiments, the source and drain regions 1204 and 1206 may be formed using one or more layers of metal and / or metal alloy.

[0125] In an embodiment, each of the source contact 1216, the drain contact 1214, and the gate contact 1212 includes a liner layer and a fill metal. In an embodiment, the liner layer includes Ti, Ru, or Al and a conductive cap on the liner layer. The conductive cap may include a material such as W, Co, or Cu.

[0126] In an embodiment, the source interconnect 1222, the gate interconnect 1224, the conductive interconnect drain interconnect 1226 comprise a material that is the same or substantially the same as the material of the source contact 1216, the gate contact 1212, or the drain contact 1214. In one such embodiment, the fill metal comprises copper.

[0127] Each of the insulator 1208 and the dielectrics 1218 and 1228 may include any material having sufficient dielectric strength to provide electrical insulation. The material may include silicon and one or more of oxygen, nitrogen, or carbon, such as silicon dioxide, silicon nitride, silicon oxynitride, carbon-doped nitride, or carbon-doped oxide.

[0128] 13 illustrates a computing device 1300 according to an embodiment of the present disclosure. As shown, the computing device 1300 houses a motherboard 1302. The motherboard 1302 may include multiple components including, but not limited to, a processor 1301 and at least one communication chip 1304 or 1305. The processor 1301 is physically and electrically coupled to the motherboard 1302. In some implementations, the communication chip 1305 is also physically and electrically coupled to the motherboard 1302. In further implementations, the communication chip 1305 is part of the processor 1301.

[0129] Depending on the application, computing device 1300 may include other components that may or may not be physically and electrically coupled to motherboard 1302. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, crypto-processors, chipsets 1306, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, Global Positioning System (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0130] The communications chip 1305 enables wireless communication for transmitting data to and from the computing device 1300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data using modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices are completely wire-free, although in some embodiments this may not be the case. The communications chip 1305 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.11 family), Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and beyond. The computing device 1300 may include multiple communication chips 1304 and 1305. For example, a first communication chip 1305 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip 1304 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0131] The processor 1301 of the computing device 1300 includes an integrated circuit die packaged in the processor 1301. In some embodiments, the integrated circuit die of the processor 1301 includes one or more transistors, such as the transistor 1200 coupled to the integrated circuit interconnect structure 100 (described in connection with FIG. 12), an interconnect structure, and a non-volatile memory (NVM) device, such as a magnetic tunnel junction and a resistive random access memory device. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory.

[0132] The communications chip 1305 also includes an integrated circuit die packaged in the communications chip 1305. In another embodiment, the integrated circuit die of the communications chips 1304, 1305 includes one or more transistor interconnect structures, such as the integrated circuit interconnect structure 100 (described in connection with FIGS. 1A-1E), and non-volatile memory devices, such as magnetic tunnel junctions and resistive random access memory devices. Depending on the application, the computing device 1300 may include other components that may or may not be physically and electrically coupled to the motherboard 1302. These other components may include, but are not limited to, volatile memory (e.g., DRAM) 1307, 1308, non-volatile memory (e.g., ROM) 1310, graphics CPU 1312, flash memory, a global positioning system (GPS) device 1313, a compass 1314, a chipset 1306, an antenna 1316, a power amplifier 1309, a touchscreen controller 1311, a touchscreen display 1317, a speaker 1315, a camera 1303, and a battery 1318, as shown, and may include other components such as digital signal processors, cryptographic processors, audio codecs, video codecs, accelerometers, gyroscopes, and mass storage devices (such as hard disk drives, solid state drives (SSDs), compact discs (CDs), digital versatile discs (DVDs), etc.). In further embodiments, any of the components described above contained in computing device 1300 may include a stand-alone integrated circuit memory die including one or more arrays of NVM devices coupled to transistors connected to external circuitry by one or more interconnect structures, such as integrated circuit interconnect structure 100 (as described in connection with FIGS. 1A-1E). In embodiments, the NVM devices may include spintronic-based devices, magnetic tunnel junction devices, resistive random access memory devices. In other embodiments, two or three terminal spin orbit torque memory devices may be coupled to one or more transistors.

[0133] In various implementations, the computing device 1300 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder, In further implementations, the computing device 1300 may be any other electronic device that processes data.

[0134] Accordingly, one or more embodiments of the present disclosure may generally relate to the fabrication of integrated circuit interconnect structures for logic and embedded memory.

[0135] In a first example, an integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line, and a dielectric is between the first and second metal lines. A second metallization level is above the first metallization level, where the second metallization level includes a third metal line extending a length in a second direction perpendicular to the first direction. The third metal line extends above the first and second metal lines, but does not extend beyond the first sidewall. A conductive via is between the first and third metal lines, where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

[0136] In a first example, an integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line, and a dielectric is between the first and second metal lines. A second metallization level is above the first metallization level, where the second metallization level includes a third metal line extending a length in a second direction perpendicular to the first direction. The third metal line extends above the first and second metal lines, but does not extend beyond the first sidewall. A conductive via is between the first and third metal lines, where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

[0137] In a second example, for any of the first examples, the conductive via is a first conductive via, and the integrated circuit interconnect structure further includes a second conductive via between the second metal line and the third metal line, and the second conductive via does not extend beyond the first sidewall or the second sidewall of the second metal line.

[0138] In a third example, for any of the first to second examples, the first conductive via has a first lateral width in the second direction, the second conductive via has a second lateral width in the second direction, and the first lateral width is substantially equal to the second lateral width.

[0139] In a fourth example, for any of the first to third examples, the first metal line has a third lateral width in the second direction, the second metal line has a fourth lateral width in the second direction, the third lateral width being substantially equal to the fourth lateral width, the first lateral width being substantially equal to the third lateral width, and the second lateral width being substantially equal to the fourth lateral width.

[0140] In a fifth example, for any of the first through fourth examples, the first lateral width decreases from a maximum at the boundary with the third metal line to a minimum at the boundary with the first metal line.

[0141] In a sixth example, for any of the first through fifth examples, the second lateral width decreases from a maximum value at the boundary with the third metal line to a minimum value at the boundary with the second metal line.

[0142] In a seventh example, for any of the first to sixth examples, the second metallization level further includes a fourth metal line extending in the second direction over the fifth metal line and the sixth metal line, the fifth metal line and the sixth metal line being in the first metallization level.

[0143] In an eighth example, for any of the first to seventh examples, the fifth metal line has a first sidewall and a second sidewall and extends a length in the first direction, and the sixth metal line has a first sidewall and a second sidewall and extends a length in the first direction.

[0144] In a ninth example, for any of the first to eighth examples, the fourth metal line includes a first portion having a first longitudinal thickness in a third direction perpendicular to the second direction and perpendicular to the first direction. The fourth metal line further includes a second portion having the first longitudinal thickness and a third portion between the first and second portions having a second longitudinal thickness, the second longitudinal thickness being greater than the first longitudinal thickness.

[0145] In a tenth example, for any of the first to ninth examples, the third portion does not extend over the fifth metal line or the sixth metal line.

[0146] In an eleventh example, for any of the first through tenth examples, the fifth metal line and the sixth metal line are separated by a space in the second direction, and the third portion has a lateral width in the second direction, the lateral width having a center point directly above the midpoint between the spaces.

[0147] In a twelfth example, for any of the first to eleventh examples, the second vertical thickness is substantially equal to a vertical thickness of the third metal line along the second direction.

[0148] In a thirteenth example, a method of fabricating an integrated circuit interconnect structure includes forming a first metal line and a second metal line extending in a first direction, the first metal line being separated from the second metal line by a first dielectric. The method further includes selectively forming a stack of polymer structures on the first metal line and the second metal line, the stack of polymer structures including the first polymer structure on the second polymer structure. The method further includes forming a second dielectric adjacent to the first polymer structure and a third dielectric adjacent to the second polymer structure, the second dielectric and the third dielectric not extending over the first metal line or the second metal line. The method further includes removing the stack of polymer structures from over the first metal line and the second metal line and forming a fourth dielectric adjacent to the second dielectric over the first metal line and the second metal line. The method further includes patterning an opening in the third dielectric in a second direction orthogonal to the first direction, the opening exposing a portion of the fourth dielectric. The method further includes forming a mesh structure by forming a fifth dielectric in the opening over a portion of the fourth dielectric and exposing a portion of the first metal line or the second metal line by etching the second dielectric and the third dielectric, forming a conductive via over the exposed portion of the first metal line or the second metal line and forming a third metal line in the second metallization layer within the conductive via, the third metal line extending in a length in a second direction perpendicular to the first direction.

[0149] In a fourteenth example, for any of the thirteenth examples, portions of the second dielectric and the third dielectric are removed by etching to expose a portion of the first metal line in the first plane and a portion of the second metal line in the first plane.

[0150] In a fifteenth example, for any of the thirteenth to fourteenth examples, the conductive via is a first conductive via, and the method further includes forming a second conductive via, the first conductive via being formed on the first metal line, and the second conductive via being formed on the second metal line.

[0151] In a 16th example, for any of examples 13 to 15, the first conductive via is formed to have a sidewall in a first direction that does not extend beyond the sidewall of the first metal line in the first direction, and the second conductive via is formed to have a sidewall along the first direction that does not extend beyond the sidewall of the second metal line in the first direction.

[0152] In a seventeenth example, for any of the thirteenth to sixteenth examples, forming the conductive via and the metal line includes depositing a liner layer over the first metal line or the second metal line, and depositing a fill material over the liner layer.

[0153] In an eighteenth example, for any of the thirteenth to seventeenth examples, the method further comprises forming a fourth metal line at the second metallization level above the fifth metal line and the sixth metal line at the first metallization level.

[0154] In a nineteenth example, a system includes a processor and a wireless transceiver coupled to the processor, the transceiver including a transistor. The transistor includes a drain contact coupled to the drain, a source contact coupled to the source, and a gate contact coupled to the gate. An integrated circuit interconnect structure is coupled to the drain contact, the integrated circuit interconnect structure including a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metallization level is above the first metallization level, where the second metallization level includes a second metal line extending a length in a second direction orthogonal to the first direction. The second metal line extends above the first metal line without exceeding the first sidewall. A conductive via is between the first metal line and the second metal line, where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

[0155] In a twentieth example, for any of the nineteenth examples, the system further comprises a battery coupled to the device for powering at least one of the processor or the memory.

[0156] [Other possible claims] (Item 1) 1. An integrated circuit interconnect structure comprising: a first metal line extending a length in a first direction and having a first sidewall and a second sidewall; a second metal line adjacent to the first metal line; a dielectric between the first metal line and the second metal line; a first metallization level including: a second metallization level above the first metallization level, the second metallization level including a third metal line extending in a second direction perpendicular to the first direction, the third metal line overlying the first metal line and the second metal line but not extending beyond the first sidewall; a conductive via between the first metal line and the third metal line, the conductive via not extending beyond the first sidewall and not extending beyond the second sidewall; 1. An integrated circuit interconnect structure comprising: (Item 2) 2. The integrated circuit interconnect structure of claim 1, wherein the conductive via is a first conductive via, and the integrated circuit interconnect structure further includes a second conductive via between the second metal line and the third metal line, the second conductive via not extending beyond a first sidewall or a second sidewall of the second metal line. (Item 3) 3. The integrated circuit interconnect structure of claim 2, wherein the first conductive via has a first lateral width in the second direction and the second conductive via has a second lateral width in the second direction, the first lateral width being substantially equal to the second lateral width. (Item 4) 4. The integrated circuit interconnect structure of claim 3, wherein the first metal line has a third lateral width in the second direction, the second metal line has a fourth lateral width in the second direction, the third lateral width being substantially equal to the fourth lateral width, the first lateral width being substantially equal to the third lateral width, and the second lateral width being substantially equal to the fourth lateral width. (Item 5) 4. The integrated circuit interconnect structure of claim 3, wherein the first lateral width decreases from a maximum value at an interface with the third metal line to a minimum value at an interface with the first metal line. (Item 6) 5. The integrated circuit interconnect structure of claim 4, wherein the second lateral width decreases from a maximum value at an interface with the third metal line to a minimum value at an interface with the second metal line. (Item 7) 2. The integrated circuit interconnect structure of claim 1, wherein the second metallization level further includes a fourth metal line extending in the second direction over a fifth metal line and a sixth metal line, the fifth metal line and the sixth metal line being in the first metallization level. (Item 8) 8. The integrated circuit interconnect structure of claim 7, wherein the fifth metal line has a first sidewall and a second sidewall and extends a length in the first direction, and the sixth metal line has a first sidewall and a second sidewall and extends a length in the first direction. (Item 9) The fourth metal wire is a first portion having a first longitudinal thickness in a third direction perpendicular to the second direction and perpendicular to the first direction; a second portion having the first longitudinal thickness; a third portion between the first portion and the second portion, the third portion having a second longitudinal thickness greater than the first longitudinal thickness; 8. The integrated circuit interconnect structure of claim 7, comprising: (Item 10) 10. The integrated circuit interconnect structure of claim 9, wherein the third portion does not extend over the fifth metal line or the sixth metal line. (Item 11) 10. The integrated circuit interconnect structure of claim 9, wherein the fifth metal line and the sixth metal line are separated by a space in the second direction, and the third portion has a lateral width in the second direction, the lateral width having a center point directly above a midpoint between the spaces. (Item 12) 10. The integrated circuit interconnect structure of claim 9, wherein the second vertical thickness is substantially equal to a vertical thickness of the third metal line along the second direction. (Item 13) 1. A method for manufacturing an integrated circuit interconnect structure, comprising: forming a first metal line and a second metal line in a first metallization layer, the first metal line extending a length in a first direction, the first metal line being separated from the second metal line by a first dielectric; selectively forming a stack of polymer structures over the first metal line and the second metal line, the stack of polymer structures including a first polymer structure over a second polymer structure; forming a second dielectric adjacent to the first polymer structure and a third dielectric adjacent to the second polymer structure, the second dielectric and the third dielectric not extending over the first metal line or the second metal line; removing the stack of polymer structures from over the first metal line and the second metal line; forming a fourth dielectric over the first metal line and the second metal line adjacent to the second dielectric; patterning an opening in the third dielectric in a second direction perpendicular to the first direction, the opening exposing a portion of the fourth dielectric; forming a fifth dielectric in the opening over a portion of the fourth dielectric to form a mesh structure; exposing a portion of the first metal line or the second metal line by etching the second dielectric and the third dielectric; forming a conductive via in the exposed portion of the first metal line or the second metal line; forming a third metal line in the second metallization layer over the conductive via, the third metal line extending in a second direction perpendicular to the first direction; A method for providing the above. (Item 14) Item 14. The method of item 13, further comprising removing portions of the second dielectric and the third dielectric by etching to expose a portion of the first metal line in the first plane and a portion of the second metal line in the first plane. (Item 15) Item 14. The method of item 13, wherein the conductive via is a first conductive via, and the method further includes forming a second conductive via, the first conductive via being formed on the first metal line, and the second conductive via being formed on the second metal line. (Item 16) Item 16. The method of item 15, wherein the first conductive via is formed to have a sidewall in the first direction that does not extend beyond a sidewall of the first metal line in the first direction, and the second conductive via is formed to have a sidewall along the first direction that does not extend beyond a sidewall of the second metal line in the first direction. (Item 17) Item 14. The method of item 13, wherein forming the conductive via and the metal line includes depositing a liner layer over the first metal line or the second metal line and depositing a filler material over the liner layer. (Item 18) 15. The method of claim 14, further comprising forming a fourth metal line in the second metallization level above the fifth and sixth metal lines in the first metallization level. (Item 19) 1. A system comprising: A processor; a wireless transceiver coupled to the processor, a drain contact coupled to the drain; a source contact coupled to the source; a gate contact coupled to the gate; a radio transceiver including a transistor including an integrated circuit interconnect structure coupled to the drain contact, a first metallization level including a first metal line extending a length in a first direction and having a first sidewall and a second sidewall; a second metallization level above the first metallization level, the second metallization level including a second metal line extending a length in a second direction above the first metal line but not beyond the first sidewall and the second sidewall; an integrated circuit interconnect structure comprising: a conductive via between the first metal line and the second metal line, the conductive via not extending beyond the first sidewall and not extending beyond the second sidewall; A system comprising: (Item 20) 20. The system of claim 19, further comprising a battery coupled to power at least one of the processor or memory.

Claims

1. 1. An integrated circuit interconnect structure comprising: a first metal line extending a length in a first direction and having a first sidewall and a second sidewall; a second metal line adjacent to the first metal line; a dielectric between the first metal line and the second metal line; a first metallization level including: a second metallization level above the first metallization level, the second metallization level including a third metal line extending in a second direction perpendicular to the first direction, the third metal line overlying the first metal line and the second metal line but not extending beyond the first sidewall; a conductive via between the first metal line and the third metal line, the conductive via not extending beyond the first sidewall and not extending beyond the second sidewall; Equipped with An integrated circuit interconnect structure, wherein a width in the first direction of a portion of the third metal line that is not over the first metal line and the second metal line is greater than a width in the first direction of a portion of the third metal line that is over the first metal line or the second metal line.

2. 2. The integrated circuit interconnect structure of claim 1, wherein the conductive via is a first conductive via, and the integrated circuit interconnect structure further comprises a second conductive via between the second metal line and the third metal line, the second conductive via not extending beyond a first sidewall or a second sidewall of the second metal line.

3. 3. The integrated circuit interconnect structure of claim 2, wherein said first conductive via has a first lateral width in said second direction and said second conductive via has a second lateral width in said second direction, said first lateral width being substantially equal to said second lateral width.

4. 4. The integrated circuit interconnect structure of claim 3, wherein said first metal line has a third lateral width in said second direction and said second metal line has a fourth lateral width in said second direction, said third lateral width being substantially equal to said fourth lateral width, said first lateral width being substantially equal to said third lateral width, and said second lateral width being substantially equal to said fourth lateral width.

5. 4. The integrated circuit interconnect structure of claim 3, wherein said first lateral width decreases from a maximum value at an interface with said third metal line to a minimum value at an interface with said first metal line.

6. 5. The integrated circuit interconnect structure of claim 4, wherein said second lateral width decreases from a maximum value at an interface with said third metal line to a minimum value at an interface with said second metal line.

7. 7. The integrated circuit interconnect structure of claim 1, wherein the second metallization level further includes a fourth metal line extending in the second direction over a fifth metal line and a sixth metal line, the fifth metal line and the sixth metal line being in the first metallization level.

8. 8. The integrated circuit interconnect structure of claim 7, wherein the fifth metal line has a first sidewall and a second sidewall and extends a length in the first direction, and the sixth metal line has a first sidewall and a second sidewall and extends a length in the first direction.

9. 1. An integrated circuit interconnect structure comprising: a first metal line extending a length in a first direction and having a first sidewall and a second sidewall; a second metal line adjacent to the first metal line; a dielectric between the first metal line and the second metal line; a first metallization level including: a second metallization level above the first metallization level, the second metallization level including a third metal line extending in a second direction perpendicular to the first direction, the third metal line overlying the first metal line and the second metal line but not extending beyond the first sidewall; a conductive via between the first metal line and the third metal line, the conductive via not extending beyond the first sidewall and not extending beyond the second sidewall; Equipped with the second metallization level further includes a fourth metal line extending in the second direction over a fifth metal line and a sixth metal line, the fifth metal line and the sixth metal line being in the first metallization level; The fourth metal wire is a first portion having a first longitudinal thickness in a third direction perpendicular to the second direction and perpendicular to the first direction; a second portion having the first longitudinal thickness; a third portion between the first portion and the second portion, the third portion having a second longitudinal thickness greater than the first longitudinal thickness; the first portion overlies the fifth metal line and the second portion overlies the sixth metal line.

10. 10. The integrated circuit interconnect structure of claim 9, wherein said third portion does not extend over said fifth metal line or said sixth metal line.

11. 10. The integrated circuit interconnect structure of claim 9, wherein the fifth metal line and the sixth metal line are separated by a space in the second direction, and the third portion has a lateral width in the second direction, the lateral width having a center point directly above a midpoint between the spaces.

12. 10. The integrated circuit interconnect structure of claim 9, wherein said second vertical thickness is substantially equal to a vertical thickness of said third metal line along said second direction.

13. The dielectric is a first dielectric, 10. The integrated circuit interconnect structure of claim 1 or 9, further comprising a second dielectric between said first dielectric and said third metal line, said first dielectric and said second dielectric being in direct contact.

14. 1. A method for manufacturing an integrated circuit interconnect structure, comprising: forming a first metallization level and a second metal line extending a length in a first direction, the first metal line being separated from the second metal line by a first dielectric; selectively forming a stack of polymer structures over the first metal line and the second metal line, the stack of polymer structures including a second polymer structure over a first polymer structure; forming a second dielectric adjacent to the first polymer structure in a second direction perpendicular to the first direction, and a third dielectric adjacent to the second polymer structure in the second direction, the second dielectric and the third dielectric not extending over the first metal line or the second metal line; removing the stack of polymer structures from above the first metal line and the second metal line; forming a fourth dielectric over the first metal line and the second metal line adjacent the second dielectric; forming a sacrificial layer over the third dielectric and the fourth dielectric; planarizing the third dielectric and the sacrificial layer to remove the sacrificial layer over the third dielectric; etching the sacrificial layer to expose the fourth dielectric; forming a first sacrificial material over the fourth dielectric; forming a first mask over the third dielectric and the first sacrificial material, the first mask forming an opening; etching the first sacrificial material and the fourth dielectric beneath the opening to expose the first metal line and the second metal line; forming a second sacrificial material over the first metal line and the second metal line; forming a masking layer over the third dielectric and the second sacrificial material; forming a second mask over the masking layer; patterning the masking layer to expose selected portions of the third dielectric; etching the third dielectric to expose the second dielectric; etching the second sacrificial material to expose the first metal line and the second metal line; forming a conductive via in the exposed portion of the first metal line or the second metal line; forming a third metal line in a second metallization level above the conductive via and the second dielectric, the third metal line extending a length in the second direction; A method for providing the above.

15. 15. The method of claim 14, wherein the conductive vias include a first conductive via formed on the first metal line and a second conductive via formed on the second metal line.

16. 16. The method of claim 15, wherein the first conductive via is formed having sidewalls in the first direction that do not extend beyond sidewalls of the first metal line in the first direction, and the second conductive via is formed having sidewalls along the first direction that do not extend beyond sidewalls of the second metal line in the first direction.

17. 15. The method of claim 14, wherein forming the conductive via comprises depositing a liner layer over the first metal line or the second metal line and depositing a fill material over the liner layer.

18. 15. The method of claim 14, further comprising forming a fourth metal line in the second metallization level above a fifth metal line and a sixth metal line in the first metallization level.

19. 1. A system comprising: A processor; a wireless transceiver coupled to the processor, a drain contact coupled to the drain; a source contact coupled to the source; a gate contact coupled to the gate; a radio transceiver including a transistor including an integrated circuit interconnect structure coupled to the drain contact, a first metallization level including a first metal line extending a length in a first direction and having a first sidewall and a second sidewall; a second metallization level above the first metallization level, the second metallization level including a second metal line extending a length in the second direction above the first metal line but not beyond the first sidewall and the second sidewall in the second direction; an integrated circuit interconnect structure comprising: a conductive via between the first metal line and the second metal line, the conductive via not extending beyond the first sidewall and not extending beyond the second sidewall; Equipped with the second metallization level further includes a third metal line extending in the second direction over a fourth metal line and a fifth metal line, the fourth metal line and the fifth metal line being in the first metallization level; The third metal wire is a first portion having a first longitudinal thickness in a third direction perpendicular to the second direction and perpendicular to the first direction; a second portion having the first longitudinal thickness; a third portion between the first portion and the second portion, the third portion having a second longitudinal thickness greater than the first longitudinal thickness; the first portion overlies the fourth metal line and the second portion overlies the fifth metal line.

20. 20. The system of claim 19, further comprising a battery coupled to power at least one of the processor or memory.

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