Low stress dielectric layers, planarization methods, and low temperature processing for 3D integrated electrical devices

Abstract

The electrical device includes a substrate (12), a dielectric layer (16) supported by the substrate, and a conductive vertical interconnect (18) extending through the dielectric layer. The dielectric layer may be formed at a temperature lower than the thermal degradation temperature of a temperature sensitive material (14) in the device. The dielectric layer (16) may be a low stress layer that imparts no stress or a stress lower than the fracture stress of a brittle material in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at the step. The vertical interconnect (18) may be diffusion bondable to another opposing interconnect at a temperature lower than the thermal degradation temperature of a temperature sensitive material in the device. To facilitate 3D integration, the vertical interconnect (18) may have a coefficient of thermal expansion (CTE) higher than the CTE of the dielectric layer (16).

Description

[Technical field]

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices with low stress dielectric layers, planarization methods, and / or low temperature processing conditions, for example for use in low temperature 3D integration. [Background technology]

[0002] Electrical devices, such as semiconductor integrated circuits (ICs) or other semiconductor devices, are typically fabricated in and / or on a substrate, such as a silicon wafer, resulting in an IC area, the size and density of which generally increases with increasing IC complexity. One recent trend in IC manufacturing is to increase the number and / or different types of ICs by stacking ICs vertically on top of each other and interconnecting them vertically. Typically, each of the vertically stacked ICs may be of a different size, come from a different sized wafer, have a different function, be formed of a different material, etc.

[0003] Conventional methods for achieving the vertical stacking integration approach of ICs include through direct bonding or hybrid bonding processes. Typically, a desired number of individual ICs are vertically stacked, and then the stacked electrical device assembly is subjected to a temperature treatment that induces diffusion between the structure(s) of the opposing ICs, resulting in a 3D integrated electrical device structure with electrical connections across the stacked ICs. Summary of the Invention

[0004] One problem with some semiconductor devices, such as photodetectors, is that the use of such devices may require temperature-sensitive materials, making them susceptible to the processing conditions leading to and during 3D integration. As an example, photodetectors for sensing infrared light are made of Hg 1-x CDx In some cases, a temperature-sensitive photoconductor material such as Te (commonly referred to as "MCT") is used. The thermal degradation temperature of MCT, at which the properties of the material are adversely affected, is about 150°C.

[0005] Another problem with some electrical devices is that they may incorporate brittle materials within their architecture, e.g., materials with low fracture toughness, which, when subjected to tension, can cause damage and / or prevent the material from functioning properly. MCT is an example of a brittle material that is susceptible to damage (e.g., defects, crack propagation, and / or interfacial failure) and / or electrical interruption (e.g., piezoelectric response) when subjected to relatively small amounts of tensile strain.

[0006] To facilitate the fabrication of such electrical devices, it would be useful to apply a low stress dielectric layer at low temperature to prevent degradation of materials such as MCT within the electrical devices.

[0007] For example, a low stress dielectric layer may be applied to an electrical device at temperatures below about 150° C. to prevent degradation of the MCT.

[0008] The low stress dielectric layer may be configured to impart little to no stress to the vulnerable material(s) within the device, preventing their degradation.

[0009] For example, a low stress dielectric layer may impart stress, if any, that is less than the yield strength, ultimate tensile strength, or fracture strength of a brittle material. IC The fracture toughness was approximately 0.20 MPa m by Vickers indentation testing. 1 / 2 Thus, when MCT is used in an electrical device, for example, a low stress dielectric layer may impart a tensile stress to the MCT layer that may be less than the MCT tensile strength, if any. In an exemplary embodiment, for example, a low stress dielectric layer may have an intrinsic in-plane biaxial stress in the range of, for example, 0.0 MPa to 3.5 MPa.

[0010] Yet another issue with the fabrication of electrical devices such as photodetectors is that the deposition of materials such as MCT can result in potential total thickness variations that may require additional processing steps to remove or make 3D integration with other electrical devices more difficult.

[0011] Thus, during the manufacture of electrical devices, low stress dielectric layers may be deposited to provide dielectric planarization to compensate for potential overall thickness variations in the underlying layers of the device.

[0012] To enable 3D integration of electrical devices, one or more conductive vertical interconnect structures may be formed in individual via holes in the low stress dielectric layer. To facilitate 3D integration at low temperatures to avoid degradation of temperature sensitive materials such as MCT, the vertical interconnect(s) may be configured to be diffusion bondable to other opposing interconnects at low temperatures. Additionally, the vertical interconnect(s) may be configured to cooperate with the low stress dielectric layer to enable such diffusion bonding between the interconnect structures.

[0013] According to one embodiment, an electrical device includes a substrate, a low stress dielectric layer supported by the substrate, the low stress dielectric layer having at least one via hole, and a conductive vertical interconnect disposed within the via hole, the conductive vertical interconnect being diffusion bondable to another opposing interconnect at a temperature of 150° C. or less, the conductive vertical interconnect having a thermal expansion coefficient higher than a thermal expansion coefficient of the low stress dielectric layer.

[0014] According to another aspect, a method of manufacturing an electrical device includes forming a dielectric layer covering at least a portion of a substrate, forming a via hole in the dielectric layer, and forming a conductive vertical interconnect in the via hole, wherein when forming the dielectric layer, the electrical device includes a temperature-sensitive material having a thermal degradation temperature in the range of 100°C to 200°C, and forming the dielectric layer is performed at a temperature below the thermal degradation temperature of the temperature-sensitive material.

[0015] According to another aspect, a method of manufacturing an electrical device includes depositing a photoconductive material layer over at least a portion of a substrate, and depositing a dielectric material to planarize a top surface of the electrical device to compensate for potential overall thickness variations in the photoconductive material layer.

[0016] The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings. [Brief description of the drawings]

[0017] The accompanying drawings illustrate various aspects of the present invention.

[0018] [Figure 1A] 4 is a flowchart illustrating at least a portion of an example method for manufacturing an example electrical device according to an embodiment. [Figure 1B] FIG. 1B is a flow chart following the method in FIG. 1A and also showing exemplary steps of 3D integration of electrical devices. [Figure 2A] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to an embodiment. [Figure 2B] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to an embodiment. [Figure 2C]1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to an embodiment. [Figure 2D] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to an embodiment. [Figure 2E] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to an embodiment. [Figure 2F] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to an embodiment. [Figure 2G] 1A-1D are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device according to an embodiment. [Figure 3A] 2H is a schematic cross-sectional view illustrating an exemplary process of 3D integration of the exemplary electrical device in FIG. 2G with another exemplary electrical device. [Figure 3B] 2H is a schematic cross-sectional view illustrating an exemplary process of 3D integration of the exemplary electrical device in FIG. 2G with another exemplary electrical device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The principles and aspects of the present disclosure have particular application to electrical devices such as integrated circuit (IC) devices, and more particularly to vertically integrated semiconductor integrated circuit (IC) devices (e.g., application specific integrated circuits (ASICs), focal plane arrays and intelligent image sensors, memory chips, monolithic microwave integrated circuits (MMICs), infrared electrical devices (e.g., infrared detectors), antenna circuits, striplines, electrical distribution networks, etc.), and will be described below primarily in this context. However, it will be appreciated that the principles and aspects of the present disclosure may also be applied to other electrical devices or circuits generally, where it is desirable to provide an aluminum nitride tensile layer to balance forces and thereby control the amount of curvature in such devices. Non-limiting examples of such electrical devices may include non-semiconductor devices, such as passive radio frequency (RF) circuits (e.g., filters or antenna arrays), or other semiconductor devices, such as diodes, photocells, transistors, sensors, etc. The exemplary methods of forming the exemplary electrical devices may also be applicable to vertically integrating both active and passive electrical devices.

[0020] As previously mentioned, a problem with some conventional electrical devices is that temperature sensitive materials within the device may be susceptible to processing conditions at elevated temperatures. Another problem with some conventional electrical devices is that they may incorporate weak materials within their architecture, where excessive forces applied to the weak materials may cause damage and / or prevent the material from operating properly. Yet another problem associated with some conventional electrical devices is that the deposition of some materials within the device may result in potential total thickness variations that may require additional process steps to remove or may make 3D integration with other electrical devices more difficult.

[0021] One particular type of electrical device that experiences one or more of the aforementioned problems is one that uses MCT (Hg 1-x CD xMCT is a temperature-sensitive material with a thermal degradation temperature of approximately 150°C. MCT is also an example of a brittle material that is susceptible to damage (e.g., defects, crack propagation, and / or interfacial failure) and / or electrical interruption (e.g., piezoelectric response) when subjected to relatively small amounts of tensile strain. For example, the K IC The fracture toughness was approximately 0.20 MPa m by Vickers indentation testing. 1 / 2 In addition, the deposited MCT is subject to potential total thickness variations that may need to be taken into account during manufacturing to obtain suitability for, for example, 3D integration.

[0022] Thus, an exemplary electrical device is described herein that solves one or more of the aforementioned problems associated with conventional electrical device designs, and more particularly, one or more problems associated with photodetectors that utilize MCT. In an exemplary embodiment, the insulating dielectric layer of the device is deposited at a temperature less than about 150° C. to prevent degradation of temperature sensitive materials such as MCT. Alternatively or additionally, in an exemplary embodiment, a dielectric material is applied to provide a low stress layer that imparts little to no stress to a weak material(s) in the device such as MCT. Alternatively or additionally, in an exemplary embodiment, a dielectric layer is applied during fabrication to provide dielectric planarization to compensate for potential overall thickness variations in underlying layers of the device such as the MCT photoconductor layer.

[0023] The exemplary electrical devices described herein may be particularly suitable for 3D integration with other electrical devices, such as, for example, read-out integrated circuits (ROICs). Thus, to enable such 3D integration, the exemplary electrical devices include one or more conductive vertical interconnect structures at least partially surrounded by an exemplary dielectric layer. In exemplary embodiments, to facilitate 3D integration at low temperatures to avoid degradation of temperature-sensitive materials such as MCT, the vertical interconnect(s) may be configured to be diffusion bondable to other opposing interconnects at low temperatures, such as temperatures below the degradation temperature of MCT. Alternatively or additionally, in exemplary embodiments, the vertical interconnect(s) are configured to enable such diffusion bonding between the interconnect structures, such as by cooperating with a low-stress dielectric layer to provide a thermal expansion coefficient of the interconnect(s) greater than the thermal expansion coefficient of the exemplary dielectric material.

[0024] FIG 1A illustrates an exemplary method 100 for forming an exemplary electrical device, such as a photodetector semiconductor device, according to an embodiment. As illustrated, FIG 1A generally includes providing a substrate for the electrical device (step 112) and forming a dielectric layer at least partially covering the substrate (step 114). The forming step 114 may include one or more of the following: (i) forming the dielectric layer at a low temperature, such as a temperature below a degradation temperature of one or more temperature-sensitive materials in the electrical device (step 114a); (ii) forming the dielectric layer to provide a low stress state (step 114b), e.g., no stress or a stress less than the fracture stress (e.g., ultimate tensile strength, fracture strength, yield strength) of one or more brittle materials in the electrical device; and / or (iii) forming the dielectric layer to provide planarization of the electrical device (step 114c), e.g., mitigating or eliminating potential total thickness variations in one or more layers underlying the dielectric layer of the device.

[0025] FIG. 1B is a continuation of the method 100 shown in FIG. 1A according to an embodiment. As shown, FIG. 1B generally includes forming at least one conductive vertical interconnect in a via hole of a dielectric layer (step 116). The forming step 116 may include one or more of the following: (i) forming the vertical interconnect(s) having a thermal expansion coefficient greater than the thermal expansion coefficient of the dielectric layer (step 116a); (ii) forming the vertical interconnect(s) that are diffusion bondable with other opposing interconnects at low temperatures (step 116b). As shown, the exemplary method 100 may continue with preparing the electrical device (first electrical device) for 3D integration with another electrical device (second electrical device). As also shown in FIG. 2, following the method for manufacturing the first exemplary electrical device, an exemplary embodiment may provide a method 200 including a step 210 of bonding the first and second electrical devices together to provide a 3D integrated electrical device.

[0026] 2A-2G are schematic cross-sectional views illustrating exemplary process steps for forming an exemplary electrical device 10 according to method 100. In the illustrated embodiment, the semiconductor device 10 is a photodetector 10 that generally includes a substrate 12, a photoconductor layer 14 supported by the substrate 12, an exemplary low stress dielectric layer 16 covering at least a portion (e.g., a major surface) of the substrate 12, and one or more conductive vertical interconnects 18 in individual via holes in the low stress dielectric layer 16. It should be appreciated that the depiction of the photoconductor 10 is exemplary and that any suitable form of electrical device may be used in accordance with the principles and aspects disclosed herein.

[0027] 2A and step 112 of FIG. 1A, the step of providing a substrate 12 includes providing any suitable substrate for the electrical device 10 that may be required for a particular application. In the illustrated embodiment, the substrate 12, which supports the dielectric layer 16 and the interconnect 18, includes a lower substrate layer 13, which supports the other layers, and a photoconductor layer 14. In the exemplary embodiment, the photoconductor layer 14 is a mercury cadmium telluride (Hg 1-xCD x The lower substrate layer 13 may be any suitable substrate configured to support the other layers, such as, for example, a silicon substrate.

[0028] The layers below the dielectric layer 16 (combined and generally referred to herein simply as substrate 12) may include additional layers (not shown) depending on the type of electrical device and manufacturing method. For example, one or more buffer layers may be provided between the photoconductor layer 14 (e.g., MCT) and the lower substrate layer 13 (e.g., silicon). The buffer layers may include cadmium and tellurium and may improve the interfacial bonding of the MCT photoconductor layer 14 described above. In addition, one or more passivation layers may be formed on the photoconductor layer 14. The passivation layers may include cadmium and tellurium and may improve the interfacial bonding between the MCT photoconductor layer 14 and the adjacent dielectric layer 16.

[0029] 2A, a cap layer 20 may be formed overlying the photoconductor layer 14. In an exemplary embodiment, the cap layer 20 is formed of CdTe, but may also be formed of SiN x or other suitable passivation layer. As shown, an opening 21 is formed at least through the cap layer 18 to expose the underlying photoconductor layer 14. An implant 22 is then formed in the photoconductor layer 14. The implant 22 provides a p-n junction with the photoconductor layer 14 to enable the photoelectric effect. For example, if the photoconductor layer 14 is an n-type material, the implant 22 is formed of a p-type material to form a p-n junction. Alternatively, if the photoconductor layer 14 is a p-type semiconductor, the implant 22 is an n-type implant. Thus, in the exemplary photodetector 10, incident IR photons can pass through the lower substrate layer 13 (e.g., through a window) and interact with the p-n junction in the photoconductor layer 14 to generate a photocurrent that is transmitted through the interconnect 18.

[0030] 2B, electrical contact pads 24 are formed in openings 21 above implants 22 to transfer electrons generated at the pn junctions in photoconductor layer 14 to interconnect 18. Contact pads 24 may be formed using any suitable technique, including deposition and patterning. As shown, conductive pads 24 may be formed to protrude above the top surface of cap layer 20. Contact pads 24 may be formed of any suitable conductive material or combination of materials, including conductive metals. In an exemplary embodiment, contact pads 24 may include a metal layer 24a (e.g., aluminum) and a barrier layer 24b (e.g., TiW) underlying metal layer 24a to prevent interdiffusion with photoconductor layer 14.

[0031] With reference to FIG. 2C and step 114 of FIG. 1A, an exemplary dielectric layer 16 is formed over at least a portion of the substrate 12. The dielectric layer 16 may be formed of any suitable material via any suitable technique as may be required for the application. As shown, the dielectric layer 16 is applied over at least the electrical contact pads 24 that protrude above the cap layer 20. In the illustrated embodiment, the dielectric layer 16 covers the entire lateral extent of the photoconductor layer 14 and surrounds the peripheral edge of the photoconductor layer 14. More specifically, the dielectric layer 16 may extend to the peripheral edge of the electrical device 10. The dielectric layer 16 may be of any suitable thickness that provides the desired functionality, such as electrical insulation, rigidity / support, etc. In the illustrated embodiment, for example, the thickness of the dielectric layer may range from 2 micrometers (microns) to 4 microns.

[0032] As discussed above and shown in step 114a of FIG. 1A, the dielectric layer 16 may be formed on the electrical device 10 using a low temperature process that is below the thermal degradation temperature of any temperature sensitive materials contained within the device 10. For example, the thermal degradation temperature of the temperature sensitive MCT material in the photoconductor layer 14 is about 150° C., and thus the dielectric layer 16 is formed at a temperature below 150° C., such as in the range of about 25° C. to about 150° C. (e.g., 25° C., 50° C., 75° C., 85° C., 90° C., 100° C., 125° C., 140° C., or 150° C., including all ranges and subranges therebetween). The low temperature process for forming the dielectric layer may include a suitable deposition process, such as physical vapor deposition (e.g., PVD reactive sputtering). Instead of or in addition to MCT, other temperature-sensitive materials having different thermal degradation temperatures may be included in device 10 prior to forming dielectric layer 16, and thus the process temperature of dielectric layer 16 preferably remains below the lowest degradation temperature of any such temperature-sensitive materials.

[0033] As also discussed above and illustrated in step 114b of FIG. 1A, the dielectric layer 16 may be formed on the device 10 as a low stress layer. In particular, the dielectric layer 16 may be tailored, via its processing parameters, to provide a structure having a low intrinsic stress, such as low tensile or compressive stress in the layer 16. In an exemplary embodiment, the low stress layer has an intrinsic in-plane biaxial stress (if any) configured to impart little to no stress to and prevent damage to the brittle material(s) in the device. For example, the MCT material of the photoconductor layer 14 has a resistivity of about 0.20 MPa·m 1 / 2 K IC It is a brittle material with low fracture toughness and is therefore susceptible to damage, especially when subjected to tension. Thus, to mitigate adverse effects on the MCT material during fabrication or operation of device 10, dielectric layer 16 may be configured to have an intrinsic stress value that imparts a stress (force) less than the fracture stress value of the MCT layer.

[0034] Instead of or in addition to MCT, other brittle materials may be included in device 10 during fabrication or operation, and thus the intrinsic stress value of dielectric layer 16, which imparts stress (force) to the brittle material(s), is preferably lower than the lowest fracture stress value of any such material. One way to determine the maximum in-plane biaxial stress value of dielectric material 16 is to determine when the in-plane stress exceeds the threading dislocation glide force at which the dislocation glides and rearranges to the lowest strain energy. By way of example and without limitation, at room temperature (25°C), a (111) oriented material on a 60° mixed Burgers vector would form at approximately 0.5 MPa (compression or tension). When threading dislocations form, slip leaves misfit lines in the base that may increase noise if in the active region. Formation of threading dislocations with the same orientation and defect type occurs at approximately 3 MPa for a 7 μm thick material. If the material already had dislocations, when the in-plane stress relaxes to the lowest stress energy configuration, dislocations then form after an additional 3 MPa in-plane stress. Using such method as an example, one skilled in the art can determine that the maximum in-plane biaxial stress of the dielectric layer 16 should not exceed 3.5 MPa. Thus, a low stress dielectric layer 16 can have an inherent in-plane biaxial stress in the range of, for example, 0.0 MPa to 3.5 MPa.

[0035] With further reference to FIG. 2C, and also with reference to step 114c of FIG. 1A, the dielectric layer 16 may be applied to the electrical device 10 to provide planarization that compensates for potential total thickness variations in the portion of the device underlying the dielectric layer 16. Generally, such planarization involves increasing the flatness or planarity of the surface of the electrical device 10. For example, the lower substrate 13 (e.g., a silicon substrate) may be relatively flat or planar, but as the device 10 undergoes various manufacturing steps, layers of different materials, shapes, and depths are deposited by different growth or deposition techniques, leading to a decrease in the flatness or planarity of the device surface. For example, MCT is a relatively soft material (e.g., Mohs hardness of about 4.0). Thus, in an exemplary embodiment, the dielectric layer 16 is formed to provide planarization that reduces or eliminates potential total thickness variations in the device 10 to that point. To facilitate such planarization, a dielectric layer 16 may be applied in the step shown in FIG. 2C to a suitable thickness that covers all structures within device 10 at that time, thus providing a planarized or flat upper surface of dielectric layer 16.

[0036] One exemplary type of material for the dielectric layer 16 that achieves each of the aforementioned functions of (i) low stress, (ii) low processing temperature, and (iii) enhanced planarization is aluminum nitride (AlN x , also referred to herein simply as AlN). Another exemplary type of material for the dielectric layer 16 that accomplishes each of the same functions is silicon nitride (SiN x, also referred to herein simply as SiN). As will be appreciated by those skilled in the art, the specific processing conditions under which AlN or SiN is formed can affect its microstructure and characteristic properties, such as low intrinsic stress. In an exemplary embodiment, AlN or SiN can be formed during a low temperature (e.g., less than 150° C.) sputtering process (such as reactive sputtering) to form a material with increased polycrystallinity in its microstructure. Of course, other suitable dielectric materials (or combinations of materials) formed by one or more other suitable techniques may be utilized in dielectric layer 16, depending on the desired properties in the electrical device and its cooperation with other materials in device 10.

[0037] 2D, after forming the dielectric layer 16, one or more via holes 26 are formed in the dielectric layer 16 to correspond to the locations of the contact pads 24. The formation of the via holes 26 may be performed by any suitable technique, such as patterning and etching. As shown, after the formation of the via holes 26, the dielectric layer 16 is still at a height above the upper surfaces of the contact pads 24.

[0038] 2E illustrates the deposition of a base layer 28. In the illustrated embodiment, the base layer 28 covers the top and each side of the via holes in the dielectric layer 16 and covers each top surface of the electrical contact pads 24. The base layer 28 may be formed of a suitable metal that facilitates electrochemical plating of the material that will form the vertical interconnects 18 (shown in FIG. 2F and described below). In the illustrated embodiment, for example, the base layer 28 is formed of tin (Sn) and is deposited by a PVD process.

[0039] 2F and step 116 of FIG. 1B, a material forming the vertical interconnect 18 is applied to the electrical device 10. The interconnect material may be any suitable conductive material formed by any suitable processing technique. In the illustrated embodiment, the interconnect material is formed as a conductive layer 30 deposited via an electrochemical plating process over the top surface of the device 10. The plating process may provide a relatively thick layer at a relatively low temperature in a relatively short time. As shown, the thickness of the conductive layer 30 is such that the remainder of the via hole 26 is filled with the interconnect material (shown at 30a) and an overburden area 30b is formed outside the via hole 26. While plating may be one suitable technique, it should be understood that the method of forming the interconnect 18 may be any suitable deposition process, such as evaporation, sputtering, or a chemical vapor process (e.g., e-beam, PVD, or CVD). In such an alternative process, the base layer 28 (e.g., tin layer) may not be required. Generally, the processing steps to form conductive layer 30 may be performed at temperatures below the thermal degradation temperatures of any temperature-sensitive materials in device 10 .

[0040] As previously discussed and shown in step 116a of Figure 1B, the material forming the interconnect 18 may have a coefficient of thermal expansion (CTE) greater than the coefficient of thermal expansion (CTE) of the dielectric layer 16. This may allow the fully formed interconnect structure 18 (shown in Figure 2G) to facilitate 3D integration with other electrical devices 50 (shown in Figure 3A). This is done by forming compressive stresses at the interfaces between the interconnects 18, 52 in each device 10, 50 during the elevated temperature bonding step due to the CTE mismatch between the interconnect 18 and the surrounding dielectric layer 16.

[0041] As also discussed above and shown in step 116b of FIG. 1B, the material forming the interconnect 18 of the electrical device 10 may be diffusion bondable with the counter interconnect 52 of the second device 50 at a temperature below the thermal degradation temperature of the temperature-sensitive material in the electrical device 10. As discussed above, the thermal degradation temperature of the temperature-sensitive MCT material in the photoconductor layer 14 is about 150° C., and therefore the interconnects 18, 52 may be diffusion bondable at a temperature below about 150° C. In place of or in addition to MCT, other temperature-sensitive materials having different thermal degradation temperatures may be included in the device 10, and thus the diffusion bonding temperature of the interconnect material may be about the same as or lower than the lowest degradation temperature of any such temperature-sensitive material.

[0042] One exemplary type of material for interconnect 18 formed as conductive layer 30 in Figure 2F and satisfying each of the aforementioned functions of (i) being electrically conductive, (ii) having a CTE greater than that of dielectric layer 16, and (ii) being diffusion bondable at a temperature below the degradation temperature of a temperature sensitive material such as MCT, is indium (In), although it will be understood that other suitable materials may be used depending on the desired properties and cooperation with other materials in device 10.

[0043] 2G and step 118 of FIG. 1B, steps are shown to prepare the electrical device for 3D integration with other electrical devices. This process may include chemical mechanical polishing (CMP) to remove overlays 30b of the conductive layer from the previous step, along with overlays of the plating base layer 28, if applicable. As shown, this results in a conductive material (e.g., indium) being disposed within the via holes in the dielectric layer 16 to form the individual vertical interconnect structures 18. In the exemplary embodiment, the individual vertical interconnects 18 are surrounded by the dielectric layer 16 over most of their axial extent, and more particularly, over their entirety. The dielectric layer 16 also surrounds most of the electrical contact pads 24. The CMP process also results in a substantially planar top surface of the electrical device 10, with the top surfaces of the individual interconnects 18 being in the same horizontal plane as the top surface of the dielectric layer 16, although some dishing of the interconnects 18 may be present due to the CMP process.

[0044] In an exemplary embodiment, preparing the electrical device 10 for 3D integration may also include applying a bonding layer on top of the dielectric layer 16. In the illustrated embodiment, the bonding layer is shown at position 32. The bonding layer may be a conformal dielectric film. The bonding layer provides an interfacial bond with an opposing bonding layer (shown at position 54) of the second electrical device 50. The bonding may include ambient room temperature bonding via van der Waals forces between the bonding layers, which may be further enhanced by covalent fusion bonding at elevated temperatures. The bonding layer may be a non-metallic material, such as an oxide, more particularly silicon oxide (SiO x ), for example, silicon dioxide (e.g., fused silica or SiO 2 The bonding layer may be formed at any suitable step in method 100 by any suitable technique, such as a deposition process including physical vapor deposition, reactive physical vapor deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, sputtering, or a spin-on glass process.

[0045] 3A and method 200 of FIG. 1B illustrate the initiation of 3D integration of a first electrical device 10 (e.g., a photodetector 10) with a second electrical device 50. In the illustrated embodiment, the second electrical device 50 is a readout integrated circuit (ROIC), which may have some of the same or similar features as the first electrical device 10, including, for example, a substrate 56, a dielectric layer 58 supported by the substrate 56, and one or more conductive vertical interconnects 52 corresponding to the interconnects 18 in the first electrical device 10. The substrate 56 may include the ROIC circuitry and electrical contacts for receiving electrons from the photodetector 10 via the interconnect structures 18, 52. The dielectric layer 58 may be the same as the dielectric layer 16, including being formed at low temperature, having low stress (low intrinsic stress value), and / or providing planarization during processing of the ROIC 50. Additionally, the interconnects 52 may be the same as the interconnects 18 to provide compatibility for diffusion bonding together. Thus, the interconnect 52 can have a larger CTE than the dielectric layer 58 to facilitate 3D integration, and the material of the interconnect 52 can be diffusion bondable even at low temperatures. As previously mentioned, a bonding layer (shown at position 54) may be applied to the second electrical device 50, which may be the same as the bonding layer (shown at position 32) of the first electrical device 10 to provide a compatible bond.

[0046] 3A, the 3D integration process includes contacting a first electrical device 10 (e.g., a photodetector) with a second electrical device 50 (e.g., a ROIC), which may be performed at standard ambient temperature (i.e., 25° C. according to the IUPAC standard). During this step, a bonding layer (e.g., SiO xInitial bonding may occur by contacting the exposed interfaces of the interconnects 18 and 52 with each other to form van der Waals bonds. In this step, the respective interconnects 18 and 52 may be aligned and contacted with each other. Due to the CMP process, the respective interconnects 18, 52 may have some dishing and therefore small gaps may exist between the interconnects 18 and 52.

[0047] 3B and with reference to step 210 of FIG. 1B, 3D integration of a first device 10 and a second device 50 is shown by thermally bonding the devices 10, 50 together to form a 3D integrated electrical device 70. As previously mentioned, due to the CTE mismatch of the interconnects 18, 52 to their respective surrounding dielectric layers 16, 58, during the thermal process, the interconnects 18, 52 expand more than their respective surrounding dielectric layers 16, 58 to make compressive contact at the interface (indicated by dashed line 80) of the respective interconnects 18, 52. This compressive contact allows for closing of gaps between the interconnects 18, 52 that may have been caused by dishing. During the thermal process, the respective bonding layers (e.g., SiO x ) are covalently bonded together and the interconnects 18, 52 fuse together into respective single integrated conductive posts 60 that extend through the integrated bonding layer.

[0048] As previously mentioned, the interconnects 18, 52 are preferably formed of materials that allow diffusion bonding at temperatures approximately equal to or lower than the thermal degradation temperature of the temperature-sensitive material(s) in the device 10. For example, the thermal degradation temperature of MCT is approximately 150° C., and indium can be diffusion bonded to itself at approximately 150° C. For example, in an exemplary embodiment using MCT, diffusion bonding of the interconnect structures 18, 52 occurs at temperatures ranging from 140° C. to less than 150° C., but may be at higher temperatures after the AlN layer is deposited by its encapsulation of the MCT. However, it is understood that there may be some overlap in the thermal degradation temperature and the diffusion bonding temperature that does not significantly affect the function of either the temperature-sensitive material (e.g., MCT) or the interconnect (e.g., In). For example, elevated temperature bonding may be performed at a temperature of approximately 160° C. without significantly degrading the MCT.

[0049] Although exemplary formations of the exemplary electrical device 10 and / or 3D integrated electrical device 70 have been described above, it should be appreciated that alternative configurations may be used in accordance with the principles and aspects described herein.

[0050] For example, while reference is made primarily to MCT as the brittle material, it will be appreciated that other brittle materials may be used in other areas within the electrical device, in which case it may be desirable to provide a low stress dielectric layer 16 that imparts little to no stress to the brittle material(s). Generally, the inherent in-plane biaxial stress level of a low stress layer may range from about -10.0 MPa to about +10.0 MPa. The acceptable level of stress for a low stress dielectric layer may be related to the amount of stress (force) that the dielectric layer imparts to the brittle material(s). Thus, as used herein, the term "low stress" is meant to refer to a stress value that imparts a stress (force) that is less than the fracture stress value of the brittle material. Generally, a "brittle material" refers to a material that is less than the fracture stress value of the brittle material, such as K IC Fracture toughness of 1MPa m 1 / 2A material having an intrinsic stress value less than 1000 . The term "fracture stress value," as used herein, generally refers to the "strength" of a material, which may include yield strength, ultimate strength, fracture strength, fracture toughness, etc., at which the underlying functionality of the material (e.g., mechanical and / or electrical properties) is significantly degraded or fails. As previously discussed, at least one method of determining the intrinsic stress value of dielectric material 16 is to determine when the in-plane stress of the material exceeds the threading dislocation glide force.

[0051] Also, while reference is made primarily to MCT as the temperature sensitive material, it should be understood that other temperature sensitive materials may be used in other regions within the electrical device, in which case it may be desirable to provide a dielectric layer 16 that can be formed at a low temperature. Generally, low temperature formation of the dielectric layer 16 may occur at temperatures ranging from about 75°C to about 150°C, more particularly 90°C to 125°C, and more particularly about 100°C. The acceptable temperatures for processing the dielectric layer 16 may be related to the thermal degradation temperature of the temperature sensitive material(s). Thus, as used herein, the term "low temperature" refers to a temperature value that is approximately equal to or less than the thermal degradation temperature of the temperature sensitive material. As used herein, the term "thermal degradation temperature" refers to the temperature at which the action of heat on a material results in loss of properties, such as physical, mechanical, and electrical properties. Such loss of properties due to thermal degradation may be manifested by changes in microstructure or composition, time-dependent deformation and resulting damage accumulation, effects of environmental attack and accelerated reactions with the environment at elevated temperatures, and the like. For example, thermal degradation temperatures may include the temperature at which pyrolysis occurs, where a substance chemically decomposes (breaks chemical bonds) into one or more constituent components, and may include the melting temperature, glass transition temperature, eutectic formation temperature, boiling / volatilization temperature, etc. for such materials.

[0052] By way of non-limiting example, some exemplary temperature sensitive materials for use in electrical devices and their thermal degradation temperatures include lead tin (PbSn), which has a eutectic melting temperature of 183° C., bismuth lead tin (BiPbSn), which has a melting temperature of about 95° C., bismuth tin (BiSn), which has a eutectic melting temperature of about 138° C., indium tin (52% In:48% Sn), which has a melting temperature of about 118° C., indium (In), which has a melting point of about 155° C., tin (Sn), which has a melting point of about 230° C., rubidium (Rb), which has a melting point of about 40° C., cadmium telluride (CdTe) or cadmium zinc telluride (CdZnTe), which has a thermal degradation temperature of about 180° C., cadmium mercury telluride (Hg), which has a thermal degradation temperature of about 150° C., and cadmium tin (CdTe), which has a melting temperature of about 150° C. 1-x CD x Te). Thus, the thermal degradation temperature of the temperature sensitive material according to the present disclosure may range from 50° C. to 250° C. As mentioned above, it may be useful if each processing step performed on an electrical device that includes a temperature sensitive material at that step is kept at about equal to or below the thermal degradation temperature of the temperature sensitive material.

[0053] Described herein is an exemplary electrical device including a substrate, a dielectric layer supported by the substrate, and an electrically conductive vertical interconnect extending through the dielectric layer. The dielectric layer may be formed at a low temperature below the thermal degradation temperature of temperature sensitive materials in the device. The dielectric layer may be a low stress layer that imparts no stress or a stress less than the fracture stress of brittle materials in the device. The dielectric layer may be formed during a processing step to planarize the electrical device at that step. The vertical interconnect may be diffusion bondable with other opposing interconnects at a low temperature below the thermal degradation temperature of temperature sensitive materials in the device. The vertical interconnect may have a coefficient of thermal expansion (CTE) higher than that of the dielectric layer to facilitate 3D integration.

[0054] According to more specific embodiment(s), the electrical device is a photodetector that provides a low-temperature dielectric layer that is low stress, has low fixed charge, and adheres well to the MCT layer (or a passivation layer thereon) that is deposited prior to bonding the dielectric layer. The oxide-oxide bond can then be adapted to the ROIC bonding layer. The dielectric layer is low stress and is made of MCT and SiO x The bonding layer may be an AlN or SiN dielectric that bonds effectively to both. The electrical device architecture has a flat surface topology, allowing the photodetector array to be bonded adjacent to the ROIC. Metal through-via interconnects in the ROIC layer bond to the photodetectors by heating the composite structure at a temperature less than 150°C. Due to the high thermal expansion coefficient of the metal interconnect compared to the surrounding dielectric, the metal extends into the opposing metal interconnect to form a seamless, integrated electrical interconnect structure.

[0055] It is to be understood that all range and ratio limits disclosed in the specification and claims may be combined in any manner, including all values, ranges and subranges between the stated values. The term "about" as used herein refers to any value within a range defined by up to ±10% variation of the stated value, for example, ±10%, ±9%, ±8%, ±7%, ±6%, ±5%, ±4%, ±3%, ±2%, ±1%, ±0.01%, or ±0.0% of the stated value, as well as intervening values ​​of such stated values.

[0056] As used herein, position or orientation terms such as "upper", "lower", "top", "bottom", "left", "right", "horizontal", "vertical", etc., are with reference to the exemplary electrical devices when viewed in a horizontal position, e.g., as shown in Figure 2H. This is done with the recognition that these devices may be oriented in a variety of other positions when manufactured, when mounted within other electrical devices, when packaged, etc.

[0057] As used herein, the terms "disposed on," "disposed onto," "disposed on," "underlying," "covering," and the like refer to direct or indirect contact of one element with another element, while the terms "directly on" or "directly onto" refer to direct contact of one element with another element, but not indirect contact between the elements.

[0058] It should be understood that references to "a," "an," and / or "the" may include one or more, and references to a singular item may include the plural, unless otherwise indicated. The term "and / or" should be understood to mean "either or both" of the elements so joined, i.e., elements that are conjunctive in some cases and disjunctive in other cases. Unless clearly indicated to the contrary, other elements may optionally be present other than the elements specifically identified by the "and / or" clause, whether associated or unassociated with the elements specifically identified. Thus, as a non-limiting example, a reference to "A and / or B," when used in conjunction with open-ended language such as "comprising," may refer in one embodiment to A without B (optionally including elements other than B), in another embodiment to B without A (optionally including elements other than A), and in yet other embodiments to both A and B (optionally including other elements), etc.

[0059] The term "or" should be understood to have the same meaning as "and / or" as defined above. For example, when separating items in a list, "or" or "and / or" shall be interpreted as inclusive, i.e., including at least one, but also including more than one, and optionally including additional non-list items, of a number or list of elements. Only terms clearly indicating the contrary, such as "only one of" or "exactly one of," may refer to the inclusion of exactly one element of a number or list of elements. In general, the term "or," as used herein, shall only be interpreted as indicating exclusive alternatives (i.e., "one or the other, but not both") when preceded by terms of exclusivity, such as "either," "one of," "only one of," or "exactly one of."

[0060] Transitional terms or phrases such as "comprising," "including," "carrying," "having," "including," "involving," "holding," "formed from," and the like, should be understood to be open-ended, i.e., meaning inclusive but not limited, unless otherwise specified.

[0061] Although the present invention has been shown and described with respect to a specific preferred embodiment or embodiments, it will be apparent that equivalent changes and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. In particular, with respect to the various functions performed by the aforementioned elements (components, assemblies, devices, compositions, etc.), the terms used to describe such elements (including references to "means") are intended, unless otherwise indicated, to correspond to any element that performs the specified function of the described element (i.e., is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs that function in the exemplary embodiment or embodiments of the present invention illustrated herein. In addition, although certain features of the present invention have been described above only with respect to one or more of some illustrated embodiments, such features may be combined with one or more other features of other embodiments, as may be desirable and advantageous for any given or particular application.

Claims

1. 1. An electrical device comprising: A substrate; a brittle material supported by the substrate and having a K IC fracture toughness of less than 1.0 MPa·m 1 / 2 ; a dielectric layer deposited on the fragile material, the dielectric layer having a via hole; a conductive vertical interconnect disposed within the via hole; any stress imparted to the brittle material by the dielectric layer is less than the fracture stress of the brittle material; the conductive vertical interconnect is diffusion bondable to another opposing interconnect at a temperature of 150° C. or less; the conductive vertical interconnect has a coefficient of thermal expansion greater than a coefficient of thermal expansion of the dielectric layer; Electrical devices.

2. The electrical device of claim 1, wherein the dielectric layer is depositable at a temperature in the range of 25°C to 150°C.

3. 10. The electrical device of claim 1, wherein the dielectric layer has an intrinsic biaxial stress in the range of 0.0 MPa to 3.5 MPa during fabrication and operation of the electrical device.

4. The electrical device of claim 1 , wherein the dielectric layer surrounds a majority of the axial extent of the vertical interconnect.

5. The dielectric layer is made of aluminum nitride (AlN ｘ 2. The electrical device of claim 1 .

6. The dielectric layer is silicon nitride (SiN ｘ 2. The electrical device of claim 1 .

7. The electrical device of claim 1 , wherein the vertical interconnect is formed of indium.

8. An electrical device as described in any preceding claim, wherein the brittle material has a thermal degradation temperature in the range of 100°C to 250°C.

9. The brittle material is Hg, which has a thermal degradation temperature of 150° C. １－ｘ Cd ｘ 8. The electrical device of claim 1, wherein the metal is Te.

10. The electrical device of claim 9, wherein the brittle material constitutes a photoconductor layer.

11. The electrical device of claim 10 , wherein the electrical device is a photodetector.

12. A first electrical device, which is the electrical device of claim 11; a second electrical device that is a readout integrated circuit; the first electrical device is bonded to and electrically integrated with the second electrical device; 3D integrated electrical devices.

13. 1. A method of manufacturing an electrical device, comprising: forming a dielectric layer overlying at least a portion of a substrate; forming a via hole in the dielectric layer; forming a conductive vertical interconnect in the via hole; when forming the dielectric layer, the electrical device comprises a temperature sensitive material having a thermal degradation temperature in the range of 100° C. to 200° C.; forming the dielectric layer at a temperature equal to or less than the thermal degradation temperature of the temperature sensitive material; method.

14. The temperature sensitive material has a resistance of 1.0 MPa m １／２ Less than K ＩＣ It is a brittle material with fracture toughness, the dielectric layer exerts a stress on the brittle material that is less than the fracture stress of the brittle material; The method of claim 13.

15. The method of claim 13 , wherein the conductive vertical interconnect has a coefficient of thermal expansion greater than a coefficient of thermal expansion of the dielectric layer.

16. 14. The method of claim 13, wherein the electrically conductive vertical interconnect is diffusion bondable to another opposing interconnect of the same material at a temperature of 150 degrees Celsius or less.

17. The temperature sensitive material is Hg １－ｘ Cd ｘ Te, The dielectric layer is made of aluminum nitride (AlN ｘ ) or silicon nitride (SiN ｘ ) and the vertical interconnect is indium; 17. A method according to any one of claims 13 to 16.

18. The forming of the dielectric layer, depositing a dielectric material to planarize a top surface of the electrical device to compensate for potential total thickness variations in the photoconductive material layer having the temperature sensitive material; The method of claim 13, comprising:

19. 20. The method of claim 18, wherein the depositing the dielectric material comprises depositing a dielectric layer over one or more electrical contact pads in electrical communication with the photoconductive material layer.

20. The dielectric material is aluminum nitride (AlN ｘ ) or silicon nitride (SiN ｘ ) and said depositing said dielectric material is performed at a temperature of 150° C. or less; 20. The method of claim 18 or 19.

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