Core Removal

Abstract

Methods, apparatus, and systems for processing substrates are provided. Generally, the processing involves a spacer-on-spacer (SoS) self-aligned quadruple patterning (SAQP) technique. The disclosed technique provides a novel process flow that reduces defects by ensuring that the core is not removed from the substrate until the substrate is transferred to a deposition chamber used to deposit a second spacer layer. This reduces or eliminates the risk of structural damage to features on the substrate while the substrate is being transferred or cleaned. Such structural damage is common when the core is removed from the substrate prior to cleaning and transfer.

Description

[Technical field]

[0001] Incorporation by Reference A PCT application has been filed contemporaneously herewith as a part of this application. Each application to which this application claims benefit or priority as identified in the contemporaneously filed PCT application is hereby incorporated by reference in its entirety for all purposes. [Background technology]

[0002] As semiconductor device dimensions continue to shrink, the fabrication of such devices becomes increasingly difficult. One problem area is the patterning of features on the semiconductor substrate. The use of multiple patterning techniques such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) has enabled the patterning of very small features.

[0003] The background art description provided herein is intended to provide a general context for the present disclosure. Work by the currently named inventors is not admitted, expressly or impliedly, as prior art against the present disclosure to the extent described in this background art section, as are aspects of the description that may not qualify as prior art at the time of filing. Summary of the Invention

[0004] Various embodiments herein relate to methods and apparatus for processing a substrate in a spacer-on-spacer self-aligned quadruple patterning scheme.

[0005] In one aspect of the disclosed embodiment, a method of processing a substrate is provided, the method including: (a) receiving a substrate including (i) an underlayer material; (ii) a core disposed on the underlayer material and having vertically oriented sidewalls; and (iii) a first spacer material covering the sidewalls of the core; (b) removing the core, thereby forming a first spacer feature from the first spacer material that previously covered the sidewalls of the core; and (c) depositing a second spacer layer over the first spacer feature, wherein (b) and (c) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (b) and (c).

[0006] In some embodiments, the method further includes cleaning the substrate to remove unwanted material from the substrate, the substrate being cleaned with a wet cleaning operation prior to (b). In these or other embodiments, the method may further include depositing a first spacer layer over the core, the first spacer layer including a first spacer material, and etching back the first spacer layer to remove the first spacer material from horizontal surfaces while leaving the first spacer material on the sidewalls of the core.

[0007] In these or other embodiments, the method may further include performing metrology to determine a time at which the core is removed during (b). In some such cases, performing metrology may include performing optical emission spectroscopy. For example, performing optical emission spectroscopy may include monitoring a signal related to the presence of carbon dioxide in the reaction chamber. In these or other embodiments, performing metrology may include performing laser interferometry. In these or other embodiments, the method may further include performing scatterometry after (b) and before (c) to measure a width of the one or more first spacer features.

[0008] In these or other embodiments, removing the core may include exposing the substrate to an oxygen-containing plasma to ashed the core. In these or other embodiments, the core may comprise carbon, the carbon of the core having a post-deposition blanket stress of about 50 MPa or less and a Young's modulus of about 30 GPa or greater.

[0009] In another aspect of the disclosed embodiments, a method of processing a substrate is provided, the method comprising: (a) providing a substrate including: (i) an underlying material; (ii) a core disposed on the underlying material, the core having vertically oriented sidewalls; (iii) a first spacer material covering the sidewalls of the core; (iv) a planarization layer disposed over the core and the first spacer material, the planarization layer having a top surface portion that is substantially flat; (v) a mask layer disposed over the planarization layer; and (vi) an opening defined in the mask layer and the planarization layer and disposed above the first spacer material covering one of the sidewalls of one of the cores. (b) removing the first spacer material at locations corresponding to the openings; (c) removing the mask layer; (d) removing the core and the planarization layer, thereby forming first spacer features from the remaining first spacer material not removed in (b) and not forming the first spacer features at locations corresponding to the openings; and (e) depositing a second spacer layer over the first spacer features, wherein (d) and (e) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (d) and (e).

[0010] In some embodiments, the core and planarization layer may be removed simultaneously. In these or other embodiments, removing the core and planarization layer may include exposing the substrate to an oxygen-containing plasma to ash the core and planarization layer. In these or other embodiments, the method may further include performing metrology to determine when the core and / or planarization layer are removed in (d). In these or other embodiments, the method may further include performing scatterometry after (d) and before (e) to measure a width of the one or more first spacer features.

[0011] In a further aspect of the disclosed embodiments, a method of processing a substrate is provided, the method including: (a) receiving a substrate including: (i) an underlying material; (ii) a core disposed on the underlying material and having vertically oriented sidewalls; (iii) a first spacer material covering the sidewalls of the core; and (iv) a planarization layer disposed over the underlying material, the core, and the first spacer material, the planarization layer patterned to form exposed regions and protected regions; (b) trimming the first spacer material to reduce a thickness of the first spacer material in the exposed regions, but leaving the first spacer material in the protected regions untrimmed; (c) removing the planarization layer and the core, thereby forming first spacer features from the first spacer material having non-uniform critical dimensions; and (d) forming a second spacer layer over the first spacer features, wherein (c) and (d) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (c) and (d).

[0012] In another aspect of the disclosed embodiments, an apparatus for processing a substrate is provided, the apparatus including: (a) a reaction chamber; (b) a substrate support disposed within the reaction chamber; (c) a plasma generator configured to generate a plasma in the reaction chamber; (d) one or more inlets to the reaction chamber; and (e) a controller having at least one processor configured to: (i) receive a substrate including: (1) an underlayer material; (2) a core disposed on the underlayer material and having vertically oriented sidewalls; and (3) a first spacer material covering the sidewalls of the core; (ii) remove the core, thereby forming first spacer features from the first spacer material that previously covered the sidewalls of the core; and (iii) deposit a second spacer layer over the first spacer features, wherein (e)(ii) and (e)(iii) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (e)(ii) and (e)(iii).

[0013] In some embodiments, the device further includes a memory. The memory and the controller may be communicatively coupled to each other. The memory may store computer-executable instructions for controlling the processor to perform any of the operations described herein. In other cases, such computer-executable instructions may be stored elsewhere (e.g., potentially remotely) and provided to the processor.

[0014] In some embodiments, the apparatus further includes optical emission spectroscopy hardware and / or laser interferometry hardware. In some such embodiments, the controller may be configured to extinguish the plasma exposed to the substrate in response to feedback from the optical emission spectroscopy hardware and / or laser interferometry hardware indicating that the core has been removed. In these or other embodiments, the apparatus may further include scatterometry hardware. In some such embodiments, the controller may be configured to cause one or more widths of the first spacer features to be measured after (e)(ii) and before (e)(iii).

[0015] In another aspect of the disclosed embodiments, an apparatus for processing a substrate is provided, the apparatus comprising: (a) a reaction chamber; (b) a substrate support disposed within the reaction chamber; (c) a plasma generator configured to generate a plasma in the reaction chamber; (d) one or more inlets to the reaction chamber; and (e) a controller having at least one processor configured to control a controller for controlling a flow of a plasma generated in the reaction chamber, the controller comprising: (i) (1) an underlayer material; (2) a core disposed on the underlayer material, the core having a vertically oriented sidewall; (3) a first spacer material covering the sidewall of the core; (4) a planarization layer disposed on the core and the first spacer material, the planarization layer having a top surface portion that is substantially flat; (5) a mask layer disposed on the planarization layer; and (6) an imaging layer configured to image a region in the mask layer and the planarization layer. and a controller configured to: (i) receive a substrate including a first spacer material having a first opening defined by a first recess and overlying a first spacer material covering one of the sidewalls of one of the cores; (ii) remove the first spacer material at a location corresponding to the opening; (iii) remove the mask layer; (iv) remove the core and the planarization layer, thereby forming a first spacer feature from the remaining first spacer material not removed in (ii) and not forming the first spacer feature at a location corresponding to the opening; and (v) deposit a second spacer layer over the first spacer feature, wherein (iv) and (v) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (d) and (e).

[0016] In some embodiments, the controller is configured to cause simultaneous removal of the core and the planarization layer. In these or other cases, removing the core and the planarization layer may include exposing the substrate to an oxygen-containing plasma to ash the core and the planarization layer. In various embodiments, the controller may be configured to cause metrology to be performed to determine the time at which the core and / or the planarization layer are removed in (iv). In these or other embodiments, the controller may be configured to cause scatterometry to be performed after (iv) and before (v) to measure a width of the one or more first spacer features.

[0017] In another aspect of the disclosed embodiments, an apparatus for processing a substrate is provided, the apparatus comprising: (a) a reaction chamber; (b) a substrate support disposed within the reaction chamber; (c) a plasma generator configured to generate a plasma in the reaction chamber; (d) one or more inlets to the reaction chamber; and (e) a controller having at least one processor configured to: (i) process a substrate having a first spacer material and a second spacer material disposed on the first spacer material; (ii) a first spacer material covering the sidewalls of the core; and (iii) a second spacer material disposed on the first spacer material; and (iv) a planarization layer disposed on the first spacer material and patterned to form an exposed region and a protected region. and a controller configured to: (i) receive a substrate including a planarization layer formed on the substrate and a core formed on the substrate; (ii) trimming the first spacer material to reduce a thickness of the first spacer material in the exposed areas but leaving the first spacer material in the protected areas untrimmed; (iii) removing the planarization layer and the core, thereby forming first spacer features from the first spacer material having non-uniform critical dimensions; and (iv) forming a second spacer layer over the first spacer features, wherein (iii) and (iv) are performed in the same reaction chamber and the substrate is not removed from the reaction chamber between (iii) and (iv).

[0018] In certain embodiments, the controller may be configured to etch back the second spacer layer such that the second spacer layer is removed from areas between adjacent first spacer features. In some such cases, the controller may be configured to remove the first spacer features, thereby forming second spacer features from the second spacer layer, where the distance between adjacent second spacer features is non-uniform due to non-uniform critical dimensions of the first spacer features. In these or other embodiments, the planarization layer and the core may be removed simultaneously. In these or other embodiments, the controller may be configured to expose the substrate to an oxygen-containing plasma to ash the core and the planarization layer.

[0019] In another aspect of the disclosed embodiments, an apparatus for processing a substrate is provided, the apparatus including: (a) a reaction chamber; (b) a substrate support disposed within the reaction chamber; (c) a plasma generator configured to generate a plasma within the reaction chamber; (d) one or more inlets to the reaction chamber; and (e) a controller having at least one processor, the controller configured to cause execution of any of the claimed methods or methods described herein.

[0020] These and other aspects are further described below with reference to the drawings. [Brief description of the drawings]

[0021] [Figure 1] FIG. 1 is a flow chart illustrating a method for spacer-on-spacer self-aligned quadruple patterning.

[0022] [Figure 2A] FIG. 2A illustrates a semiconductor substrate undergoing various steps in the method of FIG. [Figure 2B] FIG. 2B illustrates a semiconductor substrate undergoing various steps in the method of FIG. [Figure 2C] FIG. 2C illustrates a semiconductor substrate undergoing various steps in the method of FIG. [Figure 2D] FIG. 2D illustrates a semiconductor substrate undergoing various steps in the method of FIG. [Figure 2E] FIG. 2E illustrates a semiconductor substrate undergoing various steps in the method of FIG.

[0023] [Diagram 3] FIG. 3 is a flow chart illustrating a method for spacer-on-spacer self-aligned quadruple patterning using an alternative process flow, in which the core is removed in-situ during the second spacer deposition.

[0024] [Figure 4A] FIG. 4A illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 4B] FIG. 4B illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 4C] FIG. 4C illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 4D] FIG. 4D illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 4E] FIG. 4E illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 4F] FIG. 4F illustrates a semiconductor substrate undergoing various processing steps in the method of FIG.

[0025] [Diagram 5] FIG. 5 is a flow chart illustrating a method of spacer-on-spacer self-aligned patterning, in which specific first spacer features are targeted for removal before being doubled.

[0026] [Figure 6A] FIG. 6A illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 6B] FIG. 6B illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 6C] FIG. 6C illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 6D] FIG. 6D illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 6E] FIG. 6E illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 6F] FIG. 6F illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 6G]FIG. 6G illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 6H] FIG. 6H illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 6I] FIG. 6I illustrates a semiconductor substrate undergoing various processing steps in the method of FIG.

[0027] [Figure 7] FIG. 7 presents a reaction chamber that can be used to carry out the various steps in the methods described herein.

[0028] [Figure 8] FIG. 8 illustrates a multi-station processing tool that may be used to perform various steps in the methods described herein.

[0029] [Figure 9] FIG. 9 illustrates a processing system that may be used to perform various steps in the methods described herein.

[0030] [Figure 10A] FIG. 10A shows experimental results associated with the processing scheme described in FIGS. 1 and 2A-2E. [Figure 10B] FIG. 10B shows experimental results associated with the processing scheme described in FIGS. 1 and 2A-2E. [Figure 10C] FIG. 10C shows experimental results associated with the processing scheme described in FIGS. 1 and 2A-2E.

[0031] [Figure 11A] FIG. 11A shows experimental results associated with the processing scheme described in FIGS. 3 and 4A-4F. [Figure 11B] FIG. 11B shows experimental results associated with the processing scheme described in FIGS. 3 and 4A-4F. [Figure 11C]FIG. 11C shows experimental results associated with the processing scheme described in FIGS. 3 and 4A-4F.

[0032] [Figure 12A] FIG. 12A shows a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 12B] FIG. 12B illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 12C] FIG. 12C illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 12D] FIG. 12D illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 12E] FIG. 12E illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 12F] FIG. 12F illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 12G] FIG. 12G illustrates a semiconductor substrate undergoing various processing steps in the method of FIG. [Figure 12H] FIG. 12H illustrates a semiconductor substrate undergoing various processing steps in the method of FIG.

[0033] [Figure 13] FIG. 13 is a flow chart illustrating a patterning method for creating features having different critical dimensions. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. It will be understood that while the disclosed embodiments will be described in conjunction with specific embodiments, it is not intended to be limited to the disclosed embodiments.

[0035] FIG. 1 is a flow chart illustrating a patterning technique called spacer-on-spacer self-aligned quadruple patterning. FIGS. 2A-2E illustrate a substrate 201 undergoing the operations shown in FIG. 1. The operations of FIG. 1 are described in the context of FIGS. 2A-2E. Beginning in operation 101, a substrate 201 is received. The substrate 201 includes an underlying material 202, a core 203, and a first spacer layer 204. As used herein, the term underlying material refers to the material disposed under the core. FIG. 2A , an underlayer material 202 is disposed below the core 203. The underlayer material 202 is deposited prior to the formation of the core 203 and can include a variety of materials and structures. In various examples, the underlayer material 202 includes one or more layers of material, such as, for example, a dielectric material such as silicon oxide, silicon nitride, silicon carbonitride, and / or silicon carbide. The material(s) of the underlayer material 202 are selected such that they can be etched using the material of the second spacer layer 205 as a mask, as discussed further below.

[0036] The first spacer layer 204 conformally covers the core 203, as shown in FIG. 2A. Then, in operation 103, the first spacer layer 204 is etched back. As shown in FIG. 2B, the material of the first spacer layer 204 (sometimes referred to as the first spacer material) is removed from the horizontally oriented surfaces but is substantially retained on the vertically oriented surfaces. This etching operation is performed in a reaction chamber configured to perform etching. Then, in operation 105, the core 203 is removed, as shown in FIG. 2C. At this point, the remaining portions of the first spacer layer 204 are separate and distinct vertically oriented features, sometimes referred to as first spacer features 204′.

[0037] In operation 107, the substrate 201 is removed from the support (often called an electrostatic chuck) in the chamber configured to perform etching and transferred to another chamber configured to perform wet cleaning. Then, in operation 109, the substrate 201 is subjected to a wet cleaning operation to remove unwanted material. As will be appreciated by those skilled in the art, in one example, this unwanted material may be generated while the first spacer layer 204 is being etched back in operation 103. In another example, operation 105 performed to remove the core 203 may result in undesired substances such as polymer residues that can be removed in one or more cleaning processes. Then, in operation 111, the substrate 201 is transferred from the chamber configured to perform cleaning to a chamber configured to perform deposition.

[0038] FIG. 2D illustrates the substrate 201 after being transferred for cleaning, cleaned, and transferred for deposition. Various forces acting on the substrate 201 may cause the first spacer feature 204' to tip / tilt undesirably, as shown in FIG. 2D. For example, mechanical vibrations may occur whenever the substrate 201 is transferred. Such mechanical vibrations may be particularly problematic in operation 107 when removing the substrate 201 from a substrate support used to etch the substrate. Etchers often use electrostatic chucks that secure the substrate 201 to the electrostatic chuck during processing by application of a differential voltage. When the substrate 201 is dechucked (e.g., released / removed from the electrostatic chuck), the substrate 201 jumps slightly. This jump creates mechanical vibrations in the substrate 201 that may cause the first spacer feature 204' to tip. Similarly, capillary forces experienced during and after the wet cleaning process in operation 109 may cause the first spacer feature 204' to tip. For example, when solvent from a wet cleaning process dries between adjacent pairs of first spacer features 204', the first spacer features 204' may be pulled towards each other, causing them to collapse or collapse.

[0039] In operation 113, a second spacer layer 205 is deposited over the first spacer features 204', as shown in Figure 2E. The second spacer layer 205 is preferably deposited conformally. However, because the first spacer features 204' have collapsed, voids 206 are formed between adjacent sets of the first spacer features 204'. The voids 206 are undesirable and may result in failures.

[0040] 2A-2E illustrate one problem that frequently occurs during spacer-on-spacer SAQP technology. It is understood that the illustrated collapse problem does not necessarily occur at every location on the substrate, nor does it occur every time the method is performed. Rather, the figures are intended to illustrate a problem that commonly occurs in spacer-on-spacer SAQP processing that results in high defect rates and associated low yields.

[0041] It should also be understood that Figures 2A-2E omit the last two steps typically performed in spacer-on-spacer SAQP techniques, but these steps are described in the flow chart of Figure 1. Returning to Figure 1, these steps include operation 115 to etch back the second spacer layer 205, thereby removing it from the horizontally oriented surfaces while leaving it substantially intact on the vertically oriented surfaces. This step is similar to the etch back of the first spacer layer 204 in operation 103. Next, in operation 117, the first spacer layer feature 204' is removed. This step is similar to removing the core 203 in operation 105. After the first spacer feature 204' is removed, the remaining (vertically oriented) portions of the second spacer layer 205 are separate and distinct from one another, forming a second spacer feature (not shown). Figures 2A-2E omit these last two steps because the feature in Figure 2E is already damaged enough to prevent further processing from being successfully performed. As discussed above, the material(s) of the underlying material 202 (or its top surface portion) are selected such that the underlying material 202 can be etched using the second spacer features as a mask layer. In some cases, the underlying material 202 includes one or more layers of silicon nitride, silicon carbide, and / or silicon carbonitride. In some such cases, the second spacer layer 205 and the second spacer features are silicon oxide. In some other cases, the second spacer layer 205 and the second spacer features are silicon nitride. Other material combinations may be used in certain implementations.

[0042] To overcome the problems discussed above in connection with Figures 1 and 2A-2E, a new process flow is used. The new process flow delays removal of the core until after the substrate has been cleaned and transferred to a chamber for depositing the second spacer layer. The core is thus structurally supported during transfer and cleaning, thereby minimizing the risk of the first spacer feature tipping over during these steps. The core is removed in the same chamber used for depositing the second spacer layer, so core removal is considered to be in-situ during the second spacer deposition. This new process flow achieves a significantly higher yield compared to the prior art, as it significantly reduces manufacturing defects.

[0043] Figure 3 shows a flow chart for performing spacer-on-spacer self-aligned quadruple patterning according to various embodiments herein. Figures 4A-4F illustrate a partially fabricated semiconductor device on which the method described in Figure 3 has been performed. The operation of Figure 3 will be described with reference to Figures 4A-4F.

[0044] First, in operation 301, a substrate 401 is received. The substrate 401 includes an undercoat material 402, a core 403, and a first spacer layer 404. The first spacer layer 404 conformally coats the core 403 as shown in FIG. 4A. Generally, conventional materials may be used for each of these layers. In one embodiment, the core is made of or may include a material that can be ashed without leaving undesired residual material during an ashing process. As defined herein, an ashing process refers to a type of stripping process that removes one or more organic materials, such as photoresist, by exposure to heat or a plasma, such as an oxygen-containing plasma or a hydrogen-containing plasma. In one example, the material of the core may include or be selected from Group IVA of the periodic table, such as carbon, silicon, germanium, tin, lead, etc. In some examples, the material of the core may include tin oxide, lead oxide, or a combination thereof. Any combination of these materials may also be used. As a specific example, the core is a carbon or carbon-based material formed by a spin-on, chemical vapor deposition, or plasma enhanced chemical vapor deposition (PECVD) process. In these or other examples, the first spacer layer may be made of a dielectric material such as silicon nitride, titanium oxide, tin oxide, hafnium oxide, or zirconium oxide. Other materials may be used as appropriate. The first spacer layer may be deposited by atomic layer deposition or chemical vapor deposition, either of which may be driven by plasma energy or thermal energy. In some cases, the method may further include forming a core 403 on an underlayer material 402 and depositing a first spacer layer 404 on the core.

[0045] Next, in operation 303, the first spacer layer 404 is etched back. As shown in FIG. 4B, the material of the first spacer layer 404 (sometimes referred to as the first spacer material) is removed from the horizontally oriented surfaces but is substantially retained on the vertically oriented surfaces. This etching operation is performed in a chamber configured to perform etching. The first spacer layer 404 may be etched back by exposing the substrate to a combination of an etching chemistry, a plasma, and a directional ion flux configured to etch the material of the first spacer layer. The etching process is an anisotropic etch.

[0046] Next, in operation 305, the substrate 401 (e.g., having remaining material of the first spacer layer 404 adjacent the core 403 disposed on the underlying material 402, as shown in FIG. 4B) is transferred from a chamber configured to perform etching to a chamber configured to perform cleaning. In operation 307, the substrate 401 is cleaned to remove unwanted material (not shown). The unwanted material is typically material present on the substrate 401 as a result of etching back the first spacer layer in operation 303. The cleaning process may be a wet cleaning process, for example, using HF. The HF is typically diluted with water (e.g., deionized water) in a ratio of at least about 10:1 (water:HF), sometimes about 300:1, and sometimes up to about 1000:1. In certain embodiments, the HF solution may be a buffered solution. In these or other cases, the HF solution may include a weakly basic reagent, such as ammonium hydroxide and / or hydrogen peroxide. In some cases, the cleaning process may be a dry cleaning process. In that case, the substrate may be exposed to a plasma to remove the unwanted material.

[0047] In other cases, the cleaning process may be omitted entirely. For example, the material of the first spacer layer 404 and / or the material of the core 403 may be selected such that it can be cleanly removed, for example, without the formation of non-volatile materials that redeposit on the substrate. In such embodiments, there may be little or no unwanted material to remove in the cleaning operation. In embodiments where cleaning is omitted, the transfer steps associated with cleaning may be omitted as well. For example, with reference to FIG. 3, operations 305, 307, and 309 may be replaced by a single operation that includes transferring the substrate from the etching chamber to the deposition chamber. In another example, the etching chamber and the deposition chamber may be the same reaction chamber. In this case, operations 305, 307, and 309 may be omitted entirely.

[0048] One advantage of omitting the cleaning step is that it reduces the number of times the substrate is transferred between different chambers and / or tools. This further reduces the risk that any features on the substrate are damaged during processing / transfer. In one example where the etch chamber and deposition chamber are the same reaction chamber (e.g., the reaction chamber is configured to etch and deposit as desired), omitting the cleaning operation eliminates the need to transfer the substrate between operation 303 (e.g., etching back the first spacer layer) and operation 311 (removing the core, thereby forming the first spacer feature).

[0049] Returning to the embodiment of Figure 3, in operation 309, the substrate 401 is transferred from a chamber configured to perform cleaning to a chamber configured to perform deposition, which may be the same or a different chamber used to deposit the first spacer layer, and which may be the same or a different chamber used to etch back the first spacer layer.

[0050] Notably, operations 305, 307, and 309 are all performed while the core 403 is still present on the substrate 401, as shown in FIG. 4B. In this way, the core 403 provides mechanical support to the first spacer layer 404 / first spacer feature 404' to prevent them from undesirably toppling during transfer and cleaning operations. Once the substrate is transferred to a deposition chamber where the second spacer layer is deposited (discussed further below), the core 403 is removed in operation 311, as shown in FIG. 4C. The core may be removed by a drying process, such as ashing. At this point, the remaining portion of the first spacer layer 404 is a separate, distinct, vertically oriented feature, sometimes referred to as the first spacer feature 404'. The core 403 may be removed by exposing the substrate to a plasma configured to remove the core material. As mentioned above, in one example, the core 403 is a carbon or carbon-based material and can be removed by exposing the substrate to an oxygen-containing plasma. Examples of reactants include O2 and other oxygen-containing species. In some other examples, the core 403 may include one or more metal oxide materials (e.g., tin oxide, lead oxide, etc.) and may be removed by exposing the substrate to a hydrogen-containing plasma. Examples of reactants that may be used include H2, NH3, CH4, and other hydrogen-containing species. In a particular example, the plasma includes a mixture of H2 and N2. Oxidizing and reducing plasmas may be used as appropriate to remove certain core materials.

[0051] Next, in operation 313, as shown in FIG. 4D, a second spacer layer 405 is deposited on the first spacer features 404′. The second spacer layer 405 may be deposited by atomic layer deposition or chemical vapor deposition (either of which may be driven by plasma energy or thermal energy). The second spacer layer 405 may be a dielectric material such as silicon oxide, silicon nitride, titanium oxide, tin oxide, zirconium oxide, hafnium oxide, etc. In general, the material of the first spacer layer 404 should have a different composition than the material of the second spacer layer 405. Various material combinations can be used for the first spacer layer 404 and the second spacer layer 405.

[0052] In one example, the core 403 is carbon or a carbon-based material, the first spacer layer 404 is tin oxide or titanium oxide, and the second spacer layer 405 is silicon oxide or silicon nitride. In another example, the core 403 is carbon or a carbon-based material, the first spacer layer 404 is silicon oxide or silicon nitride, and the second spacer layer 405 is tin oxide, titanium oxide, or lead oxide. In another example, the core 403 is tin oxide, lead oxide, or a combination thereof, the first spacer layer 404 is titanium oxide, and the second spacer layer 405 is any oxide (e.g., silicon oxide, metal oxide, etc.) or silicon nitride.

[0053] The process flow described in Figure 3 ensures that the first spacer features 404' remain vertical and do not topple as described in connection with Figures 1 and 2D. In this manner, the second spacer layer 405 is conformally deposited on the first spacer features 404' without the formation of voids or other undesirable defects as described in connection with Figure 2E.

[0054] Next, in operation 315, the second spacer layer 405 is etched back, as shown in FIG. 4E. The etch back operation removes the second spacer layer 405 from the horizontal surfaces, but substantially retains it on the vertical surfaces. The second spacer layer 405 may be etched back by exposing the substrate to a combination of an etch chemistry, a plasma, and a directional ion flux configured to etch the material of the second spacer layer. The etch process is an anisotropic etch process.

[0055] In operation 317, the first spacer features 404' are removed, as shown in FIG. 4F. At this point, the remaining portions of the second spacer layer 405 are separate and distinct from one another, forming the second spacer features 405'. The first spacer features 404' may be removed by ashing / undermining in a low bias (e.g., ≦10V) isotropic selective etch. The first spacer features 404' are selectively removed without significantly etching the underlying material 402 of the substrate 401 or the second spacer features 405'.

[0056] As discussed above, the core may be a carbon or carbon-containing material, or a metal oxide material. In various embodiments, the core may have certain material properties. For example, the core material may exhibit relatively low stress (e.g., post-deposition blanket stress having an absolute value of about 50 MPa or less) and a high Young's modulus (e.g., greater than 30 GPa). In certain embodiments, the core material may be ashed when exposed to a plasma, such as, for example, an oxygen-containing plasma or a hydrogen-containing plasma. The ashing reaction produces volatile products from at least one solid-phase reactant, but produces little polymer or other non-volatile material that may redeposit on the substrate. In the case of carbon or carbon-containing cores, the carbon may react with an oxygen-containing plasma to form volatile carbon dioxide. In the case of metal oxide-based cores, a hydrogen-containing plasma may be used to remove the metal oxide.

[0057] As shown in Figures 4A-4F, the disclosed process flow can be used to quadruple the number of features present on a substrate surface. This process is commonly referred to as Spacer-on-Spacer (SoS) Self-Aligned Quadruple Patterning (SAQP). The particular process flow described in Figure 3 is sometimes referred to as Core Pull In-Situ to Second Spacer Deposition (CoPS). The name comes from the fact that the core is removed in-situ (e.g., in the same chamber) during the second spacer deposition. The CoPS process flow significantly reduces manufacturing defects, thereby minimizing the number of non-functional substrates / devices, reducing waste, and increasing efficiency. This results in reduced manufacturing costs.

[0058] 3 and 4A-4F, it should be understood that certain operations may be omitted in various embodiments. Likewise, additional steps may be performed in some embodiments. With reference to FIG. 3, one embodiment includes only operation 311. Another embodiment includes operations 311 and 313. Another embodiment includes operations 311, 313, and 315. Another embodiment includes operations 311, 313, 315, and 317. Any of these embodiments can be modified to include any one or more of operations 301, 303, 305, and 307.

[0059] The process flow described in Figures 3 and 4A-4F works well in contexts where a four-fold increase in the number of features is desired, such as in the fabrication of memory devices. Some other devices (e.g., logic devices) may have more complex structures, and in such cases it may be desirable to increase the number of features by less than four-fold. In such cases, certain features (e.g., the first spacer feature) may be subject to removal before being used to double the pattern. Figure 5 is a flow chart illustrating such an embodiment, sometimes referred to as a cut mask integration scheme. The method of Figure 5 is described in the context of Figures 6A-6I, which show a partially fabricated semiconductor device on which the operations of Figure 5 have been performed. In general, many of the operations of Figure 5 are similar to those of Figure 3, and the details provided in connection with Figure 3 also apply to the method of Figure 5. For the sake of brevity, many such details are omitted from the description of Figure 5.

[0060] The method of FIG. 5 begins with operation 501, in which a substrate 601 is received. The substrate 601 includes an underlayer 602, a core 603, and a first spacer layer 604, as shown in FIG. 6A. Steps relating to the deposition of the core 603 and the first spacer layer 604, and the etch-back of the first spacer layer 604 (similar to operation 303) are omitted from the figure, although these steps may be included in certain embodiments. Certain substrate transfer steps are also omitted from the figure, although it is understood that the substrate is transferred to a different tool as required for each step. The method continues with operation 502, in which the substrate is subjected to cleaning to remove unwanted material, which is frequently generated during the etch-back of the first spacer layer 604. As discussed with reference to FIG. 3, cleaning operation 502 may be omitted in certain embodiments.

[0061] The method continues with operation 503, where a planarization layer 607, an intermediate layer 608, and a patterned layer of photoresist 609 are sequentially provided on the substrate 601, as shown in FIG. 6B. Often, the planarization layer 607 is spin-on carbon or spin-on glass, which is self-planarizing. Alternatively, the planarization layer 607 may be deposited by chemical vapor deposition or other methods. The top surface / portion of the planarization layer 607 is typically flat. The planarization layer 607 may also be referred to as a mask or a block mask. A variety of different conventional materials may be used for the intermediate layer 608, which may be deposited by spin-on techniques, PECVD techniques, and the like. The photoresist 609 may be any type of photoresist. In a particular embodiment, the photoresist 609 is an extreme ultraviolet (EUV) photoresist. Such an EUV photoresist may be exposed using the standard 13.5 nm EUV wavelengths currently in use and development. However, other radiation sources may be used in some cases, including DUV (deep ultraviolet), which generally refers to the use of 248 nm or 193 nm excimer laser sources, X-ray, formally including EUV, in the lower energy range of the X-ray range, and electron beam, which can cover a wide energy range.

[0062] Photoresist is deposited and then patterned as part of operation 503 to include opening 610. In this example, opening 610 is located above the remaining third portion of first spacer layer 604, counting from the left. In other embodiments, opening 610 may be in other locations. This positioning allows opening 610 to be used to remove the remaining third portion of first spacer layer 604, as described further below, thereby preventing formation of first spacer feature 604' at this location.

[0063] In particular, operations 502 and 503 are performed while the core 603 is still on the substrate 601. This ensures that the core 603 provides mechanical support to the remaining portion of the first spacer layer 604 during the transfer and cleaning operations. In a more conventional process flow, the core 603 would be removed (thereby forming the first spacer feature 604') immediately after the first spacer layer 604 is etched back (e.g., after operation 501) and before the substrate is cleaned (e.g., before operation 502). After cleaning, the planarization layer 607 is additionally deposited at the location where the core 603 was removed. As a result of the conventional process flow, the first spacer feature 604' would lack mechanical support during the various transfer and cleaning operations and would remain vulnerable to collapse, as described in relation to FIG. 2D. Instead, by maintaining the core 603 throughout substrate transfer, cleaning, and deposition of the planarization layer 607, intermediate layer 608, and photoresist 609, the process flow of FIG. 5 ensures that the remaining portions of the first spacer layer 604 are properly supported throughout the various processing steps, preventing them from collapsing and causing further processing problems.

[0064] 5 continues with operation 505, where the intermediate layer 608 is etched at the openings 610, as shown in FIG. 6C. The photoresist 609 acts as a mask to protect the remaining portions of the intermediate layer 608. However, the photoresist 609 may be partially or completely removed as the intermediate layer 608 is etched in operation 505. The etching operation may include exposing the substrate to a chemistry and / or plasma configured to remove the material of the intermediate layer at the openings 610. The etching process may be selective in that it etches the material of the intermediate layer 608 to a greater extent than other materials, such as the photoresist 609.

[0065] The method then continues with operation 507, where the planarization layer 607 is etched at the openings 610, as shown in FIG. 6D. The intermediate layer 608 (as well as the remaining photoresist 609) acts as a mask while the planarization layer 607 is etched. In this manner, the intermediate layer 608 may also be referred to as a mask or mask layer. The planarization layer 607 may be removed at the openings 610 by exposing the substrate to a chemistry and / or plasma configured to remove the planarization layer 607. The etching process may be selective in that it etches the planarization layer 607 to a greater extent than other materials, such as the intermediate layer 608. In one example, the substrate is exposed to an oxygen-containing plasma to remove the planarization layer 607 at the openings 610. A portion of the intermediate layer 608 may be removed during operation 507. At this point, a top surface portion of the planarization layer 607 is substantially flat (e.g., flat except for the openings 610).

[0066] Next, in operation 509, as shown in FIG. 6E, a portion of the remaining first spacer layer 604 is removed at the openings 610. The intermediate layer 608 acts as a mask during this operation and may be wholly or partially removed during this step. In various embodiments, the intermediate layer 608 is completely removed during operation 509. In such a case, the remaining planarization layer 607 may act as a mask to protect various features / structures on the substrate 601 at locations other than the openings 610. The etching process may include exposing the substrate to a chemistry and / or plasma configured to remove material of the first spacer layer 604 to a greater extent than other materials, such as the intermediate layer 608 and / or the planarization layer 607.

[0067] At this point, the portion of the first spacer layer 604 corresponding to the location of the opening 610 is completely removed. As such, the first spacer layer 604 will not form a first spacer feature 604' at this location. To remove the first spacer layer 604 at the opening 610, the substrate may be exposed to a chemistry and / or plasma configured to remove material of the first spacer layer 604. In other words, the etching process is selective.

[0068] The method continues with operation 511, where the core 603 and remaining planarization layer 607 are removed, as shown in FIG. 6F. The remaining portions of the first spacer layer 604 are now separate and distinct from one another and may be referred to as first spacer features 604'. Typically, the core 603 and planarization layer 607 are removed through a drying process, such as ashing. In one embodiment, the core 603 and planarization layer 607 are removed together in a single step. In another embodiment, the core 603 may be removed after the planarization layer 607 is removed. In a conventional process flow, the core 603 has already been replaced by the planarization layer 607 by this point, so only a single ashing step is used.

[0069] At this point, the substrate 601 of FIG. 6F is similar to the substrate 501 of FIG. 4C. That is, the substrate 601 includes an underlying material 602 and a first spacer feature 604′. The method continues with steps similar to those described in FIG. 3 and FIG. 4D-4F. In operation 513, a second spacer layer 605 is deposited on the first spacer feature 604′, as shown in FIG. 6G. In operation 515, the second spacer layer 605 is etched back, as shown in FIG. 6H. In operation 517, the first spacer feature 604′ is removed, as shown in FIG. 6I. The remaining portions of the second spacer layer 605 are now separate and distinct from one another and may be referred to as second spacer features 605′.

[0070] As shown in Figures 6A-6I, the process flow described in Figure 5 tripled the number of features present on the substrate 601 (e.g., the substrate started with two features and ended with six features). Of course, in performing the method of Figure 5, features (e.g., the first spacer feature) can be targeted for removal and any number of openings 610 can be used as desired for a particular application. In general, the method of Figure 5 may be used to increase the number of features on a substrate by a factor of 3:1 to 4:1, depending on the number of openings 610 provided in the photoresist 609. The resulting layout of features can be controlled based on the positioning of the openings 610.

[0071] Figure 13 shows a flow chart illustrating a method of processing a semiconductor substrate, where the substrate is patterned to include features having non-uniform critical dimensions. Similar to the methods described in Figures 3 and 5, the method of Figure 13 ensures that the cores remain on the substrate through several processing steps and allows the cores to provide mechanical support to adjacent structures, thereby preventing such structures from collapsing. Figures 12A-12H show a partially fabricated semiconductor substrate on which the method of Figure 13 has been performed. These figures are described together for clarity.

[0072] The method of FIG. 13 begins with operation 1301, where a substrate 1201 is received in a reaction chamber. The substrate 1201 may be disposed, for example, on a substrate support. The substrate 1201 includes an undercoat material 1202, a core 1203, and a first spacer layer 1204, as shown in FIG. 12A. Next, in operation 1303, the first spacer layer 1204 is etched back, as shown in FIG. 12B. This operation is similar, for example, to the etch back of the first spacer layer in operation 303 of FIG. 3. In operation 1305, the substrate is subjected to cleaning, for example, to remove unwanted material that may occur during the etch back of the first spacer layer in operation 1303. Next, in operation 1307, a planarization layer 1205 is deposited and patterned, as shown in FIG. 12C. Planarization layer 1205 is similar to planarization layer 607 of Figures 6B-6E and may be patterned by similar techniques (eg, one or more additional layers may be used in combination with lithography).

[0073] The planarization layer 1205 is patterned to expose certain portions of the underlying structure, as shown in Figure 12C. In particular, the planarization layer 1205 is patterned to define exposed areas (e.g., areas where the planarization layer 1205 has been removed) and protected areas (e.g., areas where the planarization layer remains) on the substrate. As described further below, this allows for the formation of features having non-uniform critical dimensions.

[0074] In operation 1309, the exposed portions of the first spacer layer 1204 are trimmed through exposure to ions, chemicals, and / or plasma 1206 to reduce the thickness of the first spacer layer 1204 in the exposed regions. FIG. 12C shows the substrate 1201 at the start of this trimming operation 1309, and FIG. 12D shows the substrate 1201 at the end of this trimming operation 1309. Before trimming, the first spacer layer 1204 has a thickness A in all areas where the first spacer layer 1204 remains. The thickness is measured in a direction parallel to the substrate surface. After trimming, the first spacer layer 1204 has a thickness A in the protected areas and a smaller thickness A' in the exposed areas. At this point, these narrowed features may be referred to as trimmed first spacers 1204'. Although Figures 12D-12H show three adjacent trimmed first spacers 1204', it will be understood that any number of trimmed first spacers 1204' may be used and may be formed in any desired layout for a particular application.

[0075] Next, in operation 1311, the planarization layer 1205 is removed, as shown in FIG. 12E. This step is similar to the removal of the planarization layer in operation 511 of FIG. 5. In operation 1313, the core 1203 is removed, as shown in FIG. 12F. This step is similar to the removal of the core in operation 511 of FIG. 5. In some cases, the planarization layer 1205 and the core 1203 may be removed in separate steps, and in other cases, they may be removed together in a single step. After the core 1203 is removed, the features formed from the remaining untrimmed portions of the first spacer layer 1204 and the features formed from the trimmed first spacers 1204' are separate and distinct from one another and may be referred to as first spacer features.

[0076] 12F clearly illustrates the non-uniform critical dimensions of the first spacer features: in particular, the first spacer feature formed from the untrimmed first spacer layer 1204 (shown in light gray) has a thickness A, while the first spacer feature formed from the trimmed first spacer layer 1204' (shown in dark gray) has a narrower thickness A'.

[0077] In operation 1315, as shown in Figure 12G, a second spacer layer 1207 is deposited. The second spacer layer 1207 has a thickness B. This deposition is similar to the deposition of the second spacer layer in operation 313 of Figure 3 and operation 513 of Figure 5. Then, in operation 1317, the second spacer layer 1207 is etched back, as shown in Figure 12H. This etch back is similar to operation 315 of Figure 3 and operation 515 of Figure 5. The substrate 1201 shown in Figure 12H has two different types of features thereon having different critical dimensions. One type of feature has a thickness A+2B and is formed in an area where the planarization layer 1205 was present to protect the underlying structure during trimming in operation 1309. The other type of feature is narrower and has a thickness A'+2B and is formed in the areas where the planarization layer 1205 has been removed to expose the underlying structure, where a portion of the first spacer layer 1204 is trimmed to form a trimmed first spacer 1204'.

[0078] In certain embodiments, operations 1315 and 1317 may be omitted. Without the deposition of the second spacer layer 1207, features with different critical dimensions can be formed, for example as shown in FIG. 12F. In some embodiments, additional operations may be performed. As an example, material from the first spacer layer 1204 and the trimmed first spacers 1204' may be removed after operation 1317. This would produce features with a uniform thickness B, but with different spacing between sets of adjacent features. For example, some sets of adjacent features will be separated by a distance A, while other sets of adjacent features will be separated by a distance A'.

[0079] 13 and 12A-12H is that the core 1203 remains with the substrate 1201 through several processing steps, including etching back the first spacer layer 1204 in operation 1303, cleaning the substrate 1201 in operation 1305, depositing and patterning the planarization layer 1205 in operation 1307, and trimming the exposed portions of the first spacer layer 1204 to form trimmed first spacers 1204′ in operation 1309. Additionally, many of the processing steps outlined in FIG. 13 may be performed in the reaction chamber used to deposit the second spacer layer 1207. For example, at least the steps of trimming the first spacer layer 1204 in operation 1309, removing the planarization layer 1205 in operation 1311, removing the core 1203 in operation 1313, and depositing the second spacer layer 1207 in operation 1315 may all occur in this reaction chamber. By ensuring that the core 1203 remains on the substrate 1201 until after the substrate 1201 has been transferred to the reaction chamber used to deposit the second spacer layer 1207, the risk of feature collapse is substantially reduced or eliminated. This risk is reduced because the substrate is not transferred, cleaned, or subjected to other operations that may cause collapse while the associated feature lacks adequate support.

[0080] Various types of feedback may be used in implementing embodiments herein. For example, when removing the core (e.g., in operations 311, 511, or 1313), feedback may be used to determine the time when the core material is sufficiently removed from the substrate. The time this takes may vary from day to day or from substrate to substrate based on various factors. Examples of feedback methods that may be used to monitor the core removal process include optical emission spectroscopy (OES) and laser interferometry (LSR). Real-time feedback is useful in this context because it can stop the core removal process immediately after the core is sufficiently removed, thus minimizing excessive plasma exposure (and / or other harsh processing conditions) on the substrate, particularly on the first spacer feature. In many embodiments, the core removal process includes exposing the substrate to a plasma (e.g., an oxygen-containing plasma), sometimes referred to as an ashing plasma. The core removal process may be stopped by simply turning off the plasma. The core removal process may be stopped in response to feedback from the OES and / or LSR device indicating that the core removal process is complete or substantially complete.

[0081] In this context, optical emission spectroscopy involves monitoring the optical emission of the plasma that is exposed to the substrate to remove the core. As the core reacts with the plasma, the core material reacts and dissipates, producing gas phase products that are removed from the chamber via a vacuum connection. The optical emission spectrum is monitored to detect the presence and relative concentration of the gas phase products. The gas phase products typically increase in concentration (and measured line intensity at a particular wavelength) early in the removal process, then reach a steady state, and then decrease as the removal process approaches completion. When the measured intensity of a particular gas phase product falls to a certain threshold level, it means that the core material has been removed, and further exposure of the substrate to the plasma is unnecessary (and potentially harmful). In one example, the core is a carbon or carbon-based material, and removing the core involves ashing the carbon to form gas phase carbon dioxide. The optical emission spectrum of the plasma is monitored at wavelengths at which carbon dioxide emits. Initially, the carbon dioxide signal rises as the carbon in the core reacts and dissipates, producing carbon dioxide. The carbon dioxide signal reaches a steady state, at which point carbon dioxide is being produced at the same rate that it is being evacuated from the chamber. Eventually, the carbon dioxide signal will begin to decrease toward zero, indicating that carbon dioxide is being removed from the chamber faster than it is being produced, meaning the removal process is complete or nearing completion. Similar techniques may be used with other types of core materials and ashing plasmas.

[0082] As mentioned above, another type of feedback that can be used to detect the endpoint of the core removal process includes laser interferometry. In this context, laser interferometry involves shining one or more lasers onto the substrate (if a single laser is used, the laser is split into two or more beams), bouncing the beam off the substrate, and monitoring the interference pattern that returns from the substrate. This technique examines the interaction of photons with matter on the wafer surface and can detect when the core removal process is complete.

[0083] Another type of feedback that may be used in any of the embodiments herein relates to Optical Critical Dimension (OCD) metrology, often referred to as scatterometry. This type of feedback may be used to measure the width of the first spacer feature after the core has been removed (e.g., width from left to right in FIG. 4C or FIG. 6F). In various embodiments, the chamber used to remove the core and deposit the second spacer layer may include scatterometry hardware to perform OCD. In this way, the width of the first spacer feature may be measured in-situ in the deposition chamber without transferring the substrate to another chamber for metrology. Such substrate transfer may undesirably cause the first spacer feature to tip, for example, as described in connection with FIG. 2D. Instead, the core removal, measurement of the width of the first spacer feature, and subsequent deposition of the second spacer layer may all be performed without dechucking or otherwise disturbing the substrate. The width measured by the scatterometry hardware may be used as feedback to control upstream processes, such as the deposition of the first spacer layer. If the scatterometry indicates that the first spacer feature is narrower than desired, the duration of the process for forming the first spacer feature may be increased to form a thicker first spacer layer on future processed substrates. Similarly, if the scatterometry indicates that the first spacer feature is wider than desired, the duration of the process for forming the first spacer feature may be decreased to form a narrower first spacer layer on future processed substrates. Alternatively or in addition to changing the duration, the deposition of the first spacer layer may also be changed based on the scatterometry results to use different plasma conditions, if desired. These changes may be made based on automatic process control or may be made manually.

[0084] To obtain the feedback described herein, the deposition chamber used to deposit the second spacer layer may be modified to include associated feedback hardware. For example, the deposition chamber may be modified to include optical emission spectroscopy hardware, laser interferometry hardware, and / or optical CD metrology / scatterometry hardware. Conventional deposition chambers used to deposit the second spacer layer do not include such feedback hardware. Often, the second spacer layer is deposited by atomic layer deposition (which may be driven by plasma energy and / or thermal energy), which deposits very slowly and predictably. Due to the predictable and controllable nature of the atomic layer deposition reaction, there is no need to actively monitor the deposition process. Rather, the endpoint of the deposition reaction can be reliably predicted based only on the deposition rate and the desired film thickness. As such, conventional chambers for depositing the second spacer layer do not include hardware for endpoint detection. The same is true for other types of deposition chambers (e.g., chemical vapor deposition chambers, etc.) that have predictable deposition rates. Similarly, conventional chambers for depositing the second spacer layer do not include scatterometry hardware. Such hardware may be used in other tools earlier in the process flow, but there has heretofore been no compelling reason to include such hardware in the deposition chamber used to deposit the second spacer layer.

[0085] Device FIG. 7 illustrates a schematic of one embodiment of a process station 700 that may be used to process a substrate, according to various embodiments. For example, the process station 700 may be used to perform many of the operations described herein, including removing the core (e.g., operations 311, 511, and 1313), removing the additional planarization layer (e.g., operations 511 and 1311), depositing the second spacer layer (e.g., operations 313, 513, and 1315), and performing any metrology and feedback techniques associated with these processes. By performing these operations in the same process station 700 using the process flows described in FIG. 3, 5, and / or 13, the advantages discussed above may be achieved. For example, removing the core (and additional planarization layer, if present) and depositing the second spacer layer in the same station eliminates the need to transfer the substrate while the first spacer feature is mechanically compromised. In various embodiments, the substrate is not transferred at a time when the first spacer feature is not laterally supported, as shown in FIG. 2C, 4C, 6F, and 12F. In other words, as shown in Figures 2B, 4B, 6A, and 12B, after the first spacer layer is etched back, the substrate is transferred only if the remaining portions of the first spacer layer (or the first spacer feature) are laterally supported, for example, by the material of the core or the material of the second spacer layer.

[0086] In some embodiments, certain additional operations described herein may be performed in the process station 700 (e.g., in the same process station 700 used to remove the core and deposit the second spacer layer). For example, in some embodiments, the process station 700 may also be used to deposit the first spacer layer. In these or other embodiments, the process station 700 may be used to laterally trim the core prior to deposition of the first spacer layer. This trimming ensures uniformity of the critical dimension of the core across the surface of the substrate (and between different substrates). In these or other embodiments, the process station 700 may be used to plasma treat the substrate (e.g., with He and / or Ar plasma) and thereby activate the surface of the substrate prior to deposition to enhance conformality and adhesion of the film (e.g., the first or second spacer layer, or other layer described herein).

[0087] For simplicity, the process station 700 is depicted as a stand-alone process station having a process chamber body 702 for maintaining a low pressure environment. However, it will be understood that multiple process stations 700 may be included in a common process tool environment. Additionally, it will be understood that in some embodiments, one or more hardware parameters of the process station 700, including those discussed in detail below, may be programmatically adjusted by one or more computer controllers.

[0088] The process station 700 is in fluid communication with a reactant delivery system 701 for delivering process gases to a distribution showerhead 706. The reactant delivery system 701 includes a mixing vessel 704 for mixing and / or conditioning process gases for delivery to the showerhead 706. One or more mixing vessel inlet valves 720 may control the introduction of process gases to the mixing vessel 704. Similarly, a showerhead inlet valve 705 may control the introduction of process gases to the showerhead 706.

[0089] Some reactants, such as BTBAS, may be stored in liquid form prior to vaporization at the process station and subsequent delivery to the process station. For example, the embodiment of FIG. 7 includes a vaporization point 703 for vaporizing liquid reactants that are supplied to a mixing vessel 704. In some embodiments, the vaporization point 703 may be a heated vaporizer. Reactant vapors generated from such vaporizers may condense in downstream delivery piping. Exposure of incompatible gases to the condensed reactants may generate small particles. These small particles may also cause clogged piping, inhibit valve operation, contaminate the substrate, etc. Some approaches to address such issues include cleaning and / or evacuating the delivery piping to remove reaction residues. However, cleaning the delivery piping may increase the cycle time of the process station and may also reduce the throughput of the process station. Thus, in some embodiments, the delivery piping downstream of the vaporization point 703 may be heat traced. In some examples, the mixing vessel 704 may also be heat traced. In one non-limiting example, the piping downstream of the vaporization point 703 has an increasing temperature profile ranging from about 100° C. to about 150° C. at the mixing vessel 704 .

[0090] In some embodiments, the liquid reactants may be vaporized in a liquid injector. For example, the liquid injector may inject pulses of liquid reactants into the carrier gas stream upstream of the mixing vessel. In one scenario, the liquid injector may vaporize the reactants by decompressing and boiling the liquid from a high pressure to a low pressure. In another scenario, the liquid injector may break the liquid into atomized droplets that are then vaporized in a heated delivery tube. It will be appreciated that small droplets vaporize faster than large droplets, reducing the delay between injection and complete vaporization of the liquid. Faster vaporization may reduce the length of tubing downstream of the vaporization point 703. In one scenario, the liquid injector may be attached directly to the mixing vessel 704. In another scenario, the liquid injector may be attached directly to the showerhead 706.

[0091] In some embodiments, a liquid flow controller upstream of the vaporization point 703 may be provided to control the mass flow rate of liquid for vaporization and delivery to the process station 700. For example, the liquid flow controller (LFC) may include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC may then be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM. However, it may take more than a second to stabilize the liquid flow using feedback control. This may extend the time to dose the liquid reactant. Thus, in some embodiments, the LFC may be dynamically switched between a feedback control mode and a direct control mode. In some embodiments, the LFC may be dynamically switched from a feedback control mode to a direct control mode by disabling the sense tubes of the LFC and the PID controller.

[0092] The showerhead 706 distributes process gases toward the substrate 712. In the embodiment depicted in Figure 7, the substrate 712 is shown as being located below the showerhead 706 and resting on a pedestal 708. It will be understood that the showerhead 706 may have any suitable shape and any suitable number and arrangement of ports for distributing process gases to the substrate 712.

[0093] In some embodiments, the microvolume 707 is located under the showerhead 706. Performing processes in the microvolume rather than the full volume of the process station can reduce reactant exposure and clean-up times, reduce the time to change process conditions (e.g., pressure, temperature, etc.), limit exposure of the process station robot to process gases, etc. Examples of microvolume sizes include, but are not limited to, volumes of 0.1 liters to 2 liters. This microvolume also impacts productivity throughput. For example, when such a microvolume is used for an atomic layer deposition process, the deposition rate per cycle will be lower than for a larger volume, but the cycle time is also reduced at the same time. In certain cases, the latter effect is dramatic enough to increase the overall throughput of the module for a given target film thickness.

[0094] In some embodiments, the pedestal 708 may be raised and lowered to expose the substrate 712 to the micro-volume 707 and / or to change the volume of the micro-volume 707. For example, during a substrate transfer phase, the pedestal 708 may be lowered to allow the substrate 712 to be placed on the pedestal 708. During a substrate processing phase (e.g., depositing material on the substrate, etching material on the substrate, or processing material on the substrate), the pedestal 708 may be raised to position the substrate 712 within the micro-volume 707. In some embodiments, the micro-volume 707 may completely surround the substrate 712 with a portion of the pedestal 708 to form a region of high flow impedance while processing the substrate.

[0095] Optionally, the pedestal 708 may be lowered and / or raised while the substrate is being processed to adjust the process pressure, reactant concentration, etc., within the microvolume 707. In one scenario in which the process chamber body 702 remains at base pressure while processing the substrate, lowering the pedestal 708 may allow evacuation of the microvolume 707. Examples of ratios of the microvolume to the process chamber volume include, but are not limited to, volume ratios of 1:700 to 1:10. It will be appreciated that in some embodiments, the height of the pedestal may be programmatically adjusted by a suitable computer controller.

[0096] In another scenario, the plasma density may be able to be varied during plasma activation and / or processing cycles involved in the process by adjusting the height of the pedestal 708. At the end of the substrate processing stage, the pedestal 708 may be lowered during another substrate transfer stage so that the substrate 712 can be removed from the pedestal 708.

[0097] Although the example micro-volume variations described herein are referred to as height adjustable pedestals, it will be understood that in some embodiments, the position of the showerhead 706 may be adjusted relative to the pedestal 708 to vary the volume of the micro-volume 707. Further, it will be understood that the vertical position of the pedestal 708 and / or the showerhead 706 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 708 may include a rotation axis for rotating the orientation of the substrate 712. It will be understood that in some embodiments, one or more of these example adjustments may be performed programmatically by one or more suitable computer controllers.

[0098] Returning to the embodiment shown in FIG. 7, the showerhead 706 and pedestal 708 are in electrical communication with an RF power source 714 and a matching network 716 to provide power to the plasma. In some embodiments, the plasma energy may be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 714 and the matching network 716 may be operated at any suitable power to form a plasma having a desired composition of radical species. Examples of suitable powers are included above. Similarly, the RF power source 714 may provide RF power of any suitable frequency. In some embodiments, the RF power source 714 may be configured to control high and low frequency RF power sources independently of each other. Examples of low frequency RF frequencies may include, but are not limited to, frequencies from 50 kHz to 700 kHz. Examples of high frequency RF frequencies may include, but are not limited to, frequencies from 1.8 MHz to 2.45 GHz. It will be appreciated that any suitable parameter may be modulated discretely or continuously to provide plasma energy for surface reactions. In one non-limiting example, the plasma power may be pulsed intermittently to reduce ion bombardment with the substrate surface as compared to a continuously powered plasma.

[0099] In some embodiments, the plasma may be monitored in-situ by one or more plasma monitors. In one scenario, the plasma power may be monitored by one or more voltage, current sensors (e.g., VI probes). In another scenario, the plasma density and / or process gas concentration may be measured by one or more optical emission spectroscopy sensors (OES). In some embodiments, one or more plasma parameters may be programmatically adjusted based on measurements from such in-situ plasma monitors. For example, an OES sensor may be used in a feedback loop to provide programmatic control of the plasma power. As described above, the OES hardware may be used to determine the endpoint of the reaction used to remove the core. Alternatively or additionally, laser interferometry hardware may be used to determine the endpoint of this reaction. In these or other embodiments, the OCD / scatterometry hardware may be used to measure the width of the first spacer feature and / or other features present on the substrate surface. It will be appreciated that in some embodiments, other monitors may be used to monitor the plasma, the substrate, and other process characteristics. Such monitors may include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.

[0100] In some embodiments, the plasma may be controlled via input / output control (IOC) sequencing instructions. In one example, instructions for setting plasma conditions for a plasma process step may be included in a corresponding plasma activation recipe step of a process recipe. In some cases, process recipe steps may be sequentially arranged such that all instructions for a particular process step are executed simultaneously with that process step. In some embodiments, instructions for setting one or more plasma parameters may be included in a recipe step preceding a plasma process step. For example, a first recipe step may include instructions for setting flow rates of inert and / or reactive gases, instructions for setting a plasma generator to a power set point, and time delay instructions for the first recipe step. A second subsequent recipe step may include instructions for enabling the plasma generator and time delay instructions for the second recipe step. A third recipe step may include instructions for disabling the plasma generator and time delay instructions for the third recipe step. It will be appreciated that these recipe steps may be further subdivided and / or repeated in any suitable manner within the scope of the present disclosure.

[0101] In some deposition processes, the plasma strikes last on the order of a few seconds or more in duration. In certain embodiments, much shorter plasma strikes may be used. These may be on the order of 10 ms to 1 second, typically about 20 to 80 ms, with 50 ms being a specific example. Such very short RF plasma strikes require extremely rapid stabilization of the plasma. To achieve this, the plasma generator may be configured such that the impedance match is preset to a particular voltage, while the frequency is allowed to float. Conventionally, high frequency plasmas are generated at an RF frequency of about 13.56 MHz. In various embodiments disclosed herein, the frequency can be floated to values ​​different from this standard value. By floating the frequency while fixing the impedance match to a predetermined voltage, the plasma can be stabilized much more quickly, which may be important when using very short plasma strikes associated with certain deposition cycles.

[0102] In some embodiments, the pedestal 708 may be temperature controlled via a heater 710. Additionally, in some embodiments, pressure control of the deposition process station 700 may be provided by a butterfly valve 718. As shown in the embodiment of FIG. 7, the butterfly valve 718 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of the process station 700 may also be adjusted by varying the flow rate of one or more gases introduced to the process station 700.

[0103] FIG. 8 is a schematic diagram of an embodiment of a multi-station processing tool 800 according to certain embodiments. The multi-station processing tool 800 may be used to perform many of the operations described herein, including removing the core (e.g., operations 311, 511, and 1313), removing the additional planarization layer (e.g., operations 511 and 1311), depositing the second spacer layer (e.g., operations 313, 513, and 1315), and performing any metrology and feedback techniques associated with these processes. By performing these operations in the same multi-station processing tool 800 using the process flows described in FIG. 3, FIG. 5, and / or FIG. 13, the advantages described above may be achieved. For example, by removing the core (and additional planarization layer, if present) and depositing the second spacer layer in the same multi-station processing tool, the need to transfer the substrate between tools while the first spacer feature is mechanically compromised is eliminated. In various cases, these operations are performed in the same station of the multi-station processing tool 800, as described above in connection with FIG. 7.

[0104] In some embodiments, certain additional operations described herein may be performed in the multi-station tool 800 (e.g., in the same multi-station processing tool 800 used to remove the core and deposit the second spacer layer, e.g., within the same station of the multi-station processing tool 800). For example, in some embodiments, the multi-station processing tool 800 may also be used to deposit the first spacer layer.

[0105] The multi-station processing tool 800 includes an inbound load lock 802 and an outbound load lock 804, either or both of which may include a remote plasma source. A robot 806 is configured to move a wafer from a cassette loaded via a pod 808 to the inbound load lock 802 via an atmospheric port 810 at atmospheric pressure. The wafer is placed on a pedestal 812 in the inbound load lock 802 by the robot 806, the atmospheric port 810 is closed, and the load lock is pumped down. If the inbound load lock 802 includes a remote plasma source, the wafer may be exposed to a remote plasma process in the load lock before being introduced to the processing chamber 814. Additionally, the wafer may also be heated in the inbound load lock 802 as well, for example, to remove moisture and adsorbed gases. A chamber transfer port 816 to the processing chamber 814 is then opened, and another robot (not shown) places the wafer on a pedestal in the illustrated first station in the reactor for processing. Although the embodiment shown in FIG. 8 includes a load lock, it will be appreciated that in some embodiments the wafer may enter directly into a process station.

[0106] The illustrated processing chamber 814 includes four process stations, numbered 1 through 4 in the embodiment illustrated in FIG. 8. Each station has a heated pedestal (shown at 818 for station 1) and a gas line inlet. It will be understood that in some embodiments, each process station may have different or multiple purposes. Although the illustrated processing chamber 814 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments, a processing chamber may have three or fewer stations.

[0107] FIG. 8 also illustrates an embodiment of a wafer processing system 890 for transferring wafers within the processing chamber 814. In some embodiments, the wafer processing system 890 may transfer wafers between various process stations and / or between a process station and a load lock. It will be understood that any suitable wafer processing system may be employed. Non-limiting examples include a wafer carousel and a wafer handling robot. FIG. 8 also illustrates an embodiment of a system controller 850 employed to control the process conditions and hardware states of the process tool 800. The system controller 850 may include one or more memory devices 856, one or more mass storage devices 854, and one or more processors 852. The processor 852 may include a CPU or computer, analog and / or digital input / output connections, stepper motor control boards, etc.

[0108] In some embodiments, the system controller 850 controls all of the activity of the process tool 800. The system controller 850 executes system control software 858 stored in mass storage device 854, loaded into memory device 856, and executed on the processor 852. The system control software 858 may include instructions that control the timing, mixture of gases, chamber and / or station pressure, chamber and / or station temperature, purge conditions and timing, wafer temperature, RF power levels, RF frequency, substrate, pedestal, chuck and / or susceptor position, and other parameters of a particular process performed by the process tool 800. The system control software 858 may be configured in any suitable manner. For example, subroutines or control objects of the various process tool components may be written to control the operation of the process tool components necessary to perform the processes of the various process tools in accordance with the disclosed methods. The system control software 858 may be coded in any suitable computer readable programming language.

[0109] In some embodiments, the system control software 858 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each stage of a plasma enhanced atomic layer deposition (PEALD) process may include one or more instructions for execution by the system controller 850. Instructions for setting process conditions for a PEALD process stage may be included in a corresponding PEALD recipe stage. In some embodiments, the PEALD recipe stages may be sequenced such that all instructions for a PEALD process stage are executed simultaneously with that process stage. Similar recipe steps may be used for other types of processes.

[0110] Other computer software and / or programs stored on the mass storage device 854 and / or memory device 856 associated with the system controller 850 may also be employed in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0111] The substrate positioning program may include program code for process tool components used to place the substrate on the pedestal 818 and control the spacing between the substrate and other parts of the process tool 800 .

[0112] The process gas control program may include code for controlling the composition and flow rates of gases to stabilize the pressure in the process station, and optionally, code for flowing gases to one or more process stations prior to deposition or other processing. The process gas control program may include code for controlling the composition and flow rates of gases within any of the ranges of this disclosure. The pressure control program may include code for controlling the pressure in the process station, for example, by adjusting a throttle valve in the exhaust system of the process station, a gas flow rate to the process station, etc. The pressure control program may include code for maintaining the pressure in the process station within any of the pressure ranges of this disclosure.

[0113] The heater control program may include code for controlling current to a heating unit used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) to the substrate. The heater control program may include instructions for maintaining the temperature of the substrate within any of the ranges of the present disclosure.

[0114] The plasma control program may include code for setting the RF power levels and frequencies applied to the process electrodes at one or more process stations, for example using any of the RF power levels disclosed herein. The plasma control program may also include code for controlling the duration of each plasma exposure.

[0115] In some embodiments, there may be a user interface associated with the system controller 850. The user interface may include a display screen, a graphical software display of equipment and / or process status, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0116] In some embodiments, the parameters adjusted by the system controller 850 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF power levels, frequency, and exposure time), etc. These parameters may be provided to a user in the form of a recipe or may be entered using a user interface.

[0117] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 850 from various process tool sensors. Signals for controlling the process may be output at analog and digital output connections of the process tool 800. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, optical emission sensors (e.g., for OES implementations), laser interferometric sensors (e.g., for LSR implementations), optical CD metrology / scatterometry sensors (e.g., for scatterometry implementations), and the like. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions and control various processes.

[0118] Any suitable chamber can be used to carry out the disclosed embodiments. Examples of equipment include, but are not limited to, equipment from the STRIKER® product family, the ALTUS® product family, the VECTOR® product family, and / or the SPEED® product family, each available from Lam Research Corp., Fremont, Calif., or any of a variety of other commercially available processing systems. Two or more stations may perform the same function. Similarly, two or more stations may perform different functions. Each station can be designed / configured to perform a particular function / method or combination of functions / methods as desired. Any operations described herein as being performed in the same chamber may be performed in the same station of a multi-station tool, such that substrates do not need to be transferred between different stations for different operations.

[0119] FIG. 9 is a block diagram of a processing system suitable for performing thin film deposition, etching, cleaning, and other processes according to certain embodiments. System 900 includes a transfer module 903. The transfer module 903 provides a clean, pressurized environment to minimize the risk of contamination as the substrate being processed moves between various reactor modules. Two multi-station reactors 909 and 910 mounted on the transfer module 903 can each perform atomic layer deposition (ALD), chemical vapor deposition (CVD), core removal, and other processes described herein according to certain embodiments. The reactors 909 and 910 can include multiple stations 911, 913, 915, and 917 that can perform operations sequentially or non-sequentially according to the disclosed embodiments. Stations 911, 913, 915, and 917 can include a heated pedestal or substrate support, and one or more gas inlets or showerheads or distribution plates. As mentioned above, any of the operations described herein as occurring in the same chamber may be performed in the same station of a multi-station chamber so that there is no need to transfer the substrate between different stations for different operations.

[0120] The transfer module 903 may also be equipped with one or more single or multi-station modules 907 capable of performing plasma or chemical (non-plasma) cleaning, etching, deposition, or any other process described in connection with the disclosed method. The modules 907 may be used for various processes, in some cases, for example, to prepare the substrate for a deposition process. The modules 907 may also be designed / configured to perform various other processes, such as etching or polishing. The system 900 also includes one or more wafer source modules 901 in which wafers are stored before and after processing. An atmospheric robot (not shown) in the atmospheric transfer chamber 919 may first retrieve the wafer from the source module 901 to the load lock 921. A wafer transfer device (typically a robot arm unit) in the transfer module 903 moves the wafer from the load lock 921 to and between modules mounted on the transfer module 903.

[0121] In various embodiments, a system controller 929 is employed to control process conditions during processing. The controller 929 typically includes one or more memory devices and one or more processors. The processor may include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, etc.

[0122] The controller 929 may control all activity of the apparatus. The system controller 929 executes system control software that includes sets of instructions for controlling the timing, mixture of gases, chamber pressure, chamber temperature, wafer temperature, radio frequency (RF) power levels, wafer chuck or pedestal position, and other parameters of a particular process. Other computer programs stored in memory devices associated with the controller 929 may also be employed in some embodiments.

[0123] Typically, there is a user interface associated with the controller 929. The user interface may include a display screen, a graphical software display of equipment and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0124] The system control logic may be configured in any suitable manner. In general, logic may be designed or configured in hardware and / or software. Instructions for controlling the drive circuitry may be hard-coded or provided as software. Instructions may be provided by "programming." Such programming is understood to include any form of logic, including hard-coded logic in digital signal processors, application specific integrated circuits, and other devices that implement specific algorithms as hardware. Programming is also understood to include software or firmware instructions that may be executed on a general purpose processor. The system control software may be coded in any suitable computer readable programming language.

[0125] The computer program code for controlling the germanium-containing reducing agent pulses, hydrogen flow, and tungsten-containing precursor pulses, as well as other processes in the process sequence, can be written in any conventional computer readable programming language, such as assembly language, C, C++, Pascal, Fortran, or others. The compiled object code or script is executed by the processor to perform the tasks specified in the program. Also, as shown, the program code may be hard coded.

[0126] The parameters of the controller relate to process conditions such as, for example, process gas composition and flow rates, temperature, pressure, cooling gas pressure, substrate temperature, and chamber wall temperature. These parameters may be provided to a user in the form of a recipe and entered using a user interface. Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 929. Signals for controlling the process are output at analog and digital output connections of the deposition apparatus 900.

[0127] The system software may be designed or configured in many different ways. For example, various chamber component subroutines or control objects may be written to control the operation of the chamber components necessary to perform a deposition process (and possibly other processes) in accordance with the disclosed embodiments. Examples of programs or sections of programs for this purpose include substrate positioning code, process gas control code, pressure control code, and heater control code.

[0128] In some implementations, the controller 929 is part of a system, which may be part of the examples described above. Such a system may include semiconductor processing equipment including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of semiconductor wafers or substrates. The electronics may be referred to as a "controller" and may control various components or subparts of one or more systems. Depending on the processing requirements and / or type of system, the controller 929 may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings in some systems, RF matching circuit settings, frequency settings, flow settings, liquid delivery settings, position and motion settings, loading and unloading of wafers into and out of the tool, and loading and unloading of wafers into and out of other transfer tools and / or load locks connected or interlocked with the particular system.

[0129] Broadly speaking, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more processing steps during the manufacture of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0130] The controller may in some implementations be part of or connected to a computer that is integrated into, connected to, or otherwise networked to the system, or a combination thereof. For example, the controller may be all or part of a "cloud" or fab host computer system, which allows remote access of wafer processing. The computer may allow remote access to the system to monitor the current progress of a manufacturing operation, examine the history of past manufacturing operations, examine trends or performance criteria from multiple manufacturing operations, change parameters of a current process, set processing steps to track a current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as discussed above, the controller may be distributed, such as by including one or more individual controllers networked together and operating toward a common purpose, such as the processes and controls described herein. One example of a distributed controller for such purposes is one or more integrated circuits on the chamber that are located remotely (e.g., at the platform level or as part of a remote computer) and communicate with one or more integrated circuits that cooperatively control the processes in the chamber.

[0131] Examples of systems may include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0132] As described above, depending on the process step or steps being performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used to transport materials to and from containers of wafers to and from tool locations and / or load ports within a semiconductor manufacturing factory.

[0133] experiment Experimental results show that the disclosed methods can be used to minimize defects, such as defects associated with a first spacer feature collapsing before a second spacer layer is deposited. Figures 10A-10C and 11A-11C illustrate some of these results. Figures 10A-10C and 11A-11C characterize SEMs obtained from actual experiments.

[0134] FIG. 10A illustrates first spacer features fabricated according to the method of FIG. 1. Specifically, FIG. 10A shows the first spacer features after operation 109 of FIG. 1 (e.g., after performing a wet clean on the substrate to remove unwanted material generated during the etch-back of the first spacer layer). As shown in FIG. 10A, the first spacer features are not vertical. Rather, a pair of adjacent first spacer features are tilted inwardly toward one another. Such tilting is undesirable.

[0135] Figures 10B and 10C are top views of the substrate shown in Figure 10A. Figure 10B shows the substrate after operation 103 of Figure 1 (e.g., after the first spacer layer has been etched back and before the cores have been removed), and Figure 10C shows the substrate after operation 109 (e.g., after the cores have been removed and the substrate has been cleaned). The circled portion of Figure 10C shows an area where the first spacer features (shown as white lines) exhibit bowing / collapse. The bowing / collapse can be seen based on the uneven thickness of the dark grey lines between adjacent sets of first spacer features. These results clearly demonstrate the bowing problem described herein.

[0136] In contrast, Figure 11A shows a first spacer feature covered with a second spacer layer, fabricated according to the method of Figure 3. Specifically, Figure 11A shows the first spacer feature / second spacer layer after act 313 of Figure 3 (e.g., after the second spacer has been deposited). The first spacer feature and the second spacer layer form adjacent pairs of lines that are perpendicular. The adjacent pairs of lines are not inwardly tilted relative to one another, representing a substantial improvement over the results of Figure 10A.

[0137] Figures 11B and 11C show top views of the substrate shown in Figure 11A. Figure 11B shows the substrate after act 303 of Figure 3 (e.g., after the first spacer layer has been etched back) and Figure 11C shows the substrate after act 313 (e.g., after the second spacer layer has been deposited). Compared to the lines shown in Figure 10C, the lines in Figure 11C show that the thickness is much more uniform and the lines / features are vertical and not bent / fallen.

[0138] The results shown in Figures 10A-C and 11A-C demonstrate that the disclosed process flow can be used to reduce the number of manufacturing defects (e.g., defects especially related to line bending / collapse) when performing spacer-on-spacer self-aligned quadruple patterning techniques. Reducing defects translates into improved process efficiency and reduced costs.

[0139] conclusion Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Thus, the present embodiments are to be considered as illustrative and not restrictive, and the present embodiments are not to be limited to the details given herein. The present disclosure may be realized in the following forms. [Form 1] 1. A method for processing a substrate, comprising: a) i. a base material; ii. a core disposed on said substrate material, said core having vertically oriented sidewalls; iii. a first spacer material covering the sidewall of the core; and receiving a substrate comprising: b) removing the core, thereby forming first spacer features from the first spacer material that previously covered the sidewalls of the core; and c) depositing a second spacer layer over the first spacer features; and Preparation, A method wherein (b) and (c) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (b) and (c). [Form 2] 2. The method of claim 1, further comprising cleaning the substrate to remove unwanted material, the substrate being cleaned with a wet cleaning operation prior to (b). [Form 3] 2. The method of claim 1, further comprising depositing a first spacer layer over the core, the first spacer layer comprising the first spacer material, and etching back the first spacer layer to remove the first spacer material from horizontal surfaces while leaving the first spacer material on the sidewalls of the core. [Form 4] 2. The method of claim 1, further comprising taking measurements to determine the time at which the core is removed during (b). [Form 5] 5. The method of claim 4, wherein performing the measurement comprises performing optical emission spectroscopy. [Form 6] 6. The method of claim 5, wherein performing optical emission spectroscopy comprises monitoring a signal associated with the presence of carbon dioxide in the reaction chamber. [Form 7] 5. The method of claim 4, wherein performing the measurements includes performing laser interferometry. [Form 8] A method according to any one of claims 1 to 7, further comprising performing scatterometry after (b) and before (c) to measure a width of one or more of the first spacer features. [Form 9] 8. The method of any one of claims 1 to 7, wherein removing the core comprises exposing the substrate to an oxygen-containing plasma to ash the core. [Form 10] 8. The method of any one of claims 1 to 7, wherein the core comprises carbon, the carbon of the core having a post-deposition blanket stress of about 50 MPa or less and a Young's modulus of about 30 GPa or more. [Form 11] 1. A method of processing a substrate, the method comprising: a) i. a base material; ii. a core disposed on said substrate material, said core having vertically oriented sidewalls; iii. a first spacer material covering the sidewall of the core; and iv. a planarization layer disposed over the core and the first spacer material, wherein a top surface portion of the planarization layer is substantially flat; and v. a mask layer disposed over the planarization layer; vi. an opening defined in the mask layer and the planarization layer and disposed above the first spacer material covering one of the sidewalls of one of the cores; receiving a substrate comprising: b) removing the first spacer material at a location corresponding to the opening; and c) removing the mask layer; and d) removing the core and the planarizing layer, thereby forming first spacer features from remaining first spacer material not removed in (b), and not forming first spacer features at the locations corresponding to the openings; e) depositing a second spacer layer over the first spacer features; Equipped with A method wherein (d) and (e) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (d) and (e). [Form 12] 12. The method of claim 11, wherein the core and the planarizing layer are removed simultaneously. [Form 13] 12. The method of claim 11, wherein removing the core and the planarization layer comprises exposing the substrate to an oxygen-containing plasma to ash the core and the planarization layer. [Form 14] 14. The method of any one of claims 11 to 13, further comprising taking measurements to determine the time at which the core and / or planarization layer is removed in (d). [Form 15] 14. A method according to any one of claims 11 to 13, further comprising performing scatterometry after (d) and before (e) to measure a width of one or more of the first spacer features. [Form 16] 1. A method of processing a substrate, the method comprising: a) i. a base material; ii. a core disposed on said substrate material, said core having vertically oriented sidewalls; iii. a first spacer material covering the sidewall of the core; and iv. a planarization layer disposed over the underlying material, the core, and the first spacer material, the planarization layer being patterned to form exposed and protected regions; and receiving a substrate comprising: b) trimming the first spacer material to reduce a thickness of the first spacer material in the exposed areas, but leaving the first spacer material in the protected areas untrimmed; and c) removing the planarization layer and the core, thereby forming first spacer features from the first spacer material having non-uniform critical dimensions; and d) forming a second spacer layer over the first spacer features; and Equipped with A method wherein (c) and (d) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (c) and (d). [Form 17] 17. The method of claim 16, further comprising etching back the second spacer layer such that the second spacer layer is removed from areas between adjacent first spacer features. [Form 18] 18. The method of claim 17, further comprising removing the first spacer features, thereby forming second spacer features from the second spacer layer; A method, wherein the distance between adjacent second spacer features is non-uniform due to non-uniform critical dimensions of said first spacer features. [Form 19] 19. The method of any one of claims 16 to 18, wherein the planarization layer and the core are removed simultaneously. [Form 20] 20. The method of claim 19, wherein removing the core and the planarization layer comprises exposing the substrate to an oxygen-containing plasma to ash the core and the planarization layer.

Claims

1. 1. A method for processing a substrate, comprising: a) i. a base material; ii. a core disposed on the substrate and having vertically oriented sidewalls; iii. a first spacer material covering the sidewall of the core; receiving a substrate comprising: b) removing the core, thereby forming first spacer features from the first spacer material that previously covered the sidewalls of the core; c) depositing a second spacer layer over the first spacer features; Preparation, (b) and (c) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (b) and (c); The method further comprising cleaning the substrate to remove unwanted material, the substrate being cleaned in a wet cleaning operation prior to (b).

2. 1. A method for processing a substrate, comprising: a) i. a base material; ii. a core disposed on the substrate and having vertically oriented sidewalls; iii. a first spacer material covering the sidewall of the core; receiving a substrate comprising: b) removing the core, thereby forming first spacer features from the first spacer material that previously covered the sidewalls of the core; c) depositing a second spacer layer over the first spacer features; Preparation, (b) and (c) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (b) and (c); The method further comprising taking measurements to determine the time at which the core is removed during (b).

3. 1. A method for processing a substrate, comprising: a) i. a base material; ii. a core disposed on the substrate and having vertically oriented sidewalls; iii. a first spacer material covering the sidewall of the core; receiving a substrate comprising: b) removing the core, thereby forming first spacer features from the first spacer material that previously covered the sidewalls of the core; c) depositing a second spacer layer over the first spacer features; Preparation, (b) and (c) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (b) and (c); The method further comprising performing scatterometry after (b) and before (c) to measure a width of one or more of the first spacer features.

4. 1. A method for processing a substrate, comprising: a) i. a base material; ii. a core disposed on the substrate and having vertically oriented sidewalls; iii. a first spacer material covering the sidewall of the core; receiving a substrate comprising: b) removing the core, thereby forming first spacer features from the first spacer material that previously covered the sidewalls of the core; c) depositing a second spacer layer over the first spacer features; Preparation, (b) and (c) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (b) and (c); The method of claim 1, wherein the core comprises carbon, the carbon of the core having a post-deposition blanket stress of 50 MPa or less and a Young's modulus of 30 GPa or more.

5. 5. The method of claim 1, further comprising depositing a first spacer layer over the core, the first spacer layer comprising the first spacer material, and etching back the first spacer layer to remove the first spacer material from horizontal surfaces while leaving the first spacer material on the sidewalls of the core.

6. The method of claim 2 , wherein performing the measurement comprises performing optical emission spectroscopy.

7. 7. The method of claim 6, wherein performing optical emission spectroscopy comprises monitoring a signal related to the presence of carbon dioxide in the reaction chamber.

8. The method of claim 2 , wherein performing metrology comprises performing laser interferometry.

9. 5. The method of claim 1, wherein removing the core comprises exposing the substrate to an oxygen-containing plasma to ash the core.

10. 1. A method of processing a substrate, the method comprising: a) i. a base material; ii. a core disposed on the substrate and having vertically oriented sidewalls; iii. a first spacer material covering the sidewall of the core; iv. a planarization layer disposed over the core and the first spacer material, a top surface portion of the planarization layer being flat; v. a mask layer disposed over the planarization layer; vi. an opening defined in the mask layer and the planarization layer and disposed above the first spacer material covering one of the sidewalls of one of the cores; receiving a substrate comprising: b) removing the first spacer material at a location corresponding to the opening; c) removing the mask layer; and d) removing the core and the planarizing layer, thereby forming first spacer features from remaining first spacer material not removed in (b), while not forming first spacer features at the locations corresponding to the openings; e) depositing a second spacer layer over the first spacer features; Equipped with A method wherein (d) and (e) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (d) and (e).

11. The method of claim 10 , wherein the core and the planarization layer are removed simultaneously.

12. 11. The method of claim 10, wherein removing the core and the planarization layer comprises exposing the substrate to an oxygen-containing plasma to ash the core and the planarization layer.

13. 11. The method of claim 10, further comprising taking measurements to determine the time at which the core and / or planarization layer is removed in (d).

14. 11. The method of claim 10, further comprising performing scatterometry after (d) and before (e) to measure a width of one or more of the first spacer features.

15. 1. A method of processing a substrate, the method comprising: a) i. a base material; ii. a core disposed on the substrate and having vertically oriented sidewalls; iii. a first spacer material covering the sidewall of the core; iv. a planarization layer disposed over the underlayer material, the core, and the first spacer material, the planarization layer being patterned to form exposed and protected regions; receiving a substrate comprising: b) trimming the first spacer material to reduce a thickness of the first spacer material in the exposed areas, but leaving the first spacer material in the protected areas untrimmed; c) removing the planarization layer and the core, thereby forming first spacer features from the first spacer material having non-uniform critical dimensions; and d) forming a second spacer layer over the first spacer features; and Equipped with A method wherein (c) and (d) are performed in the same reaction chamber, and the substrate is not removed from the reaction chamber between (c) and (d).

16. 16. The method of claim 15, further comprising etching back the second spacer layer such that the second spacer layer is removed from areas between adjacent first spacer features.

17. 17. The method of claim 16, further comprising removing the first spacer feature, thereby forming a second spacer feature from the second spacer layer; A method wherein the distance between adjacent second spacer features is non-uniform due to non-uniform critical dimensions of said first spacer features.

18. 16. The method of claim 15, wherein the planarization layer and the core are removed simultaneously.

19. 20. The method of claim 18, wherein removing the core and the planarization layer comprises exposing the substrate to an oxygen-containing plasma to ash the core and the planarization layer.

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