Semiconductor Device

Abstract

To provide a semiconductor device in which a parasitic inductance is reduced and a parasitic resistance is reduced.SOLUTION: A semiconductor device A1 includes: a semiconductor element 1; a semiconductor element 2; a control element 3; a leadframe 4 including a plurality of leads; a wire 5B bonded to a source electrode 12 of the semiconductor element 1; and a wire 5C bonded to a drain electrode 21 of the semiconductor element 2. The plurality of leads include a lead 4A on which the semiconductor element 1 is mounted, a lead 4B on which the semiconductor element 2 is mounted, and a lead 4C on which the control element 3 is mounted. The lead 4A and the lead 4B overlap with each other as viewed in an x direction, and the lead 4C overlaps with both the lead 4A and the lead 4B as viewed in a y direction. The lead 4A includes a die pad portion 411 to which the semiconductor element 1 is bonded, and a bonding portion 412 to which the wire 5B is bonded. The bonding portion 412 is located between the semiconductor element 1 and the semiconductor element 2 as viewed in a z direction, and the wire 5C is bonded thereto.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device having a plurality of semiconductor elements mounted thereon. [Background technology]

[0002] Conventionally, semiconductor devices in which multiple semiconductor elements are molded in a single resin member are known. Such semiconductor devices are called system-in-packages. Patent Document 1 discloses a semiconductor device in which two switching elements and a control IC are packaged together. The control IC is a semiconductor element that controls each switching element. Each switching element performs switching operation in response to a signal from the control IC. Such semiconductor devices are mounted on a circuit board of an electronic device, for example, and used in power supply circuits such as DC / DC converters. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-218309 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, with the trend toward more energy-efficient and higher performance electronic devices, semiconductor devices are being required to reduce power consumption and improve switching response. Reducing parasitic inductance and parasitic resistance is effective in reducing power consumption and improving switching response.

[0005] The present disclosure has been devised in view of the above circumstances, and its purpose is to provide a semiconductor device in which multiple semiconductor elements are packaged together, and which aims to reduce parasitic inductance and parasitic resistance. [Means for solving the problem]

[0006] The semiconductor device provided by the present disclosure comprises: a first semiconductor element having a first main surface and a first back surface spaced apart in a thickness direction, and a first drain electrode, a first source electrode, and a first gate electrode arranged on the first main surface; a second semiconductor element having a second main surface and a second back surface spaced apart in the thickness direction, and a second drain electrode, a second source electrode, and a second gate electrode arranged on the second main surface; a control element conducting to the first gate electrode and the second gate electrode; and a lead frame including a plurality of leads spaced apart from each other, wherein the plurality of leads include a first lead facing the first back surface and carrying the first semiconductor element, a second lead facing the second back surface and carrying the second semiconductor element, and a third lead carrying the control element, wherein the first lead and the second lead overlap each other when viewed in a first direction perpendicular to the thickness direction, and the third lead overlaps both the first lead and the second lead when viewed in a second direction perpendicular to both the thickness direction and the first direction. [Effects of the Invention]

[0007] According to the semiconductor device of the present disclosure, in a semiconductor device in which a plurality of semiconductor elements and a control element are packaged together, parasitic inductance and parasitic resistance can be reduced. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a perspective view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. [Figure 5] FIG. 3 is a cross-sectional view taken along line VV in FIG. 2. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7]FIG. 1 is a circuit configuration diagram showing a semiconductor element according to a first embodiment. [Figure 8] FIG. 10 is a plan view showing a semiconductor device according to a second embodiment. [Figure 9] FIG. 10 is a plan view showing a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a cross-sectional view taken along line XX in FIG. 9. [Figure 11] FIG. 11 is a cross-sectional view showing a semiconductor device according to a modified example of the third embodiment. [Figure 12] FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 10 is a perspective view showing a semiconductor device according to a modified example. [Figure 14] FIG. 10 is a bottom view showing a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the accompanying drawings. Identical or similar components are designated by the same reference numerals and will not be described again.

[0010] In this disclosure, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B when viewed in a certain direction" and "an object A overlaps a part of an object B when viewed in a certain direction." Furthermore, terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not necessarily intended to assign an order to the objects.

[0011] First Embodiment A semiconductor device A1 according to a first embodiment will be described with reference to Figures 1 to 7. The semiconductor device A1 is used in a power converter such as an inverter or converter.

[0012] First, the module structure of the semiconductor device A1 according to the first embodiment will be described with reference to Figures 1 to 6. In its module structure, the semiconductor device A1 includes two semiconductor elements 1 and 2, a control element 3, a lead frame 4, a plurality of connecting members 5, and a sealing member 6. In the semiconductor device A1, the lead frame 4 includes a plurality of leads 4A to 4J that are separated from one another. The plurality of connecting members 5 include a plurality of wires 5A to 5N.

[0013] FIG. 1 is a perspective view showing the semiconductor device A1, as viewed from the bottom side. FIG. 2 is a plan view showing the semiconductor device A1, with the sealing member 6 indicated by an imaginary line (two-dot chain line). FIG. 3 is a bottom view showing the semiconductor device A1, with the sealing member 6 indicated by an imaginary line (two-dot chain line). FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a cross-sectional view taken along line VV in FIG. 2. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 2. Note that multiple connection members 5 are not shown in FIGS. 4 to 6.

[0014] For ease of explanation, three mutually orthogonal directions are defined as the x-direction, y-direction, and z-direction. The z-direction is the thickness direction of the semiconductor device A1. The x-direction is the left-right direction in the plan view of the semiconductor device A1 (see FIG. 2). The y-direction is the up-down direction in the plan view of the semiconductor device A1 (see FIG. 2). One of the x-directions is the x1-direction, and the other of the x-directions is the x2-direction. Similarly, one of the y-directions is the y1-direction, the other of the y-directions is the y2-direction, one of the z-directions is the z1-direction, and the other of the z-directions is the z2-direction. In the present disclosure, the z1-direction may be referred to as down, and the z2-direction as up. The x-direction and y-direction correspond to the "first direction" and "second direction" described in the claims.

[0015] The semiconductor device A1 is mounted on a circuit board of an electronic device, etc. The semiconductor device A1 has, for example, a surface-mount package structure, and in this embodiment, for example, a package format called SON (Small Outline Non-lead).

[0016] The two semiconductor elements 1 and 2 are elements that exert the electrical functions of the semiconductor device A1. Each of the semiconductor elements 1 and 2 is a switching element, for example, an n-type MOSFET. Note that each of the semiconductor elements 1 and 2 is not limited to an n-type MOSFET, but may be a p-type MOSFET. Furthermore, each of the semiconductor elements 1 and 2 is not limited to a MOSFET, but may be a field effect transistor including a MISFET (Metal-Insulator-Semiconductor FET) or a HEMT (High Electron Mobility Transistor), a bipolar transistor, or another transistor such as an IGBT (Insulated Gate Bipolar Transistor). It is also possible.

[0017] As shown in FIG. 2, each of the semiconductor elements 1 and 2 has, for example, a rectangular shape in a plan view (as viewed in the z direction). The semiconductor element 1 is mounted on a lead 4A, and the semiconductor element 2 is mounted on a lead 4B. The two semiconductor elements 1 and 2 are aligned in the x direction as shown in FIGS. 2 and 4. The constituent material of each of the semiconductor elements 1 and 2 includes, for example, GaN (gallium nitride). Note that the constituent material of each of the semiconductor elements 1 and 2 is not limited to GaN and may include, for example, SiC (silicon carbide), Si (silicon), GaAs (gallium arsenide), or Ga2O3 (gallium oxide). The semiconductor element 1 corresponds to a "first semiconductor element" and the semiconductor element 2 corresponds to a "second semiconductor element" as defined in the claims.

[0018] The semiconductor element 1 has an element principal surface 1a and an element rear surface 1b. The element principal surface 1a and the element rear surface 1b are spaced apart in the z direction. The element principal surface 1a faces the z2 direction, and the element rear surface 1b faces the z1 direction. The element rear surface 1b faces the lead 4A. The element principal surface 1a corresponds to the "first principal surface" in the claims, and the element rear surface 1b corresponds to the "first rear surface" in the claims.

[0019] The semiconductor element 1 is a three-terminal element having three electrodes. In this embodiment, the semiconductor element 1 includes a drain electrode 11, a source electrode 12, and a gate electrode 13. The drain electrode 11, the source electrode 12, and the gate electrode 13 are arranged on the main surface 1a of the element. The drain electrode 11 corresponds to a "first drain electrode" in the claims, the source electrode 12 corresponds to a "first source electrode" in the claims, and the gate electrode 13 corresponds to a "first gate electrode" in the claims.

[0020] The drain electrode 11 includes a plurality of pad portions 111. Each pad portion 111 is strip-shaped and extends in the x direction. Each pad portion 111 is electrically connected to a drain region inside the semiconductor element 1. The source electrode 12 includes a plurality of pad portions 121. Each pad portion 121 is strip-shaped and extends in the x direction. Each pad portion 121 is electrically connected to a source region inside the semiconductor element 1. The plurality of pad portions 111 and the plurality of pad portions 121 are aligned in the y direction and arranged alternately. The gate electrode 13 includes two pad portions 131 and 132. Each pad portion 131 and 132 is electrically connected to a gate region (channel region) inside the semiconductor element 1. Each pad portion 131 and 132 is arranged at an edge portion farther from the semiconductor element 2 in the x direction. The two pad portions 131 and 132 are spaced apart in the y direction. In the example shown in FIG. 2, the pad portion 131 is arranged at a corner on the x1 and y1 direction sides in a plan view. The pad portion 132 is arranged at a corner on the x1 and y2 direction sides in a plan view. The two pad portions 131 and 132 are both at the same potential. Note that the gate electrode 13 does not necessarily have to include the pad portion 132. Each of the pad portions 131 and 132 corresponds to a "first pad portion" in the claims.

[0021] A drive signal is input to the semiconductor element 1 from the control element 3, and the semiconductor element 1 switches between a conductive state and a cut-off state in response to the drive signal (performs a switching operation). The drive signal is input to the gate electrode 13. The semiconductor element 1 corresponds to a "first semiconductor element" set forth in the claims.

[0022] The semiconductor element 2 has an element principal surface 2a and an element rear surface 2b. The element principal surface 2a and the element rear surface 2b are spaced apart in the z direction. The element principal surface 2a faces the z2 direction, and the element rear surface 2b faces the z1 direction. The element rear surface 2b faces the lead 4B. The element principal surface 2a corresponds to the "second principal surface" in the claims, and the element rear surface 2b corresponds to the "second rear surface" in the claims.

[0023] The semiconductor element 2 is a three-terminal element having three electrodes. In this embodiment, the semiconductor element 2 includes a drain electrode 21, a source electrode 22, and a gate electrode 23. The drain electrode 21, the source electrode 22, and the gate electrode 23 are arranged on the element main surface 2a. The drain electrode 21 corresponds to a "second drain electrode" in the claims, the source electrode 22 corresponds to a "second source electrode" in the claims, and the gate electrode 23 corresponds to a "second gate electrode" in the claims.

[0024] The drain electrode 21 includes a plurality of pad portions 211. Each pad portion 211 is strip-shaped and extends in the x direction. Each pad portion 211 is electrically connected to a drain region inside the semiconductor element 2. The source electrode 22 includes a plurality of pad portions 221. Each pad portion 221 is strip-shaped and extends in the x direction. Each pad portion 221 is electrically connected to a source region inside the semiconductor element 2. The plurality of pad portions 211 and the plurality of pad portions 221 are aligned in the y direction and arranged alternately. The gate electrode 23 includes two pad portions 231 and 232. Each pad portion 231 and 232 is electrically connected to a gate region (channel region) inside the semiconductor element 2. Each pad portion 231 and 232 is arranged at an edge portion farther from the semiconductor element 1 in the x direction. The two pad portions 231 and 232 are spaced apart in the y direction. In the example shown in FIG. 2, the pad portion 231 is arranged at a corner on the x2 and y1 direction sides in a plan view. The pad portion 232 is arranged at a corner on the x2 and y2 direction sides in a plan view. The two pad portions 231 and 232 are both at the same potential. Note that the gate electrode 23 does not necessarily have to include the pad portion 232. Each of the pad portions 231 and 232 corresponds to a "second pad portion" in the claims.

[0025] A drive signal is input to the semiconductor element 2 from the control element 3, and the semiconductor element 2 switches between a conductive state and a cut-off state in response to the drive signal (performs a switching operation). The drive signal is input to the gate electrode 23. The semiconductor element 2 corresponds to a "second semiconductor element" recited in the claims.

[0026] The control element 3 controls the switching operations of the two semiconductor elements 1 and 2. The control element 3 generates a drive signal for driving each of the semiconductor elements 1 and 2, and outputs the generated drive signal to each of the semiconductor elements 1 and 2. The control element 3 is, for example, an IC (integrated circuit). The control element 3 is a semiconductor element that includes a semiconductor material. The control element 3 is mounted on a lead 4C. When viewed in the y direction, the control element 3 overlaps a portion of each of the semiconductor elements 1 and 2.

[0027] The control element 3 has a main surface 3a and a rear surface 3b. The main surface 3a and the rear surface 3b are spaced apart in the z direction. The main surface 3a faces the z2 direction, and the rear surface 3b faces the z1 direction. The rear surface 3b faces the lead 4C.

[0028] The control element 3 includes an element electrode 31. The element electrode 31 is disposed on the element main surface 3a. The element electrode 31 includes a plurality of pad portions 311 to 318. Each of the pad portions 311 to 318 is an input terminal or an output terminal of the control element 3. Each of the pad portions 311 to 318 is a portion to which a connection member 5 is bonded. The arrangement of the pad portions 311 to 318 in a plan view is not limited to the example shown in FIG. 2.

[0029] The pad portion 311 is joined to one end of a wire 5L and is electrically connected to the lead 4H via the wire 5L. The pad portion 312 is joined to one end of a wire 5J and is electrically connected to the lead 4C via the wire 5J. The pad portion 313 is joined to one end of a wire 5M and is electrically connected to the lead 4I via the wire 5M. The pad portion 314 is joined to one end of a wire 5N and is electrically connected to the lead 4J via the wire 5N. The pad portion 315 is joined to one end of a wire 5F and is electrically connected to the gate electrode 13 (pad portion 131) of the semiconductor element 1 via the wire 5F. The pad portion 316 is joined to one end of a wire 5H and is electrically connected to the gate electrode 23 (pad portion 231) of the semiconductor element 2 via the wire 5H. The pad portion 317 is joined to one end of a wire 5K and is electrically connected to the lead 4G via the wire 5K. One end of a wire 5E is joined to the pad portion 318, and the pad portion 318 is electrically connected to the lead 4A via the wire 5E.

[0030] The lead frame 4 has two semiconductor elements 1 and 2 and a control element 3 mounted thereon. The lead frame 4, together with a plurality of connection members 5, forms a conductive path in the semiconductor device A1. The lead frame 4 is made of a conductive material. The constituent material of the lead frame 4 is, for example, a metal containing Cu (copper). The constituent material may be a metal other than Cu. Furthermore, the surface of the lead frame 4 may be appropriately plated. As shown in FIG. 2, the lead frame 4 includes a plurality of leads 4A to 4J spaced apart from one another. A portion of each of the leads 4A to 4J is exposed from the sealing member 6, and the exposed portion serves as a terminal when the semiconductor device A1 is mounted on an external circuit board.

[0031] The lead 4A carries the semiconductor element 1. One ends of a plurality of wires 5B are joined to the lead 4A, and the lead 4A is electrically connected to the source electrode 12 of the semiconductor element 1 via the wires 5B. One ends of a plurality of wires 5C are joined to the lead 4A, and the lead 4A is electrically connected to the drain electrode 21 of the semiconductor element 2 via the wires 5C. One end of a wire 5E is joined to the lead 4A, and the lead 4A is electrically connected to the element electrode 31 (pad portion 318) of the control element 3 via the wire 5E. The lead 4B carries the semiconductor element 2. One ends of a plurality of wires 5D are joined to the lead 4B, and the lead 4C is electrically connected to the source electrode 22 of the semiconductor element 2 via the wires 5D. The lead 4C carries the control element 3. One end of a wire 5J is joined to the lead 4C, and the lead 4C is electrically connected to the element electrode 31 (pad portion 312) of the control element 3 via the wire 5J. The lead 4D is joined to one end of each of a plurality of wires 5A and is electrically connected to the drain electrode 11 of the semiconductor element 1 via the plurality of wires 5A. The lead 4E is joined to one end of a wire 5G and is electrically connected to the gate electrode 13 (pad portion 132) of the semiconductor element 1 via the wire 5G. The lead 4F is joined to one end of a wire 5I and is electrically connected to the gate electrode 23 (pad portion 232) of the semiconductor element 2 via the wire 5I. The lead 4G is joined to one end of a wire 5K and is electrically connected to the element electrode 31 (pad portion 317) of the control element 3 via the wire 5K. The lead 4H is joined to one end of a wire 5L and is electrically connected to the element electrode 31 (pad portion 311) of the control element 3 via the wire 5L. The lead 4I is joined to one end of a wire 5M and is electrically connected to the element electrode 31 (pad portion 313) of the control element 3 via the wire 5M. The lead 4J is connected to one end of a wire 5N, and is electrically connected to the element electrode 31 (pad portion 314) of the control element 3 via the wire 5N.

[0032] 2 and 4, the lead 4A includes a die pad portion 411 and a bonding portion 412. The die pad portion 411 and the bonding portion 412 are integrally formed. The die pad portion 411 and the bonding portion 412 may be separated.

[0033] The die pad portion 411 is a portion on which the semiconductor element 1 is mounted. The semiconductor element 1 is bonded to the die pad portion 411 via a bonding material (not shown). The die pad portion 411 faces the element back surface 1b. The die pad portion 411 corresponds to a "first die pad portion" recited in the claims.

[0034] The bonding portion 412 is a portion to which any one of the plurality of connection members 5 is bonded. In this embodiment, one end of each of a plurality of wires 5B, a plurality of wires 5C, and a wire 5E is bonded to the bonding portion 412. The bonding portion 412 is electrically connected to the source electrode 12 of the semiconductor element 1 via the plurality of wires 5B, and is electrically connected to the drain electrode 21 of the semiconductor element 2 via the plurality of wires 5C. The bonding portion 412 is also electrically connected to the element electrode 31 (pad portion 318) of the control element 3 via the wire 5E. The bonding portion 412 is disposed between the semiconductor element 1 and the semiconductor element 2 in a plan view. The bonding portion 412 corresponds to a "first bonding portion" recited in the claims.

[0035] 2 and 4, the lead 4B includes a die pad portion 421 and a bonding portion 422. The die pad portion 421 and the bonding portion 422 are integrally formed. Alternatively, the die pad portion 421 and the bonding portion 422 may be separate.

[0036] The die pad portion 421 is a portion on which the semiconductor element 2 is mounted. The semiconductor element 2 is bonded to the die pad portion 421 via a bonding material (not shown). The die pad portion 421 faces the element back surface 2b. The die pad portion 421 corresponds to a "second die pad portion" recited in the claims.

[0037] The bonding portion 422 is a portion to which one of the plurality of connection members 5 is bonded. In this embodiment, one end of each of the plurality of wires 5D is bonded to the bonding portion 422. The bonding portion 422 is electrically connected to the source electrode 22 of the semiconductor element 2 via the plurality of wires 5D. The bonding portion 422 corresponds to a "second bonding portion" recited in the claims.

[0038] As shown in FIG. 2, both lead 4A and lead 4B are disposed further in the y2 direction than lead 4C. Both lead 4A and lead 4B overlap lead 4C when viewed in the y direction, but do not overlap lead 4C when viewed in the x direction. Furthermore, lead 4A and lead 4B are adjacent to each other in the x direction. Lead 4A and lead 4B overlap when viewed in the x direction.

[0039] Lead 4E and lead 4F overlap each other when viewed in the x direction. As shown in Fig. 2, lead 4E is arranged near pad portion 132 in plan view, and is closer to pad portion 132 than the other leads (except lead 4A). As shown in Fig. 2, lead 4F is arranged near pad portion 232 in plan view, and is closer to pad portion 132 than the other leads (except lead 4B).

[0040] The bonding portion 422 of the lead 4D and the lead 4B overlap each other when viewed in the x direction. Furthermore, the lead 4D, the lead 4A, and the lead 4B overlap each other when viewed in the x direction, and are arranged in this order in the x direction. The lead 4D is electrically connected to the drain electrode 11 of the semiconductor element 1, the lead 4A is electrically connected to the source electrode 12 of the semiconductor element 1 and the drain electrode 21 of the semiconductor element 2, and the lead 4B is electrically connected to the source electrode 22 of the semiconductor element 2. Therefore, the two The current path from the lead 4D to the lead 4B via the semiconductor elements 1 and 2 is formed along the x direction.

[0041] Lead 4E, lead 4D, lead 4G, and lead 4H overlap one another when viewed in the y direction and are arranged in this order in the y direction. Also, lead 4F, bonding portion 422 of lead 4B, lead 4I, and lead 4J overlap one another when viewed in the y direction and are arranged in this order in the y direction.

[0042] Lead 4G, lead 4H, lead 4I, and lead 4J each overlap lead 4C when viewed in the x direction. The two leads 4G and 4H are arranged further in the x1 direction than lead 4C, and the two leads 4I and 4J are arranged further in the x2 direction than lead 4C. Lead 4G and lead 4I overlap each other when viewed in the x direction. Lead 4H and lead 4J overlap each other when viewed in the x direction.

[0043] As shown in FIGS. 3 to 6, each lead 4A to 4J has a recess 49 formed therein. The recess 49 is a portion of each lead 4A to 4J that is recessed in the z2 direction from a surface facing the z1 direction. As shown in FIG. 3, the recess 49 is formed along the outer periphery of each lead 4A to 4J in plan view. The recess 49 is covered with a sealing member 6. In the examples shown in FIGS. 4 to 6, the recess 49 has a curved wall surface, but it does not have to be curved. The recess 49 is provided to prevent the leads 4A to 4J from coming off.

[0044] In this embodiment, lead 4A corresponds to the "first lead" in the claims. Lead 4B corresponds to the "second lead" in the claims. Lead 4C corresponds to the "third lead" in the claims. Lead 4D corresponds to the "fourth lead" in the claims. Lead 4E corresponds to the "fifth lead" in the claims. Lead 4F corresponds to the "sixth lead" in the claims. Each of leads 4G to 4J corresponds to the "seventh lead" in the claims.

[0045] Each of the plurality of connection members 5 electrically connects two spaced apart members. Each of the connection members 5 is made of a conductive material. As shown in FIG. 2, the plurality of connection members 5 includes a plurality of wires 5A to 5N. Each of the wires 5A to 5N is a so-called bonding wire. The material of each of the wires 5A to 5N may be, for example, a metal containing Au (gold), a metal containing Al (aluminum), or a metal containing Cu.

[0046] As shown in FIG. 2, one end of each of the plurality of wires 5A is bonded to the pad portion 111 of the drain electrode 11 of the semiconductor element 1, and the other end is bonded to the lead 4D. Each of the plurality of wires 5B is bonded to the pad portion 121 of the source electrode 12 of the semiconductor element 1, and the other end is bonded to the bonding portion 412 of the lead 4A. Each of the plurality of wires 5C is bonded to the pad portion 211 of the drain electrode 21 of the semiconductor element 2, and the other end is bonded to the bonding portion 412 of the lead 4A. Each of the plurality of wires 5D is bonded to the pad portion 221 of the source electrode 22 of the semiconductor element 2, and the other end is bonded to the bonding portion 422 of the lead 4B. One end of the wire 5E is bonded to the pad portion 318 of the element electrode 31 of the control element 3, and the other end is bonded to the bonding portion 412 of the lead 4A. One end of the wire 5F is joined to the pad portion 315 of the element electrode 31 of the control element 3, and the other end is joined to the pad portion 131 of the gate electrode 13 of the semiconductor element 1. The wire 5G is joined to the lead 4E, and the other end is joined to the pad portion 132 of the gate electrode 13 of the semiconductor element 1. The wire 5H is joined to the pad portion 316 of the element electrode 31 of the control element 3, and the other end is joined to the pad portion 231 of the gate electrode 23 of the semiconductor element 2. The wire 5I is joined to the lead 4F, and the other end is joined to the pad portion 232 of the gate electrode 23 of the semiconductor element 2. The wire 5J is joined to the pad portion 312 of the element electrode 31 of the control element 3, and the other end is joined to the lead 4C. One end of the wire 5K is joined to the pad portion 317 of the element electrode 31 of the control element 3, and the other end is joined to the lead 4G. One end of the wire 5L is joined to the pad portion 311 of the element electrode 31 of the control element 3, and the other end is joined to the lead 4H. One end of the wire 5M is joined to the pad portion 313 of the element electrode 31 of the control element 3, and the other end is joined to the lead 4I. One end of the wire 5N is joined to the pad portion 314 of the element electrode 31 of the control element 3, and the other end is joined to the lead 4J.

[0047] 2, three wires 5A are bonded to each of the three pad portions 111. Furthermore, three wires 5B are bonded to each of the two pad portions 121. Similarly, three wires 5C are bonded to each of the three pad portions 211. Furthermore, three wires 5D are bonded to each of the two pad portions 221. Furthermore, the portion of wire 5E bonded to bonding portion 412 is located between the portion of each wire 5B bonded to bonding portion 412 and the portion of each wire 5C bonded to bonding portion 412 in the x direction. The number of wires 5A to 5N is not limited to the number shown in Figure 2, and may be changed as appropriate taking into consideration the area of ​​each pad portion 111, 121, 131, 132, 211, 221, 231, 232, 311 to 318 in a planar view, the wire diameter of each wire 5A to 5N, and the amount of current flowing through each wire 5A to 5N, etc.

[0048] In this embodiment, wire 5A corresponds to the "first connecting member" in the claims. Wire 5B corresponds to the "second connecting member" in the claims. Wire 5C corresponds to the "third connecting member" in the claims. Wire 5D corresponds to the "fourth connecting member" in the claims. Wire 5E corresponds to the "fifth connecting member" in the claims. Wire 5F corresponds to the "sixth connecting member" in the claims. Wire 5G corresponds to the "seventh connecting member" in the claims. Wire 5H corresponds to the "eighth connecting member" in the claims. Wire 5I corresponds to the "ninth connecting member" in the claims. Each of wires 5K to 5N corresponds to a "tenth connecting member" in the claims.

[0049] The sealing member 6 is a protective member for the semiconductor elements 1 and 2 and the control element 3. The sealing member 6 covers the semiconductor elements 1 and 2, the control element 3, part of the lead frame 4, and the plurality of connecting members 5. The constituent material of the sealing member 6 is an electrically insulating resin material, such as epoxy resin. The sealing member 6 has, for example, a rectangular shape in plan view. Note that the shape of the sealing member 6 is not limited to the examples shown in FIGS. 1 to 6. The sealing member 6 has a resin main surface 61, a resin back surface 62, and a plurality of resin side surfaces 631 to 634.

[0050] As shown in FIGS. 4 to 6, the resin main surface 61 and the resin back surface 62 are spaced apart in the z direction. The resin main surface 61 faces the z2 direction, and the resin back surface 62 faces the z1 direction. A portion of each lead 4A to 4J (the surface facing the z1 direction) is exposed from the resin back surface 62. Each of the multiple resin side surfaces 631 to 634 is sandwiched between the resin main surface 61 and the resin back surface 62 in the z direction and is connected to both. The resin side surfaces 631 and 632 are spaced apart in the x direction, with the resin side surface 631 facing the x1 direction and the resin side surface 632 facing the x2 direction. The resin side surfaces 633 and 634 are spaced apart in the y direction, with the resin side surface 633 facing the y1 direction and the resin side surface 634 facing the y2 direction.

[0051] Next, the circuit configuration of the semiconductor device A1 according to the first embodiment will be described with reference to Fig. 7. In the following description, the reference potential is defined as the ground voltage V GND There are cases where .

[0052] FIG. 7 shows a case where the semiconductor device A1 is applied to a synchronous rectification step-down DC / DC converter. 7 shows a circuit diagram for the case where the DC / DC converter is a power supply circuit that steps down an input voltage Vin to generate a desired output voltage Vout. The output voltage Vout is supplied to a load LO. Note that the circuit diagram shown in FIG. 7 is just an example.

[0053] As shown in Fig. 7, the semiconductor device A1 has a circuit configuration including a plurality of external terminals T1 to T10, two semiconductor elements 1 and 2, and a control element 3. Also, as shown in Fig. 7, the semiconductor device A1 is connected to two external power supplies PS1 and PS2 and a plurality of discrete components (a plurality of capacitors C1 to C4 and an inductor L1). Note that one or more of the plurality of discrete components may be built into the semiconductor device A1.

[0054] The external power supply PS1 generates a power supply voltage VCC for driving the control element 3. The high-potential terminal of the external power supply PS1 is connected to the external terminal T1. The low-potential terminal of the external power supply PS1 is connected to the first ground terminal GND1 and is grounded to the reference potential. A capacitor C1 is connected in parallel to the external power supply PS1. The capacitor C1 is a bypass capacitor that stabilizes the power supply voltage VCC.

[0055] The external power supply PS2 generates an input voltage Vin. The high-potential terminal of the external power supply PS2 is connected to the external terminal T3. The low-potential terminal of the external power supply PS2 is connected to the second ground terminal GND2 and is grounded to the reference potential. Note that, although the first ground terminal GND1 and the second ground terminal GND2 are both ground terminals with a reference potential, the reference potential of the first ground terminal GND1 and the reference potential of the second ground terminal GND2 may be different. A capacitor C2 is connected in parallel to the external power supply PS2. The capacitor C2 is a bypass capacitor that stabilizes the input voltage Vin.

[0056] The inductor L1 has a first end connected to the external terminal T7 and a second end connected to the load LO and the capacitor C3. The capacitor C3 has a first end connected to the inductor L1 and a second end connected to the second ground terminal GND2. The inductor L1 and the capacitor C3 form an LC filter circuit. The capacitor C4 has a first end connected to the external terminal T7 and a second end connected to the external terminal T8. The capacitor C4, together with the diode D1 described below, forms a bootstrap circuit. The capacitor C4 generates a boot voltage VB.

[0057] The external terminal T1 is an input terminal for the power supply voltage VCC. The external terminal T1 is connected to a high-potential terminal of the external power supply PS1. The external terminal T1 is connected to a control element 3 (a connection terminal TC1 described later) inside the semiconductor device A1. The external terminal T1 corresponds to, for example, a lead 4H in the module structure of the semiconductor device A1.

[0058] The external terminal T2 is connected to a first ground terminal GND1 and is grounded to a reference potential. The external terminal T2 is connected to a control element 3 (a connection terminal TC2 described below) inside the semiconductor device A1. The external terminal T2 corresponds to, for example, a lead 4C in the module structure of the semiconductor device A1.

[0059] The external terminal T3 is an input terminal for the input voltage Vin. The external terminal T3 is connected to a high-potential terminal of the external power supply PS2. The external terminal T3 is connected to the drain of the semiconductor element 1 inside the semiconductor device A1. The external terminal T3 corresponds to, for example, a lead 4D in the module structure of the semiconductor device A1.

[0060] The external terminal T4 is connected to the second ground terminal GND2 and is grounded to the reference potential. The external terminal T4 is connected to the source of the semiconductor element 2 inside the semiconductor device A1. The external terminal T4 corresponds to, for example, the lead 4B in the module structure of the semiconductor device A1.

[0061] The external terminal T5 is an input terminal for a control signal SH. The control signal SH is a signal for controlling the switching operation of the semiconductor element 1. The control signal SH is, for example, a rectangular pulse wave that alternates between high and low levels. The external terminal T5 is connected to a control element 3 (a connection terminal TC3 described below) inside the semiconductor device A1. The external terminal T5 corresponds to, for example, a lead 4I in the module structure of the semiconductor device A1.

[0062] The external terminal T6 is an input terminal for a control signal SL. The control signal SL is a signal for controlling the switching operation of the semiconductor element 2. The control signal SL is, for example, a rectangular pulse wave that alternates between high and low levels. The high-level periods and low-level periods of the control signal SL and the control signal SH are inverted relative to each other. The external terminal T6 is connected to a control element 3 (connection terminal TC4 described below) inside the semiconductor device A1. The external terminal T6 corresponds to, for example, a lead 4J in the module structure of the semiconductor device A1.

[0063] External terminal T7 is the output voltage V SW The output terminal of the output voltage V SWis a voltage signal generated by the switching operations of semiconductor element 1 and semiconductor element 2. External terminal T7 is connected to the connection point between the source of semiconductor element 1 and the drain of semiconductor element 2 inside semiconductor device A1. External terminal T7 corresponds to, for example, lead 4A in the module structure of semiconductor device A1.

[0064] The external terminal T8 is an input terminal for a boot voltage VB. The boot voltage VB is a voltage signal generated by a capacitor C4 and a diode D1 (described later). A second terminal of the capacitor C4 is connected to the external terminal T8. The external terminal T8 is connected to a control element 3 (a connection terminal TC7 (described later)) inside the semiconductor device A1. The external terminal T8 corresponds to, for example, a lead 4G in the module structure of the semiconductor device A1.

[0065] The external terminal T9 is an input terminal for the drive signal GH2. The drive signal GH2 is a signal for driving the semiconductor element 1 and is input directly from an external device (not shown). The drive signal GH2 is, for example, a rectangular pulse wave that alternates between high and low levels. The external terminal T9 is connected to the gate of the semiconductor element 1 inside the semiconductor device A1. The external terminal T9 corresponds, for example, to the lead 4E in the module structure of the semiconductor device A1.

[0066] The external terminal T10 is an input terminal for the drive signal GL2. The drive signal GL2 is a signal for driving the semiconductor element 2 and is input directly from an external device (not shown). The drive signal GL2 is, for example, a rectangular pulse wave that alternates between high and low levels. The high-level periods and low-level periods of the drive signals GH2 and GL2 are inverted relative to each other. The external terminal T10 is connected to the gate of the semiconductor element 2 inside the semiconductor device A1. The external terminal T10 corresponds, for example, to a lead 4F in the module structure of the semiconductor device A1.

[0067] The correspondence between the external terminals T1 to T10 in the circuit configuration and the leads 4A to AJ in the module structure is not limited to the above. For example, the combination of the correspondence between the external terminals T1, T5, T6, and T8 and the leads 4G to 4J can be changed as needed. The combination of the correspondence can be changed as needed depending on the arrangement of the pads 311, 313, 314, and 317 of the control element 3 in a plan view.

[0068] As mentioned above, the two semiconductor elements 1 and 2 are configured by n-type MOSFETs. Each of the semiconductor elements 1 and 2 switches between a conductive state (ON state) and a cut-off state (OFF state) in response to the drive signals GH1, GH2, GL1, and GL2 input to the gate. The two semiconductor elements 1 and 2 configure a half-bridge switching circuit, and the semiconductor element 1 is The semiconductor element 1 is the upper arm of the switching circuit, and the semiconductor element 2 is the lower arm of the switching circuit.

[0069] The drain of semiconductor element 1 is connected to external terminal T3, and the source of semiconductor element 1 is connected to the drain of semiconductor element 2. The gate of semiconductor element 1 is connected to control element 3 (connection terminal TC5 described below) and also to external terminal T9.

[0070] The semiconductor element 1 performs a switching operation in response to a drive signal GH1 input from the control element 3 to its gate. The semiconductor element 1 is in a conductive state when the drive signal GH1 input to its gate is high, and in a cut-off state when the drive signal GH1 input to its gate is low. The semiconductor element 1 also performs a switching operation in response to a drive signal GH2 input from an external terminal T9 to its gate. The semiconductor element 1 is in a conductive state when the drive signal GH2 input to its gate is high, and in a cut-off state when the drive signal GH2 input to its gate is low. The semiconductor element 2 is assumed to be a normally-off type, but may also be a normally-on type. The signal input to the gate of the semiconductor element 1 may be both or either of the two drive signals GH1 and GH2.

[0071] The drain of semiconductor element 2 is connected to the source of semiconductor element 1, and the source of semiconductor element 2 is connected to external terminal T4. The gate of semiconductor element 2 is connected to control element 3 (connection terminal TC6 described below) and also to external terminal T10.

[0072] The semiconductor element 2 performs a switching operation in response to a drive signal GL1 input from the control element 3 to its gate. The semiconductor element 2 is in a conductive state when the drive signal GL1 input to its gate is at a high level, and in a cut-off state when the drive signal GL1 input to its gate is at a low level. The semiconductor element 2 also performs a switching operation in response to a drive signal GL2 input from an external terminal T10 to its gate. The semiconductor element 2 is in a conductive state when the drive signal GL2 input to its gate is at a high level, and in a cut-off state when the drive signal GL2 input to its gate is at a low level. The semiconductor element 2 is assumed to be a normally-off type, but may also be a normally-on type. The signal input to the gate of the semiconductor element 2 may be both or either of the two drive signals GL1 and GL2.

[0073] The connection point between the source of semiconductor element 1 and the drain of semiconductor element 2 is connected to external terminal T7 and also to control element 3 (connection terminal TC8 described later). The switching operation of semiconductor element 1 and the switching operation of semiconductor element 2 cause an output voltage V SW is applied.

[0074] The control element 3 mainly controls the switching operations of the two semiconductor elements 1 and 2. The control element 3 generates drive signals GH1 and GL1 based on control signals SH and SL, and inputs the generated drive signals GH1 and GL1 to the semiconductor elements 1 and 2. The control element 3 includes, in its internal circuitry, a plurality of connection terminals TC1 to TC8, two drive circuits DR1 and DR2, and a diode D1. The control element 3 is an IC in which the two drive circuits DR1 and DR2 and the diode D1 are integrated into a single chip.

[0075] The connection terminal TC1 is connected to the external terminal T1 and is an input terminal of the power supply voltage VCC in the control element 3. The connection terminal TC2 is connected to the external terminal T2 and is grounded to the reference potential. The connection terminal TC3 is connected to the external terminal T5 and is an input terminal of the control signal SH in the control element 3. The connection terminal TC4 is connected to the external terminal T6 and is an input terminal of the control signal SL in the control element 3. The connection terminal TC5 is an output terminal of the drive signal GH1. The connection terminal TC5 is connected to the gate of the semiconductor element 1. The connection terminal TC6 is an output terminal for the drive signal GL1. The connection terminal TC6 is connected to the gate of the semiconductor element 2. The connection terminal TC7 is connected to the external terminal T8, and is an input terminal for the boot voltage VB in the control element 3. The connection terminal TC8 is connected to the connection point between the semiconductor element 1 (source) and the semiconductor element 2 (drain).

[0076] The drive circuit DR1 generates a drive signal GH1 based on the input control signal SH. The drive signal GH1 is a signal for switching the semiconductor element 1, and is a signal obtained by raising the control signal SH to a level required for the switching operation of the semiconductor element 1. The drive circuit DR1 outputs the generated drive signal GH1 from the connection terminal TC5. Since the connection terminal TC5 is connected to the gate of the semiconductor element 1, the drive signal GH1 is input to the gate of the semiconductor element 1. The drive signal GH1 is a signal that sets the boot voltage VB to a high level and the source voltage of the semiconductor element 1 to a low level. The source voltage of the semiconductor element 1 is input to the drive circuit DR1 via the connection terminal TC8. The gate voltage of the semiconductor element 1 is applied based on the source voltage of the semiconductor element 1.

[0077] The drive circuit DR2 generates a drive signal GL1 based on the input control signal SL. The drive signal GL1 is a signal for switching the semiconductor element 2, and is a signal obtained by raising the control signal SL to a level necessary for the switching operation of the semiconductor element 2. The drive circuit DR2 outputs the generated drive signal GL1 from the connection terminal TC6. Since the connection terminal TC6 is connected to the gate of the semiconductor element 2, the drive signal GL1 is input to the gate of the semiconductor element 2. The drive signal GL1 is generated by raising the power supply voltage VCC to a high level and the ground voltage V GND The gate voltage of the semiconductor element 2 is a signal that is at a low level. Voltage V GND is given based on the criteria.

[0078] The anode of the diode D1 is connected to the connection terminal TC1, and the cathode is connected to the connection terminal TC7. The diode D1 and the capacitor C4 form a bootstrap circuit. The bootstrap circuit generates a boot voltage VB and supplies it to the drive circuit DR1. The diode D1 may be disposed outside the control element 3.

[0079] Next, an example of the operation of the semiconductor device A1 will be described.

[0080] In the semiconductor device A1, when control signals SH and SL are input to the control element 3 from the external terminals T5 and T6, the control element 3 generates drive signals GH1 and GL1. Then, the control element 3 inputs the drive signals GH1 and GL1 to the gates of the semiconductor elements 1 and 2, respectively. Alternatively, the drive signals GH2 and GL2 are input to the gates of the semiconductor elements 1 and 2 from the external terminals T9 and T10, respectively. As a result, a first period in which the semiconductor element 1 is in a conductive state and the semiconductor element 2 is in a cutoff state and a second period in which the semiconductor element 1 is in a cutoff state and the semiconductor element 2 is in a conductive state are alternately repeated. At this time, during the first period, an input voltage Vin is applied to the external terminal T7. On the other hand, during the second period, the external terminal T7 is grounded to the reference potential (ground voltage V GND is applied). , the output voltage V from external terminal T7 SW The high level is the input voltage Vin and the low level is the ground voltage V GND Then, the output voltage V SW is the inductor L The input voltage Vin is converted into a DC output voltage Vout by being smoothed by the capacitor C1 and the capacitor C3. By operating as described above, the semiconductor device A1 transforms (steps down) the input voltage Vin into the output voltage Vout.

[0081] The first period and the second period are alternately repeated at a predetermined cycle, and the step-down ratio can be changed according to the ratio of the first period to the second period in one cycle. For example, when the first period is 25% of one cycle (the second period is 75% of one cycle), the output voltage Vout is 1 / 2 times the input voltage Vi The voltage is transformed to 1 / 4 of n (Vout=Vin×(25 / 100)). Note that a dead time during which both semiconductor elements 1 and 2 are in the cutoff state may be provided between the first and second periods.

[0082] The semiconductor device A1 configured as above has the following advantages.

[0083] According to the first embodiment, the semiconductor device A1 includes leads 4A, 4B, and 4C. Leads 4A and 4B overlap each other when viewed in the x direction, and lead 4C overlaps both leads 4A and 4B when viewed in the y direction. A semiconductor element 1 is mounted on lead 4A, a semiconductor element 2 is mounted on lead 4B, and a control element 3 is mounted on lead 4C. This allows the distance between the semiconductor element 1 and the semiconductor element 2 to be shorter than in the semiconductor device described in Patent Document 1. Specifically, in the semiconductor device described in Patent Document 1, two semiconductor elements (switching elements) are arranged on opposite sides of a control element (control IC) in a plan view. Therefore, the wiring between the two semiconductor elements needs to avoid the control element, which tends to increase the wiring distance. In contrast, in the semiconductor device A1, the control element 3 is not arranged between the semiconductor element 1 and the semiconductor element 2. This allows the wiring distance connecting the semiconductor element 1 and the semiconductor element 2 (in this embodiment, the length of each of the wires 5B, 5C and a portion of the lead 4A) to be shorter. Therefore, the semiconductor device A1 can reduce parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0084] According to the first embodiment, both the lead 4A and the lead 4B are positioned further in the y2 direction than the lead 4C and overlap the lead 4C when viewed in the y direction. Therefore, the lead 4A carrying the semiconductor element 1 and the lead 4B carrying the semiconductor element 2 can be positioned on one side in the y direction (the y2 direction), and the lead 4C carrying the control element 3 can be positioned on the other side in the y direction (the y1 direction). When the semiconductor device A1 is powered on, the semiconductor elements 1 and 2 and the control element 3 generate heat. The amount of heat generated by the semiconductor elements 1 and 2 is greater than the amount of heat generated by the control element 3. If this heat from the semiconductor elements 1 and 2 is transferred to the control element 3, the heat generated by the semiconductor elements 1 and 2 may cause malfunction or performance degradation of the control element 3. However, in the semiconductor device A1, the leads 4A and 4B are positioned on one side in the y direction (the y2 direction) of the lead 4C, thereby separating the semiconductor elements 1 and 2 from the control element 3. As a result, the semiconductor device A1 can suppress the heat transferred from the semiconductor elements 1 and 2 to the control element 3, thereby suppressing malfunctions and performance degradation of the control element 3.

[0085] According to the first embodiment, the lead 4D, the lead 4A, and the lead 4B overlap when viewed in the x direction and are arranged in this order in the x direction. Furthermore, the pad portions 111, 121, 211, and 221 of the semiconductor elements 1 and 2 are each strip-shaped extending in the x direction. This allows the semiconductor device A1 to linearly wire the paths of currents (power current paths) flowing between the drain and source of the semiconductor element 1 and between the drain and source of the semiconductor element 2. The power current paths are current paths for power conversion in the semiconductor device A1. In particular, when the semiconductor elements 1 and 2 are driven at high frequencies, the power current paths do not form right-angled wiring, which is effective in reducing noise.

[0086] According to the first embodiment, the lead 4A includes a die pad portion 411 and a bonding portion 412, which are integrally formed. This allows heat from the semiconductor element 1 to be diffused not only to the die pad portion 411 but also to the bonding portion 412. Therefore, the semiconductor device A1 can prevent the junction temperature of the semiconductor element 1 from rising due to heat generated by the semiconductor element 1. The rise in junction temperature is the cause of damage to the semiconductor element 1. In other words, the semiconductor device A1 can prevent damage to the semiconductor element 1. Similarly, the lead 4B includes a die pad portion 421 and a bonding portion 422, which These are integrally formed. This allows heat from the semiconductor element 2 to be diffused not only to the die pad portion 421 but also to the bonding portion 422. Therefore, the semiconductor device A1 can prevent the junction temperature of the semiconductor element 2 from increasing due to heat generated by the semiconductor element 2. In other words, the semiconductor device A1 can prevent damage to the semiconductor element 2.

[0087] According to the first embodiment, the pad portion 131 of the gate electrode 13 of the semiconductor element 1 is disposed on the edge side of the element principal surface 1a that is closer to the lead 4C in the y direction. This allows the semiconductor device A1 to shorten the distance between the pad portion 131 and the control element 3 in a plan view. This allows the length of the wire 5F to be shortened, thereby suppressing the parasitic inductance and parasitic resistance of the wire 5F. In particular, since the wire 5F is a transmission line for the drive signal GH1, this allows suppressing a decrease in the responsiveness of the switching operation of the semiconductor element 1 and malfunctions in the switching operation. Similarly, the pad portion 231 of the gate electrode 23 of the semiconductor element 2 is disposed on the edge side of the element principal surface 2a that is closer to the lead 4C in the y direction. This allows the semiconductor device A1 to shorten the distance between the pad portion 231 and the control element 3 in a plan view. This allows the length of the wire 5H to be shortened, thereby suppressing the parasitic inductance and parasitic resistance of the wire 5H. In particular, since the wire 5H is a transmission line for the drive signal GL1, it is possible to suppress a decrease in the response of the switching operation of the semiconductor element 2 and malfunction of the switching operation.

[0088] According to the first embodiment, the lead 4E is disposed near the pad portion 132 in a plan view and is closer to the pad portion 132 than the other leads (except the lead 4A). This allows the length of the wire 5G connecting the lead 4E and the pad portion 132 to be shortened, thereby suppressing the parasitic inductance and parasitic resistance of the wire 5G. In particular, when a drive signal GH2 is input from an external device to the semiconductor device A1, the wire 5G is a transmission line for the drive signal GH2, which can suppress a decrease in responsiveness of the switching operation of the semiconductor element 1 and malfunction of the switching operation. Furthermore, the lead 4F is disposed near the pad portion 232 in a plan view and is closer to the pad portion 132 than the other leads (except the lead 4B). This allows the length of the wire 5I connecting the lead 4F and the pad portion 232 to be shortened, thereby suppressing the parasitic inductance and parasitic resistance of the wire 5I. In particular, when the drive signal GL2 is input to the semiconductor device A1 from an external device, the wire 5I is a transmission line for the drive signal GL2, so that a decrease in response of the switching operation of the semiconductor element 2 and malfunction of the switching operation can be suppressed.

[0089] Second Embodiment Next, a semiconductor device A2 according to a second embodiment will be described with reference to Fig. 8. Fig. 8 is a plan view showing the semiconductor device A2, in which the sealing member 6 is indicated by an imaginary line (two-dot chain line).

[0090] 8, the semiconductor device A2 is different from the semiconductor device A1 in the configuration of the lead frame 4. Specifically, unlike the lead frame 4 of the semiconductor device A1, the lead frame 4 of the semiconductor device A2 does not include leads 4E and 4F.

[0091] In the lead frame 4 of the semiconductor device A2, as shown in Fig. 8, since lead 4E is absent, lead 4D is extended to the position where lead 4E was located. Similarly, as shown in Fig. 8, since lead 4F is absent, bonding portion 422 of lead 4B is extended to the position where lead 4E was located. Furthermore, since leads 4E and 4F are absent, the multiple connection members 5 do not include wires 5G and 5I.

[0092] According to the second embodiment, the semiconductor device A2 has leads 4A, 4B, and 4C, similar to the semiconductor device A1. The leads 4A and 4B overlap each other when viewed in the x direction, and the lead 4C overlaps both the leads 4A and 4B when viewed in the y direction. Therefore, similar to the semiconductor device A1, the semiconductor device A2 can shorten the distance of the wiring connecting the semiconductor element 1 and the semiconductor element 2 (in this embodiment, the length of each of the wires 5B, 5C and a part of the lead 4A). Therefore, the semiconductor device A2 can reduce the parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0093] According to the second embodiment, the semiconductor device A2 has an extended lead 4D compared to the semiconductor device A1. This allows the semiconductor device A2 to have a lower wiring resistance in the lead 4D compared to the semiconductor device A1. In particular, since the lead 4D is part of the aforementioned power current path, the semiconductor device A2 can suppress power loss in power conversion compared to the semiconductor device A1. Similarly, the semiconductor device A2 has an extended bonding portion 422 of the lead 4B compared to the semiconductor device A1. This allows the semiconductor device A2 to have a lower wiring resistance in the lead 4B compared to the semiconductor device A1. In particular, since the lead 4B is part of the aforementioned power current path, the semiconductor device A2 can suppress power loss in power conversion compared to the semiconductor device A1. Furthermore, the lead 4B has a semiconductor element 2 mounted thereon, and heat from the semiconductor element 2 is transferred through the lead 4B. Therefore, the extended lead 4B (bonding portion 422) can improve the efficiency of heat diffusion from the semiconductor element 2.

[0094] <Third embodiment> Next, a semiconductor device A3 according to a third embodiment will be described with reference to Fig. 9 and Fig. 10. Fig. 9 is a plan view showing the semiconductor device A3, with the sealing member 6 indicated by an imaginary line (two-dot chain line). Fig. 10 is a cross-sectional view taken along line XX in Fig. 9. Note that in the semiconductor device A3 as well, as in the second embodiment, the lead frame 4 does not necessarily have to include leads 4E and 4F.

[0095] 9 and 10, the semiconductor device A3 differs from the semiconductor device A1 in that the plurality of connection members 5 includes clips 7A, 7B, 7C, and 7D instead of wires 5A, 5B, 5C, and 5D. Note that the semiconductor device A3 shown in FIG. 9 differs from the semiconductor device A1 in that the plurality of pad portions 111 (drain electrodes 11) and the plurality of pad portions 121 (source electrodes 12) in the semiconductor element 1 are interchanged.

[0096] The clips 7A to 7D are each made by bending a plate-shaped metal member. The clips 7A to 7D are made of a material such as a metal containing Cu or a metal containing Al. Alternatively, they may be made of a clad material such as CIC (Copper-Invar-Copper). In the example shown in 10, the clips 7A to 7D are bent perpendicularly to the upper surfaces of the leads 4A, 4B, and 4D, but may be inclined relative to the z direction.

[0097] The clip 7A has a comb-like shape on one side in the x direction (the x2 direction side in FIG. 9), and the comb-like portions are respectively joined to the plurality of pad portions 111. The clip 7B has a comb-like shape on one side in the x direction (the x1 direction side in FIG. 9), and the comb-like portions are respectively joined to the plurality of pad portions 121. The clip 7C has a comb-like shape on one side in the x direction (the x2 direction side in FIG. 9), and the comb-like portions are respectively joined to the plurality of pad portions 211. The clip 7D has a comb-like shape on one side in the x direction (the x2 direction side in FIG. 9), and the comb-like portions are respectively joined to the plurality of pad portions 221. The shape of each of the clips 7A to 7D is not limited to the example shown in FIG. 9.

[0098] According to the third embodiment, the semiconductor device A3 has leads 4A, 4B, and 4C, similar to the semiconductor device A1. The leads 4A and 4B overlap each other when viewed in the x direction, and the lead 4C overlaps both the leads 4A and 4B when viewed in the y direction. Therefore, similar to the semiconductor device A1, the semiconductor device A3 can shorten the distance of the wiring connecting the semiconductor element 1 and the semiconductor element 2 (in this embodiment, the length of each of the clips 7B, 7C and a part of the lead 4A). Therefore, the semiconductor device A3 can reduce parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0099] According to the third embodiment, the multiple connection members 5 include clips 7A instead of wires 5A. The clips 7A can reduce wiring resistance more than the wires 5A. In particular, since the clips 7A are part of the aforementioned power current path, the semiconductor device A3 can reduce power loss in power conversion more than the semiconductor device A1. Similarly, the multiple connection members 5 include clips 7B, 7C, and 7D instead of wires 5B, 5C, and 5D. Each of the clips 7B, 7C, and 7D can reduce wiring resistance more than each of the wires 5B, 5C, and 5D. In particular, since each of the clips 7B, 7C, and 7D are part of the aforementioned power current path, the semiconductor device A3 can reduce power loss in power conversion more than the semiconductor device A1.

[0100] In the third embodiment, each of the clips 7A to 7D has a partially bent structure, but this is not limiting. For example, as shown in FIG. 11, each of the clips 7A to 7D may have a structure in which the thickness (dimension in the z direction) of a portion thereof is changed. FIG. 11 is a cross-sectional view of a semiconductor device according to this modification, and corresponds to the cross-section shown in FIG. 10. For example, as shown in FIG. 11, each of the clips 7A to 7D has a thin portion bonded to the semiconductor element 1 or semiconductor element 2 and a thick portion bonded to one of the leads 4A, 4B, and 4D.

[0101] In the third embodiment, the clip 7A has a comb-like portion that is joined to a plurality of pad portions 111 (drain electrodes 11), but this is not limiting. For example, a plurality of strip-shaped clips 7A may be provided, and one clip 7A may be joined to each of the plurality of pad portions 111. The same applies to clips 7B to 7D.

[0102] <Fourth embodiment> Next, a semiconductor device A4 according to a fourth embodiment will be described with reference to Fig. 12. Fig. 12 is a plan view showing the semiconductor device A4, with the sealing member 6 indicated by an imaginary line (two-dot chain line). As in the second embodiment, the lead frame 4 in the semiconductor device A4 may not include the leads 4E, 4F. As in the third embodiment, the semiconductor device A4 may also use clips 7A to 7D instead of the wires 5A to 5D.

[0103] 12, the semiconductor device A4 is different from the semiconductor device A1 in the configuration of each electrode (drain electrodes 11, 21 and source electrodes 12, 22) of the semiconductor elements 1, 2. Specifically, the planar shapes of each pad portion 111, 121, 211, 221 are different.

[0104] Each pad portion 111 of the semiconductor device A4 is tapered. Specifically, the dimension of each pad portion 111 in the y direction decreases from the edge on the x1 direction side toward the edge on the x2 direction side in the x direction. Each pad portion 111 is approximately triangular in plan view. Each pad portion 121, pad portion 211, and pad portion 221 are also tapered. Specifically, the dimension of each pad portion 121 in the y direction decreases from the edge on the x2 direction side toward the edge on the x1 direction side in the x direction. Each pad portion 211 in the y direction decreases from the edge on the x1 direction side toward the edge on the x2 direction side in the x direction. Each pad portion 221 in the y direction decreases from the edge on the x2 direction side toward the edge on the x1 direction side in the x direction. Each pad portion 121, 211, and 221 are approximately triangular in plan view.

[0105] According to the fourth embodiment, the semiconductor device A4, like the semiconductor device A1, includes leads 4A, 4B, and 4C. Lead 4A and lead 4B overlap each other when viewed in the x direction, and lead 4C overlaps both lead 4A and lead 4B when viewed in the y direction. Therefore, like the semiconductor device A1, the semiconductor device A4 can shorten the distance of the wiring connecting the semiconductor element 1 and the semiconductor element 2 (in this embodiment, the respective lengths of the wires 5B, 5C and a portion of the lead 4A). Therefore, the semiconductor device A4 can reduce parasitic inductance and parasitic resistance, thereby achieving high efficiency and energy savings.

[0106] In the first to fourth embodiments, recesses 49 are formed in the leads 4A to 4J of the semiconductor devices A1 to A4. However, this is not a limitation and recesses 49 may not be formed. Furthermore, in the semiconductor devices A1 to A4, recesses 49 are formed along the outer periphery of each lead 4A to 4J in a plan view. However, this is not a limitation. For example, as shown in FIG. 13, recesses 49 may be formed along the edge of each lead 4A to 4J that contacts one of the resin side surfaces 631 to 634 in a plan view. FIG. 13 is a perspective view of a semiconductor device according to this modification, viewed from the bottom. In this case, recesses 69 are formed in the sealing member 6 along the outer periphery in a plan view. The recesses 49 and 69 are connected. The semiconductor device shown in FIG. 13 is prone to forming solder fillets when mounted on a circuit board of an electronic device or the like by soldering. This increases the likelihood that the soldering state of a leadless package semiconductor device can be visually confirmed.

[0107] In the first to fourth embodiments, the semiconductor devices A1 to A4 are shown to be in a SON type package, but are not limited to this and may be configured in other package types, such as BGA (Ball Grid Array) type, LGA (Land Grid Array) type, QFP (Quad Flat Package) type, and QFN (Quad Flat Non-lead) type packages. The semiconductor device may be configured in a QFN type package. Note that these package formats are merely examples and are not limiting. For example, FIG. 14 shows a bottom view of a semiconductor device formed in a QFN type package.

[0108] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0109] The semiconductor device according to the present disclosure includes embodiments relating to the following supplementary notes. [Appendix 1] a first semiconductor element having a first main surface and a first back surface spaced apart in a thickness direction, with a first drain electrode, a first source electrode, and a first gate electrode disposed on the first main surface; a second semiconductor element having a second main surface and a second back surface spaced apart in the thickness direction, with a second drain electrode, a second source electrode, and a second gate electrode disposed on the second main surface; a control element conducting to the first gate electrode and the second gate electrode; a lead frame including a plurality of spaced apart leads; It is equipped with the plurality of leads include a first lead facing the first rear surface and having the first semiconductor element mounted thereon, a second lead facing the second rear surface and having the second semiconductor element mounted thereon, and a third lead having the control element mounted thereon; the first lead and the second lead overlap each other when viewed in a first direction perpendicular to the thickness direction, The semiconductor device is characterized in that the third lead overlaps both the first lead and the second lead when viewed in a second direction perpendicular to both the thickness direction and the first direction. [Appendix 2] the first gate electrode is disposed at an edge portion farther from the second semiconductor element in the first direction; 2. The semiconductor device according to claim 1, wherein the second gate electrode is disposed at an edge portion farther from the first semiconductor element in the first direction. [Appendix 3] 3. The semiconductor device according to claim 2, wherein the first drain electrode and the first source electrode are both strip-shaped extending in the first direction and aligned in the second direction. [Appendix 4] 4. The semiconductor device according to claim 3, wherein the second drain electrode and the second source electrode are both strip-shaped extending in the first direction and aligned in the second direction. [Appendix 5] a first connection member having one end joined to the first drain electrode; the plurality of leads further includes a fourth lead to which the other end of the first connection member is joined; The semiconductor device described in Appendix 4, wherein the fourth lead overlaps both the first lead and the second lead when viewed in the first direction, and is located on the opposite side of the second lead in the first direction, across the first lead. [Appendix 6] a second connection member having one end joined to the first source electrode; the first lead includes a first die pad portion to which the first semiconductor element is bonded and a first bonding portion to which the other end of the second connection member is bonded; 6. The semiconductor device according to claim 5, wherein the first bonding portion is located between the first semiconductor element and the second semiconductor element when viewed in the thickness direction. [Appendix 7] a third connection member having one end joined to the second drain electrode; 7. The semiconductor device according to claim 6, wherein the other end of the third connection member is bonded to the first bonding portion. [Appendix 8] 8. The semiconductor device according to claim 7, wherein the first die pad portion and the first bonding portion are integrally formed. [Appendix 9] a fourth connection member having one end joined to the second source electrode; the second lead includes a second die pad portion to which the second semiconductor element is bonded and a second bonding portion to which the other end of the fourth connection member is bonded; 9. The semiconductor device according to claim 7, wherein the second die pad portion is closer to the first die pad portion than the second bonding portion when viewed in the thickness direction. [Appendix 10] 10. The semiconductor device according to claim 9, wherein the second die pad portion and the second bonding portion are integrally formed. [Appendix 11] a fifth connecting member having one end joined to the control element; 11. The semiconductor device according to claim 9, wherein the other end of the fifth connection member is bonded to the first bonding portion. [Appendix 12] The semiconductor device described in Appendix 11, wherein the other end of the fifth connection member is joined between the other end of the second connection member and the other end of the third connection member in the first direction. [Appendix 13] a sixth connecting member having one end joined to the control element; the first gate electrode has two first pad portions spaced apart from each other in the second direction; 13. The semiconductor device according to claim 9, wherein the other end of the sixth connecting member is joined to one of the two first pad portions. [Appendix 14] 14. The semiconductor device according to claim 13, wherein the two first pad portions are at the same potential in the first semiconductor element. [Appendix 15] Further provided is a seventh connecting member, one end of which is joined to the other of the two first pad portions, 15. The semiconductor device according to claim 13, wherein the plurality of leads further includes a fifth lead to which the other end of the seventh connection member is joined. [Appendix 16] one of the two first pad portions is disposed on an edge side of the first main surface, in the second direction, that is closer to the third lead, as viewed in the thickness direction; A semiconductor device as described in Appendix 15, wherein the other of the two first pad portions is arranged on the edge side of the first main surface in the second direction, farthest from the third lead, when viewed in the thickness direction. [Appendix 17] 17. The semiconductor device according to claim 16, wherein the fifth lead is arranged adjacent to the fourth lead in the second direction. [Appendix 18] an eighth connecting member having one end joined to the control element; the second gate electrode has two second pad portions spaced apart from each other in the second direction; 18. The semiconductor device according to claim 15, wherein the other end of the eighth connection member is joined to one of the two second pad portions. [Appendix 19] 19. The semiconductor device according to claim 18, wherein the two second pad portions are at the same potential in the second semiconductor element. [Appendix 20] Further provided is a ninth connecting member, one end of which is joined to the other of the two second pad portions, 20. The semiconductor device according to claim 18, wherein the plurality of leads further includes a sixth lead to which the other end of the ninth connection member is joined. [Appendix 21] one of the two second pad portions is disposed on an edge side of the second main surface, in the second direction, that is closer to the third lead, as viewed in the thickness direction; A semiconductor device as described in Appendix 20, wherein the other of the two second pad portions is arranged on the edge side of the second main surface in the second direction, farthest from the third lead, when viewed in the thickness direction. [Appendix 22] 22. The semiconductor device according to claim 21, wherein the sixth lead is disposed adjacent to the second die pad portion in the second direction. [Appendix 23] 23. The semiconductor device according to claim 22, wherein the fifth lead and the sixth lead overlap when viewed in the first direction. [Appendix 24] a plurality of tenth connection members, each having one end joined to the control element; the plurality of leads further includes a plurality of seventh leads to which the other ends of the plurality of tenth connection members are joined, 24. The semiconductor device according to claim 9, wherein all of the seventh leads overlap the third lead when viewed in the first direction. [Appendix 25] The semiconductor device described in Appendix 24, wherein the multiple seventh leads include one that overlaps the fourth lead when viewed in the second direction and one that overlaps the second die pad portion when viewed in the second direction. [Appendix 26] 26. The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element are made of gallium nitride. [Explanation of symbols]

[0110] A1 to A4: Semiconductor device 1: Semiconductor element 1a: Element main surface 1b: Back side of element 11: Drain electrode 111: Pad section 12: Source electrode 121: Pad section 13: Gate electrode 131, 132: Pad section 2: Semiconductor elements 2a: Main surface of element 2b: Back side of element 21: Drain electrode 211: Pad section 22: Source electrode 221: Pad section 23: Gate electrode 231, 232: Pad section 3: Control element 3a: Main surface of element 3b: Back side of element 31: Element electrode 311~318: Pad section 4: Lead frame 4A~4J: Lead 411, 421: Die pad section 412, 422: Bonding section 49: Recess 5: Connection parts 5A~5N: Wire 6: Sealing member 7A~7D: Clips 61: Resin main surface 62: Resin back 631~634: Resin side 69: Recess C1 to C4: Capacitors D1: Diode DR1, DR2: Drive circuit GND1: 1st ground terminal GND2: 2nd ground terminal L1: Inductor LO:Load PS1,PS2: External power supply T1 to T10: External terminals TC1 to TC8: Connection terminals

Claims

1. a first semiconductor element having a first main surface facing one side in a thickness direction, the first main surface having a first drain electrode, a first source electrode, and a first gate electrode disposed thereon; a second semiconductor element having a second main surface facing in the same direction as the first main surface in the thickness direction, a second drain electrode, a second source electrode, and a second gate electrode disposed on the second main surface; a lead frame including a first lead, a second lead, a third lead and a fourth lead; Equipped with the first lead includes a first die pad portion on which the first semiconductor element is mounted and a first bonding portion disposed adjacent to the first die pad portion; the second lead includes a second die pad portion on which the second semiconductor element is mounted, the second die pad portion being disposed a first distance away from the first bonding portion in a first direction from the first die pad portion toward the first bonding portion, the third lead is disposed a second distance away from the first lead in a second direction perpendicular to the first direction; the fourth lead includes a second bonding portion arranged a third distance away from the first die pad portion on the opposite side of the second lead relative to the first lead in the first direction.

2. A first connection member electrically connecting the first drain electrode and the second bonding portion; a second connection member electrically connecting the first source electrode and the first bonding portion; The semiconductor device according to claim 1 , further comprising a third connection member electrically connecting said second drain electrode and said first bonding portion.

3. A semiconductor device as described in claim 2, wherein each of the first connecting member, the second connecting member and the third connecting member extends in the first direction when viewed in the thickness direction.

4. Further comprising a control element mounted on the third lead, 4. The semiconductor device according to claim 2, wherein said control element is electrically connected to said first gate electrode and said second gate electrode.

5. a fourth connecting member having one end connected to the control element; The semiconductor device according to claim 4 , wherein the other end of said fourth connection member is joined to said first bonding portion.

6. A semiconductor device as described in Claim 5, wherein the other end of the fourth connecting member is joined between the second connecting member and the third connecting member in the first direction.

7. 7. The semiconductor device according to claim 1, wherein said first die pad portion and said first bonding portion are integrally formed.

8. The second lead includes a third bonding portion arranged adjacent to the second die pad portion in the first direction, 8. The semiconductor device according to claim 1, wherein the third bonding portion is located on an opposite side to the first lead with respect to the second die pad portion in the first direction.

9. The semiconductor device described in Claim 8, further comprising a fifth connection member electrically connecting the second source electrode and the third bonding portion.

10. A semiconductor device as described in Claim 9, wherein the fifth connecting member extends in the first direction when viewed in the thickness direction.

11. 11. The semiconductor device according to claim 8, wherein the second die pad portion and the third bonding portion are integrally formed.

12. A semiconductor device as described in any one of claims 1 to 11, wherein the first lead and the second lead overlap each other when viewed in the first direction.

13. A semiconductor device as described in any one of claims 1 to 12, wherein the third lead overlaps the first die pad portion and the second die pad portion when viewed in the second direction.

14. 14. The semiconductor device according to claim 1, wherein the first drain electrode and the first source electrode are both strip-shaped extending in the first direction and aligned in the second direction.

15. 15. The semiconductor device according to claim 1, wherein the second drain electrode and the second source electrode are both strip-shaped extending in the first direction and are aligned in the second direction.

16. A semiconductor device as described in any one of claims 1 to 15, wherein each of the second distance and the third distance is different from the first distance.

17. 17. The semiconductor device according to claim 1, wherein the first semiconductor element and the second semiconductor element are made of gallium nitride.

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