Secure Chip Identification Using Random Threshold Voltage Differences in Field-Effect Transistor Structures as a Function of Physical Uncloning

Abstract

The semiconductor structure may include one or more metal gates, one or more channels beneath the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide a threshold voltage difference in the one or more metal gates. The high-k material may be a first high-k material or a second high-k material. The semiconductor structure may include only the first high-k material embedded in the gate dielectric layer. The semiconductor structure may include only the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

Description

[Technical field]

[0001] The present invention relates generally to semiconductor structures and methods for forming the same. More particularly, the present invention relates to a method for generating random threshold voltages (V) in field effect transistor (FET) structures as a physically unclonable function (PUF). th This paper relates to identification of secure chips using the variation of [Background technology]

[0002] A PUF is a physically defined "digital fingerprint" that serves as a unique identification for a semiconductor device, e.g. a microprocessor. A PUF is a physical entity embedded in a physical structure. PUFs are based on unique physical differences that can naturally occur during semiconductor manufacturing. PUFs can be implemented in integrated circuits. PUFs can further be used in applications with high security requirements, e.g. cryptography. Summary of the Invention

[0003] According to one embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include one or more metal gates, one or more channels under the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide a threshold voltage difference in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may include only the first high-k material embedded in the gate dielectric layer. The semiconductor structure may include only the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

[0004] According to another embodiment of the present invention, a semiconductor structure is provided. The semiconductor structure may include one or more gate regions of one or more field effect transistors. The one or more gate regions may be above one or more channels. The semiconductor structure may include a metal gate separated from the one or more channels by a gate dielectric layer, a high-k material embedded in the gate dielectric layer, and an interlayer dielectric. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The interlayer dielectric may surround the one or more gate regions. The high-k material may be a first high-k material or a second high-k material. The semiconductor structure may include only the first high-k material embedded in the gate dielectric layer. The semiconductor structure may include only the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer. The high-k material may provide a threshold voltage difference in the one or more metal gates.

[0005] According to another embodiment of the invention, a method is provided. The method can include forming one or more gate regions over a channel, causing random nucleation of a high-k material in the one or more gate regions, and depositing a gate dielectric layer on each of the one or more gate regions. The causing random nucleation of the high-k material in the one or more gate regions can promote a random threshold voltage in the one or more gate regions. The random threshold voltage in the one or more gate regions can be used as a physical hard-to-clone function. The one or more gate regions can be surrounded by a gate spacer. The gate dielectric layer can cover an entire surface of the channel. The second high-k material can partially cover a surface of the channel. The high-k material can be a first high-k material or a second high-k material. The method can include embedding only the first high-k material in the gate dielectric layer. The method can include embedding only the second high-k material in the gate dielectric layer. The method can include embedding both the first high-k material and the second high-k material in the gate dielectric layer. The method may include forming a first source drain and a second source drain, depositing a metal gate on an upper surface of the gate dielectric layer, depositing an interlayer dielectric around the one or more gate regions, and forming a first source drain contact and a second source drain contact. The first source drain and the second source drain may be separated from the one or more gate regions by a gate spacer. The interlayer dielectric may be on an upper surface of the first source drain and the second source drain.

[0006] The following detailed description, given by way of example and not intended to limit the invention thereto, will be best understood when read in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0007] [Figure 1]FIG. 2 is a cross-sectional view illustrating a fin and buried oxide disposed on a substrate according to an illustrative embodiment. [Diagram 2] FIG. 2 is a cross-sectional view illustrating a dummy gate and a gate spacer disposed on a fin according to an illustrative embodiment. [Diagram 3] FIG. 2 is a cross-sectional view illustrating a first and second source-drain and an interlayer dielectric according to an illustrative embodiment. [Figure 4] FIG. 2 is a cross-sectional view illustrating multiple gate regions including trenches formed to expose a top surface of a fin according to an illustrative embodiment. [Diagram 5] 2 is a cross-sectional view illustrating a plurality of gate regions including a first high-k material according to an illustrative embodiment. [Figure 6] FIG. 2 is a cross-sectional view illustrating a plurality of gate regions including a second high-k material according to an illustrative embodiment. [Figure 7] 2 is a cross-sectional view illustrating multiple gate regions including a gate dielectric layer according to an illustrative embodiment. [Figure 8] 1 is a cross-sectional view illustrating multiple gate regions including gate metal and contacts according to an illustrative embodiment. [Figure 9] FIG. 2 is a top view of a gate region illustrating random nucleation of first and second high-k materials according to an illustrative embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to depict specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbers represent like elements.

[0009] Although detailed embodiments of the claimed structures and methods are disclosed herein, it is understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that can be implemented in various forms. However, the present invention can be implemented in many different forms and should not be construed as being limited to the exemplary embodiments mentioned herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. In the description, details of well-known features and techniques are omitted to avoid unnecessarily obscuring the present embodiments.

[0010] For purposes of the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall refer to the disclosed structures and methods as oriented in the drawings. The terms "on", "on top", "on top of", "disposed on" or "disposed on top" mean that a first element, such as a first structure, is on a second element, such as a second structure, and that an intervening element, such as an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0011] In order not to obscure the presentation of the embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and explanation, and in some instances may not be described in detail. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description focuses on the characteristic features or elements of various embodiments of the present invention.

[0012] FIELD OF THE DISCLOSURE

[0002] Embodiments of the present invention generally relate to semiconductor structures and methods of forming the same. More particularly, the present invention relates to a method for generating random threshold voltages (V) in field effect transistor (FET) structures as a physically unclonable function (PUF). th ) to identify secure chips.

[0013] The integrity of the semiconductor supply chain is a vital security necessity, especially for the nation's defense. The decline of trusted foundries in the United States highlights the need to prove the authenticity of chips installed in critical systems. For example, fake components, if replaced with genuine ones, could result in loss of functionality or contain malicious circuitry that allows snooping. Thus, there is a need to manufacture semiconductor devices that can be identified as secure.

[0014] Many semiconductor devices use PUFs as a security measure. A PUF is a physically defined "digital fingerprint" that serves as a unique identification for a semiconductor device, e.g., a microprocessor. A PUF is a physical object that can provide a physically defined "digital fingerprint" output (response) that serves as a unique identifier for a given input and condition (challenge). PUFs are based on unique physical differences that can occur naturally during semiconductor manufacturing. PUFs can be implemented in integrated circuits. PUFs can also be used in applications with high security requirements, e.g., cryptography.

[0015] Silicon PUFs are increasingly being used as hardware roots of trust and entropy sources for cryptographic applications. In these applications, the reliability of the PUF output is key to the successful implementation. Both weak and strong PUFs derive their output by amplifying an analog signal from a physical property in an integrated circuit block. The analog signal can be derived from propagation delays, ring oscillators, time-controlled oxide breakdown, or the V of an SRAM transistor. thThese physical measurements are inherently sensitive to environmental conditions, e.g., temperature, operating voltage, transistor thermal / interface noise, process corners, and aging. As a result, it is difficult to obtain a stable PUF output without taking additional stabilization and error correction techniques, e.g., temporal majority voting (TMV), pre-burning in the PUF pieces for end-of-life (EOL) prediction and reliability screening, concealment algorithms, and utilization of parity bits for error correction code (ECC). Therefore, there is a need to manufacture semiconductor devices with stable PUF outputs.

[0016] An embodiment of the present invention provides a random V th The present invention provides a structure and a method for forming a difference between the random V and the gate structure. The FET can be a planar FET, a nanosheet FET, a vertical FET, a nanowire FET, a fin FET, or any other FET or semiconductor device having a gate structure. th is used as a PUF and is achieved by randomly depositing different high-k materials in multiple gate regions of the device. Figures 1-8 show the random V th Figure 9 shows how to fabricate a FET structure with various V th FIG. 1 is a top cross-sectional view of a gate region including randomly distributed high-k material that enables generation of

[0017] Referring now to FIG. 1, a structure 100 is shown according to one embodiment. The structure 100 can include a substrate 102, a buried oxide 104, and a fin 106. The substrate 102 can include one or more semiconductor materials. Non-limiting examples of suitable substrate 102 materials can include Si (silicon), strained Si, Ge (germanium), SiGe (silicon germanium), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or indium gallium arsenide (InGaAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride)), or any combination thereof. In one embodiment, the substrate 102 can include silicon.

[0018] A buried oxide 104 is disposed on the substrate 102. The buried oxide 104 may be, for example, an oxide layer, such as silicon oxide, buried in a silicon wafer. A fin 106 is disposed on a top surface of the buried oxide 104. The fin 106 may be made of silicon. In one embodiment, the fin 106 may be a silicon-on-insulator fin. In an alternative embodiment, the fin 106 may be a bulk fin. Additionally, while a silicon-on-insulator fin is illustrated, it should be understood that embodiments of the present invention may be implemented in any CMOS device or transistor device including gate structures.

[0019] 2, a structure 100 is shown including a dummy gate 108, a gate spacer 110, a first source drain 112, and a second source drain 114, according to one embodiment. A sacrificial gate material may be deposited on a top surface of the fin 106. The sacrificial gate material may then be patterned to form the dummy gate 108.

[0020] The dummy gate 108 may be formed from a sacrificial gate material, such as amorphous silicon (α-Si) or polycrystalline silicon (polysilicon). The sacrificial material may be deposited by a deposition process, including, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICPCVD), or any combination thereof. The thickness of the sacrificial material forming the dummy gate 108 may be from about 50 nm to about 250 nm, or from about 100 nm to about 200 nm.

[0021] After the formation of the dummy gate 108, a gate spacer 110 is then conformally deposited on the dummy gate 108. The gate spacer 110 is then patterned to remove a portion of the gate spacer 110 on the top surface of the fin 106. As a result, the gate spacer 110 surrounds the dummy gate 108. The gate spacer 110 is on the top surface and sidewalls of the dummy gate 108.

[0022] The gate spacer 110 may include an insulating material such as, for example, silicon dioxide, silicon nitride, SiOCN, or SiBCN. Other non-limiting examples of the gate spacer 110 material may include a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The gate spacer 110 material is deposited by a deposition process, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). The thickness of the gate spacer 110 may be from about 3 to about 15 nm, or from about 5 to about 8 nm. The gate spacer 110 isolates the dummy gate 108 from other materials formed or deposited around the dummy gate 108. Additionally, the gate spacer 110 isolates the dummy gate 108 from the first and second source-drains 112, 114.

[0023] After deposition of the gate spacer 110, an epitaxial layer is grown on the surface of the fin 106 to form a first source-drain 112 and a second source-drain 114. The first and second source-drain 112, 114 may be grown using any suitable growth process, for example, chemical vapor deposition (CVD) (low pressure (LP) or reduced pressure chemical vapor deposition (RPCVD)), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), metal organic chemical vapor deposition (MOCVD) or any other suitable process.

[0024] The material source of the epitaxial layer can be, for example, silicon, germanium, or a combination thereof. The gas source for deposition of the epitaxial semiconductor material can include a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, the epitaxial silicon layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. The epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. The epitaxial silicon-germanium alloy layer can be formed utilizing a combination of such gas sources. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0025] The first and second source-drain 112, 114 may be in-situ doped with a p-type or n-type dopant. For example, for a p-type FET, the first and second source-drain 112, 114 may be made of silicon germanium and doped in-situ with a p-type dopant, such as boron. For an n-type FET, the first and second source-drain 112, 114 may be made of silicon and doped in-situ with an n-type dopant, such as phosphorus or arsenic.

[0026] 3, a structure 100 is shown including an interlayer dielectric (ILD) 116, according to one embodiment. After formation of the first and second source-drains 112, 114, the ILD 116 may be deposited (not shown) on top surfaces of the first and second source-drains 112, 114 such that its top surface is substantially coplanar with the top surface of the gate spacer 110. The ILD 116 surrounds the gate spacer 110. The ILD 116 may be formed from a low-k dielectric material (k<4.0), including, for example, but not limited to, silicon oxide, spin-on glass, flowable oxide, high density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof.

[0027] The ILD 116 is deposited by a deposition process including, but not limited to, CVD, PVD, plasma enhanced CVD, evaporation, chemical solution deposition, or a similar process. After deposition of the ILD 116, a planarization process, such as a CMP process, may be used to remove excess ILD 116 from the top surface of the structure 100. The CMP process may further be used to remove the portion of the gate spacer 110 directly above the dummy gate 108. By removing the gate spacer 110 directly above the dummy gate 108, the top surface of the dummy gate 108 is exposed, allowing the dummy gate 108 to be removed in a next process step.

[0028] Referring now to Figure 4, a plurality of structures 100 including trenches 118 are shown according to one embodiment. Although three structures 100 are shown, it should be understood that embodiments of the present invention contemplate the formation of multiple structures 100 on a single substrate wafer. Each structure 100 includes a gate region surrounded by an ILD. Three gate regions are shown in Figure 4, gate region 1, gate region 2, and gate region 3, to illustrate that there may be more than one structure 100 on a silicon wafer and therefore more than one gate region on a silicon wafer.

[0029] An etching process, such as a wet etching process, may be performed to remove the dummy gate 108 from each gate region of the structure 100 until the top surface of the fin 106 is exposed to form trenches 118. Each trench 118 may extend from the top surface of the gate spacer 110 to the top surface of the fin 106. The etching process removes the dummy gate 108 material selectively to the fin 106 material. However, the etching process does not remove the gate spacer 110. As a result, the gate spacer 110 separates the first and second source-drains 112, 114 from the gate regions.

[0030] Referring now to FIG. 5, three gate regions of a structure 100 are shown, according to one embodiment. A first high-k material 120 is randomly deposited in the trenches 118 of the structure 100 using a timed atomic layer deposition process. The first high-k material 120 is deposited on the surface of the exposed fin 106 (in the gate region). A deposition time is chosen that is very close to the nucleation time to promote random nucleation. Due to the difference in nucleation, some of the first high-k material 120 may be randomly deposited in some gate regions, such that the first high-k material 120 partially covers the surface of the exposed fin 106 (in the gate region). As a result, some gate regions may have at least a portion of the exposed top surface of the fin 106 remaining after the formation of the first high-k material 120. Furthermore, not all gate regions of the structure 100 have the first high-k material 120. As shown, gate regions 1 and 3 include the first high-k material 120, while gate region 2 does not. In addition, the randomness of the nucleation cannot be reproduced. As a result, other deposition runs of the first high-k material 120 may not produce the same results as gate regions 1 and 3 that include the first high-k material 120. It should be understood that a typical substrate wafer may include thousands or even millions of gate regions. Due to the random nucleation, each substrate wafer can have millions of gate regions with different first high-k material 120 nucleation. As a result, no two wafers will have the first high-k material 120 nucleated exactly the same in all of their gate regions.

[0031] The first high-k material 120 may be made of a material such as aluminum oxide (Al2O3). Other materials may be used as the first high-k material 120, such as lutetium oxide (Lu2O3), yttrium oxide (Y2O3), magnesium oxide (MgO) and other rare earth oxides. The composition of the first high-k material 120, the deposition process and post-deposition treatments will affect the threshold voltage (V) of the structure 100 depending on whether the structure 100 is a pFET or nFET, the electrical properties of the interface between the high-k material 120 and the top surface of the fin 106 (including oxide formation at the interface during or after high-k material deposition), the composition of the gate metal, the polarity of the charge distributed through the high-k dielectric at the high-k dielectric / fin interface, and other device and process parameters known in the art. th ) may have different effects.

[0032] 6, three gate regions of the structure 100 are shown including a second high-k material 122, according to one embodiment. Using a timed atomic layer deposition process, the second high-k material 122 is deposited in the trenches 118 of the structure 100. The second high-k material 122 is deposited on the exposed surface of the fin 106 (at the gate region). Just like the first high-k material 120, the second high-k material 122 can also randomly nucleate in different gate regions, thus partially covering the exposed surface of the fin 106 (at the gate region). As a result, some gate regions can have at least a portion of the exposed surface of the fin 106 (at the gate region) remaining after the formation of the second high-k material 122. As a result, some gate regions can include both the first high-k material 120 and the second high-k material 122, while some gate regions can have either the first high-k material 120 or the second high-k material 122. Additionally, there may be gate regions that are devoid of either the first high-k material 120 or the second high-k material 122. As discussed above with reference to the first high-k material 120, the second high-k material 122 also nucleates randomly within millions of gate regions on the substrate wafer.

[0033] During nucleation, the second high-k material 122 may overlap the first high-k material 120. Additionally, the second high-k material 122 may be adjacent to the first high-k material 120. Even if both the first and second high-k materials 120, 122 are present in the same gate region, the second high-k material 122 may or may not be in contact with the first high-k material 120.

[0034] The second high-k material 122 can be made from materials such as lanthanum oxide (La2O3) or other materials such as lutetium oxide (Lu2O3), yttrium oxide (Y2O3), magnesium oxide (MgO) and other rare earth oxides. Like the first high-k material 120, the second high-k material 122 can have a V th For example, the first high-k material 120 may have a different effect on V th while the second high-k material 122 may increase V th or vice versa, or they may reduce V th This may result in both an increase or a decrease in

[0035] Referring now to FIG. 7, three gate regions of the structure 100 are shown including a gate dielectric layer 124, according to one embodiment. Using an atomic layer deposition process, the gate dielectric layer 124 is conformally deposited in the trenches 118 of the structure 100 along the bottom and sidewalls of the trenches 118. The gate dielectric layer 124 is deposited in the trenches 118 of all open gate regions. The gate dielectric layer 124 is made of a high-k dielectric material. Non-limiting examples of suitable materials for the gate dielectric layer 124 include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials include, but are not limited to, metal oxides, such as hafnium oxide (HfO2). The portion of the fin 106 below the gate dielectric layer 124 may also be referred to as a channel.

[0036] 8, three gate regions of the structure 100 are shown including a metal gate 126, according to one embodiment. After a gate dielectric layer 124 is deposited along the sidewalls and bottom surface of the trench 118, the trench 118 is filled with a conductive metal to form the metal gate 126. Non-limiting examples of conductive materials forming the metal gate 126 may include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive metal may be deposited by any suitable deposition process, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, plating, thermal or electron beam evaporation, and sputtering.

[0037] In addition to forming the metal gate 126, the structure 100 undergoes further processing to form contacts including first and second source drain contacts 128, 130 shown in gate region 1 of FIG. 8. The first and second source drain contacts 128, 130 extend through the ILD 116 to the first and second source drains 112, 114, respectively, and are formed within trenches. A resist, such as photoresist, may be deposited and patterned to remove the ILD 116 and form contact trenches. An etching process, such as reactive ion etching, may be performed using the patterned resist as an etch mask to remove the ILD 116 until the first and second top source drains 112, 114 are exposed. The contact trenches are filled with a conductive material or combination of conductive materials to form the first and second source drain contacts 128, 130. The filled conductive material can be a conductive metal, for example, aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material can be deposited by a suitable deposition process, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, plating, thermal or electron beam evaporation, or sputtering. A planarization process, for example, chemical mechanical planarization, is performed to remove any conductive material from the surface of the ILD 116.

[0038] As shown in FIG. 8, the resulting structure 100 includes gate regions that can include different combinations of first and second high-k materials 120, 122. For example, some gate regions may include both first and second high-k materials 120, 122, as shown in gate region 1. Some gate regions may include only the first high-k material 120, as shown in gate region 2, or only the second high-k material 122, as shown in gate region 3. Additionally, although not shown, there may be gate regions that do not include either the first high-k material 120 or the second high-k material 122. However, all of the gate regions include a gate dielectric layer 124. All of the gate regions may also include a metal gate 126.

[0039] Having a first or second high-k material 120, 122, or both, in certain gate regions of a circuit device creates or promotes different threshold voltages in those gate regions. Different threshold voltages are achieved by using first and second high-k materials 120, 122 with different chemical compositions in combination with a gate dielectric layer 124. For example, the first high-k material 120 is designated A, the second high-k material 122 is designated B, and the gate dielectric layer 124 is designated C. As described above in this specification, all gate regions contain C. Some gate regions only contain C. Some gate regions have a combination of C and A, some gate regions have a combination of C and B, and some gate regions have a combination of C, A, and B, where A and B may be adjacent or even overlapping. As a result, different threshold voltages can result in a random set of transistors within a given chip. The randomness is achieved by the random nucleation of the first and / or second high-k materials 120, 122 in the gate regions of the structure 100. As described above, the nucleation in the gate regions is random, and therefore each substrate wafer can have various combinations of the first and / or second high-k materials 120, 122. As a result, some gate regions include both the first and second high-k materials 120, 122, some gate regions include only one of the high-k materials, and some gate regions include neither the first high-k material 120 nor the second high-k material 122. In addition, a typical substrate wafer may include millions of gate regions. Because the nucleation of the high-k materials is random, no two substrate wafers will have the same deposition pattern of the first and second high-k materials 120, 122 in each gate region of both wafers. As a result, each gate region of each substrate wafer has a specific threshold voltage. These threshold voltages can be used to identify each chip as a PUF.

[0040] 9, a top view of the gate region is shown illustrating the random nucleation of the first and second high-k materials, according to one embodiment. As described herein above, V th indicates the "effective" or "extrapolated" threshold voltage of a transistor. For example, the effective threshold voltage may indicate the minimum voltage required to turn on a transistor and have a current (e.g., a measurable or detectable current) flow from the first source-drain 112 to the second source-drain 114, or vice versa. By having either or both of the first or second high-k materials 120, 122 nucleate in the gate region, the randomness of the nucleation process results in a difference in the effective threshold voltage.

[0041] The cross-section in the top row shows the first high-k material 120 and the second high-k material 122 extending from top to bottom. In this exemplary embodiment, the composition of the high-k materials and the device and process parameters are such that the portion of the transistor channel covered by the second high-k material 122 has a "locally" higher threshold voltage than the portion of the transistor channel covered by the first high-k material 120. As a result, the addition of the second high-k material 122 increases the effective threshold voltage of the transistor. This increase in the effective threshold voltage of the transistor is most noticeable when the second high-k material 122 spans the entire channel width of the transistor, as shown in the top row. This is because when the gate voltage of the transistor is lower than the local threshold voltage for the channel region covered by the second high-k material 122 but higher than the local threshold voltage for the channel region covered by the first high-k material 120, the presence of the second high-k material 122 across the entire channel width effectively blocks current flow between the two source-drains 112, 114, whereas in the embodiment illustrated in the bottom row, there is still a current flow path between the two source-drains 112, 114 through the locally lower threshold voltage channel region covered by the first high-k material 120. Thus, the presence of the second high-k material 122 in the embodiment illustrated in the bottom row may result in a relatively small or negligible increase in the effective threshold voltage compared to the embodiment illustrated in the top row. However, the presence of the second high-k material 122 in the embodiment illustrated in the bottom row may reduce the on-current of the transistor due to a reduction in the effective channel width available for current flow. The presence of the second high-k material 122 in the embodiment illustrated in the top row can also reduce the on-current of the transistor by increasing the effective threshold voltage of the transistor.

[0042] The peripheral circuitry can detect variability in effective threshold voltages between transistors, variability in on-currents between transistors (for a given gate bias or gate bias range), or a combination of both. As mentioned above, threshold voltage sensing circuits are most effective at detecting differences resulting from random nucleation in the embodiments illustrated in the top row of FIG. 9, while current sensing circuits may be effective at detecting differences resulting from random nucleation in the embodiments illustrated in both rows. The peripheral circuitry for sensing threshold voltages may be based, for example, on switched capacitors or other circuit configurations known in the art. The current sensing circuits may be based, for example, on sense amplifiers or other circuit configurations known in the art. Both methods of detecting variability between transistors are within the scope of the present invention.

[0043] Embodiments of the present invention use the nucleation effect of atomic layer deposition of high-k materials in the gate region to provide random V-channel junctions for any field effect transistor structure or other structure that includes a gate and a gate dielectric layer. th The randomness of the nucleation of the first and second high-k materials 120, 122 allows the formation of a V th This allows for the use of a chip / wafer identification and authenticity.

[0044] The description of various embodiments of the present invention has been provided for illustrative purposes, and is not intended to be exhaustive or to limit the description to only the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification have been selected to best explain the principles, practical applications, or technical improvements of the embodiments over commercially available technology, or to enable those skilled in the art to understand the embodiments described herein.

Claims

1. A method for fabricating a semiconductor device comprising: forming a plurality of gate regions over respective channels, the plurality of gate regions being surrounded by a gate spacer; causing random nucleation of a high-k material at the gate regions, the high-k material partially covering a surface of a corresponding one of the channels; depositing a gate dielectric layer on each of the plurality of gate regions, the gate dielectric layer covering an entire surface of the corresponding channel; whereby the high-k material is applied to provide different dielectric combinations between the plurality of gate regions.

2. forming one or more gate regions over a channel, the one or more gate regions being surrounded by a gate spacer; causing random nucleation of a high-k material in the one or more gate regions, the high-k material partially covering a surface of the channel; depositing a gate dielectric layer on each of the one or more gate regions, the gate dielectric layer covering an entire surface of the channel; wherein causing random nucleation of the high-k material in the one or more gate regions promotes a random threshold voltage in the one or more gate regions, and the random threshold voltage in the one or more gate regions is used as a physical hard-to-clone function.

3. The method of claim 1 or 2, wherein the high-k material is a first high-k material or a second high-k material.

4. The method of claim 3 , wherein only the first high-k material is embedded in the gate dielectric layer.

5. The method of claim 3 , wherein only the second high-k material is embedded in the gate dielectric layer.

6. The method of claim 3 , wherein both the first high-k material and the second high-k material are embedded in the gate dielectric layer.

7. forming a first source-drain and a second source-drain separated from the gate region by the gate spacer; depositing a metal gate on an upper surface of the gate dielectric layer; depositing an interlayer dielectric around the gate region, the interlayer dielectric overlying an upper surface of the first source-drain and the second source-drain; forming a first source-drain contact and a second source-drain contact; The method of any one of claims 1 to 6, further comprising:

8. 1. A semiconductor structure comprising: a plurality of metal gates for the plurality of gate regions; a plurality of channels beneath the plurality of metal gates; a gate dielectric layer separating the plurality of metal gates from the plurality of channels; a high-k material embedded in the gate dielectric layer, the high-k material and the gate dielectric layer both in direct contact with the one or more channels; wherein the high-k material is provided to provide different dielectric combinations between the gate regions.

9. A semiconductor structure comprising: one or more metal gates; one or more channels beneath the one or more metal gates; a gate dielectric layer separating the one or more metal gates from the one or more channels; a high-k material embedded in the gate dielectric layer, the high-k material and the gate dielectric layer both in direct contact with the one or more channels; wherein the high-k material provides a threshold voltage differential in the one or more metal gates.

10. A semiconductor structure comprising: one or more metal gates; one or more channels beneath the one or more metal gates; a gate dielectric layer separating the one or more metal gates from the one or more channels; a high-k material embedded in the gate dielectric layer, the high-k material and the gate dielectric layer both in direct contact with the one or more channels; wherein the high k material is a first high k material or a second high k material, the first high k material being made of aluminum oxide and the second high k material being made of lanthanum oxide.

11. 10. The semiconductor structure of claim 8 or 9, wherein the high-k material is a first high-k material or a second high-k material.

12. 12. The semiconductor structure of claim 10 or 11, wherein only said first high-k material is embedded in said gate dielectric layer.

13. 12. The semiconductor structure of claim 10 or 11, wherein only said second high-k material is embedded in said gate dielectric layer.

14. 12. The semiconductor structure of claim 10 or 11, wherein both said first high-k material and said second high-k material are embedded in said gate dielectric layer.

15. 1. A semiconductor structure comprising: a plurality of gate regions of a plurality of field effect transistors overlying the plurality of channels; a metal gate separated from the plurality of channels by a gate dielectric layer; a high-k material embedded in the gate dielectric layer, the high-k material and the gate dielectric layer both in direct contact with the one or more channels; an interlevel dielectric surrounding the plurality of gate regions; wherein the high-k material is provided to provide different dielectric combinations between the gate regions.

16. A semiconductor structure comprising: one or more gate regions of one or more field effect transistors overlying the one or more channels; a metal gate separated from the one or more channels by a gate dielectric layer; a high-k material embedded in the gate dielectric layer, the high-k material and the gate dielectric layer both in direct contact with the one or more channels; an interlevel dielectric surrounding the one or more gate regions; wherein the high-k material provides a threshold voltage differential in the one or more metal gates.

17. 17. The semiconductor structure of claim 15 or 16 wherein said high k material is a first high k material or a second high k material.

18. 20. The semiconductor structure of claim 17 wherein only said first high-k material is embedded in said gate dielectric layer.

19. 20. The semiconductor structure of claim 17 wherein only said second high-k material is embedded in said gate dielectric layer.

20. 20. The semiconductor structure of claim 17 wherein both said first high-k material and said second high-k material are embedded in said gate dielectric layer.

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