Power operating states for core logic in the memory physical layer

Abstract

The electronic device has a memory functional block including a memory circuit and a memory physical layer (PHY) functional block having core logic that controls operation of the memory functional block, a memory PHY voltage regulator, a system voltage regulator, and a controller. The electronic device includes a switch having an input coupled to an output of the memory PHY voltage regulator, another input coupled to the output of the system voltage regulator, and an output coupled to a power supply input of the core logic. The controller configures the switch to provide power from the memory PHY voltage regulator to the core logic in a full-power operating state. The controller configures the switch to provide power from the system voltage regulator to the core logic in one or more low-power operating states.

Description

[Background technology]

[0001] For many electronic devices, especially those that operate using power provided by a battery, power consumption is an important concern. Thus, some electronic devices support low-power operating states that are used to help the electronic device conserve power during operation. For example, some electronic devices support at least one low-power operating state in which the voltage provided to the circuitry (e.g., integrated circuits, discrete components, etc.) within the electronic device is reduced compared to the voltage provided to the circuitry in a full-power operating state. Since power consumption is proportional to the voltage used in the circuitry, reducing the voltage in at least one low-power operating state has the effect of reducing the power consumed by such electronic devices. As another example, an electronic device may support low-power operating states in which operating parameters such as current, clock frequency control, operating speed, etc. are reduced, either alone or in combination with each other (and / or with voltage), to conserve power.

[0002] Although low-power operating states are beneficial in helping electronic devices conserve power, the low-power operating states may be associated with inefficiencies of their own. For example, a power circuit that provides power to other circuits in an electronic device may be designed and provided to operate effectively at a maximum power load for the other circuits, and may operate inefficiently in a lower power operating state. For example, a voltage regulator that is provided for a maximum power load, but is also used to reduce a relatively high input voltage to a lower voltage provided to the circuits in the low-power operating state, may itself experience significant power loss at low power. As another example, entering and leaving a low-power state may be relatively slow and / or require significant effort, which may lead to undesirable delays in transitions between operating states. For example, the electronic device may need to store the electronic device in an operating state before reducing the voltage below a predetermined voltage in the low-power operating state, and then restore the operating state before resuming operation in the operating state where the higher power is provided. [Brief description of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram illustrating an electronic device in accordance with some embodiments. [Diagram 2] 1 is a block diagram illustrating a voltage regulator in an electronic device according to some embodiments. [Diagram 3] FIG. 2 is a block diagram illustrating controller, switch, and memory physical layer (PHY) core logic according to some embodiments. [Figure 4] FIG. 2 is a state diagram illustrating several operating states and transitions between operating states according to some embodiments. [Diagram 5] 4 is a flowchart illustrating a process for setting operational states in memory PHY core logic in accordance with some embodiments. [Figure 6] 4 is a flowchart illustrating a process for determining an operational state in which memory PHY core logic operates, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0004] Throughout the drawings and description, like numbers refer to like figure elements.

[0005] The following description is presented to enable any person skilled in the art to make and use the described embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications. Thus, the described embodiments are not limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features disclosed herein.

[0006] (term) In the following description, various terms are used to describe the embodiments. The following is a simplified and brief summary of one of these terms. Please note that this term may have important additional aspects that are not listed here for clarity and conciseness, and thus the description is not intended to limit the term.

[0007] Functional Block: A functional block refers to a group, collection, and / or set of one or more interrelated circuit elements, such as integrated circuit elements / circuits, discrete circuit elements / circuits, etc. The circuit elements are "interrelated" in that they share at least one attribute. For example, the interrelated circuit elements may be contained within, fabricated on, or otherwise coupled to a particular integrated circuit chip, substrate, circuit board, or portion thereof, may participate in performing a certain function (e.g., a computational or processing function, a memory function, etc.), may be controlled by a common control element and / or a common clock, etc. A functional block may include a circuit having any number of circuit elements, from a single circuit element (e.g., a single integrated circuit logic gate or discrete circuit element) to millions or billions of circuit elements (e.g., integrated circuit memory).

[0008] (overview) In a described embodiment, the electronic device includes subsystems such as a processing subsystem, a display subsystem, a media processing subsystem, and a memory subsystem that are communicatively coupled via a fabric (e.g., one or more buses, interconnects, networks, etc.). The memory subsystem includes memory circuitry for storing copies of data (e.g., inputs or results from computational operations, instructions, control, or configuration values, etc.) and memory physical layer (PHY) circuitry for accessing the data stored in the memory. The memory PHY includes core logic circuitry that manages access to the memory as well as controls other operations in the memory subsystem. The electronic device also includes several voltage regulators that provide power to the subsystems in the electronic device. The voltage regulators include a system voltage regulator that provides power to at least a portion of the media processing subsystem, the display subsystem, and the fabric, and a memory PHY voltage regulator that provides power to the memory subsystem. In a described embodiment, the system voltage regulator and the memory PHY voltage regulator are selectively used to provide power to the core logic in a corresponding operating state for the core logic.

[0009] In the described embodiment, the electronic device supports several operating states for the core logic in the memory PHY. The operating states include a full power operating state and several low power operating states, each associated with a different respective voltage at which power is supplied to the core logic. Generally, for the full power operating state, the core logic is powered at a full power voltage and therefore operates in a typical or normal manner (i.e., has no performance reduction due to reduced voltage levels). For each of the low power operating states, the core logic is provided with power at a respective reduced voltage level and therefore operates with a corresponding reduced performance.

[0010] In some embodiments, for a full-power operating state for the core logic in the memory PHY, the core logic is powered by the memory PHY voltage regulator via a local low dropout (LDO) voltage regulator in the memory PHY (or elsewhere in the electronic device). The memory PHY voltage regulator, which also supplies power to the memory circuits and input output (IO) circuits in the memory PHY, supplies power at a higher voltage (e.g., at a voltage sufficient to operate the memory circuits and IO circuits). The LDO receives the power output of the memory PHY voltage regulator and supplies power to the core logic at a full-power voltage (e.g., 0.6V or another voltage). For a low-power operating state for the core logic in the memory PHY, the core logic is powered by the system voltage regulator. In the low-power operating state, power is supplied to the core logic directly from the system voltage regulator, and the local LDO voltage regulator is bypassed (and possibly powered down). The system voltage regulator, which also supplies power to the display subsystem and the media processing subsystem, supplies power at various voltage levels based on criteria related to the activity and / or busyness of the electronic device or functional blocks therein.

[0011] In some embodiments, the low-power operating states include a "low activity" operating state during which the system voltage regulator supplies power to the core logic at a low activity voltage (e.g., 0.5V or another voltage) lower than the full power voltage. The low activity voltage is sufficient for circuits in the core logic to continue limited operation, but low enough that the core logic experiences a corresponding reduction in performance (e.g., performs operations more slowly than in the full power operating state). The low-power operating states also include a "retention" operating state during which the system voltage regulator supplies power to the core logic at a voltage lower than the low activity voltage (e.g., 0.4V or another voltage). The retention voltage is insufficient for circuits in the core logic to continue reliable operation, but is sufficient to retain state information for circuits in the core logic. The low-power operating states further include a "power off" operating state during which the system voltage regulator does not supply any power to the core logic.

[0012] In a described embodiment, the core logic in the memory PHY receives power from a voltage regulator, and the electronic device includes a two-input, one-output switch circuit used to control the voltage regulator. A first input of the switch is coupled to a power output of the memory PHY voltage regulator, a second input of the switch is coupled to a power output of the system voltage regulator, and an output of the switch is coupled to a power input of the core logic. For full power operating states, a controller in the electronic device sets the switch such that the memory PHY voltage regulator provides power to the core logic via the local LDO. For low activity, retention, and power off states, the controller sets the switch such that the system voltage regulator provides power to the core logic.

[0013] In some embodiments, a controller in the electronic device monitors memory access activity and busy / idle states of the core logic and sets the operating state of the core logic based on the rate of memory access activity and / or the length of time that the core logic is idle. In these embodiments, the controller monitors memory access activity in the electronic device and sets a switch such that the memory PHY voltage regulator provides power to the core logic for a full-power operating state when memory access activity is above a rate threshold (e.g., N memory accesses in the past M milliseconds). On the other hand, the controller sets a switch such that the system voltage regulator provides power to the core logic in one of the low-power operating states when memory access activity is below the rate threshold.

[0014] In some embodiments, for a low-power operating state, the controller maintains the core logic in the memory PHY in low-activity operation as long as the memory access activity is below the speed threshold but there is at least some memory access activity. In this case, the controller (or another entity in the electronic device) sets the system voltage regulator to power the core logic at a low-activity voltage. However, if there is no memory access activity, the controller sets the core logic in either a retained operating state or a powered-off operating state based on the idle state of the core logic. More specifically, the controller monitors the period during which the core logic is idle, i.e., not performing one or more specific activities, such as processing an interrupt. If the core logic experiences an idle period that is shorter in length than the time threshold, the controller sets the system voltage regulator to power the core logic at the retained voltage in the retained operating state. If the core logic experiences an idle period that is longer in length than the time threshold, the controller sets the system voltage regulator to not supply any power to the core logic in the powered-off operating state. It should be noted that in some embodiments, using the powered off operating state involves saving core logic operating state information (e.g., register values, etc.) to a memory (e.g., a state memory within the memory PHY) and then restoring the core logic operating state information from the memory to the core logic before commencing subsequent operation in an operating state other than the powered off operating state.

[0015] In some embodiments, the controller includes one or more operating state change limiting mechanisms that limit the rate at which the controller switches operating states for the core logic in the memory PHY. For example, the controller may maintain a record of previous operating state switches (e.g., from a full power operating state to a low activity operating state, etc.) and use the record to determine the rate at which to switch operating states. The controller may limit some or all switches based on the record. For example, if the operating state switching rate is higher than a threshold, the controller may preferentially keep the core logic in a higher power operating state (rather than automatically switching the core logic to a lower power operating state). As another example, the controller may use an average, maximum / minimum, or other value of the memory access activity level and / or the length of the idle period of the core logic over some specified time, rather than an instantaneous memory access activity level and / or the length of the idle period of the core logic, to determine whether to switch operating states for the core logic.

[0016] By using full-power and low-power operating states for the core logic in the memory PHY, the described embodiments ensure that the core logic is in an appropriate operating state based on memory access activity and / or idle periods of the core logic. This helps to conserve power where possible, but also ensures that the core logic, and therefore the memory subsystem, responds appropriately to memory access requests. By using a combination of memory PHY voltage regulators and system voltage regulators to power the core logic in the respective full-power and low-power operating states, the described embodiments enable more efficient use of power (e.g., lower dynamic power dissipation, etc.) in the electronic device. Thus, the electronic device remains relatively responsive but avoids unnecessary consumption of power, which translates into higher user satisfaction with the electronic device.

[0017] (Electronic Devices) 1 is a block diagram illustrating an electronic device 100, according to some embodiments. As can be seen in FIG. 1, the electronic device 100 includes a processing subsystem 102, a graphics processing subsystem 104, a display subsystem 106, a media processing subsystem 108, a memory subsystem 110, and a fabric subsystem 114. Generally, the processing subsystem 102, the graphics processing subsystem 104, the display subsystem 106, the media processing subsystem 108, the memory subsystem 110, the networking subsystem 112, and the fabric subsystem 114 are functional blocks that are implemented in hardware, i.e., using various circuits, circuit elements, and devices. For example, the processing subsystem 102, the graphics processing subsystem 104, the display subsystem 106, the media processing subsystem 108, the memory subsystem 110, the networking subsystem 112, and the fabric subsystem 114 may be fabricated entirely on one or more semiconductor chips, including on one or more separate semiconductor chips, may be fabricated from semiconductor chips in combination with discrete circuit elements, may be fabricated exclusively from discrete circuits, etc. As described herein, at least some of the processing subsystem 102, graphics processing subsystem 104, display subsystem 106, media processing subsystem 108, memory subsystem 110, networking subsystem 112, and fabric subsystem 114 perform operations related to setting operational states for core logic in a memory physical layer (PHY) of the memory subsystem 110.

[0018] The processing subsystem 102 is a functional block that performs computational and other operations (e.g., control operations, configuration operations, etc.) in the electronic device 100. For example, the processing subsystem 102 can be or include one or more microprocessors, central processing unit (CPU) cores, and / or other processing mechanisms.

[0019] Graphics processing subsystem 104 is a functional block in electronic device 100 that performs computational operations and other operations (e.g., control operations, configuration operations, etc.) related to graphics processing (e.g., rendering, etc.) and / or general-purpose computational operations in electronic device 100. For example, processing subsystem 102 can be or include one or more general-purpose graphics processing unit (GPGPU) cores and / or other graphics processing mechanisms.

[0020] Display subsystem 106 is a functional block that performs operations to display information on a display (e.g., a display screen) for electronic device 100 (not shown). Display subsystem 106 includes one or more controllers, drivers, and / or other circuitry for providing information to and / or receiving information from the display.

[0021] The media processing subsystem 108 is a functional block that performs operations to process audio media (e.g., audio files, audio streams, etc.), video media (e.g., video files, video streams, etc.), haptics, and / or other types of media for storage in memory (e.g., in the memory subsystem 110), streaming over a network, and / or output via speakers, displays and / or other human interface devices. The media processing subsystem 108 includes one or more receivers, processors, encoders / decoders, controllers, drivers, and / or other circuitry for processing media.

[0022] Memory subsystem 110 is a functional block that performs memory (e.g., "main" memory) operations. Memory subsystem 110 includes other functional blocks in electronic device 100, as well as volatile and / or non-volatile memory circuitry, such as fourth generation double data rate synchronous DRAM (DDR4 SDRAM), and / or other types of memory circuitry, for storing data and instructions for use by control circuitry to handle access to data and instructions stored in the memory circuitry and to perform other control or configuration operations. As described below, in the described embodiment, the memory subsystem includes a memory physical layer (PHY) having a core logic circuitry that can operate in several different operating states.

[0023] The networking subsystem 112 is a functional block that performs operations to discover, connect, configure, and communicate over wired and / or wireless electronic communication networks. The networking subsystem 112 includes transceivers, controllers, processors, and / or other circuits for communicating over wired and / or wireless networks.

[0024] Electronic device 100 has been simplified for purposes of explanation. However, in some embodiments, electronic device 100 includes additional or different functional blocks, subsystems, elements, and / or communication paths. For example, electronic device 100 may include an input / output (I / O) subsystem, etc. Generally, electronic device 100 includes sufficient functional blocks to perform the operations described herein.

[0025] Electronic device 100 can be or can be included within any device that performs the operations described herein. For example, electronic device 100 can be or can be included in a desktop computer, a laptop computer, a wearable computing device, a tablet computer, a virtual reality or augmented reality device, a smartphone, an artificial intelligence (AI) or machine learning device, a server, a network appliance, a toy, an audiovisual device, a home appliance, a vehicle, and / or combinations thereof.

[0026] (Voltage regulator) In the described embodiment, electronic device 100 includes a set of voltage regulators, each of which supplies power to a respective functional block within electronic device 100. FIG. 2 is a block diagram illustrating voltage regulators within electronic device 100, according to some embodiments. As can be seen in FIG. 2, the voltage regulators include a voltage regulator 200, a system voltage regulator 204, and a memory physical layer (PHY) voltage regulator 210 (collectively, "voltage regulators"). Each of the voltage regulators includes a voltage regulator circuit, such as a switching voltage regulator or another type of voltage regulator. For example, in some embodiments, some or all of the voltage regulators may be or include one or more step-down or boost converters. Each voltage regulator receives an input voltage, for example, from a power rail within electronic device 100 or another source (not shown), and supplies power at a regulated voltage.

[0027] In the described embodiments, the particular regulated voltage for the power provided by each of the voltage regulators is set using the circuit elements of that voltage regulator. The circuit elements used to control the output of each voltage regulator depend on the type of voltage regulator, i.e., the circuit elements present therein. For example, in some embodiments, the bias or reference voltages provided to the circuit elements of a given voltage regulator may be set to a specified value to cause those circuit elements to begin providing power at their respective voltages. As another example, in some embodiments, amplifiers, resistors, capacitors, inductors, etc. within a given voltage regulator may be configured or set to cause the given voltage regulator to begin providing power at a specified voltage. As another example, in some embodiments, values ​​in registers or memory elements may be used by one or more control circuits or control elements for a given voltage regulator to determine how to set the output voltage for the given voltage regulator to a specified value in order to cause the given voltage regulator to begin providing power at the specified voltage.

[0028] In some embodiments, each of the voltage regulators provides power to a designated "domain" that includes a respective, distinct subset of the functional blocks in electronic device 100. For example, voltage regulator 200 provides power to a domain that includes processing subsystem 102, graphics processing subsystem 104, and a portion of fabric subsystem 114 (shown in FIG. 2 as fabric 202) (e.g., a particular bus, driver, or receiver circuitry of a communications interconnect used in the processing subsystem, etc.). In some embodiments, the domains, and thus the functional blocks contained therein, are configured such that the constituent functional blocks can operate as a group in various operating states. For example, in some embodiments, system voltage regulator 204 provides power to a domain that includes functional blocks that are typically at least partially active in a low-power operating state of the electronic device, even when other voltage regulators, such as voltage regulator 200, provide power at significantly lower voltages or do not provide any power at all. For example, the media processing subsystem 108, the display subsystem 106, and a portion of the fabric subsystem 114 (shown in FIG. 2 as fabric 206) may be at a lower power but still in an active operating state for use in decoding and displaying video media on a display of the electronic device, while the processing subsystem 102 and the graphics processing subsystem 104 are in a low-voltage retention operating state or are powered down. In some of these embodiments, the power domain to which the system voltage regulator 204 supplies power is referred to as a "stutter" domain because functional blocks therein may be switched, or "stuttered," between on and off states as needed to perform corresponding operations in a particular low-power mode (e.g., displaying information on a display of the electronic device 100).

[0029] As shown in FIG. 2, the memory subsystem 110 includes a memory physical layer (MEM PHY) core logic 214, a memory physical layer (MEMPHY) input output (IO) 216, and a memory circuit 218. The memory circuit 218 is a functional block that includes memory circuits used to store copies of data for access (e.g., read, write, delete, modify, etc.) by other functional blocks in the electronic device 100, and circuits for accessing the data in the memory circuit. For example, the memory circuit 218 may include an array of DDR4 SDRAD circuits with a capacity to store gigabytes or terabytes of data. The memory PHY IO 216 is a functional block that performs operations to transmit data obtained from the memory circuit 218 to other functional blocks in the electronic device 100 (e.g., the processing subsystem 102, etc.) and to receive data to be stored in the memory circuit 218 from other functional blocks in the electronic device 100. The memory PHY IO 216 includes circuits such as drivers, receivers, buffers, etc. used to transmit and receive data. Memory PHY core logic 214 is a functional block that contains circuitry for managing access of memory circuitry 218 as well as controlling other operations within memory subsystem 110. Memory PHY core logic 214 includes circuits such as memory access state machine circuitry, memory access routing controller circuitry, memory PHY clock generation circuitry, and memory PHY state information storage memory circuitry.

[0030] Memory PHY IO 216 and memory circuitry 218 are powered (regardless of the operational state of memory PHY core logic 214) by memory PHY voltage regulator 210. In some embodiments, memory PHY voltage regulator 210 provides power at a fixed, sufficiently high and substantially stable voltage to enable reliable operation of circuitry within memory PHY IO 216 and memory circuitry 218.

[0031] Memory PHY core logic 214 is powered from either system voltage regulator 204 or memory PHY voltage regulator 210 via switch (SW) 212. Switch 212 is a two-input, one-output switch (e.g., multiplexer) controlled by controller 208 to selectively supply power from either system voltage regulator 204 or memory PHY voltage regulator 210 according to an operating state of memory PHY core logic 214. One of the inputs of switch 212 is coupled to a power output of memory PHY voltage regulator 210, the other input of switch 212 is coupled to a power output of system voltage regulator 204, and the output of switch 212 is coupled to a power input of memory PHY core logic 214. For a full power operating state, controller 208 sets switch 212 via a switch control input of switch 212 such that memory PHY voltage regulator 210 supplies power to the core logic. For the low activity, retain and power off operating states, the controller 208 configures the switch 212 so that the system voltage regulator 204 provides power to the memory PHY core logic 214. The functionality of the switch 212 and the full power, low activity, retain and power off operating states are described in more detail below.

[0032] In this description, a voltage regulator is described as "providing power" at a particular voltage (e.g., full power voltage, low activity voltage, etc.). As used herein, "providing power" involves supplying sufficient current to meet the demands of an electrical load (e.g., a circuit, a functional block, etc.) at a substantially stable regulated voltage. A "substantially stable" voltage is one that, to the extent possible, is maintained by the voltage regulator at a desired regulated voltage, but which may change in response to, e.g., changes in power demand from, e.g., the electrical load.

[0033] Although a particular number and configuration of voltage regulators is shown in Figure 2, in some embodiments, electronic device 100 includes a different number and / or configuration of voltage regulators. For example, in some embodiments, electronic device 100 includes additional voltage regulators to power functional blocks not shown in Figure 2, such as networking subsystem 112. In general, electronic device 100 includes sufficient voltage regulators to perform the operations described herein.

[0034] (Controller and memory PHY core logic) In the described embodiment, the controller configures the switch such that the desired voltage regulator provides power to the core logic circuitry in the memory PHY through the switch. FIG. 3 is a block diagram illustrating the controller 208, the switch 212, and the memory PHY core logic 214, according to some embodiments. As can be seen in FIG. 3, the controller 208 includes a control logic 300, an activity monitor 302, an idle monitor 304, and a state machine 306. The control logic 300 is a functional block that performs operations to control the switch 212 using the state machine 306 based on inputs received from the activity monitor 302 and the idle monitor 304. The control logic 300 sends a signal to the switch 212, which causes the switch 212 to transfer power received from either the system voltage regulator 204 or the memory PHY voltage regulator 210 to the memory PHY core logic 214. For example, in an embodiment in which the switch 212 is a multiplexer, the control logic 300 controls the switch 212 via a logical high / low level of a multiplexer control signal. As another example, in embodiments in which switch 212 is part of other circuitry, control logic 300 may communicate one or more values ​​(e.g., a bit sequence, a signal level, or an edge, etc.) that cause the other circuitry to set switch 212 appropriately.

[0035] Activity monitor 302 is a functional block that performs operations to determine the rate at which memory accesses are occurring or occur in memory circuit 218 and report the rate of memory access to control logic 300. For example, in some embodiments, activity monitor 302 determines the rate of memory access based on information received or obtained from memory PHY core logic 214 regarding memory access operations that have been performed, are being performed, or will be performed by memory PHY core logic 214. As another example, in some embodiments, activity monitor 302 determines the memory access rate based on queue depths, software or hardware workload profiles, information regarding estimated memory access rates, and / or other information received from other functional blocks in electronic device 100 (e.g., processing subsystem 102, etc.). In some embodiments, activity monitor 302 maintains a record of past memory access rates and / or a running average of memory access rates over one or more time periods and uses this record to support the determination or estimation of memory access rates.

[0036] Idle monitor 304 is a functional block that performs operations to determine the length of idle periods that have been or will be experienced by memory PHY core logic 214 and report the length to control logic 300. In other words, idle monitor 304 determines the actual or estimated length of time that memory PHY core logic 214 is idle (i.e., not engaged in memory access, control, interrupt processing, and / or other operations) and provides a representation of the actual or estimated length of time to control logic 300. For example, in some embodiments, based on information obtained from memory PHY core logic 214 regarding operations that have been, are being, or will be performed by memory PHY core logic 214, idle monitor 304 determines the length or estimated length of idle periods for memory PHY core logic 214. As another example, in some embodiments, based on queue depths, software or hardware workload profiles, information regarding upcoming memory access operations, and / or other information received from other functional blocks in electronic device 100 (e.g., processing subsystem 102, etc.), idle state monitor 304 determines the length or estimated length of an idle period for memory PHY core logic 214. In some embodiments, idle state monitor 304 maintains a record of past idle periods for memory PHY core logic 214 and / or a running average of past idle period lengths for memory PHY core logic 214 and uses this record to support the determination or estimation of the length of a given idle period.

[0037] State machine 306 is a functional block that performs operations to determine an operational state to be used for memory PHY core logic 214 based on the speed of memory access and the length of idle periods of memory PHY core logic 214. State machine 306 includes circuitry that stores or otherwise represents the states of memory PHY core logic 214 and the transitions between states. In operation, state machine 306 receives information regarding the speed of memory access and / or the length of idle periods for memory PHY core logic 214 and returns an indication of the operational state in which memory PHY core logic 214 is to operate based on the received information. The states for the state machine and the transitions between states are shown in FIG. 4 and described below.

[0038] In some embodiments, state machine 306, control logic 300, and / or another functional block includes an operational state change limiting mechanism that limits the rate at which control logic 300 switches operational states for core logic in memory PHY. For example, in some embodiments, operational state change limiting mechanism includes one or more counters that maintain the time since the last transition between two or more respective operational states. In these embodiments, the one or more counters are used to ensure that a particular amount of time has elapsed between each of two or more operational states before a subsequent transition occurs. In some of these embodiments, the particular amount of time is related to or proportional to the latency of the transition between the two or more operational states, with operational states having higher transition latencies having a longer particular amount of time. As another example, in some embodiments, operational state change limiting mechanism includes one or more records of a running average of the time between transitions between two or more respective operational states, one or more records of an average number of operational state transitions between two or more respective operational states within a given period of time, and / or other records representative of the rate of transitions between operational states. In these embodiments, the one or more records are used to control the rate at which transitions are made between operational states. Generally, the operational state change limiting mechanism prevents excessive transitions back and forth between two or more operational states to avoid inconsistent operation (caused by rapid switching between two or more operational states) and unnecessary effort in performing transitions between two or more operational states. In some embodiments, the operational state change limiting mechanism preferentially keeps memory PHY core logic 214 in a higher power operating state (e.g., a full power operating state, a low activity operating state, etc.) rather than allowing memory PHY core logic 214 to rapidly bounce back and forth from a higher power operating state to a lower power operating state (e.g., a low activity operating state, a retained operating state, etc.).

[0039] Memory PHY core logic 214 includes logic circuits 308, state memory (MEM) 310, and low dropout regulators (LDO) 312. Logic circuits 308 are functional blocks that perform operations to control, configure, and operate memory PHY core logic 214. For example, in some embodiments, logic circuits 308 include memory access state machine circuitry used to control accesses of memory circuit 218, memory access routing controller circuitry used to route memory accesses to / from memory circuit 218, memory PHY clock generation circuitry used to generate one or more clocks used for memory accesses in memory circuit 218 and / or operations in memory PHY core logic 214, and / or other circuitry.

[0040] State memory 310 is a functional block that performs operations to store operational state information from circuitry within memory PHY core logic 214. State memory 310 includes memory, such as static random access memory (SRAM), that is used by logic circuitry 308 to store operational state information, such as register contents, configuration bits / flags, settings, operational values ​​(results, inputs, etc.), and / or other state information used by memory PHY core logic 214 or functional blocks therein during operation. In some embodiments, operational state information is read, received, or otherwise obtained from circuitry within memory PHY core logic 214 prior to entering a low-power operational state (e.g., a retention operational state, etc.) in which memory PHY core logic 214 is powered at a sufficiently low voltage that operational state information is not reliably retained in circuitry within memory PHY core logic 214. The state is then stored in state memory 310 until the circuitry in memory PHY core logic 214 is restored to a higher power operating state (such as a full power operating state) in which power is provided to PHY core logic 214 at a high enough voltage to ensure that the operational state information is retained in the circuitry in memory PHY core logic 214. When the circuitry in memory PHY core logic 214 transitions from a lower power operating state to a higher power operating state, the operational state information is read from state memory 310 and used to restore the operational state of the circuitry in memory PHY core logic 214 to the operational state it was in before the transition to the lower power operating state. In some embodiments, there is a delay or latency associated with obtaining and storing the operational state information in state memory 310, and a delay or latency associated with reading the operational state information from state memory 310 and using the operational state information to restore the operational state of the circuitry in memory PHY core logic 214.

[0041] The LDO 312 is a voltage regulator, such as a low dropout regulator, a linear voltage regulator, or another type of voltage regulator. The LDO 312 provides power to the logic circuitry 308 and the state memory 310. More specifically, the LDO 312 receives power from the memory PHY voltage regulator 210, which provides power at a voltage high enough to enable reliable operation of the circuitry in the memory PHY IO 216 and the memory circuitry 218. The LDO 312 reduces (or otherwise regulates) the voltage provided by the memory PHY voltage regulator 210 to a voltage level used by the logic circuitry 308 and the state memory 310. In some embodiments, the LDO 312 includes circuit elements, such as decoupling capacitors, that reduce the effects of undesirable voltage fluctuations, such as transients and noise.

[0042] In some embodiments, the LDO 312 provides power only to the logic circuitry 308 and state memory 310 in certain operating states, and the system voltage regulator 204 provides power to the logic circuitry 308 and state memory 310 in other operating states. In these embodiments, the controller 208 uses the switch 212 to control which voltage regulator, from within the memory PHY voltage regulator 210 or the system voltage regulator 204, provides power to the logic circuitry 308 and state memory 310. For example, in some embodiments, the controller 208 sets the switch 212 such that the memory PHY voltage regulator 210 provides power (via the switch 212 and the LDO 312) to the logic circuitry 308 and state memory 310 only in a full power operating state. In these embodiments, the controller 208 sets the switch 212 such that the system voltage regulator 204 provides power to the logic circuitry 308 and state memory 310 in a low power operating state (e.g., a low activity operating state, etc.).

[0043] In some embodiments, the LDO 312 is bypassed, and possibly powered down, when it is not being used to regulate voltage in full power operating conditions. This is seen in FIG. 3 via the dashed line (dashed for clarity) that goes from the system voltage regulator 204 to the logic circuitry 308 and state memory 310 without including the LDO 312. The dashed line shows the approximate route of power flow in a low power operating condition. As can be seen from the dashed line, the system voltage regulator 204 powers the logic circuitry 308 and state memory 310 more directly than the memory PHY voltage regulator 210. In contrast, the solid line shows the approximate path of power flow (from the memory PHY voltage regulator 210, through the switch 212, to the LDO 312, to the logic circuitry 308 and state memory 310) in a full power operating condition. By bypassing and possibly powering down the LDO 312, these embodiments can avoid unnecessary power dissipation in the LDO 312 when the LDO 312 is not being used to power the logic circuitry 308 and state memory 310.

[0044] In some embodiments, some or all of the circuitry for controller 208 is located in close physical proximity to switch 212 and / or memory PHY core logic 214. For example, circuitry such as control logic 300 and state machine 306 may be located in the same area or section of an integrated circuit chip as switch 212 and / or memory PHY core logic 214. Thus, in these embodiments, controller 208 may respond relatively quickly to, and thus cause, transitions between operational states. Combined with the use of retained operational states in which operational states are maintained in logic circuitry 308, this ability to transition relatively quickly between operational states means that low power operational states can be used more frequently and for shorter periods of time. This is appropriate because the latency of entering and exiting low power states is shorter given the proximity of the circuitry in controller 208 and the retained state information in logic circuitry 308.

[0045] (State Machine) 4 is a state diagram illustrating some operational states and transitions between operational states in a state machine, according to some embodiments. In some embodiments, memory PHY core logic 214 is operated in selected ones of the operational states. In these embodiments, controller 208 uses the state machine to transition memory PHY core logic 214 between the operational states (such that memory PHY core logic 214 is in one of the operational states) based on criteria associated therewith.

[0046] 4, the operating states include a full power 400 operating state, a low activity 402 operating state, a retention 404 operating state, and a power off 406 operating state (collectively, "operating states"). For the full power 400 operating state, power is provided from memory PHY voltage regulator 210 through switch 212 and LDO 312 to memory PHY core logic 214 at a full power voltage (e.g., 0.6V or another voltage). The full power voltage is a voltage at which memory PHY core logic 214 operates normally or normally and does not have the performance reduction associated with lower voltage levels. In other words, the full power voltage is high enough that memory PHY core logic 214 operates at a certain full speed (which may not be the fastest possible operating speed) and is not hindered from operating due to a lack of voltage. In some embodiments, the controller 208 places and maintains the memory PHY core logic 214 in a full power 400 operating state (i.e., sets and holds the switch 212 appropriately) as long as the rate of memory access activity exceeds a rate threshold. For example, the rate threshold may be N memory accesses in M ​​milliseconds, where N and M are particular numbers.

[0047] For the low activity 402 operating state, power is supplied from system voltage regulator 204 through switch 212 to memory PHY core logic 214 at a low activity voltage. The low activity voltage is lower than the full power voltage (e.g., 0.5V or another voltage). The low activity voltage is sufficient for circuits within the memory PHY core logic to continue limited operation, but low enough that the memory PHY core logic experiences a corresponding reduction in performance. For example, the memory PHY core logic may perform operations more slowly at an activity voltage lower than the full power voltage. In some embodiments, controller 208 places and maintains memory PHY core logic 214 in the low activity 402 operating state if the rate of memory access activity falls below a rate threshold, but there is at least some memory access activity.

[0048] For the Retain 404 operating state, power is provided from system voltage regulator 204 through switch 212 to memory PHY core logic 214 at a Retain voltage. The Retain voltage is lower than a low activity voltage (e.g., 0.4V or another voltage). The Retain voltage is low enough that it is insufficient for circuits in memory PHY core logic 214 (e.g., logic circuits 308, etc.) to continue reliable operation, but sufficient to retain state information for circuits in memory PHY core logic 214. For example, at the Retain voltage, registers, memory elements, etc. in memory PHY core logic 214 used to store register values, configuration bits / flags, settings, operational values ​​(results, inputs, etc.), and / or other state information may continue to reliably store these values. In some embodiments, controller 208 places and maintains memory PHY core logic 214 in the Retain 404 operating state when no memory accesses are being performed and memory PHY core logic 214 experiences a short idle period (e.g., the idle period is less than a time threshold T).

[0049] For the power off 406 operating state, no power is provided to the memory PHY core logic 214 from the system voltage regulator 204. In the power off operating state, due to the lack of power, the memory PHY core logic 214 is shut down or powered off and does not perform any operations. Also, unlike the retain 404 operating state, the memory PHY core logic 214 does not retain operational state information. Instead, prior to entering the power off 406 operating state, the operational state information is copied to the state memory 310, where the operational state information is retained until it is used to restore the operational state of the memory PHY core logic 214 following a transition from the power off 406 operating state to another operating state. In some embodiments, the controller 208 places and maintains the memory PHY core logic 214 in the power off 406 operating state when no memory accesses are being performed and the memory PHY core logic 214 experiences a long idle period (e.g., an idle period longer than a time threshold T).

[0050] As indicated by the arrows in FIG. 4, in some embodiments, the controller can transition the memory PHY core logic from any operating state to any other operating state. For example, the controller can transition the memory PHY core logic from a full power 400 operating state to a low activity 402 operating state, a retention 404 operating state, or a power off 406 operating state, or vice versa. In these embodiments, the controller 208 transitions the memory PHY core logic 214 between states based on the speed of memory accesses and / or the length of idle periods. However, in some embodiments, a particular sequence of transitions is performed. For example, in some of these embodiments, the sequence of transitions is full power 400, low activity 402, retention 404, and power off 406, or vice versa. Generally, in the described embodiments, the controller can transition the memory PHY core logic between at least some of the operating states based on the speed of memory accesses and / or the length of idle periods.

[0051] Although embodiments are described above in which only memory PHY core logic 214 is powered at different voltages in each operating state, in some embodiments, one or more other functional blocks in electronic device 100 are powered by system voltage regulator 204 at the same voltages in some or all operating states. For example, in some embodiments, system voltage regulator 204 provides power to display subsystem 106, media processing subsystem 108, etc. at a low active voltage, at a retention voltage, and / or does not provide any power (in the power off 406 operating state). Thus, in these embodiments, memory PHY core logic 214 is in the "same" low power state as other functional blocks in the power domain provided by system voltage regulator 204.

[0052] 4, in some embodiments, a different number or configuration of operating states, criteria for transitioning into / out of operating states, and / or voltage regulators are used. For example, in some embodiments, memory PHY voltage regulator 210 powers memory PHY core logic 214 in one or more low-power operating states at a corresponding reduced voltage (not shown). In general, in the described embodiments, any number of operating states may be used, provided that at least some of the operating states are as described herein.

[0053] (Process for setting the operating state for the memory physical layer (PHY) core logic) In the described embodiment, a controller (e.g., controller 208) controls the operating states for the memory PHY core logic (e.g., memory PHY core logic 214) and therefore the voltage at which power is supplied to the memory PHY core logic. FIG. 5 is a flow chart illustrating a process for setting the operating states for the memory PHY core logic, according to some embodiments. It should be noted that the operations illustrated in FIG. 5 are provided as general examples of operations performed by some embodiments. Operations performed by other embodiments include different operations, operations performed in a different order, and / or operations performed by different functional blocks.

[0054] The process of Figure 5 begins when the controller determines the power operating state in which the memory PHY core logic is to be operated (step 500). For this operation, the controller tracks the rate at which memory accesses are being performed and / or the length of idle periods for the memory PHY core logic and uses the rate at which memory accesses are being performed and / or the length of the idle periods to determine the operating state in which the memory PHY core logic is to be operated. In some embodiments, the controller uses state machine circuitry (e.g., state machine 306) to determine the operating state in which the memory PHY core logic is to be operated. The determination operation is described in more detail below with respect to Figure 6.

[0055] If the memory PHY core logic is not operated in a low-power operating state (step 502), the controller sets a switch (e.g., switch 212) such that the memory PHY core logic is powered in a full-power operating state from a memory PHY voltage regulator (e.g., memory PHY voltage regulator 210) (step 504). For this operation, the controller configures a path for power to flow through the switch to the memory PHY core logic such that power is provided from the memory PHY voltage regulator, passed through the switch to a local LDO (e.g., LDO 312) within the memory PHY core logic, and then provided from the LDO to circuits (e.g., logic circuit 308, etc.) within the memory PHY core logic.

[0056] If the memory PHY core logic is operated in a low power operating state (step 502), the controller sets a switch (e.g., switch 212) such that the memory PHY core logic is powered in the low power operating state (step 506) from a system voltage regulator (e.g., system voltage regulator 204). For this operation, the controller configures a path for power to flow through the switch to the memory PHY core logic such that power is provided from the system voltage regulator, through the switch, and to circuits within the memory PHY core logic (e.g., logic circuit 308, etc.). As noted above, in some embodiments, the LDOs are bypassed and possibly powered down in the low power operating state.

[0057] 6 is a flow chart illustrating a process for determining an operational state in which memory PHY core logic operates, according to some embodiments. In some embodiments, the operations in FIG. 6 are performed as part of process 500, although this is not a requirement. Note that the operations illustrated in FIG. 6 are provided as general examples of operations performed by some embodiments. Operations performed by other embodiments include different operations, operations performed in a different order, and / or operations performed by different functional blocks.

[0058] The process in FIG. 6 begins when a controller (e.g., controller 208) monitors memory access activity in a memory subsystem (memory subsystem 110) (step 600). For this operation, the controller determines the rate at which memory accesses are occurring in the memory subsystem based on information received from an activity monitor (e.g., activity monitor 302) and / or another functional block. For example, the activity monitor may periodically provide information to the controller indicative of the number of memory accesses in the previous second, the average percentage of all time available to perform memory accesses used to perform memory accesses, etc. The controller also monitors the idleness of core logic in the memory PHY (e.g., memory PHY core logic 214) (step 602). For this operation, the controller determines the length of one or more idle periods during which the memory PHY core logic is idle based on information received from an idle monitor (e.g., idleness monitor 304) and / or another functional block. For example, the idle state monitor may periodically provide information to the controller indicative of the length of a particular idle period, the average length of two or more idle periods, the average percentage of total time available to perform operations in the memory PHY core logic used to perform the operations, etc.

[0059] If the rate of memory access exceeds a rate threshold (step 604), the controller configures the memory PHY core logic into a full-power operating state (step 606). For this operation, the controller maintains the memory PHY core logic in a full-power operating state if the memory subsystem is busy enough to perform memory accesses. In this operating state, the memory PHY core logic is powered by a memory PHY voltage regulator (e.g., memory PHY voltage regulator 210) through a local LDO (e.g., LDO 312) at the full power voltage. In the full-power operating state, the memory PHY core logic responds normally or normally to memory access requests and performing other operations.

[0060] If the rate of memory access falls below a rate threshold (step 604) but there is memory access activity (step 608), the controller configures the memory PHY core logic in a low-power operating state (step 610). In this operation, the controller keeps the memory PHY core logic in a low-activity operating state when the memory subsystem is not busy performing memory accesses but is performing at least some memory accesses. In this low-activity operating state, power is provided to the memory PHY core logic by a system voltage regulator (e.g., system voltage regulator 204) at a low-activity voltage. In some embodiments, due to the difference between the low-activity voltage and the full-power voltage, the operating speed of the memory PHY core logic is slower in the low-activity operating state than in the full-power operating state. Thus, in the low-activity operating state, the memory PHY core logic responds to memory access requests and performs other operations slower, but also conserves power.

[0061] If there is no memory access activity (step 608) and the memory PHY core logic experiences an idle period shorter than a time threshold (step 612), the controller configures the memory PHY core logic in a retained operating state (step 614). For this operation, if the memory subsystem is not performing any memory accesses and the core logic experiences a relatively short idle period, the controller holds the memory PHY core logic in a retained operating state in which the memory PHY core logic is powered at a retained voltage. In the retained operating state, the memory PHY core logic cannot operate reliably due to a low retained voltage, but the retained voltage is high enough to maintain operating state information within the memory PHY core logic. Storing and retaining the operating state information within the memory PHY core logic (instead of saving the operating state information in a state memory) allows for a quicker recovery from the retained operating state to a more highly powered operating state (i.e., a low activity operating state, a full power operating state, etc.).

[0062] If there is no memory access activity (step 608) and the memory PHY core logic experiences an idle period longer than a time threshold (step 612), the controller configures the memory PHY core logic into a powered off operational state (step 616). For this operation, if the memory subsystem is not performing any memory accesses and the core logic experiences a relatively long idle period, the controller powers down the memory PHY core logic so as not to provide any power to the memory PHY core logic. In the powered off operational state, the memory PHY core logic cannot perform operations. In some embodiments, entering the powered off operational state involves saving operational state information for the memory PHY core logic. For example, the operational state information can be obtained from the memory PHY core logic and stored in a state memory (e.g., state memory 310) and / or another memory (e.g., memory in memory subsystem 110, etc.).

[0063] In some embodiments, at least one electronic device (e.g., electronic device 100) uses code and / or data stored in a non-transitory computer-readable storage medium to perform some or all of the operations described herein. More specifically, at least one electronic device reads the code and / or data from the computer-readable storage medium and executes the code and / or uses the data when performing the operations described. The computer-readable storage medium can be any device, medium, or combination thereof that stores code and / or data for use by the electronic device. For example, the computer-readable storage medium can include, but is not limited to, volatile and / or non-volatile memory including flash memory, random access memory (e.g., eDRAM, RAM, SRAM, DRAM, DDR4 SDRAM, etc.), non-volatile RAM (e.g., phase change memory, ferroelectric random access memory, spin transfer torque random access memory, magnetoresistive random access memory, etc.), read only memory (ROM), and / or magnetic or optical storage media (e.g., disk drives, magnetic tapes, CDs, DVDs, etc.).

[0064] In some embodiments, one or more hardware modules perform the operations described herein. For example, hardware modules may include, but are not limited to, one or more central processing units (CPUs) / CPU cores, graphic processors (GPUs) / GPU cores, application specific integrated circuits (ASICs) chips, field programmable gate arrays (FPGAs), compressors or encoders, computational units, embedded processors, accelerated processing units (APUs), controllers, neural network processors, and / or other functional blocks. When circuits (e.g., integrated circuit elements, discrete circuit elements, etc.) within such hardware modules are activated, the circuits perform some or all of the operations. In some embodiments, hardware modules include general purpose circuits, such as execution pipelines, computational or processing units, that perform operations in conjunction with the execution of instructions (program code, firmware, etc.). In some embodiments, hardware modules include unique or dedicated circuits that perform operations, and in some cases, include circuits that perform some or all of the operations "in hardware" without executing instructions.

[0065] In some embodiments, data structures representing some or all of the functional blocks and circuit elements described herein (e.g., electronic device 100 or portions thereof) are stored in a non-transitory computer-readable storage medium, including a database or other data structure, which can be read by the electronic device or used directly or indirectly to manufacture hardware including the functional blocks and circuit elements. For example, the data structure may be a behavioral level description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL, or a register transfer level (RTL) description. The description may be read by a synthesis tool, which may synthesize the description to generate a netlist from a synthesis library that includes a list of transistors / circuit elements that represent the functionality of the hardware including the functional blocks and circuit elements described above. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing processes to manufacture one or more semiconductor circuits (e.g., integrated circuits) corresponding to the functional blocks and circuit elements described above. Alternatively, the database on the computer accessible storage medium may be a netlist (with or without a synthesis library) or a data set, as appropriate, or may be Graphic Data System (GDS) II data.

[0066] In this specification, variables or unspecified values ​​(i.e., general descriptions of values ​​without specific examples of values) are represented by letters such as N, M, X, etc. As used herein, similar letters may be used elsewhere in this specification in some cases, but the variables and unspecified values ​​in each instance are not necessarily the same, i.e., there may be different variable quantities and values ​​that cover some or all of the general variables and unspecified values. In other words, the specific instances of N and any other letters used to represent variables and unspecified values ​​in this specification are not necessarily related to each other.

[0067] The phrase "etc.," as used herein, is intended to indicate instances of "and / or," i.e., the equivalent of "at least one of" the elements in the list with which the "etc." is associated. For example, in the sentence "the electronic device performs a first operation, a second operation, etc.," the electronic device performs at least one of the first operation, the second operation, and other operations. Also, the elements in the list with which the "etc." is associated are merely examples from a series of examples, and at least some of the examples may not appear in some embodiments.

[0068] The foregoing descriptions of the embodiments have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Accordingly, numerous modifications and variations will be apparent to those skilled in the art. Furthermore, the above disclosure is not intended to limit the embodiments. The scope of the embodiments is defined by the appended claims.

Claims

1. A memory functional block including a plurality of memory circuits and a memory physical layer (PHY) functional block, the memory PHY functional block including a core logic that controls an operation of the memory PHY functional block; A memory PHY voltage regulator; A system voltage regulator; a switch having a first input coupled to an output of the memory PHY voltage regulator, a second input coupled to an output of the system voltage regulator, and an output coupled to a power supply input of the core logic; a controller coupled to the switch; The controller: configuring the switch to supply power from the memory PHY voltage regulator to the core logic in a full power operating state based on a rate of memory access activity in the memory functional block exceeding a rate threshold; configuring the switch to power the core logic from the system voltage regulator in each of a plurality of low power operating states based on a rate of memory access activity in the memory functional block falling below the rate threshold; 4. The method of claim 3, Electronic devices.

2. The plurality of low power operating states include: a low activity operating state in which the system voltage regulator powers the core logic at a reduced voltage, the reduced voltage being less than a full operating voltage of circuitry within the core logic but sufficient to allow circuitry within the core logic to continue limited operation; a retain operating state in which the system voltage regulator powers the core logic at a retain voltage, the retain voltage being lower than the reduced voltage and not sufficient to ensure that circuitry within the core logic continues the limited operation, but sufficient to retain state information of circuitry within the core logic; a power off operating state in which the system voltage regulator does not supply power to the core logic. The electronic device of claim 1 .

3. The controller: determining a rate of memory access activity in the memory functional block; configuring the core logic to a full power operating state when the rate of memory access activity exceeds the rate threshold, the configuring including setting the switch such that power is supplied to the core logic from the memory PHY voltage regulator; configuring the core logic into the low activity operating state when the rate of memory access activity falls below the rate threshold but is greater than zero, the configuring including setting the switch such that power is supplied from the system voltage regulator to the core logic at the reduced voltage; configuring the core logic into either the retained operational state or the powered off operational state based on an idle state of the core logic when the rate of memory access activity is zero and therefore the memory functional block is not performing memory accesses; 4. The method of claim 3, The electronic device of claim 2.

4. The controller: determining a length of an idle period during which the core logic is idle; configuring the core logic into the retained operating state when the rate of memory access activity is zero and the length of the idle period is less than a length of a time threshold, said configuring including setting the system voltage regulator to supply power to the core logic at the retained voltage; configuring the core logic into the powered off operational state when the rate of memory access activity is zero and the length of the idle period is greater than the length of the time threshold, said configuring including setting the system voltage regulator to not supply power to the core logic; 4. The method of claim 3, The electronic device of claim 3.

5. the controller includes a state machine circuit; The controller: configured to use the state machine circuitry to determine transitions between the full-power operating state, the low activity operating state, the retained operating state, and the power-off operating state based on a rate of memory access activity and / or a length of the idle period. The electronic device of claim 4.

6. the controller includes one or more operating state change limiting mechanisms; the controller is configured to use the operational state change limiting mechanism to limit a rate at which the controller transitions the operational state of the core logic between the full power operational state, the low activity operational state, the retained operational state, and the power off operational state. The electronic device of claim 4.

7. a low dropout (LDO) regulator for the core logic, the LDO regulator having a first input coupled to the power supply input of the core logic and an output coupled to a circuit within the core logic, the LDO regulator configured to supply power to the circuit within the core logic; the LDO regulator is enabled in the full power operating state such that the circuit receives power from the memory PHY voltage regulator through the LDO regulator; the LDO regulator is disabled or bypassed in the low activity operating state such that the circuit receives power from the system voltage regulator. The electronic device of claim 2.

8. The LDO voltage regulator includes circuitry for reducing noise and transient signals.

8. The electronic device of claim 7.

9. the memory PHY functional block includes input output (IO) circuitry; the memory PHY voltage regulator provides power to the IO circuitry regardless of the operating state of the core logic; The electronic device of claim 1 .

10. the core logic includes one or more of a memory access state machine circuit, a memory access routing controller circuit, a memory PHY clock generation circuit, and a memory PHY state information storage memory circuit; The electronic device of claim 1 .

11. the electronic device includes one or more external functional blocks separate from the memory functional block; the system voltage regulator is configured to provide power to the external functional blocks regardless of an operating state of the core logic. The electronic device of claim 1 .

12. 1. A method for providing power to a functional block in an electronic device, comprising: The electronic device comprises: A memory functional block including a plurality of memory circuits and a memory physical layer (PHY) functional block, the memory PHY functional block including a core logic that controls an operation of the memory PHY functional block; A memory PHY voltage regulator; A system voltage regulator; a switch having a first input coupled to an output of the memory PHY voltage regulator, a second input coupled to an output of the system voltage regulator, and an output coupled to a power supply input of the core logic; a controller coupled to the switch; the controller configuring the switch to supply power from the memory PHY voltage regulator to the core logic in a full power operating state based on a rate of memory access activity in the memory functional block exceeding a rate threshold; and configuring the switch to supply power from the system voltage regulator to the core logic in each of a plurality of low power operating states based on a rate of memory access activity in the memory functional block falling below the rate threshold. method.

13. The plurality of low power operating states include: a low activity operating state in which the system voltage regulator powers the core logic at a reduced voltage, the reduced voltage being less than a full operating voltage of circuitry within the core logic but sufficient to allow circuitry within the core logic to continue limited operation; a retain operating state in which the system voltage regulator powers the core logic at a retain voltage, the retain voltage being lower than the reduced voltage and not sufficient to ensure that circuitry within the core logic continues the limited operation, but sufficient to retain state information of circuitry within the core logic; a power off operating state in which the system voltage regulator does not supply power to the core logic.

13. The method of claim 12.

14. the controller determining a rate of memory access activity in the memory functional block; when the rate of memory access activity exceeds the rate threshold, the controller configuring the core logic to a full power operating state, the configuring including setting the switch such that power is supplied to the core logic from the memory PHY voltage regulator; when the rate of memory access activity falls below the rate threshold but is greater than zero, the controller configuring the core logic into the low activity operating state, the configuring including setting the switch such that power is supplied from the system voltage regulator to the core logic at the reduced voltage; and when the rate of memory access activity is zero and thus the memory functional block is not performing memory accesses, the controller configures the core logic into either the retained operational state or the powered off operational state based on an idle state of the core logic.

14. The method of claim 13.

15. the controller determining a length of an idle period during which the core logic is idle; if the rate of memory access activity is zero and the length of the idle period is less than a length of a time threshold, the controller configuring the core logic to the retained operating state, the configuring including setting the system voltage regulator to supply power to the core logic at the retained voltage; and if the rate of memory access activity is zero and the length of the idle period is greater than the length of the time threshold, the controller configuring the core logic to the powered off operational state, the configuring including setting the system voltage regulator to not supply power to the core logic.

15. The method of claim 14.

16. the controller includes a state machine circuit; The method comprises: the controller using the state machine circuitry to determine transitions between the full power operating state, the low activity operating state, the retained operating state, and the power off operating state based on a rate of the memory access activity and / or a length of the idle period.

16. The method of claim 15.

17. the controller includes one or more operating state change limiting mechanisms; the controller using the operational state change limiting mechanism to limit a rate at which the controller transitions the operational state of the core logic between the full power operational state, the low activity operational state, the retained operational state, and the power off operational state.

16. The method of claim 15.

18. the memory PHY functional block comprises a low dropout (LDO) regulator for the core logic, the LDO regulator having a first input coupled to the power supply input of the core logic and an output coupled to a circuit within the core logic, the LDO regulator configured to supply power to the circuit within the core logic; The method comprises: the controller enabling the LDO regulator in the full power operating state such that the circuit receives power from the memory PHY voltage regulator through the LDO regulator; and the controller disabling or bypassing the LDO regulator in the low activity operating state such that the circuit receives power from the system voltage regulator.

14. The method of claim 13.

19. The LDO voltage regulator includes circuitry for reducing noise and transient signals.

20. The method of claim 18.

20. the memory PHY functional block includes input output (IO) circuitry; The method comprises: the memory PHY voltage regulator providing power to the IO circuitry regardless of an operating state of the core logic.

13. The method of claim 12.

21. the core logic includes one or more of a memory access state machine circuit, a memory access routing controller circuit, a memory PHY clock generation circuit, and a memory PHY state information storage memory circuit; 13. The method of claim 12.

22. the electronic device includes one or more external functional blocks separate from the memory functional block; The method comprises: the system voltage regulator providing power to the external functional blocks regardless of an operating state of the core logic.

13. The method of claim 12.

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