Gallium Nitride Power Transistor

Abstract

The present disclosure relates to a gallium nitride power transistor (100), comprising a buffer layer (110) and a barrier layer (111) having a top surface (111a) and a bottom surface (111b), with the bottom surface (111b) facing the buffer layer (110) and the bottom surface (111b) of the barrier layer (111) disposed on the buffer layer (110), and an intermediate layer (111) interposed between the barrier layer and a p-type doped gallium nitride layer (112) and a metal gate layer (114). and an intermediate layer made of a III-V compound semiconductor having a combination of at least one Group III element and at least one Group V element, wherein a p-type doped gallium nitride layer (112) is disposed on a top surface (111a) of the barrier layer (111), and a metal gate layer (114) is electrically connected to the p-type doped gallium nitride layer (112) through the intermediate layer (113) to form a rectifying metal-semiconductor junction (115) with the p-type doped gallium nitride layer (112).

Description

[Technical field]

[0001] The present disclosure relates to the field of gallium nitride (GaN) technology for power device applications. In particular, the present disclosure relates to gallium nitride power transistors, and more particularly to GaN power field effect transistors (FETs) with rectifying metal-semiconductor junctions. The present disclosure particularly relates to Schottky pGaN gate modules with intermediate layers. [Background technology]

[0002] Intensive efforts have been made in the semiconductor industry for the past 15-20 years to develop gallium nitride technology as a possible replacement for traditional Si-based field effect transistors. The use of wide band gap materials offers the potential for unprecedented performance improvements at both device and system levels. Today, enhancement mode GaN power FETs are becoming a reality, with several major semiconductor manufacturers already having products in the market. The most mature GaN device concept utilized by the majority of players is the pGaN normally-off concept. Two general approaches are currently followed for the fabrication of normally-off pGaN power FETs. The main difference lies in the fabrication strategy of the metal / pGaN interface. The two possible approaches are i) Ohmic interface and ii) Schottky interface. With the Schottky approach, a significant reduction in DC gate current can be achieved, but at the expense of two main drawbacks: threshold voltage instability and poor gate reliability. Summary of the Invention

[0003] The objective of this disclosure is to provide a solution for GaN power transistors that do not suffer from the above-mentioned drawbacks of threshold voltage instability and poor gate reliability, or at least in which the problems of threshold voltage instability and poor gate reliability are significantly reduced.

[0004] This object is achieved by means of the features of the independent claims. Further implementations become apparent from the dependent claims, the description and the drawings.

[0005] The basic idea of ​​this disclosure is to provide a new structure for the gate module of normally-off pGaN transistors, which makes it possible to optimize the overall performance and to solve the main problems of state-of-the-art pGaN Schottky gates, namely threshold voltage instability and gate reliability.

[0006] In this disclosure, a stable pGaN Schottky gate solution with an interlayer is presented, in which a dedicated III-V interlayer is interposed between the pGaN layer and the metal gate, the thickness and composition of which, when properly selected in conjunction with the detailed composition of the gate stack, makes it possible to have a stable pGaN Schottky operation and significantly improves the threshold voltage stability and overall gate reliability.

[0007] In this disclosure, we describe intermediate layers made of group III and group V elements, as well as III-V intermediate layers, i.e., III-V compound semiconductors. III-V compound semiconductors are obtained by combining group III elements (particularly Al, Ga, In) with group V elements (particularly N, P, As, Sb). This gives 12 possible main combinations and a further number of subcombinations when combining one or more group III elements with one or more group V elements, the most important of which in this disclosure are GaN, AlGaN, AlN, and InAlN.

[0008] To describe this disclosure in detail, the following terms, abbreviations, and notations are used: GaN Gallium Nitride FET Field Effect Transistor pGaN p-doped GaN AlGaN Aluminum Gallium Nitride 2DEG Two-dimensional electron gas HV High voltage (operating), e.g. >600V MV Medium voltage (operating), e.g. 200-600V V TH Threshold Voltage TDDB Time Dependent Dielectric Breakdown.

[0009] In this disclosure, two approaches to fabricating a metal / pGaN interface are described: an Ohmic interface approach and a Schottky interface approach.

[0010] In the ohmic interface approach, the interface between the metal gate and the pGaN surface is nearly ideal, which leads to a large DC current that sustains device operation during the on-state condition, but also complicates the driving strategy and significantly increases the driving losses.

[0011] The ohmic interface approach offers the following advantages: (i) the pGaN node is neatly connected to the gate metal terminal, and therefore the device is V TH (ii) the reliability is good, and gate breakdown is due to thermal runaway when a large DC current flows through the gate; (iii) a large amount of holes injected from the gate improves the dynamic performance.

[0012] However, the ohmic interface approach introduces the following drawbacks: (i) a large amount of holes injected into the buffer requires a negative off-phase gate voltage; (ii) hole accumulation can cause tail current; (iii) a dedicated driving scheme is required: a current-driven gate driver, an external RC network; and (iv) the large DC gate current leads to drive losses, limiting the scalability of the concept to high voltages (400-600 V) and large R DSON (>30mOhm).

[0013] In the Schottky interface approach, a reverse-biased Schottky diode is inserted in series with the pn-p GaN / AlGaN diode, which allows for a significant reduction in the DC gate current.

[0014] The Schottky interface approach offers the following advantages: (i) the pGaN node is isolated from the gate terminal by a reverse-biased Schottky diode; (ii) the V TH A low DC gate current is obtained at the expense of instability; (iii) a low DC current implies a more difficult dynamic effect optimization due to a smaller amount of holes injected into the buffer; (iv) the gate module breaks down via the TDDB mechanism (like the oxide in Si-MOS devices); (v) the dynamic effects, gate reliability, and V TH A difficult interplay between stability.

[0015] However, the Schottky interface approach presents the following drawbacks: (i) it does not offer the best FOM (figure of merit) (low C GS and C GD (ii) there is essentially no DC gate current; (iii) the approach allows standard driving schemes such as voltage driving approaches, no external RC network; (iv) the concept can be used in both HV and MV operation; (v) the concept has a very low R DSON Allows device scaling to

[0016] According to a first aspect, the present disclosure relates to a gallium nitride power transistor having a buffer layer, a barrier layer having a top surface and a bottom surface, the bottom surface facing the buffer layer, the bottom surface of the barrier layer being disposed on the buffer layer, and an intermediate layer interposed between a p-type doped gallium nitride layer and a metal gate layer, the intermediate layer being made of a III-V compound semiconductor having a combination of at least one group III element and at least one group V element, wherein the p-type doped gallium nitride layer is disposed on the top surface of the barrier layer, and the metal gate layer is configured to electrically connect to the p-type doped gallium nitride layer through the intermediate layer to form a rectifying metal-semiconductor junction with the p-type doped gallium nitride layer.

[0017] Such a GaN power transistor with a rectifying metal-semiconductor junction and an interlayer provides a new Schottky pGaN gate module concept for enhancement mode GaN-based power transistors, which allows for the following advantages: normally-off operation; stable threshold voltage and suppression of dynamic instabilities that characterize conventional pGaN Schottky gate approaches; and improved gate reliability due to the significant reduction of the peak electric field at the metal / pGaN interface and in the pGaN bulk by the interlayer.

[0018] In one exemplary implementation of the GaN power transistor, the gate region of the gallium nitride power transistor is formed by a contact region of the p-type doped gallium nitride layer with the barrier layer at the top surface of the barrier layer.

[0019] This provides the advantage that the contact areas can be precisely and selectively defined during the etching process. A further advantage is that the manufacturing process can be precisely performed, allowing GaN power transistors to be manufactured with high gate reliability.

[0020] In one exemplary implementation of the GaN power transistor, the at least one group III element comprises one of the following chemical elements: aluminum, gallium, and indium. In one exemplary implementation of the GaN power transistor, the at least one group V element comprises one of the following chemical elements: nitrogen, phosphorus, arsenic, and antimony.

[0021] This offers the advantage that III-V compound semiconductors, obtained by combining these group III elements (especially Al, Ga, In) with group V elements (especially N, P, As, Sb), result in wider band gap semiconductors. For example, gallium arsenide (GaAs) has six times higher electron mobility than silicon, which allows for faster operation. The wider band gap allows power devices to operate at higher temperatures and gives lower thermal noise for low power devices at room temperature.

[0022] In one exemplary implementation of the GaN power transistor, the metal gate layer is electrically connected to the p-type doped gallium nitride layer through an intermediate layer and is configured to form a Schottky barrier with the p-type doped gallium nitride layer.

[0023] This provides the advantage that the overall performance of the power transistor is optimized while exhibiting a stable threshold voltage and reliable gate by electrically connecting through the interlayer to the p-type doped gallium nitride layer and forming a Schottky barrier with the p-type doped gallium nitride layer. With a properly selected thickness and composition of this III-V interlayer, the power transistor can be operated with stable pGaN Schottky action, and the threshold voltage stability and overall gate reliability are significantly improved.

[0024] In one exemplary implementation of the GaN power transistor, the intermediate layer comprises aluminum gallium nitride.

[0025] Aluminum gallium nitride offers the advantage that its bandgap can be tuned over a wide range, namely from about 3.4 eV to about 6.2 eV. Due to its mobility, AlGaN can be efficiently used in AlGaN / GaN high electron mobility transistors. AlGaN can be advantageously used with gallium nitride or aluminum nitride to form heterojunctions.

[0026] In one exemplary implementation of the GaN power transistor, the intermediate layer comprises aluminum nitride.

[0027] Aluminum nitride offers the advantage of being stable at high temperatures in inert atmospheres, melting at about 2200° C. Aluminum nitride is stable in hydrogen and carbon dioxide atmospheres up to 980° C. Aluminum nitride can be advantageously used with aluminum gallium nitride to form heterojunctions.

[0028] In one exemplary implementation of the GaN power transistor, the intermediate layer comprises indium aluminum nitride.

[0029] The use of indium aluminum nitride offers the following advantages: Indium gallium aluminum nitride is typically prepared by epitaxial methods, such as pulsed laser deposition and molecular beam epitaxy. Adding indium to gallium nitride to form a light-emitting layer leads to ultraviolet and visible light emission. Indium aluminum nitride can be advantageously used with aluminum gallium nitride to form heterojunctions with high electron mobility.

[0030] In one exemplary implementation of the GaN power transistor, the thickness of the intermediate layer is in the range of approximately 5 nanometers to 40 nanometers.

[0031] This provides the advantage that the reduced electric field strength at the metal-interlayer interface leads to a stable threshold voltage of the transistor.

[0032] Exemplary thicknesses for the intermediate layer are 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, and 40 nm, or any other value between 5 nm and 40 nm. Other values ​​may be used as well.

[0033] In one exemplary implementation of the GaN power transistor, the Group III element content in the III-V compound semiconductor is between about 5 percent and about 50 percent.

[0034] This provides the advantage that the formation of electric field peaks at the metal-interlayer interface can be prevented or at least significantly reduced.

[0035] Exemplary contents of Group III elements in III-V compound semiconductors are 5, 10, 15, 20, 25, 30, 35, 40, 45, 50 percent, or any other percentage between 5 percent and 50 percent.

[0036] In one exemplary implementation of the GaN power transistor, the thickness of the intermediate layer is 5 nanometers, and the content of group III elements in the III-V compound semiconductor is 5 percent.

[0037] These values ​​provide a significant reduction in the electric field strength at the metal-semiconductor interfaces, especially at the metal-interlayer interfaces.

[0038] In one exemplary implementation of the GaN power transistor, the thickness of the intermediate layer is 20 nanometers, and the content of group III elements in the III-V compound semiconductor is 5 percent.

[0039] These values ​​have also been shown to provide significant reductions in electric field strength at the metal-semiconductor interfaces, and in particular at the metal-interlayer interfaces.

[0040] In one exemplary implementation of the GaN power transistor, the thickness of the intermediate layer is 20 nanometers, and the content of group III elements in the III-V compound semiconductor is 50 percent.

[0041] These values ​​have also been shown to provide significant reductions in electric field strength at the metal-semiconductor interfaces, and in particular at the metal-interlayer interfaces.

[0042] In one exemplary implementation of the GaN power transistor, the metal gate layer has a top surface and a bottom surface, the intermediate layer has a top surface and a bottom surface, the p-type doped gallium nitride layer has a top surface and a bottom surface, the bottom surface of the metal gate layer is disposed on the top surface of the intermediate layer, and the bottom surface of the intermediate layer is disposed on the top surface of the p-type doped gallium nitride layer.

[0043] Such sandwich-type structures offer the advantage of efficiently constructing rectifying metal-semiconductor junctions that can be used at low electric field strengths and exhibit stable behavior and reliable gate electrodes.

[0044] In one exemplary implementation of the GaN power transistor, a metal gate layer covers at least a portion of the top surface of the intermediate layer.

[0045] This offers the advantage of flexible design: the metal gate layer can completely cover the top surface of the intermediate layer, or it can cover only the central region of the intermediate layer, for example forming a symmetric structure around the center, or even an asymmetric structure around the center.

[0046] In one exemplary implementation of the GaN power transistor, a metal gate layer is disposed both on top of the intermediate layer and on top of the p-type doped gallium nitride layer.

[0047] This offers the advantage of design flexibility: the metal gate layer can completely cover the top surface and each side surface of the intermediate layer, or the metal gate layer can cover only a portion of the top surface and only a portion of the side surfaces of the intermediate layer.

[0048] In one exemplary implementation of the GaN power transistor, the intermediate layer has one or more sides connecting a top surface of the intermediate layer to a bottom surface of the intermediate layer, and a metal gate layer covers the top surface of the intermediate layer and at least one of the sides of the intermediate layer.

[0049] This offers the advantage of flexible design: the metal gate layer can cover the top surface of the intermediate layer and one (or two, three, or four) side surfaces of the intermediate layer.

[0050] In one exemplary implementation of the GaN power transistor, the p-type doping concentration of the p-type doped gallium nitride layer 112 is 5e19 cm -3 Less than, especially, 1e19cm -3 It may be less than.

[0051] Such GaN power transistors have a high p-type doping concentration (>1e19 cm) in the pGaN layer. -3 This provides a much more robust design over currently available Schottky pGaN gate approaches, which rely on Schottky pGaN gates (SbGaN) and generally have typical thicknesses of the pGaN layer between 60 nm and 250 nm.

[0052] In one exemplary implementation, the GaN power transistor is configured to operate in normally-off operation, thus supporting normal operating methods with higher threshold voltage stability and better gate reliability.

[0053] In one exemplary implementation of the GaN power transistor, the buffer layer comprises a gallium nitride layer or an aluminum gallium nitride layer.

[0054] The buffer layer comprising GaN or AlGaN improves the electron mobility of the transistor, which in turn reduces the reverse leakage current in the transistor and improves the on-off ratio of the transistor.

[0055] In one exemplary implementation of the GaN power transistor, the barrier layer comprises an aluminum gallium nitride layer.

[0056] Transistors having such barrier layers exhibit improved RF and DC performance.

[0057] According to a second aspect, the present disclosure relates to a metal-semiconductor junction in a gallium nitride power transistor, the metal-semiconductor junction having an intermediate layer interposed between a p-type doped gallium nitride layer and a metal gate layer, the intermediate layer being made of a III-V compound semiconductor having a combination of at least one group III element and at least one group V element, the metal gate layer being configured to be electrically connected to the p-type doped gallium nitride layer through the intermediate layer to form a rectifying metal-semiconductor junction with the p-type doped gallium nitride layer.

[0058] Such metal-semiconductor junctions in GaN power transistors offer the following advantages: normally-off operation; stable threshold voltage and suppression of the dynamic instabilities that characterize conventional pGaN Schottky gate approaches; and improved gate reliability due to the significant reduction of the peak electric field at the metal / pGaN interface and in the pGaN bulk by the intermediate layer.

[0059] In one exemplary implementation of the metal-semiconductor junction, the at least one group III element comprises one of the following chemical elements: aluminum, gallium, and indium. In one exemplary implementation of the metal-semiconductor junction, the at least one group V element comprises one of the following chemical elements: nitrogen, phosphorus, arsenic, and antimony.

[0060] This offers the advantage that III-V compound semiconductors, obtained by combining these group III elements (especially Al, Ga, In) with group V elements (especially N, P, As, Sb), result in wider band gap semiconductors. For example, gallium arsenide (GaAs) has six times higher electron mobility than silicon, which allows for faster operation. The wider band gap allows power devices to operate at higher temperatures and gives lower thermal noise for low power devices at room temperature.

[0061] In one exemplary implementation of such a metal-semiconductor junction, the metal gate layer is electrically connected to the p-type doped gallium nitride layer through an intermediate layer and is configured to form a Schottky barrier with the p-type doped gallium nitride layer.

[0062] This provides the advantage that by electrically connecting to the p-type doped gallium nitride layer through the interlayer and forming a Schottky barrier with the p-type doped gallium nitride layer, the overall performance of the metal-semiconductor junction is optimized while exhibiting a stable threshold voltage and reliable gate. With a properly selected thickness and composition of this III-V interlayer, the metal-semiconductor junction can be operated with stable pGaN Schottky action, greatly improving the threshold voltage stability and overall gate reliability.

[0063] In one exemplary implementation of such a metal-semiconductor junction, the rectifying metal-semiconductor junction includes a reverse-biased Schottky diode separating the p-type doped gallium nitride layer from the metal gate layer.

[0064] This provides the following advantages: the pGaN node is isolated from the gate terminal by a reverse-biased Schottky diode; the interlayer design allows TH No instability or at least reduced V TH Low DC gate current with no instability; improved gate reliability and V TH Stability. [Brief description of the drawings]

[0065] Further embodiments of the present disclosure are described with respect to the following figures. [Figure 1] 1 shows a design of a GaN power transistor 100 with a Schottky barrier according to a first example. [Diagram 2] 2 shows a design of a GaN power transistor 200 with a Schottky barrier according to a second example. [Diagram 3]3 illustrates an equivalent circuit design 300 of a gate module of a GaN power transistor with a Schottky barrier according to an example of the present disclosure. [Figure 4] 4 illustrates an example of an electric field distribution 400 along a metal-semiconductor interface of a GaN power transistor according to an example of the present disclosure for different design parameters. [Diagram 5] 5 shows an example performance simulation 500 of threshold voltage stability of a pGaN Schottky gate according to an example of the present disclosure as a function of stress time. [Figure 6] 6 illustrates a design of a metal-semiconductor junction 600 for a GaN power transistor according to an example of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0066] In the following detailed description, references are made to the accompanying drawings, which form a part of the detailed description, and which show, by way of illustration, specific aspects in which the present disclosure may be practiced. It is to be understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0067] It is understood that a comment made in connection with a described method may also apply to a corresponding device or system configured to perform the method, and vice versa. For example, where a particular method step is described, a corresponding device may include units for performing the described method step, even if such units are not explicitly described or shown. It is also understood that features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

[0068] The semiconductor devices and systems described herein may be implemented in wireless communication schemes, particularly in communication schemes according to 5G. The described semiconductor devices may be used to produce integrated circuits and / or power semiconductors and may be manufactured according to various technologies. For example, these semiconductor devices may be used in logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, optical circuits, memory circuits, and / or integrated passive components.

[0069] A Schottky barrier, as described in this disclosure, is a potential energy barrier for electrons that forms at a metal-semiconductor junction. A Schottky barrier has rectifying properties that make it suitable for use as a diode. One of the main properties of a Schottky barrier is its Schottky barrier height. The Schottky barrier height depends on the metal and semiconductor combination. Not all metal-semiconductor junctions form a rectifying Schottky barrier, and metal-semiconductor junctions that conduct current in both directions without rectification, perhaps because their Schottky barrier is too low, are called ohmic contacts.

[0070] FIG. 1 shows the design of a GaN power transistor 100 with a Schottky barrier according to a first example.

[0071] The gallium nitride power transistor 100 comprises a buffer layer 110 and a barrier layer 111 having a top surface 111a and a bottom surface 111b, with the bottom surface 111b facing the buffer layer 110. The bottom surface 111b of the barrier layer 111 is disposed on the buffer layer 110.

[0072] The gallium nitride power transistor 100 has an intermediate layer 113 interposed between a p-type doped gallium nitride layer 112 and a metal gate layer 114. The intermediate layer 113 is made of a III-V compound semiconductor having a combination of at least one group III element and at least one group V element.

[0073] A p-type doped gallium nitride layer 112 is disposed on the top surface 111a of the barrier layer 111. A metal gate layer 114 is electrically connected to the p-type doped gallium nitride layer 112 through the intermediate layer 113 and is configured to form a rectifying metal-semiconductor junction 115 with the p-type doped gallium nitride layer 112.

[0074] In one example, as shown in FIG. 1, the gate region 120 of the gallium nitride power transistor 100 is formed by the contact region of the p-type doped gallium nitride layer 112 with the barrier layer 111 at the top surface 111a of the barrier layer 111.

[0075] The at least one group III element may comprise one of the following chemical elements: aluminum, gallium, and indium. The at least one group V element may comprise one of the following chemical elements: nitrogen, phosphorus, arsenic, and antimony.

[0076] The metal gate layer 114 may be configured to electrically connect to the p-type doped gallium nitride layer 112 through the intermediate layer 113 to form a Schottky barrier 115 with the p-type doped gallium nitride layer 112 .

[0077] Different designs of intermediate layer 113 can be provided. In one example, intermediate layer 113 comprises aluminum gallium nitride. In one example, intermediate layer 113 comprises aluminum nitride. In one example, intermediate layer 113 comprises indium aluminum nitride.

[0078] In one example, the thickness of the intermediate layer 113 may be in the range of about 5 nanometers to 40 nanometers. In one example, the content of the group III element in the III-V compound semiconductor may be between about 5 percent and about 50 percent. In one example, the thickness of the intermediate layer may be 5 nanometers and the content of the group III element in the III-V compound semiconductor may be 5 percent. In one example, the thickness of the intermediate layer may be 20 nanometers and the content of the group III element in the III-V compound semiconductor may be 5 percent. In one example, the thickness of the intermediate layer may be 20 nanometers and the content of the group III element in the III-V compound semiconductor may be 50 percent. However, other values ​​are possible as well.

[0079] 1, the metal gate layer 114 has a top surface 114a and a bottom surface 114b, the intermediate layer 113 has a top surface 113a and a bottom surface 113b, and the p-type doped gallium nitride layer 112 has a top surface 112a and a bottom surface 112b. The bottom surface 114b of the metal gate layer 114 is disposed on the top surface 113a of the intermediate layer 113. The bottom surface 113b of the intermediate layer 113 is disposed on the top surface 112a of the p-type doped gallium nitride layer 112.

[0080] 1, the metal gate layer 114 covers at least a portion of the top surface 113a of the intermediate layer 113. In one example, the metal gate layer 114 may completely cover the top surface 113a of the intermediate layer 113.

[0081] 1, the metal gate layer 114 is disposed only on the top surface 113a of the intermediate layer 113, and is not disposed on the p-type doped gallium nitride layer 112. The metal gate layer 114 does not cover either the top surface 113a or the side surfaces 113c of the intermediate layer 113.

[0082] In one example, the buffer layer 110 may include a gallium nitride layer or an aluminum gallium nitride layer.

[0083] In one example, the barrier layer 111 may comprise an aluminum gallium nitride layer.

[0084] In one example of transistor 100, buffer layer 110 may be formed on at least one transition layer (not shown in FIG. 1), which may be formed on a silicon substrate.

[0085] Transistor 100 further includes source and drain metal layers (not shown in FIG. 1 ). Such source (S) and drain (D) metal layers may be formed laterally relative to barrier layer 111. The source and drain metal layers may be separated from pGaN layer 112, intermediate layer 113, and metal gate layer 114 by barrier layer 111. In one example, the source and drain metal layers may extend to the same height as barrier layer 111.

[0086] A GaN power transistor 100 with a Schottky barrier including the intermediate layer 113 described above offers the following advantages: normally-off operation; stable threshold voltage and suppression of the dynamic instabilities that characterize conventional pGaN Schottky gate approaches; and improved gate reliability due to a significant reduction in the peak electric field at the metal / pGaN interface and within the pGaN bulk.

[0087] The design guidelines for such a GaN power transistor 100 can be summarized as follows: 1) insertion of a III-V interlayer between the metal layer and the pGaN layer; 2) an AlGaN interlayer with a thickness between 5 nm and 40 nm; b) an AlGaN interlayer with an Al content between 5% and 40%; 3) the materials of choice for the interlayer can be AlN, InAlN, AlGaN; different embodiments can be realized.

[0088] FIG. 1 also shows a schematic diagram of a newly proposed gate stack for stable and reliable pGaN Schottky devices. In this newly proposed approach, a III-V layer 113 is interposed between a pGaN layer 112 and a gate metal 114. When the thickness and composition of this interlayer 113 are appropriately selected, it allows to improve the threshold voltage stability of the conventional pGaN Schottky approach. Also, due to the wider depletion region at the metal / semiconductor interface, the presence of this interlayer 113 allows for a significant electric field reduction and thus a dramatic improvement in the overall gate reliability. Exemplary compositions of this III-V interlayer 113 are a) an AlGaN layer with Al content ranging from 5% to 40%, b) an AlN layer, and c) an InAlN layer.

[0089] FIG. 2 shows a design of a GaN power transistor 200 with a Schottky barrier according to a second example.

[0090] GaN power transistor 200 may be designed similarly to transistor 100 described above with respect to FIG.

[0091] That is, the gallium nitride power transistor 200 has a buffer layer 110 and a barrier layer 111 having a top surface 111a and a bottom surface 111b, with the bottom surface 111b facing the buffer layer 110. The bottom surface 111b of the barrier layer 111 is disposed on the buffer layer 110.

[0092] The gallium nitride power transistor 100 has an intermediate layer 113 interposed between a p-type doped gallium nitride layer 112 and a metal gate layer 114. The intermediate layer 113 is made of a III-V compound semiconductor having a combination of at least one group III element and at least one group V element.

[0093] A p-type doped gallium nitride layer 112 is disposed on the top surface 111a of the barrier layer 111. A metal gate layer 114 is electrically connected to the p-type doped gallium nitride layer 112 through the intermediate layer 113 and is configured to form a rectifying metal-semiconductor junction 115 with the p-type doped gallium nitride layer 112.

[0094] In one example, as shown in FIG. 2, the gate region 120 of the gallium nitride power transistor 200 is formed by a contact region of the p-type doped gallium nitride layer 112 with the barrier layer 111 at the top surface 111a of the barrier layer 111.

[0095] As mentioned above, the at least one group III element may comprise one of the following chemical elements: aluminum, gallium, and indium. The at least one group V element may comprise one of the following chemical elements: nitrogen, phosphorus, arsenic, and antimony.

[0096] As described above, the metal gate layer 114 may be configured to electrically connect to the p-type doped gallium nitride layer 112 through the intermediate layer 113 to form a Schottky barrier 115 with the p-type doped gallium nitride layer 112.

[0097] As discussed above, different designs of intermediate layer 113 can be provided. In one example, intermediate layer 113 comprises aluminum gallium nitride. In one example, intermediate layer 113 comprises aluminum nitride. In one example, intermediate layer 113 comprises indium aluminum nitride.

[0098] As discussed above with respect to FIG. 1, the thickness of the intermediate layer 113 may be in the range of about 5 nanometers to 40 nanometers. In one example, the content of the group III element in the III-V compound semiconductor may be between about 5 percent and about 50 percent. In one example, the thickness of the intermediate layer may be 5 nanometers and the content of the group III element in the III-V compound semiconductor may be 5 percent. In one example, the thickness of the intermediate layer may be 20 nanometers and the content of the group III element in the III-V compound semiconductor may be 5 percent. In one example, the thickness of the intermediate layer may be 20 nanometers and the content of the group III element in the III-V compound semiconductor may be 50 percent. However, other values ​​are possible as well.

[0099] 2, the metal gate layer 114 has a top surface 114a and a bottom surface 114b, the intermediate layer 113 has a top surface 113a and a bottom surface 113b, and the p-type doped gallium nitride layer 112 has a top surface 112a and a bottom surface 112b. The bottom surface 114b of the metal gate layer 114 is disposed on the top surface 113a of the intermediate layer 113. The bottom surface 113b of the intermediate layer 113 is disposed on the top surface 112a of the p-type doped gallium nitride layer 112.

[0100] In FIG. 2, the bottom surface 114b of the metal gate layer 114 is disposed on the top surface 113a of the intermediate layer 113, and the bottom surface 113b of the intermediate layer 113 is disposed on the top surface 112a of the p-type doped gallium nitride layer 112. In FIG.

[0101] The metal gate layer 114 may cover at least a portion of the top surface 113a of the intermediate layer 113, or may completely cover the top surface 113a of the intermediate layer 113, as shown in FIG.

[0102] As shown in FIG. 2, a metal gate layer 114 may be disposed on both the top surface 113a of the intermediate layer 113 and the top surface 112a of the p-type doped gallium nitride layer 112.

[0103] 2, the intermediate layer 113 has one or more side surfaces 113c connecting the top surface 113a of the intermediate layer 113 with the bottom surface 113b of the intermediate layer 113. The metal gate layer 114 can cover the top surface 113a of the intermediate layer 113 and at least one of the side surfaces 113c of the intermediate layer 113. In the example of FIG. 2, the metal gate layer 114 covers both the top surface 113a of the intermediate layer 113 and all of the side surfaces 113c of the intermediate layer 113.

[0104] The buffer layer 110 may comprise a gallium nitride layer or an aluminum gallium nitride layer. The barrier layer 111 may comprise an aluminum gallium nitride layer.

[0105] As discussed above with respect to FIG. 1, the buffer layer 110 may be formed on at least one transition layer (not shown in FIG. 2), which may be formed on a silicon substrate.

[0106] Transistor 200 further includes source and drain metal layers (not shown in FIG. 2). Such source (S) and drain (D) metal layers may be formed laterally relative to barrier layer 111, as described above with respect to FIG. 1. The source and drain metal layers may be separated from pGaN layer 112, intermediate layer 113, and metal gate layer 114 by barrier layer 111. In one example, the source and drain metal layers may extend to the same height as barrier layer 111.

[0107] FIG. 3 shows an equivalent circuit design 300 of a gate module of a GaN power transistor with a Schottky barrier according to the present disclosure.

[0108] In the Schottky approach as shown in FIG. 3, a reverse-biased Schottky diode 302 is inserted in series with the pn-p GaN / AlGaN diode 301 as shown in driving scheme 300b. This allows for a significant DC gate current reduction. A capacitance C W A series connection of a pn-p GaN / AlGaN diode 301 with a capacitance Cp 303 connected in parallel with a reverse biased Schottky diode 302 with capacitance 304 is shown in the equivalent circuit 300a.

[0109] Threshold voltage instability (positive and negative) is observed in the Schottky approach, which means that the device TH (in the case of positive V TH For example, dynamic behavior of the threshold voltage can be observed for pGaN Schottky gates when a positive stress voltage is applied to the gate electrode.

[0110] Weak gate robustness is also observed with the Schottky approach. Time-dependent dielectric breakdown (TDDB) behavior is observed, similar to the breakdown of the gate dielectric in conventional Si-based power devices. Several theories have been proposed to explain the gate failure mechanism, and one possible root cause has been identified as an impact ionization effect in the depletion region of the reverse-biased Schottky diode, caused by electrons injected into the pGaN layer from the AlGaN barrier. Tests with the electric field distribution in the pGaN layer under a positive voltage applied to the gate electrode show that the maximum electric field is located at the metal / pGaN interface.

[0111] Most Schottky-gate pGaN approaches today use very high p-type doping concentrations (>5e19 cm) in the pGaN layer. -3 ) The typical thickness of the pGaN layer is generally between 60 and 250 nm. The p-type doping concentration can be extracted via conventional SIMS profile measurements.

[0112] It has been demonstrated that hole depletion and accumulation (time- and geometry-dependent) causes threshold voltage instability. Also, the very high doping concentration used in the pGaN layer induces a very narrow depletion region at the metal / pGaN interface. The main drawback of this approach is that the electric field in the narrow depletion region reaches very high values ​​(about 5-10 MV / cm), strongly compromising the overall gate reliability. It is believed that the high electric field in the depletion region causes a strong acceleration of electrons injected from the 2DEG into the pGaN layer. These accelerated electrons can promote carrier multiplication through impact ionization effects and the presence of a large number of high-energy carriers, causing damage (percolation pathways) at the metal / pGaN interface, ultimately compromising the overall gate reliability.

[0113] Several attempts have been investigated in the past few years to improve the gate reliability of pGaN gate modules and to mitigate the threshold voltage instability of pGaN Schottky gates. For example, a direct correlation between the static DC gate current and the overall gate reliability has been observed. A reduction in the static gate current unfortunately leads to a higher threshold voltage instability due to the presence of a large amount of floating holes in the pGaN layer that can be injected into the AlGaN barrier and / or recombine with electrons injected into the pGaN layer from the 2DEG without being replenished by the metal gate electrode.

[0114] For the reasons mentioned above, the present disclosure presents a solution of how to overcome the above-mentioned shortcomings of pGaN Schottky gate modules, which are large positive and negative threshold voltage instability and poor gate reliability.

[0115] The solution according to the present disclosure provides a new structure for the gate module of normally-off pGaN transistors, which allows optimizing the overall performance and solving the main problems of state-of-the-art pGaN Schottky gates, namely threshold voltage instability and gate reliability. In this disclosure, a stable pGaN Schottky gate solution with an interlayer is presented, in which a dedicated III-V interlayer is interposed between the pGaN layer and the metal gate. When the thickness and composition of this III-V interlayer are appropriately selected in relation to the detailed composition of the gate stack, it allows to have a stable pGaN Schottky operation and significantly improves the threshold voltage stability and overall gate reliability.

[0116] 4 shows an example of an electric field distribution 400 along the metal-semiconductor interface of a GaN power transistor according to the present disclosure for different design parameters. In particular, the 1D electric field distribution is shown along the A-A' cut line shown in FIG. 1 for a pGaN Schottky gate stack under positive gate stress. Four different gate stack configurations are considered: (i) Conventional pGaN Schottky interface, graph 401; (ii) a hidden layer according to a first design parameter setting, graph 402; (iii) the intermediate layer according to the second design parameter setting, graph 403; (iv) The hidden layer, graph 404 according to the third design parameter setting.

[0117] The metal-semiconductor interface along cut line A-A' is divided into three sections. The first section 114 shows the extension of the metal gate layer 114 as shown in Figure 1. The second section 113 shows the extension of the intermediate layer 113 as shown in Figure 1. The third section 112 shows the extension of the metal gate layer 114 as shown in Figure 1.

[0118] The electric field distribution 400 in Figure 4 shows that a significant reduction in the electric field can be achieved by inserting a III-V interlayer (graphs 402, 403, 404) compared to a conventional pGaN Schottky gate stack 401. It can be observed that by inserting the III-V interlayer 113 according to different design parameter settings, the reduction in the electric field peak at the metal / semiconductor interface becomes more significant.

[0119] It can also be observed that when applying certain design parameter settings (see graph 404), due to the presence of polarization charges at the intermediate layer / pGaN interface, an electronic inversion layer forms and another electric field peak suddenly appears, this time located at the intermediate layer / pGaN interface 113 / 112. Based on these considerations, the thickness and composition of the intermediate layer 113 can be selected to avoid the latter considered case.

[0120] 5 shows an example performance simulation 500 of threshold voltage stability of a pGaN Schottky gate according to the present disclosure as a function of stress time. In particular, FIG. 5 shows the dynamic threshold voltage of a simulated pGaN Schottky gate for different interlayer configurations as a function of stress time applied to the gate electrode. For comparison, a conventional pGaN Schottky gate without an interlayer is also shown.

[0121] That is, Fig. 5 shows the simulated dynamic variation of threshold voltage under application of positive gate stress to the gate stack for different stress times considered. Again, four different gate stack configurations are considered as shown in Fig. 4: (i) Conventional pGaN Schottky interface, graph 501; (ii) the hidden layer according to the first design parameter setting, graph 502; (iii) the intermediate layer according to the second design parameter setting, graph 503; (iv) Hidden layer according to the third design parameter setting, graph 504.

[0122] For the conventional pGaN Schottky gate (graph 501), it can be observed that the device threshold voltage experiences both positive and negative variations. TH The instability has been largely confirmed by experiments and simulations already widely published in the literature. Figure 5 also shows that when the intermediate layer 113 is present, for example according to Figures 1 and 2, the impact and improvement on dynamic threshold voltage instability is small when certain design parameter settings are used, for example case (ii), as can be seen by graph 502. On the other hand, when other design parameter settings are used, for example in cases (iii) and (iv), as can be seen by graphs 503 and 504, the V TH A dramatic improvement in instability can be achieved. It can be observed that the III-V interlayer 113 described in this disclosure allows achieving a stable threshold voltage VTH even in the case of a long stress time.

[0123] In summary, the pGaN Schottky gate threshold voltage stability performance simulation 500 of FIG. 5 results show that the detailed composition of the III-V intermediate layer 113 can be chosen in such a way that it is possible to simultaneously obtain a dramatic reduction in the electric field peak at the metal / semiconductor interface and suppress the dynamic threshold voltage instability that affects conventional pGaN Schottky gate approaches.

[0124] FIG. 6 shows one design of a metal-semiconductor junction 600 for a GaN power transistor in accordance with this disclosure.

[0125] The metal-semiconductor junction 600 includes an intermediate layer 113 interposed between a p-type doped gallium nitride layer 112 and a metal gate layer 114, for example according to the structure 115 shown in Figures 1 and 2. The intermediate layer 113 is made of a III-V compound semiconductor having a combination of at least one group III element and at least one group V element. The metal gate layer 114 is electrically connected to the p-type doped gallium nitride layer 112 through the intermediate layer 113 and is configured to form a rectifying metal-semiconductor junction 115 with the p-type doped gallium nitride layer 112.

[0126] In one example, the at least one group III element can include one of the following chemical elements: aluminum, gallium, and indium. In one example, the at least one group V element can include one of the following chemical elements: nitrogen, phosphorus, arsenic, and antimony.

[0127] The metal gate layer 114 may be configured to electrically connect to the p-type doped gallium nitride layer 112 through the intermediate layer 113 to form a Schottky barrier 115 with the p-type doped gallium nitride layer 112 .

[0128] The rectifying metal-semiconductor junction 115 may include a reverse-biased Schottky diode 302 separating the p-type doped gallium nitride layer 112 from the metal gate layer 114, for example according to the design 300 shown in Figures 3a and 3b.

[0129] Although a particular feature or aspect of the present disclosure may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of other implementations as may be desirable and advantageous for any given or particular application. Also, to the extent that the terms "including," "having," "comprising," or other variations thereof are used in either the detailed description or the claims, such terms are intended to be as inclusive as the term "having." Also, the terms "exemplary," "for example," and "example" are not meant to be best or optimal, but merely as an example. Along with derivatives, the terms "coupled" and "connected" may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical or electrical contact with each other or are not in direct contact with each other.

[0130] While specific aspects have been illustrated and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent implementations may be substituted for the specific aspects illustrated and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects described herein.

[0131] Although elements in the following claims are described in a particular order with corresponding labeling, the elements are not necessarily intended to be limited to being implemented in that particular order, unless the claim recitation otherwise indicates a particular order for implementing some or all of those elements.

[0132] In light of the above teachings, numerous alternatives, modifications, and variations will be apparent to those skilled in the art. Of course, those skilled in the art will readily recognize that there are many applications of the present disclosure other than those described herein. Although the present disclosure has been described with reference to one or more specific embodiments, those skilled in the art will recognize that numerous modifications can be made thereto without departing from the scope of the present disclosure. Thus, it is to be understood that, within the scope of the appended claims and their equivalents, the present disclosure may be practiced other than as specifically described herein.

Claims

1. 1. A gallium nitride power transistor, comprising: A buffer layer; a barrier layer having a top surface and a bottom surface, the bottom surface facing the buffer layer, the bottom surface of the barrier layer being disposed on the buffer layer; an intermediate layer interposed between the p-type doped gallium nitride layer and the metal gate layer, the intermediate layer being made of a III-V compound semiconductor having a combination of at least one group III element and at least one group V element; having the p-type doped gallium nitride layer is disposed on the top surface of the barrier layer; the metal gate layer is configured to be electrically connected to the p-type doped gallium nitride layer through the intermediate layer to form a rectifying metal-semiconductor junction with the p-type doped gallium nitride layer; The intermediate layer comprises aluminum nitride. Gallium nitride power transistor.

2. A gallium nitride power transistor, A buffer layer; a barrier layer having a top surface and a bottom surface, the bottom surface facing the buffer layer, the bottom surface of the barrier layer being disposed on the buffer layer; an intermediate layer interposed between the p-type doped gallium nitride layer and the metal gate layer, the intermediate layer being made of a III-V compound semiconductor having a combination of at least one group III element and at least one group V element; having the p-type doped gallium nitride layer is disposed on the top surface of the barrier layer; the metal gate layer is configured to be electrically connected to the p-type doped gallium nitride layer through the intermediate layer to form a rectifying metal-semiconductor junction with the p-type doped gallium nitride layer; The intermediate layer comprises indium aluminum nitride. Gallium nitride power transistor.

3. a gate region of the gallium nitride power transistor is formed by a contact region of the p-type doped gallium nitride layer with the barrier layer at the top surface of the barrier layer.

3. A gallium nitride power transistor according to claim 1 or 2.

4. the metal gate layer is electrically connected to the p-type doped gallium nitride layer through the intermediate layer to form a Schottky barrier with the p-type doped gallium nitride layer.

4. A gallium nitride power transistor according to claim 1.

5. The thickness of the intermediate layer is in the range of about 5 nanometers to 40 nanometers.

5. A gallium nitride power transistor according to claim 1.

6. the content of the Group III element in the Group III-V compound semiconductor is between about 5 percent and about 50 percent; 6. A gallium nitride power transistor according to claim 1.

7. the thickness of the intermediate layer is 5 nanometers, and the content of the group III element in the group III-V compound semiconductor is 5 percent; 7. A gallium nitride power transistor according to claim 1.

8. The thickness of the intermediate layer is 20 nanometers, and the content of the group III element in the group III-V compound semiconductor is 5 percent.

7. A gallium nitride power transistor according to claim 1.

9. The thickness of the intermediate layer is 20 nanometers, and the content of the group III element in the group III-V compound semiconductor is 50 percent.

7. A gallium nitride power transistor according to claim 1.

10. the metal gate layer having a top surface and a bottom surface; the intermediate layer having a top surface and a bottom surface; the p-type doped gallium nitride layer has a top surface and a bottom surface; the bottom surface of the metal gate layer is disposed on the top surface of the intermediate layer; the bottom surface of the intermediate layer being disposed on the top surface of the p-type doped gallium nitride layer.

10. A gallium nitride power transistor according to claim 1.

11. the metal gate layer covers at least a portion of the top surface of the intermediate layer; 11. The gallium nitride power transistor of claim 10.

12. the metal gate layer is disposed on both the top surface of the intermediate layer and on the top surface of the p-type doped gallium nitride layer.

12. A gallium nitride power transistor according to claim 10 or 11.

13. A gallium nitride power transistor, comprising: A buffer layer; a barrier layer having a top surface and a bottom surface, the bottom surface facing the buffer layer, the bottom surface of the barrier layer being disposed on the buffer layer; an intermediate layer interposed between the p-type doped gallium nitride layer and the metal gate layer, the intermediate layer being made of a III-V compound semiconductor having a combination of at least one group III element and at least one group V element; having the p-type doped gallium nitride layer is disposed on the top surface of the barrier layer; the metal gate layer is configured to be electrically connected to the p-type doped gallium nitride layer through the intermediate layer to form a rectifying metal-semiconductor junction with the p-type doped gallium nitride layer; the metal gate layer having a top surface and a bottom surface; the intermediate layer having a top surface and a bottom surface; the p-type doped gallium nitride layer has a top surface and a bottom surface; the bottom surface of the metal gate layer is disposed on the top surface of the intermediate layer; the bottom surface of the intermediate layer is disposed on the top surface of the p-type doped gallium nitride layer; the intermediate layer having one or more sides connecting the top surface of the intermediate layer to the bottom surface of the intermediate layer; the metal gate layer covers the top surface of the intermediate layer and at least one of the side surfaces of the intermediate layer. Gallium nitride power transistor.

14. The at least one Group III element comprises one of the following chemical elements: aluminum, gallium, and indium.

14. The gallium nitride power transistor of claim 13.

15. The method of claim 1, wherein the at least one Group V element comprises one of the following chemical elements: nitrogen, phosphorus, arsenic, and antimony.

15. A gallium nitride power transistor according to claim 13 or 14.

16. The intermediate layer comprises aluminum gallium nitride.

16. A gallium nitride power transistor according to any one of claims 13 to 15.

17. The intermediate layer comprises aluminum nitride.

16. A gallium nitride power transistor according to any one of claims 13 to 15.

18. The intermediate layer comprises indium aluminum nitride.

16. A gallium nitride power transistor according to any one of claims 13 to 15.

19. The buffer layer comprises a gallium nitride layer or an aluminum gallium nitride layer.

19. A gallium nitride power transistor according to any preceding claim.

20. The barrier layer comprises an aluminum gallium nitride layer.

20. A gallium nitride power transistor according to any preceding claim.

21. A metal-semiconductor junction in a gallium nitride power transistor, the metal-semiconductor junction comprising: an intermediate layer interposed between the p-type doped gallium nitride layer and the metal gate layer, the intermediate layer being made of a III-V compound semiconductor having a combination of at least one Group III element and at least one Group V element; having the metal gate layer is configured to be electrically connected to the p-type doped gallium nitride layer through the intermediate layer to form a rectifying metal-semiconductor junction with the p-type doped gallium nitride layer; The intermediate layer comprises aluminum nitride. Metal-semiconductor junction.

22. A metal-semiconductor junction for a gallium nitride power transistor, the metal-semiconductor junction comprising: an intermediate layer interposed between the p-type doped gallium nitride layer and the metal gate layer, the intermediate layer being made of a III-V compound semiconductor having a combination of at least one Group III element and at least one Group V element; having the metal gate layer is configured to be electrically connected to the p-type doped gallium nitride layer through the intermediate layer to form a rectifying metal-semiconductor junction with the p-type doped gallium nitride layer; The intermediate layer comprises indium aluminum nitride. Metal-semiconductor junction.

23. the metal gate layer is electrically connected to the p-type doped gallium nitride layer through the intermediate layer to form a Schottky barrier with the p-type doped gallium nitride layer.

23. The metal-semiconductor junction according to claim 21 or 22.

24. the rectifying metal-semiconductor junction comprises a reverse-biased Schottky diode separating the p-type doped gallium nitride layer from the metal gate layer. The metal-semiconductor junction according to any one of claims 21 to 23.

Images