Variable Resistance Memory Element

Abstract

To provide a variable resistance memory device.SOLUTION: A variable resistance memory device includes: a variable resistance layer which includes a first layer formed of a first material and a second layer located on the first layer, the second layer being formed of a second material having a density different from a density of the first material; and a first conductive element and a second conductive element which are located on the variable resistance layer to be spaced apart from each other, so as to form a current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a non-volatile memory device utilizing a variable resistance material. [Background technology]

[0002] As a semiconductor memory device, a non-volatile memory device is a memory device in which stored data is not lost even if the power supply is interrupted. Examples of such non-volatile memory devices include programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash memory devices.

[0003] Recently, in response to the trend toward a demand for technology that has high integration, low power consumption, and allows random access to memory cells, next-generation semiconductor memory devices such as MRAM (magnetic random access memory) and PRAM (phase-change random access memory) are being developed.

[0004] Such next-generation semiconductor memory devices employ variable resistance elements whose resistance changes depending on an applied current or voltage and whose resistance value remains the same even if the supply of the current or voltage is interrupted. In order to realize high integration and low power consumption, it is desirable for the variable resistance element to have a wide resistance change range and a low applied voltage. Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a variable resistance memory element having improved variable resistance performance. [Means for solving the problem]

[0006] According to one type, a variable resistance memory element is provided, comprising: a variable resistance layer including a first layer made of a first material and a second layer disposed on the first layer and made of a second material having a density different from that of the first material; and a first conductive element and a second conductive element disposed spaced apart from each other on the variable resistance layer so as to form a current path in the variable resistance layer in a direction perpendicular to a stacking direction of the first layer and the second layer.

[0007] The density of the second material is greater than the density of the first material. The density difference between the first material and the second material is 1 g / cm 3 will be greater than. The resistance variable layer may further include a third layer disposed on the second layer and made of a third material having a lower density than the second material.

[0008] The density difference between the second material and the third material is 1 g / cm 3 will be greater than. The first material and the third material may be the same material. Among the first layer, the second layer, and the third layer, the second layer has the smallest thickness.

[0009] The first material and the second material are also oxides having a band gap energy of 2 eV or more.

[0010] The first substance and the second substance are each Rb 2 O, TiO 2 , BaO, ZrO 2 , CaO, HfO 2 , SrO, Sc 2 O 3 , MgO, Li 2 O, Al 2 O 3 , SiO 2 , BeO.

[0011] The first and second substances have the same atomic valence and a density difference of 1.5 g / cm3 will be greater than.

[0012] The first substance is HfO 2 and the second material is TiO 2 , MnO 2 , ZrO 2 , SiO 2 or Cr 2 O 3 It is also.

[0013] The first substance is Gd 2 O 3 and the second material is Cr 2 O 3 Or La 2 O 3 It is also.

[0014] The first material is NiO and the second material is also SrO, CaO or BeO. The first substance is WO 3 and the second material is MoO 3 It is also.

[0015] According to one type, a variable resistance memory element is provided, comprising: an insulating layer; a variable resistance layer disposed on the insulating layer, the variable resistance layer including a first layer made of a first material and a second layer disposed on the first layer and made of a second material having a density different from that of the first material; a channel layer disposed on the variable resistance layer; a gate insulating layer formed on the channel layer; and a plurality of gate electrodes disposed spaced apart from each other on the gate insulating layer.

[0016] The density of the second material is greater than the density of the first material. The density difference between the first material and the second material is 1 g / cm 3 will be greater than.

[0017] The resistance variable layer may further include a third layer disposed on the second layer and made of a third material having a lower density than the second material.

[0018] The first layer, the second layer, and the third layer each have a thickness of 10 nm or less. The second layer also has a thickness of 2 nm or less. The third layer is in contact with the channel layer and has a thickness of 5 nm or more.

[0019] The density difference between the second material and the third material is 1 g / cm 3 will be greater than. The first material and the third material may be the same material.

[0020] The first material and the second material are also oxides having a band gap energy of 2 eV or more.

[0021] The first substance and the second substance are each Rb 2 O, TiO 2 , BaO, ZrO 2 , CaO, HfO 2 , SrO, Sc 2 O 3 , MgO, Li 2 O, Al 2 O 3 , SiO 2 , BeO. Effect of the Invention

[0022] In the variable resistance memory element of the present invention, resistance changes can occur under a low applied voltage. The variable resistance memory element of the present invention can exhibit a wide variable resistance range. The variable resistance memory device of the present invention can easily realize low power consumption and high integration. [Brief description of the drawings]

[0023] [Figure 1] 1 is a cross-sectional view illustrating a schematic structure of a variable resistance memory element according to an embodiment; [Diagram 2] 2 is a conceptual diagram for explaining the principle of resistance variation occurring in a variable resistance layer provided in the variable resistance memory element of FIG. 1. FIG. [Diagram 3]11 is a cross-sectional view showing a schematic configuration of a variable resistance memory element according to another embodiment. [Figure 4] 11 is a cross-sectional view showing a schematic configuration of a variable resistance memory element according to another embodiment. [Diagram 5] 5 is a conceptual diagram for explaining the principle of resistance variation occurring in a variable resistance layer provided in the variable resistance memory element of FIG. 4. FIG. [Figure 6] 1 is a cross-sectional view showing a schematic configuration of a sample produced for experimenting variable resistance performance relating to a configuration in which variable resistance materials having different densities are adjacently laminated. FIG. [Figure 7] 1 is a cross-sectional view showing a schematic configuration of a sample produced for experimenting variable resistance performance relating to a configuration in which variable resistance materials having different densities are adjacently laminated. FIG. [Figure 8] 11 is a cross-sectional view showing a schematic configuration of a variable resistance memory element according to another embodiment. [Figure 9] 9 is a diagram showing an equivalent circuit of the variable resistance memory element of FIG. 8; [Figure 10] 9 is a conceptual diagram for illustratively explaining the operation of the variable resistance memory element of FIG. 8. FIG. [Figure 11] 11 is a cross-sectional view illustrating a schematic structure of a variable resistance memory element according to another embodiment; [Figure 12] 11 is a cross-sectional view illustrating a schematic structure of a variable resistance memory element according to another embodiment; [Figure 13] 13 is a perspective view showing a schematic structure of a memory string included in the variable resistance memory device of FIG. 12. [Figure 14] 13 is an equivalent circuit diagram of the variable resistance memory element of FIG. 12. [Figure 15] 11 is a cross-sectional view illustrating a schematic structure of a variable resistance memory element according to another embodiment; [Figure 16] 16 is a perspective view showing a schematic structure of a memory string included in the variable resistance memory element of FIG. 15. [Figure 17] FIG. 1 is a block diagram of a memory system according to an embodiment. [Figure 18]FIG. 1 is a block diagram illustrating a neuromorphic device and an external device coupled thereto, according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] Hereinafter, the present embodiment will be described in detail with reference to the attached drawings. The described embodiment is merely exemplary, and various modifications are possible from such an embodiment. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation.

[0025] In the following description, the terms "upper" and "above" may include not only something that is directly above in contact with something, but also something that is above without contacting something.

[0026] Terms such as first and second may be used to describe various components, but are used only to distinguish one component from another, and are not intended to limit the components to being different in material or structure.

[0027] The singular expression includes the plural expression unless otherwise clearly indicated in the context. Furthermore, when a part "includes" a certain element, it does not mean excluding other elements, but means that other elements may be further included, unless otherwise specified to the contrary.

[0028] In addition, terms such as "unit" and "module" used in the specification refer to a unit that processes at least one function or operation, and may be embodied in hardware or software, or a combination of hardware and software.

[0029] Use of the terms "said" and similar referents refers to both the singular and the plural.

[0030] The steps constituting the method may be performed in any suitable order unless expressly stated to be performed in the order described. In addition, the use of all exemplary terms (e.g., "for example") is merely intended to describe the technical idea in detail, and the scope of the rights is not limited by such terms, except as otherwise provided by the claims.

[0031] FIG. 1 is a cross-sectional view showing a schematic structure of a variable resistance memory element according to one embodiment, and FIG. 2 is a conceptual diagram explaining the principle of resistance variation occurring in a variable resistance layer provided in the variable resistance element of FIG.

[0032] Referring to FIG. 1, a variable resistance memory element 100 includes a variable resistance layer 120 having a first layer 11 and a second layer 12, and a first conductive element E1 and a second conductive element E2 for applying a voltage to the variable resistance layer 120.

[0033] The resistance variable layer 120 includes a first layer 11 made of a first material and a second layer 12 made of a second material having a different density than the first material and disposed on the first layer 11. The first layer 11 is also a layer having a higher density than the second layer 12.

[0034] The first conductive element E1 and the second conductive element E2 are disposed on both ends of the variable resistance layer 120, and are also disposed so as to form a current path in the horizontal direction, i.e., in a direction perpendicular to the direction in which the first layer 11 and the second layer 12 are stacked, in the variable resistance layer 120 when a voltage is applied. The first conductive element E1 and the second conductive element E2 are also formed so as to contact both ends of the second layer 12. However, this is merely an example, and the first conductive element E1 and the second conductive element E2 are also formed so as to contact both ends of the first layer 11.

[0035] The resistance variable layer 120 is a layer that exhibits different resistance characteristics depending on the applied voltage. The resistance characteristics of the resistance variable layer 120 depend on whether conductive filaments are formed due to the behavior of oxygen in the resistance variable layer 120 by the voltage applied to the first conductive element E1 and the second conductive element E2 formed on the resistance variable layer 120. Depending on whether the conductive filaments are formed, the resistance variable layer 120 can exhibit a low resistance state or a high resistance state, thereby recording information "1" or "0". The applied voltage that causes the resistance variable layer 120 to change from a high resistance state to a low resistance state is called a set voltage V set The applied voltage that changes the resistance state from the low resistance state to the high resistance state is called the reset voltage V reset That is, the resistance variable memory element 100 according to an embodiment provides a variable resistance layer 120 that can implement a low set voltage.

[0036] Referring to FIG. 2, if an applied voltage causes a current to flow across the variable resistance layer 120, it will cause oxygen vacancies (V o ) and interstitial oxygen ions (O 2- ) is formed. Oxygen vacancies (V o ) come together to form a conductive filament, which causes the resistance of the variable resistance layer 120 to become low.

[0037] Even at a low applied voltage, the conductive filament is well formed, and the larger the difference in resistance between the low resistance state and the high resistance state caused by the applied voltage, the better the variable resistance performance. o ) must be well formed. When the variable resistance layer 120 is formed of multiple layers in which the low-density first layer 11 and the high-density second layer 12 are adjacent to each other as in one embodiment, the low-density oxide has a larger interatomic space than the high-density oxide, so that oxygen ions (O 2- ) can be diffused more smoothly from the first layer 11 to the second layer 12.2- ) is diffused, oxygen vacancies (V o ) can be gathered together to successfully form a conductive filament.

[0038] When the variable resistance layer 120 is configured in this manner, a desired resistance change range can be realized with a smaller thickness than an existing charge trap based variable resistance element or a variable resistance element using a phase change material. The first layer 11 and the second layer 12 constituting the variable resistance layer 120 may each have a thickness of, for example, 10 nm or less.

[0039] The first and second materials included in the resistance variable layer 120 may be various oxides. For example, the first and second materials may include an oxide of at least one element selected from the group including zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), praseodymium (Pr) and silicon (Si). As the first and second materials, oxides having a band gap energy of 2 eV or more are used, for example, Rb 2 O, TiO 2 , BaO, ZrO 2 , CaO, HfO 2 , SrO, Sc 2 O 3 , MgO, Li 2 O, Al 2 O 3 , SiO 2 , BeO, Sc 2 O 3 , Nb 2 O 5 , NiO, Ta 2 O 5 , WO 3 , V 2 O 5 , La 2 O 3 , Gd 2 O 3 , CuO, MoO 3 , Cr 2 O3 , MnO 2 The first substance and the second substance can be selected from among the above. The density of the above material is as shown in Table 1 below.

[0040] [Table 1]

[0041] Referring to Table 1, it can be seen that the first layer 11 can be made of a low density material, and a material having a relatively higher density can be selected to make the second layer 12. The density difference between the first layer 11 and the second layer 12 can be set so that oxygen ions can be smoothly diffused and conductive filaments can be well formed by oxygen vacancies. For example, the density difference between the first layer 11 and the second layer 12 can be set to 1 g / cm. 3 The materials of the first layer 11 and the second layer 12 can be set so that the density difference is larger than 1.5 g / cm. The larger the density difference is, the smoother the diffusion of oxygen ions becomes. Therefore, the density difference is set to 1.5 g / cm. 3 Greater than or equal to 2g / cm 3 The materials of the first layer 11 and the second layer 12 can be set to be larger. For example, the first layer 11 can be made of SiO 2 and the second layer 12 may include HfO 2 In addition, the following combinations may be adopted:

[0042] [Table 2]

[0043] In each of the illustrated combinations, the first and second substances are of the same valence and have a density difference of 1 g / cm 3 For example, HfO is a combination of substances with a valence of 4. 2 / TiO 2 , HfO 2 / MnO 2 , HfO 2 / ZrO 2or HfO 2 / SiO 2 The density difference between these combinations is 4g / cm 3 The combination of substances with a valence of 3 is Gd 2 O 3 / Cr 2 O 3 or Gd 2 O 3 / La 2 O 3 The density difference between these combinations is 2g / cm 3 As combinations of materials with a valence of 2, NiO / SrO, NiO / CaO, or NiO / BeO are selected, and the density difference between these combinations is 1.5 g / cm 3 The combination of substances with a valence of 6 is WO 3 / MoO 3 However, the combination of materials is not limited to the above examples, and materials having different valences and a density difference of 1 g / cm 3 A material that is equal to or greater than this can be selected.

[0044] FIG. 3 is a cross-sectional view showing a schematic configuration of a variable resistance memory element 101 according to another embodiment.

[0045] 1 in the arrangement order of the first layer 11 and the second layer 12 that form the variable resistance layer 120. The first layer 11 made of a low-density material may be arranged on the second layer 12 made of a high-density material, and the first conductive element E1 and the second conductive element E2 may be arranged on both ends of the first layer 11.

[0046] FIG. 4 is a cross-sectional view showing a schematic configuration of a variable resistance memory element according to another embodiment, and FIG. 5 is a conceptual diagram explaining the principle of resistance variation occurring in a variable resistance layer provided in the variable resistance element of FIG.

[0047] 4, the variable resistance memory element 102 includes a variable resistance layer 122 including a first layer 11, a second layer 12, and a third layer 13. The second layer 12 located in the middle of the variable resistance layer 122 is also a layer having a higher density than the first layer 11 and the third layer 13. The first layer 11 and the third layer 13 are layers having a lower density than the second layer 12 and are made of the same material. However, the first layer 11 and the third layer 13 are not limited thereto, and may be made of different materials having a lower density than the second layer 12. The first layer 11 and the third layer 13 are made of SiO 2 and the second layer 12 may include HfO 2 Alternatively, the first layer 11 and the third layer 13 may contain a first substance, and the second layer 12 may contain a second substance, and the combination of the first substance and the second substance may be selected as shown in Table 2.

[0048] The first layer 11, the second layer 12, and the third layer 13 may each have a thickness of 10 nm or less. The second layer 12 is the thinnest and may have a thickness of, for example, 2 nm or less.

[0049] In this embodiment, the second layer 12 made of a substance with a high density is disposed in the middle, and the first layer 11 and the third layer 13 made of a substance with a low density are disposed adjacent to both sides of the second layer 12. 2- ) will be spread into a much larger space.

[0050] As shown in FIG. 5, the application of a voltage causes oxygen vacancies (V o ) and interstitial oxygen ions (O 2- ) is formed, oxygen ions (O 2- ) can be diffused quickly into the first layer 11 or the third layer 13, which have a low density and a large interatomic space in the second layer 12. As a result, oxygen vacancies (V o ) can be more easily formed. Such diffusion occurs more smoothly in the structure of FIG. 1 or FIG. 3, for example, and the formation of the conductive filaments can be more favorably achieved.

[0051] 6 and 7 are cross-sectional views showing a schematic configuration of a sample fabricated for testing variable resistance performance relating to a structure in which variable resistance materials having different densities are adjacently laminated.

[0052] As shown in Figure 6, a 100 nm SiO 2 layer, 400nm N-type Si layer, 10nm SiO 2 A 50 nm N-type Si layer was deposited in this order, and a patterning and etching process was used to form an N-type Si (50 nm) / SiO 2 A cylindrical element of N-type Si (10 nm) / N-type Si (50 nm) was created. The side of the cylindrical element was coated with HfO 2 When a voltage is applied between the upper N-type Si and the lower N-type Si, HfO 2 / SiO 2 The current flows along the layer. In order to improve the contact resistance between the N-type Si upper electrode and the probe station terminal, Ti (10 nm) / Pt (40 nm) were evaporated on the N-type Si upper electrode.

[0053] FIG. 7 shows the structure of FIG. 6 with HfO 2 The layer is 2 nm thick, and then SiO 2 When a voltage is applied between the upper electrode (N-type Si) and the lower electrode (N-type Si), the SiO 2 / HfO 2 / SiO 2 A current will flow along the layer.

[0054] The structures of FIGS. 6 and 7 are intended to replicate the performance of the two-layer variable resistance layer 120 and the three-layer variable resistance layer 122 illustrated in FIGS. 1 and 4, respectively.

[0055] In the two structures, the set voltage V set The average V for 35 samples was measured as shown in Figure 6. setis 12.36V, the average V for 58 samples as in Figure 7. set was measured at 11.17V.

[0056] Such a V set is a V that is usually indicated at 15V or more in variable resistance elements that use existing charge trap layers. set When comparing the two layers with different densities, it can be seen that there is a set voltage reduction effect in the structure with two adjacent layers with different densities. Also, when the variable resistance layer is formed in a three-layer structure with the layer with the lowest density placed in the middle, the set voltage reduction effect is even greater.

[0057] FIG. 8 is a cross-sectional view showing a schematic configuration of a variable resistance memory element according to another embodiment, and FIG. 9 shows an equivalent circuit related to the variable resistance memory element of FIG.

[0058] 8, the variable resistance memory element 200 includes an insulating layer 210, a variable resistance layer 220 disposed on the insulating layer 210, a channel layer 240 disposed on the variable resistance layer 220, a gate insulating layer 250 disposed on the channel layer 240, and a plurality of gate electrodes 260 formed on the gate insulating layer 250. Spaces between the plurality of gate electrodes 260 are also filled with an insulating layer 270. However, this is merely an example, and the insulating layer 270 may be omitted.

[0059] The variable resistance layer 220 includes a first layer 11 made of a first material and a second layer 12 made of a second material having a density different from that of the first material. The second layer 12 may have a higher density than the first layer 11. The material and characteristics of the variable resistance layer 220 are substantially the same as those described for the variable resistance layer 120 of FIG. 1. That is, the variable resistance layer 220 is composed of multiple layers in which the low-density first layer 11 and the high-density second layer 12 are adjacent to each other, and oxygen ions diffuse smoothly to the low-density oxide side having a wider interatomic space, forming oxygen vacancies (V o ) can be successfully formed into a conductive filament.

[0060] Although the high-density second layer 12, which is the variable resistance layer 220, is illustrated as being disposed on the low-density first layer 11, this is not limiting, and the stacking order of the first layer 11 and the second layer 12 may be changed. That is, the low-density first layer 11 may be formed on the high-density second layer 12, and the first layer 11 may be in contact with the channel layer 240.

[0061] The channel layer 240 may be made of a semiconductor material, for example, poly-Si. A source electrode S and a drain electrode D may be connected to both ends of the channel layer 240.

[0062] The gate insulating layer 250 can be made of various insulating materials, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0063] A voltage for turning on / off the channel layer 240 can be selectively applied to each of the plurality of gate electrodes 260 .

[0064] The illustrated variable resistance memory device 200 has a structure in which a plurality of memory cells MC are arrayed, and each memory cell MC has a transistor and a variable resistor connected in parallel, as shown in the equivalent circuit of Fig. 9. Each variable resistor is set by a voltage applied to a gate electrode and a voltage between a source electrode S and a drain electrode D, and has a value corresponding to information 1 or 0.

[0065] The operation of the variable resistance memory device 200 will be described with reference to FIG.

[0066] When a memory cell to be recorded is selected, the gate voltage value of the selected cell is adjusted so that a channel is not formed in the selected cell, i.e., the channel is turned off, and the gate voltage values ​​of the unselected cells are adjusted so that the channels are turned on.

[0067] 10 shows a case where a gate voltage is applied to the gate electrode 260 of each cell so that the center memory cell MC2 is turned off (OFF) and the two memory cells MC1 and MC2 on either side are turned on (ON). When a voltage is applied between the source electrode S and the drain electrode D, a conduction path is formed as shown by the arrow (A). The applied voltage is V set Value or V reset value, and a desired information of 1 or 0 can be recorded in the selected memory cell MC2.

[0068] Similarly, in a read operation, a selected cell may be read. That is, the gate voltage applied to each gate electrode 260 is adjusted so that the selected memory cell MC2 is in a channel-off state and the unselected memory cells MC1 and MC2 are in a channel-on state. Then, the applied voltage V between the source electrode S and the drain electrode D is adjusted. read By measuring the current flowing through the cell MC2, the cell state (1 or 0) can be confirmed.

[0069] FIG. 11 is a cross-sectional view showing a schematic structure of a variable resistance memory element according to another embodiment. The variable resistance memory element 201 of this embodiment differs from the variable resistance memory element 200 of Figure 8 in that the variable resistance layer 221 includes a first layer 11, a second layer 12, and a third layer 13, but the remaining configuration is substantially identical to the variable resistance memory element 200 of Figure 8.

[0070] The resistance variable layer 221 includes a first layer 11, a second layer 12, and a third layer 13. The second layer 12 located in the middle of the resistance variable layer 221 is also a layer having a higher density than the first layer 11 and the third layer 13. The first layer 11 and the third layer 13 are layers having a lower density than the second layer 12, and may be made of the same material. However, this is not limited thereto, and the first layer 11 and the third layer 13 may be made of different materials.

[0071] In the variable resistance memory element 201 of the present embodiment, the second layer 12 made of a high density material is disposed in the middle, and the first layer 11 and the third layer 13 made of a low density material are disposed adjacent to both sides of the second layer 12. The diffusion of oxygen ions occurs well in the low density layer having a large interatomic space, and the formation of conductive filaments by oxygen vacancies is further facilitated. The variable resistance memory element 201 of the embodiment may have a low set voltage, for example, a lower set voltage than the variable resistance memory element 200 of FIG. 8.

[0072] Fig. 12 is a cross-sectional view showing a schematic structure of a variable resistance memory device according to another embodiment, and Fig. 13 is a perspective view showing a schematic structure of a memory string included in the variable resistance memory device of Fig. 12. Fig. 14 is an equivalent circuit diagram of the variable resistance memory device of Fig. 12.

[0073] The variable resistance memory device 500 of this embodiment is a vertical NAND (VNAND) memory in which a plurality of memory cells MC having a variable resistance material are arrayed in the vertical direction.

[0074] 12 to 14, the detailed configuration of the variable resistance memory device 500 will be described as follows. First, referring to FIG. 12, a plurality of cell strings CS are formed on a substrate 530 .

[0075] The substrate 530 may include a silicon material doped with a first type impurity. For example, the substrate 530 may include a silicon material doped with a P-type impurity. For example, the substrate 530 may also be a P-type well (e.g., a pocket p-well). In the following, it is assumed that the substrate 530 is P-type silicon. However, the substrate 530 is not limited to P-type silicon.

[0076] A doping region 535 is provided on the substrate 530. For example, the doping region 535 has a second type different from the substrate 530. For example, the doping region 535 may have an N-type. In the following, it is assumed that the doping region 535 is an N-type. However, the doping region 535 is not limited to being an N-type. Such a doping region 535 is also coupled to a common source line CSL.

[0077] As shown in the circuit diagram of Fig. 14, k*n cell strings CS are arranged in a matrix and are named CSij (1 ≤ i ≤ k, 1 ≤ j ≤ n) according to their row and column positions. Each cell string CSij is connected to a bit line BL, a string selection line SSL, a word line WL, and a common source line CSL.

[0078] Each cell string CSij includes memory cells MC and string selection transistors SST. The memory cells MC and string selection transistors SST of each cell string CSij are also stacked in the height direction.

[0079] The rows of the cell strings CS are respectively connected to different string selection lines SSL1 to SSLk. For example, the string selection transistors SSTs of the cell strings CS11 to CS1n are commonly connected to the string selection line SSL1. The string selection transistors SSTs of the cell strings CSk1 to CSkn are commonly connected to the string selection line SSLk.

[0080] A column of cell strings CS may be connected to different bit lines BL1 to BLn, respectively. For example, memory cells and string select transistors SST of cell strings CS11 to CSk1 may be commonly connected to bit line BL1, and memory cells MC and string select transistors SST of cell strings CS1n to CSkn may be commonly connected to bit line BLn.

[0081] The rows of the cell strings CS are also connected to different common source lines CSL1 to CSLk, respectively. For example, the string select transistors SST of the cell strings CS11 to CS1n may be commonly connected to the common source line CSL1, and the string select transistors SST of the cell strings CSk1 to CSkn may be commonly connected to the common source line CSLk.

[0082] The memory cells MC located at the same height from the substrate 530 or the string selection transistor SST may be commonly connected to one word line WL, and the memory cells MC located at different heights may be connected to different word lines WL1 to WLm, respectively.

[0083] The illustrated circuit structure is merely exemplary. For example, the number of rows of the cell strings CS may be increased or decreased. By changing the number of rows of the cell strings CS, the number of string selection lines connected to the rows of the cell strings CS and the number of cell strings CS connected to one bit line may also be changed. By changing the number of rows of the cell strings CS, the number of common source lines connected to the rows of the cell strings CS may also be changed.

[0084] The number of columns of the cell strings CS may be increased or decreased. By changing the number of columns of the cell strings CS, the number of bit lines connected to the columns of the cell strings CS and the number of cell strings CS connected to one string selection line may also be changed.

[0085] The height of the cell strings CS may also be increased or decreased. For example, the number of memory cells MC stacked in each cell string CS may be increased or decreased. By changing the number of memory cells MC stacked in each cell string CS, the number of word lines WL may also be changed. For example, the number of string selection transistors provided in each cell string CS may be increased. By changing the number of string selection transistors provided in each cell string CS, the number of string selection lines or common source lines may also be changed. If the number of string selection transistors is increased, the string selection transistors are also stacked in the same form as the memory cells MC.

[0086] For example, writing and reading may be performed in row units of the cell strings CS. The cell strings CS may be selected row by row by the common source line CSL, and the cell strings CS may be selected row by row by the string selection line SSL. In addition, a voltage may be applied to the common source lines CSL with at least two common source lines as one unit. A voltage may be applied to the entire common source line CSL as one unit.

[0087] In a selected row of the cell string CS, writing and reading are also performed in units of a page, which is also a row of memory cells connected to one word line WL. In a selected row of the cell string CS, memory cells are also selected in units of a page by the word line WL.

[0088] 13, the cell string CS includes a cylindrical pillar PL, and a plurality of gates 560 and a plurality of insulators surrounding the cylindrical pillar PL in a ring shape. The plurality of gates 560 and the plurality of insulators may be stacked to cross each other along the vertical direction (Z direction).

[0089] The gates 560 may be made of a metal material or a highly doped silicon material, and each gate 560 is connected to one of a word line WL and a string select line SSL.

[0090] The insulator may be made of a variety of insulating materials such as silicon oxide and silicon nitride. The pillar PL may also be composed of multiple layers. The outermost layer of the pillar PL may also be a gate insulating layer 550. For example, the gate insulating layer 550 may be made of various insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The gate insulating layer 550 may also be conformally deposited on the pillar PL.

[0091] A channel layer 540 is also conformally deposited along the inner surface of the gate insulating layer 550. The channel layer 540 may include a semiconductor material doped to a first type. The channel layer 540 may include a silicon material doped to the same type as the substrate 530, for example, if the substrate 530 includes a silicon material doped to a P type, the channel layer 540 may also include a silicon material doped to a P type. Alternatively, the channel layer 540 may include a material such as Ge, IGZO, GaAs, etc.

[0092] A variable resistance layer 520 may be disposed along an inner surface of the channel layer 540. The variable resistance layer 520 may also be disposed in contact with the channel layer 540 and may also be conformally deposited on the channel layer 540.

[0093] The variable resistance layer 520 is a layer that changes to a high resistance state or a low resistance state depending on an applied voltage, and may include a first layer 11 and a second layer 12 made of oxides with different densities. The variable resistance layer 520 is also substantially the same as the variable resistance layer 120 described in FIG. 1.

[0094] The first layer 11 and the second layer 12 of the variable resistance layer 520 may contain an oxide of at least one element selected from the group including zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), praseodymium (Pr), and silicon (Si). An oxide having a band gap energy of 2 eV or more is used as the material of each of the first layer 11 and the second layer 12, and for example, Rb 2 O, TiO 2 , BaO, ZrO 2 , CaO, HfO 2 , SrO, Sc 2 O 3 , MgO, Li 2 O, Al 2 O 3 , SiO 2 , BeO may be used. That is, the first layer 11 may be made of a low density material, and a material having a relatively higher density may be selected to make the second layer 12. As a result, oxygen ions are smoothly diffused and conductive filaments are well formed by oxygen vacancies, so that the resistance variable memory element 500 may have low set voltage and reset voltage characteristics.

[0095] The channel layer 540 and the variable resistance layer 520 may be in contact with a doped region 535, ie, a common source region.

[0096] A drain 580 may be provided on the pillar PL. The drain 580 may include a silicon material doped to a second type. For example, the drain 580 may include a silicon material doped to an N type.

[0097] A bit line 590 may be provided on the drain 580. The drain 580 and the bit line 550 may also be connected via a contact plug.

[0098] Each gate 560 and the gate insulating layer 550, channel layer 540, and variable resistance layer 520 at a position facing the gate 560 in the horizontal direction (X direction) constitute a memory cell MC. That is, the memory cell MC has a circuit structure in which a transistor including the gate 560, gate insulating layer 550, and channel layer 540 and a variable resistance formed by the variable resistance layer 520 are connected in parallel.

[0099] Such parallel connection structures are continuously arranged in the vertical direction (Z direction) to form a cell string CS. Both ends of the cell string CS may be connected to a common source line CSL and a bit line BLt as shown in the circuit diagram of Fig. 14. When voltages are applied to the common source line CSL and the bit line BLt, a program process, a read process, and an erase process are performed on a plurality of memory cells MC.

[0100] For example, when a memory cell MC to be written is selected, the gate voltage value of the selected cell is adjusted so that a channel is not formed in the selected cell, i.e., the channel is turned off, and the gate voltage value of the unselected cells is adjusted so that the channel is turned on. As a result, the current path due to the voltage applied to the common source line CSL and the bit line BL passes through the variable resistance layer 520 region of the selected memory cell MC, and at this time, the applied voltage is set to V set Value or V reset The value can be set to create a low resistance state or a high resistance state, and a desired piece of information, 1 or 0, can be written to the selected memory cell MC.

[0101] Similarly, in a read operation, a selected cell may be read. That is, the gate voltage applied to each gate electrode 560 is adjusted so that the selected memory cell MC is in a channel-off state and the unselected memory cells are in a channel-on state. Then, the applied voltage V between the common source line CSL and the bit line BL is adjusted. read By measuring the current flowing through the cell MC, the cell state (1 or 0) can be confirmed.

[0102] FIG. 15 is a cross-sectional view showing a schematic structure of a variable resistance memory device according to another embodiment, and FIG. 16 is a perspective view showing a schematic structure of a memory string included in the variable resistance memory device of FIG.

[0103] The variable resistance memory element of this embodiment differs from the variable resistance memory element 500 of FIG. 12 in that the variable resistance layer 521 includes a first layer 11, a second layer 12, and a third layer 13 having different densities, but the remaining configuration is substantially the same.

[0104] The second layer 12 is also a layer having a higher density than the first layer 11 and the third layer 13. The first layer 11 and the third layer 13 are layers having a lower density than the second layer 12 and may be made of the same material. However, the first layer 11 and the third layer 13 may be made of different materials having a lower density than the second layer 12, without being limited thereto. The first layer 11 and the third layer 13 may be made of SiO 2 and the second layer 12 may include HfO 2 Alternatively, the first layer 11 and the third layer 13 may contain a first material, and the second layer 12 may contain a second material, and the combination of the first material and the second material may be selected as exemplified in Table 2. The first layer 11, the second layer 12, and the third layer 13 may each have a thickness of 10 nm or less. The second layer 12 has the thinnest thickness, and may have a thickness of, for example, 2 nm or less. The third layer 13 in contact with the channel layer 540 may also have a thickness of 5 nm or more.

[0105] In this embodiment, the second layer 12 made of a substance with a high density is disposed in the middle, and the first layer 11 and the third layer 13 made of a substance with a low density are disposed adjacent to both sides of the second layer 12. 2- ) is diffused into a larger space, and the conductive filament due to the oxygen vacancies can be more easily formed. The resistance variable memory element can have a lower set voltage than that of, for example, FIG.

[0106] In the above-described embodiment, the variable resistance layer is exemplified as having two or three layers, but is not limited thereto, and may be configured as a multi-layer structure having more than three layers in which layers having a predetermined density difference are adjacently arranged.

[0107] As described above, the variable resistance memory device 500 according to an embodiment uses the variable resistance layers 520, 521 having a structure in which conductive filaments due to oxygen vacancies are easily formed to form memory cells MC, and then arrays the memory cells to implement a memory device, so that the variable resistance layers 520, 521 can be formed thinner and have a lower operating voltage than memory devices having existing structures, for example, a phase-change material-based or charge trap-based memory device. Such a variable resistance memory device 500 can solve a scaling issue between memory cells in next-generation VNAND, increase density, and implement low power.

[0108] The variable resistance memory device 500 according to the present disclosure may be implemented in a chip-like memory block and used in a neuromorphic computing platform or in a neural network configuration.

[0109] FIG. 17 is a block diagram of a memory system according to one embodiment. 17, memory system 1700 may include a memory controller 1701 and a memory device 1702. Memory controller 1701 performs control operations on memory device 1702, for example, memory controller 1701 provides addresses (ADD) to memory device 1702 and commands CMD for causing memory device 1702 to perform programming (or writing), read and / or erase operations. Data for programming operations and read data may be transferred between memory controller 1701 and memory device 1702.

[0110] The memory device 1702 may include a memory cell array 1710 and a voltage generator 1720. The memory cell array 1710 may include a plurality of memory cells arranged in an area where a plurality of word lines and a plurality of bit lines intersect with each other. The memory cell array 1710 includes non-volatile memory cells based on the embodiments of FIGS. 1-5 and 8-15.

[0111] The memory controller 1701 may include a processing circuit, such as hardware including logic circuits, a combination of hardware / software, such as a processor running software, or a combination thereof. For example, the processing circuit may be, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The memory controller 1701 may operate in response to a request from a host (not shown) and may also be configured to access the memory device 1702 and control the aforementioned control operations (e.g., the write / read operations of FIG. 10 ), thereby converting the memory controller 1701 into a special purpose controller. The memory controller 1701 may generate addresses ADD and commands CMD to perform programming / read / erase operations on the memory cell array 1710. Also, in response to instructions from the memory controller 1701, a voltage generator 1720 (e.g., a power circuit) can generate voltage control signals to control the voltage levels of the word lines in the memory cell array 1710 for data programming or data reading.

[0112] The memory controller 1701 may also perform a decision operation on data read from the non-volatile memory device 1702. For example, the number of on cells and / or the number of off cells may be determined from the data read from the memory cells. The memory device 1702 may provide a pass / fail signal P / F to the memory controller 1701 according to a read result of the read data. The memory controller 1701 may control a write operation and a read operation of the memory cell array 1710 by referring to the pass / fail signal P / F.

[0113] FIG. 18 is a block diagram illustrating a neuromorphic device and an external device coupled thereto, according to one embodiment.

[0114] 18, a neuromorphic device 1800 may include a processing circuit 1810 and / or a memory 1820. The neuromorphic device 1800 may include a memory based on the embodiments of FIGS. 1-5 and 8-16.

[0115] In some exemplary embodiments, the processing circuit 1810 is also configured to control functions for driving the neuromorphic device 1800. For example, the processing circuit 1810 is also configured to control the neuromorphic device 1800 by executing programs stored in the memory 1820 of the memory 1820. In some exemplary embodiments, the processing circuit 1810 may include hardware such as logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof. For example, the processor may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1800, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, an FPGA, a SoC, a programmable logic unit, a microprocessor, an ASIC, etc. In some exemplary embodiments, the processing circuit 1810 is also configured to read / write various data to the external device 1830 and / or use the data read / written to execute the neuromorphic device 1800. In some embodiments, external device 1830 may include external memory and / or a sensor array having an image sensor (eg, complementary metal oxide semiconductor (CMOS) image sensor circuitry).

[0116] In some embodiments, the neuromorphic device of Figure 18 is also applied to a machine learning system, which may utilize a variety of artificial neural network structures and processing models, such as convolutional neural networks (CNNs), deconvolutional neural networks, recurrent neural networks (RNNs) optionally including long short-term memory (LSTM) units and / or gated recurrent units (GRUs), stacked neural networks (SNNs), state-space dynamic neural networks (SSDNNs), deep faith networks (DBNs), generative adversarial networks (GANs), and / or restricted Boltzmann machines (RBMs).

[0117] Alternatively, or in addition, such machine learning systems may include combinations of other forms of machine learning models, including, for example, linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, expert systems, and / or ensembles such as random forests. Such machine learning models may also be used to provide a variety of services and / or applications, such as image classification services, biometric or biometric data-based user authentication services, advanced driver assistance system (ADAS) services, voice assistant services, automatic speech recognition (ASR) services, and the like, performed by the electronic device.

[0118] The variable resistance memory device described above has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and those skilled in the art will understand that various modifications and other equivalent embodiments are possible. Although many specific details are described in the above description, they should be construed as examples of specific embodiments rather than limiting the scope of the invention. The scope of the present invention is therefore not defined by the described embodiments, but by the technical ideas described in the claims. [Explanation of symbols]

[0119] 100,101,102,200,201,500,501 Variable resistance memory element 120,121,122,220,221,520,521 Variable resistance layer 210,510,270,570 Insulating layer 240,540 Channel Layer 250,550 Gate insulation layer 260,560 Gates CS Cell String MC memory cell

Claims

1. a variable resistance layer including a first layer made of a first material, a second layer disposed on the first layer and made of a second material having a higher density than the first material, and a third layer disposed on the second layer and made of a third material having a lower density than the second material; A variable resistance memory element comprising: a first conductive element and a second conductive element arranged spaced apart from each other on the variable resistance layer so as to form a current path in the variable resistance layer in a direction perpendicular to a stacking direction of the first layer and the second layer.

2. The density difference between the first material and the second material is 1 g / cm ３ The variable resistance memory element of claim 1 .

3. The density difference between the second material and the third material is 1 g / cm ３ The variable resistance memory element according to claim 1 or 2,

4. The resistance variable memory element of claim 3 , wherein the first material and the third material are the same material.

5. The variable resistance memory element according to claim 3 , wherein the second layer has a smallest thickness among the first layer, the second layer, and the third layer.

6. The variable resistance memory element according to claim 1 , wherein the first material and the second material are oxides having a band gap energy of 2 eV or more.

7. The first substance and the second substance are each Rb ２ O, TiO ２ , BaO, ZrO ２ , CaO, HfO ２ , SrO, Sc ２ O ３ , MgO, Li ２ O, Al ２ O ３ , SiO ２ , BeO, Sc ２ O ３ , Nb ２ O ５ , NiO, Ta ２ O ５ , W.O. ３ , V ２ O ５ , La ２ O ３ , Gd ２ O ３ , CuO, MoO ３ , Cr ２ O ３ , MnO ２ The variable resistance memory element according to claim 1 , wherein the variable resistance memory element is any one of the following:

8. The first material and the second material have the same valence and a density difference of 1.5 g / cm ３ The variable resistance memory element of claim 1 .

9. The first material is HfO ２ and The second material is TiO ２ , MnO ２ , ZrO ２ , SiO ２ or Cr ２ O ３ 2. The variable resistance memory element according to claim 1 ,

10. The first material is Gd ２ O ３ and The second material is Cr ２ O ３ Or La ２ O ３ 2. The variable resistance memory element according to claim 1 ,

11. the first material is NiO; The resistance variable memory element of claim 1 , wherein the second material is SrO, CaO or BeO.

12. The first substance is WO ３ and The second material is MoO ３ 2. The variable resistance memory element according to claim 1 ,

13. An insulating layer; a variable resistance layer disposed on the insulating layer, the variable resistance layer including a first layer made of a first material, and a second layer disposed on the first layer and made of a second material having a density different from that of the first material; a channel layer disposed on the variable resistance layer; a gate insulating layer formed on the channel layer; a plurality of gate electrodes spaced apart from one another on the gate insulating layer.

14. The variable resistance memory element of claim 13 , wherein the density of the second material is greater than the density of the first material.

15. The density difference between the first material and the second material is 1 g / cm ３ The variable resistance memory element of claim 14 .

16. The variable resistance layer is The variable resistance memory element of claim 14 or 15, further comprising a third layer of a third material disposed on the second layer and having a lower density than the second material.

17. The variable resistance memory element according to claim 16 , wherein the first layer, the second layer, and the third layer each have a thickness of 10 nm or less.

18. The variable resistance memory element of claim 17 , wherein the second layer has a thickness of 2 nm or less.

19. The variable resistance memory element according to claim 17 , wherein the third layer is in contact with the channel layer and has a thickness of 5 nm or more.

20. The density difference between the second material and the third material is 1 g / cm ３ The variable resistance memory element of claim 16 .

21. The variable resistance memory element of claim 16 , wherein the first material and the third material are the same material.

22. The variable resistance memory element of claim 13 , wherein the first material and the second material are oxides having a band gap energy of 2 eV or more.

23. The first substance and the second substance are each Rb ２ O, TiO ２ , BaO, ZrO ２ , CaO, HfO ２ , SrO, Sc ２ O ３ , MgO, Li ２ O, Al ２ O ３ , SiO ２ , BeO, Sc ２ O ３ , Nb ２ O ５ , NiO, Ta ２ O ５ , W.O. ３ , V ２ O ５ , La ２ O ３ , Gd ２ O ３ , CuO, MoO ３ , Cr ２ O ３ , MnO ２ The variable resistance memory element according to claim 13 , wherein the variable resistance memory element is any one of the following:

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