Semiconductor Device

Abstract

This semiconductor device (100) comprises: an insulating substrate (30); a pattern (40) comprising metal, the pattern being formed as a thin plate on the upper surface of the insulating substrate (30); and a semiconductor chip (50) bonded to the upper surface of the pattern (40). The semiconductor device further comprises a wire (70) made of metal, the wire following the outer periphery of the pattern (40) and being connected to the pattern (40) at a plurality of connection points (C) above the pattern (40).

Description

[Technical field]

[0001] The present application relates to a semiconductor device. [Background technology]

[0002] In a semiconductor device, an insulating substrate is bonded to the upper surface of a grounded base plate, and an electrode is formed on the upper surface of the insulating substrate. In this structure, the end of the electrode is prone to dielectric breakdown due to electric field concentration. Therefore, a semiconductor device structure is known in which a second metal substrate having the same potential as the electrode is disposed symmetrically to the base plate as viewed from the electrode, thereby reducing the maximum electric field and improving the insulating ability (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2003-086763 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in conventional semiconductor devices, a second metal substrate must be disposed, making it difficult to simultaneously improve the insulating ability and further reduce the size of the semiconductor device.

[0005] The present application discloses a technique for solving the above-mentioned problems, and has an object to provide a semiconductor device that can be miniaturized while improving insulation performance. [Means for solving the problem]

[0006] The semiconductor device disclosed in the present application comprises: The semiconductor device includes an insulating substrate, a pattern made of a thin metal plate formed on an upper surface of the insulating substrate, and a semiconductor chip bonded to the upper surface of the pattern, A metal wire is provided above the pattern along the periphery of the pattern and connected to the pattern at a plurality of connection points. 、 Between the adjacent connection points, the wire is curved so as to protrude outward from the region above the pattern toward the end side of the insulating substrate. It is something 。 Effect of the Invention

[0007] According to the semiconductor device disclosed in the present application, it is possible to provide a semiconductor device that can be miniaturized while improving the insulating ability. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a perspective view showing a main part of a semiconductor device according to a first embodiment. [Diagram 3] 3 is a schematic cross-sectional view showing a main part of the semiconductor device according to the first embodiment, taken along the dashed line A in FIG. 2 in the vertical direction. [Figure 4] 11 is a schematic cross-sectional view showing a main part of a semiconductor device according to a second embodiment. FIG. [Diagram 5] FIG. 11 is a perspective view showing a main part of a semiconductor device according to a third embodiment. [Figure 6] 6 is a schematic cross-sectional view showing a main part of a semiconductor device according to a third embodiment, taken along dashed line B in FIG. 5 in the vertical direction. [Figure 7] 7A to 7D are perspective views showing the process of providing wires in a pattern. [Figure 8] FIG. 13 is a schematic plan view showing one corner of a pattern according to a fourth embodiment. [Figure 9] 13 is a schematic plan view showing a main part of a semiconductor device according to a fourth embodiment, illustrating a corner of a pattern to which a wire is attached. FIG. [Figure 10] 13 is a schematic cross-sectional view showing a main part of a semiconductor device according to a fifth embodiment, illustrating the vicinity of the outer periphery of a pattern. [Figure 11] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment. [Figure 12]FIG. 23 is a schematic cross-sectional view showing the vicinity of the outer periphery of a pattern according to a sixth embodiment. [Figure 13] 13 is a schematic plan view showing the vicinity of a corner of a pattern according to a sixth embodiment. FIG. [Figure 14] FIG. 23 is a schematic plan view of a modified example of the pattern according to the sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Embodiment 1 The semiconductor device according to the first embodiment will now be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a semiconductor device 100 according to the first embodiment. In this specification, when referring to the inside and the outside, the center side of the semiconductor device 100 is referred to as the inside and the opposite side is referred to as the outside. In addition, when referring to the top-bottom relationship, the base plate 20 side of the semiconductor device 100 is referred to as the bottom and the opposite side is referred to as the top.

[0010] The semiconductor device 100 comprises a substantially rectangular parallelepiped base plate 20 made of metal, and a thin plate-like insulating substrate 30 bonded to the upper surface of the base plate 20, and a thin plate-like pattern 40 made of metal is formed on the other surface (upper surface) of the insulating substrate 30 that is not bonded to the base plate 20, and a thin plate-like semiconductor chip 50 is bonded to the upper surface of the pattern 40. The insulating substrate 30 may be formed into a thin plate-like shape by kneading an insulating epoxy resin with an equally insulating filler, or may be formed of other materials such as ceramics.

[0011] The semiconductor chip 50 is a power semiconductor element such as an insulated gate bipolar transistor, a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), a free wheeling diode (FWD), etc., and one or more of these may be used in combination. The semiconductor chip 50 may be formed on a silicon substrate, or may be formed on silicon carbide, gallium nitride, or other semiconductor materials.

[0012] The semiconductor device 100 includes a case 80 having a square-shaped cross section and terminals 90 for connecting to an external circuit. The case 80 has a locking portion 81 that protrudes inward at the center between the top and bottom of the inner wall. The base plate 20 and the insulating substrate 30 that is layered on the upper surface of the base plate 20 are fitted inside the case 80 so that the edge of the upper surface of the insulating substrate 30 abuts against the locking portion 81, thereby closing one opening of the case 80. The insulating substrate 30 and the case 80 may be bonded together.

[0013] The connection terminals 90 are electrically connected to the pattern 40 and the semiconductor chip 50 by metal conductors (not shown) so as to form a desired electric circuit.

[0014] The inside of the case 80 is filled with sealing resin 60, which protects and electrically insulates the semiconductor chip 50 and the pattern 40. As the sealing resin 60, an epoxy resin kneaded with an insulating filler is typically used, but any solid having insulating properties may be used, and another example of the epoxy resin is silicone gel.

[0015] A metal wire 70 is provided above the pattern 40 along the outer periphery 40G of the pattern 40 facing the inner surface 80in of the case 80, and this wire 70 is connected to the pattern 40 at multiple points. Therefore, the wire 70 has the same electrical potential as the pattern 40. Examples of the material of the wire 70 include aluminum and copper, but it is not particularly limited as long as it is a metal.

[0016] Fig. 2 is a perspective view showing a main part of the semiconductor device 100. The case 80, the sealing resin 60, and the connection terminals 90 are omitted in Fig. 2. The wire 70 is provided above the pattern 40 along a portion of the outer periphery 40G of the pattern 40 where the outer surface 40out of the pattern 40 faces the inner surface 80in of the case 80, and the wire 70 and the pattern 40 are electrically connected at multiple points as described above.

[0017] 2, multiple wires 70 may be arranged on the same pattern 40, or only a single wire 70 may be arranged continuously. Between connection points C of the wire 70 and the pattern 40, the wire 70 forms an arch-shaped wire loop, and the distance between the wire 70 and the pattern 40 is 5 times the diameter of the wire 70 or less.

[0018] If the interval between adjacent connection points C between the wire 70 and the pattern 40 is too long, the wire 70 may flow away together with the resin when the sealing resin 60 is injected in the manufacturing process of the semiconductor device 100, and may deviate from a predetermined position, so that the connection points C are typically arranged at intervals of 5 mm or less. The interval may be determined in accordance with the material and injection method of the sealing resin 60 so as to prevent the wire 70 from flowing away.

[0019] Fig. 3 is a schematic cross-sectional view of a main part of the semiconductor device 100, cut vertically at the portion of the dashed line A in Fig. 2. Next, the effect of improving the insulating ability by the wire 70 will be described with reference to Fig. 3. In Fig. 3, the potential of the base plate 20 is the ground potential, and a high voltage is applied to the pattern 40 and the wire 70. Therefore, electric field concentration occurs at the joint end S between the insulating substrate 30 and the pattern 40.

[0020] To make matters worse, the joint end S is a location where voids are likely to remain when the sealing resin 60 hardens, and where peeling is likely to occur between the sealing resin 60 and the insulating substrate 30, making it a weak point in terms of insulation.

[0021] Therefore, by relaxing the electric field at the joint end S, it is possible to improve the insulating ability of the semiconductor device 100. Here, by providing the wire 70 having the same potential as the pattern 40 along and above the outer periphery 40G of the pattern 40, it is possible to flatten the electric field distribution on the outer surface 40out of the pattern 40, and to relax the electric field at the joint end S, compared to the case where the wire 70 is not present.

[0022] The region where the wire 70 is provided is a region that would have been filled with the sealing resin 60 even in the conventional structure (when the wire 70 is not used), so providing the wire 70 does not require any increase in size of the semiconductor device 100. In addition, since the electric field relaxation effect can be obtained, it is possible to reduce the region where the pattern 40 is not provided at the end of the insulating substrate 30 compared to the conventional structure, so that the semiconductor device 100 can be further miniaturized.

[0023] According to the semiconductor device 100 of the first embodiment, it is possible to provide a semiconductor device that can be miniaturized while improving the insulating ability.

[0024] Embodiment 2 The semiconductor device according to the second embodiment will be described below, focusing on the differences from the first embodiment. FIG. 4 is a schematic cross-sectional view showing a main part of the semiconductor device 200. This is a schematic cross-sectional view showing the vicinity of the outer periphery 40G of the pattern 40, and corresponds to FIG. 3 of the first embodiment. Along the outer periphery 40G of the pattern 40 facing the inner side surface 80in of the case 80, the wire 270 is connected to the upper surface of the pattern 40 at the connection point C in the same manner as in the first embodiment. Between the adjacent connection points C, the wire 270 is curved so as to protrude outward from the region above the pattern 40 toward the end side of the insulating substrate 30. With this structure, the electric field distribution of the outer side surface 40out of the pattern 40 can be further flattened immediately below the protruding portion of the wire 270, the electric field of the joint end S can be alleviated, and the insulation of the semiconductor device 200 can be further strengthened. In order to make the wire 270 have such a structure, the manufacturing process of the semiconductor device 100 includes a process of connecting the wire along the outer periphery 40G of the pattern 40 and a process of curving the wire to a predetermined position.

[0025] Embodiment 3 The semiconductor device according to the third embodiment will be described below, focusing on the differences from the second embodiment. Fig. 5 is a perspective view showing a main part of the semiconductor device 300. In Fig. 5, the case 80, the sealing resin 60, and the connection terminals 90 are omitted. The wires 370 are connected to the upper surface of the pattern 40 at multiple points along the outer periphery 40G of the pattern 40 that faces the inner surface 80in of the case 80. Two wires 370 are connected to each side of the outer periphery 40G of the pattern 40 to which the wires 370 are attached, and the two wires 370 cross each other.

[0026] FIG. 6 is a schematic cross-sectional view of a main portion of the semiconductor device 300, taken along the dashed line B in FIG. Of the two wires 370 connected to one side of pattern 40, in the cross section of Figure 6, at the portion where one wire 370a is connected to pattern 40 and connection point C, the other wire 370b is curved outward so that it protrudes horizontally from insulating substrate 30.

[0027] 7A to 7D are perspective views showing the process of installing wire 370 on pattern 40. First, as shown in FIG. 7A, a first wire 370a is connected at multiple connection points C along the outer periphery 40G of pattern 40. A wire loop of a predetermined height is formed between the connection points C. Next, as shown in FIG. 7B, the first wire 370a is bent at a predetermined position so as to protrude outward from the end of pattern 40.

[0028] Next, as shown in Fig. 7C, a second wire 370b is connected to the pattern 40. At this time, the second wire 370b is connected to the pattern 40 so that a connection point C of the newly connected wire 370b is provided between two adjacent connection points C of the previously placed first wire 370a and the pattern 40 in the outer periphery direction of the pattern 40. Next, as shown in Fig. 7D, the second wire 370b is arranged to be curved so as to protrude outward from the outer periphery 40G of the pattern 40, similar to the first wire 370a.

[0029] According to the semiconductor device 300 of the third embodiment, even directly below the curved portion of the wire 370b, an area where the electric field distribution can be flattened over the entire outer surface 40out of the pattern 40 can be secured, thereby mitigating the electric field at the joint end S and providing a semiconductor device 300 with further enhanced insulation properties.

[0030] Embodiment 4 The semiconductor device according to the fourth embodiment will be described below, focusing on the differences from the first to third embodiments. FIG. 8 is a schematic plan view showing one corner of the pattern 440. As shown in FIG. FIG. 9 is a schematic plan view showing a main portion of the semiconductor device 400, that is, a corner portion of a pattern 440 to which wires 470in and 470out are attached. 8, pattern 440 has four corners of outer periphery 440G rounded in the same manner, and two wire connection parts 441in, 441out are set roughly parallel to each other along outer periphery 440G including rounded parts 440R. Wire connection parts 441in, 441out shown in the figure are lines connecting connection points C of two wires 470in, 470out.

[0031] Of the two wires 470in, 470out connected along the outer periphery 440G of pattern 440, the outer wire 470out is installed so as to have connection point C only at the outer wire connection portion 441out, and the inner wire 470in is installed so as to have connection point C only at the inner wire connection portion 441in.

[0032] The process of installing wires 470in, 470out includes the steps of connecting a first wire 470out to the wire connection portion 441out closer to the outer periphery 440G of pattern 440, bending the wire 470out to a predetermined position toward the outside of pattern 440, connecting a second wire 470in to the inner wire connection portion 441in, and bending the second wire 470in toward the outside of pattern 440.

[0033] According to the semiconductor device 400 of the fourth embodiment, the area where the electric field distribution of the outer side surface 440out of the pattern 440 can be flattened directly under the curved parts of the wires 470in and 470out can be expanded to the entire outer periphery 440G of the pattern 440, so that the electric field of the joint end S can be relaxed and the semiconductor device 400 with further enhanced insulation can be provided. Furthermore, since two wire connection parts 441out and 441in are provided in parallel along the R-processed part 440R of the outer periphery 440G of the pattern 440, when the second wire 470in is connected to the pattern 440, the first wire 470out and the second wire 470in do not interfere with each other. This makes it possible to realize a semiconductor device 400 and a manufacturing process with higher reliability.

[0034] Embodiment 5. The semiconductor device according to the fifth embodiment will be described below, focusing on the differences from the first to fourth embodiments. 10 is a schematic cross-sectional view showing a main portion of semiconductor device 500, and showing the vicinity of outer periphery 540G of pattern 540. Wire 570 is connected along outer periphery 540G of pattern 540, and protrudes to the outside of pattern 540. In addition, insulating coating G is provided between wire 570 and insulating substrate 30.

[0035] The insulating coating G is a resin that can be hardened by some means after application, and one example is silicone rubber, but it is not limited to silicone rubber and can be any resin that has both insulating properties and hardening properties. The hardening means is not particularly limited and may be a material that can be hardened by heat like silicone rubber, or another example may be a material that can be hardened by the action of ultraviolet light.

[0036] The process of installing the wire 570 includes a process of applying an insulating coating G to the insulating substrate 30, a process of curing the insulating coating G, and a process of connecting the wire 570 to the pattern 540. The structure of bending the wire 70 described in the second embodiment, the structure of providing two wires 270 that cross each other described in the third embodiment, or the structure of providing two wires with their connection portions offset in parallel described in the fourth embodiment can be appropriately combined based on design needs.

[0037] According to the semiconductor device 500 of the fifth embodiment, in the process of bending the wires 570 and the process of injecting and curing the sealing resin 60, it is possible to prevent the wires 570 from falling more than necessary toward the insulating substrate 30, which would result in the electric field relaxation effect being lost. This makes it possible to provide a semiconductor device 500 with even higher reliability.

[0038] Embodiment 6 The semiconductor device according to the sixth embodiment will be described below, focusing on the differences from the first to fifth embodiments. FIG. 11 is a schematic cross-sectional view of a semiconductor device 600 according to the sixth embodiment. Along an outer periphery 640G of the pattern 640 facing the inner surface 80in of the case 80, a metal protrusion 640P is provided so as to make the thickness of the pattern 640 thicker on the upper side of the insulating substrate 30, and the protrusion 640P and the pattern 640 are electrically connected to have the same potential. The protrusion 640P may be formed by providing a thick pattern 640 on the insulating substrate 30 and then scraping away the portions other than the protrusion 640P, or may be formed by separately joining a metal member to the thin pattern 640.

[0039] FIG. 12 is a schematic cross-sectional view showing the vicinity of an outer periphery 640G of the pattern 640. As shown in FIG. By providing protrusions 640P only on the outer periphery of pattern 640 facing the inner surface 80in of case 80, the electric field at the joint end S between insulating substrate 30 and pattern 640 can be alleviated without increasing the overall thickness of pattern 640.

[0040] FIG. 13 is a schematic plan view showing the vicinity of a corner of the pattern 640. As shown in FIG. A protrusion 640P is formed along an outer periphery 640G of the pattern 640 facing the inner surface 80in of the case 80. This makes it possible to provide a region for alleviating the electric field over the entire periphery of the insulating substrate 30. Therefore, it is possible to provide a semiconductor device 600 with further enhanced insulation properties.

[0041] By configuring pattern 640 in this manner, it is even more advantageous to make the thickness of pattern 640 thinner in the central region of pattern 640, which does not affect the electric field relaxation, so that the thermal resistance of pattern 640 can be reduced when dissipating heat generated by semiconductor chip 50 to base plate 20.

[0042] FIG. 14 is a schematic plan view showing a variation of the sixth embodiment, a pattern 640B different from that in FIG. A narrow pattern on which the semiconductor chip 50 is not mounted may be provided at the end of the insulating substrate 30 for convenience of the circuit configuration. In this way, cases are assumed in which the pattern width is too narrow to provide a protrusion. In such cases, the entire pattern of the relevant portion may be made thicker to form a thick pattern 642, and the thick pattern may be mixed with a pattern 640B provided with a protrusion 640P. The thickness of the thick pattern 642 may be the same as the thickness of the portion of the pattern 640B provided with the protrusion 640P.

[0043] Although the present application describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not exemplified are assumed within the scope of the technology disclosed in this application, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component and combining it with a component of another embodiment. [Explanation of symbols]

[0044] 100,200,300,400,500,600 semiconductor device, 20 base plate, 30 insulating substrate, 40,440,540,640,640B pattern, 40out,440out outer surface, 40G,440G,540G,640G outer periphery, 440R R processed portion, 441in,441out wire connection portion, 640P protrusion, 642 thick pattern, 50 semiconductor chip, 60 sealing resin, 70,270,370,370a,370b,470in,470out,570 wire, 80 case, 80in inner surface, 81 locking portion, 90 connection terminal, A,B dashed line, C connection point, G insulating coating, S joint end portion.

Claims

1. The semiconductor device includes an insulating substrate, a pattern made of a thin metal plate formed on an upper surface of the insulating substrate, and a semiconductor chip bonded to the upper surface of the pattern, a metal wire is provided above the pattern along an outer periphery of the pattern and connected to the pattern at a plurality of connection points; Between adjacent connection points, the wire is curved so as to protrude outward from the region above the pattern toward the edge of the insulating substrate.

2. Two of the wires are provided, 2. The semiconductor device according to claim 1, wherein the connection point of one of the wires is provided between two adjacent connection points of the other wire.

3. 3 . The semiconductor device according to claim 2 , wherein a line connecting the connection points of one of the wires and a line connecting the connection points of the other of the wires are aligned parallel to an outer periphery of the pattern.

4. 4. The semiconductor device according to claim 3, wherein the pattern has rounded corners.

5. 5. The semiconductor device according to claim 1, further comprising an insulating coating made of an insulating and curable resin between the insulating substrate and a portion of the wire that protrudes outward from the region above the pattern toward the end of the insulating substrate.

6. 6. The semiconductor device according to claim 1, wherein the wire forms an arch-shaped wire loop.

7. a case; and a base plate provided inside the case so as to close one opening of the case, 7. The semiconductor device according to claim 1, wherein the insulating substrate is overlaid on an upper surface of the base plate, and the wire is provided along an outer periphery of the pattern that faces an inner surface of the case.

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