Dynamic Peak Power Management for Multi-Die Operation

Abstract

To provide dynamic peak power management for a multi-die operation.SOLUTION: Provided is a method of peak power management (PPM) for a memory chip having a plurality of memory dies, in which each of the plurality of memory dies includes a PPM circuit having a PPM contact pad, and the PPM contact pads of the plurality of memory dies are electrically connected to each other. The PPM method includes the steps of: turning on a pull-down driver of the PPM circuit on the selected memory die of the next memory chip; verifying a PPM enable signal conditioned by a pull-down current flowing through the pull-down driver; and performing peak power operation on the selected memory die when the PPM enable signal indicates that the total current of the memory chip is less than the maximum total current allowed for the memory chip.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly to circuit designs and methods for peak power management in storage systems. [Background technology]

[0002] In many servers and mobile devices, NAND storage systems are widely used as the primary non-volatile storage device due to their high storage density and relatively small access latency. However, the performance of a high-density storage system, such as a three-dimensional (3D) NAND storage system, is often limited by the maximum amount of power (or peak current) it can use. Currently, the high-power consuming operations (i.e., peak power operations) performed by the various memory dies of a NAND storage system can be interleaved by a system controller. Only a limited number of peak power operations can be performed simultaneously. This approach can result in increased system load due to unnecessary over-management. Communication between different memory dies can be established to coordinate peak power operations. Currently, communication between two memory dies can be established, and peak power operations can be interleaved between these two memory dies. However, only one peak power operation can be performed at a time. In addition, two or more contact pads are used on each memory die for communication between different memory dies on the same memory chip. Therefore, it is necessary to optimize peak power management circuits and schemes to coordinate across multiple memory dies so that multiple peak power operations can be performed simultaneously on a memory chip, thus fully utilizing the power or current budget of the storage system. Summary of the Invention [Means for solving the problem]

[0003] One aspect of the present disclosure is to provide effective peak power management for memory storage systems.

[0004] One aspect of the present disclosure provides a peak power management (PPM) system for a memory chip with multiple memory dies. The PPM system includes a PPM circuit on each of the multiple memory dies. Each PPM circuit includes a pull-up driver electrically connected to a power source and a PPM resistor, a pull-down driver electrically connected to the PPM resistor, and a PPM contact pad connected to the PPM resistor. The PPM contact pads of the multiple memory dies are electrically connected to each other. The PPM system is also configured to manage peak power operation based on a potential of the PPM contact pad.

[0005] In some embodiments, the PPM system further includes a comparator having a first input terminal electrically connected to the PPM contact pads of the plurality of memory dies and a second input terminal electrically connected to a reference voltage. In some embodiments, an output terminal of the comparator is connected to an inverter. In some embodiments, an RC filter is electrically connected to the PPM contact pads of the plurality of memory dies and the first input terminal of the comparator. In some embodiments, the reference voltage is based on a maximum total current allowed for the memory chips.

[0006] In some embodiments, the potential of the PPM contact pad is regulated by a pull-down current flowing through a pull-down driver in the PPM circuit, hi some embodiments, the pull-down current includes a high current level, the high current level corresponding to a peak current of a peak power operation.

[0007] In some embodiments, the pull-up driver includes a p-channel metal-oxide-semiconductor field effect transistor (MOSFET).

[0008] In some embodiments, the pull-down driver includes an n-channel metal-oxide-semiconductor field effect transistor (MOSFET).

[0009] In some embodiments, the PPM contact pad, the PPM resistor, and the pull-down driver are electrically connected.

[0010] In some embodiments, the PPM contact pad, the PPM resistor, and the pull-up driver are electrically connected.

[0011] In some embodiments, the PPM contact pads are electrically connected through inter-die connections, each inter-die connection including a metal interconnect.

[0012] In some embodiments, the PPM contact pads are electrically connected together through flip-chip bonding, die-to-die bonding, or wire bonding.

[0013] Another aspect of the present disclosure provides a method of peak power management (PPM) for a memory chip with multiple memory dies, each of the multiple memory dies including a PPM circuit having PPM contact pads. The PPM contact pads of the multiple memory dies are electrically connected to each other. The PPM method includes the steps of: switching on a pull-down driver of a PPM circuit on a selected memory die of the memory chip, verifying a PPM enablement signal conditioned by a pull-down current flowing through the pull-down driver, and implementing a peak power operation on the selected memory die when the PPM enablement signal indicates that a total current of the memory chip is less than a maximum total current allowed for the memory chip.

[0014] In some embodiments, the method also includes, after switching on the pull-down driver, setting a pull-down current flowing through the pull-down driver on the selected memory die to a high current level, the high current level corresponding to a peak current of a peak power operation for the selected memory die.

[0015] In some embodiments, the method further includes setting a pull-down current flowing through a pull-down driver on the selected memory die to a low current level after performing a peak power operation, the low current level corresponding to a base current for the selected memory die.

[0016] In some embodiments, the method further includes switching off the pull-down drivers on the selected memory die if the PPM enablement signal indicates that the total current of the memory chips exceeds a maximum total current allowed for the memory chips.

[0017] In some embodiments, the method also includes waiting for a delay period after switching off the pull-down driver.

[0018] In some embodiments, the method further includes generating the PPM enablement signal by comparing a reference voltage to the potential of the PPM contact pad before verifying the PPM enablement signal, the reference voltage being selected according to a maximum total current allowed for the memory chip.

[0019] In some embodiments, the method also includes adjusting the potential of the PPM contact pad through a pull-down current of a pull-down driver, where the total current of the memory chip corresponds to the sum of the pull-down currents flowing through each pull-down driver on the memory chip.

[0020] In some embodiments, if the potential of the PPM contact pad is higher than the reference voltage, the PPM enablement signal is set to 0, and if the potential of the PPM contact pad is lower than the reference voltage, the PPM enablement signal is set to 1.

[0021] Those skilled in the art will appreciate other aspects of the present disclosure in light of the description, claims, and drawings of the present disclosure.

[0022] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure and to enable one skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0023] [Figure 1A] FIG. 1 illustrates a storage system with one or more memory chips in accordance with some embodiments of the present disclosure. [Figure 1B] FIG. 2 illustrates a top view of a memory die according to some embodiments of the present disclosure. [Diagram 2] FIG. 2 illustrates a peak power management system in a memory chip according to some embodiments of the present disclosure. [Diagram 3] FIG. 2 illustrates a peak power management circuit according to some embodiments of the present disclosure. [Figure 4] FIG. 2 illustrates a current profile for a memory die according to some embodiments of the present disclosure. [Diagram 5] FIG. 2 illustrates a circuit of a peak power management group according to some embodiments of the present disclosure. [Figure 6] FIG. 1 illustrates a peak power management scheme in accordance with some embodiments of the present disclosure. [Figure 7] FIG. 2 illustrates another peak power management circuit according to some embodiments of the present disclosure. [Figure 8] FIG. 2 illustrates a current profile for a memory die according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the drawings, in which like reference numbers identify corresponding elements throughout, and in which like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements.

[0025] Embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0026] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to one skilled in the art that the present disclosure can also be used in a variety of other applications.

[0027] It will be noted that references herein to "one embodiment," "one embodiment," "an example embodiment," "some embodiments," and the like, indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described with respect to one embodiment, it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic with respect to other embodiments, whether or not explicitly described.

[0028] Generally, terms can be understood, at least in part, from their usage in the context. For example, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense, at least in part, depending on the context. Similarly, terms such as "a," "an," or "the" can also be understood to suggest a singular use, or can also be understood to suggest a plural use, at least in part, depending on the context. In addition, the term "based on" can be understood as not necessarily intended to suggest an exclusive set of elements, but instead may allow for the presence of additional elements not necessarily explicitly described, again at least in part, depending on the context.

[0029] As used herein, the term "nominal" refers to a desired or target value of a characteristic or parameter for a component or process step, which is set during the design phase of the product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations or tolerances in the manufacturing process. As used herein, the term "about" refers to the value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of interest. Based on a particular technology node, the term "about" may refer to the value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0030] FIG. 1A illustrates a storage system 10 according to some embodiments of the present disclosure. The storage system 10 (also referred to as a NAND storage system or solid-state drive) can include a host controller 20 and one or more memory chips 25-1, 25-2, 25-3, ..., 25-n. Each semiconductor memory chip 25 (hereafter simply "memory chip") can be a NAND chip (i.e., "flash", "NAND flash", or "NAND"). The solid-state drive (SSD) 10 can communicate with a host computer 15 through a host controller 20, which can be connected to one or more memory chips 25-1, 25-2, 25-3, ..., 25-n via one or more memory channels 30-1, 30-2, 30-3, ..., 30-n. In some embodiments, each memory chip 25 can be managed by the host controller 20 via the memory channel 30.

[0031] The host computer 15 sends data to be stored in the NAND storage system or SSD 10 or retrieves data by reading the SSD 10. The host controller 20 can handle I / O requests received from the host computer 15, ensure data integrity and efficient storage, and manage the memory chips 25. The memory channel 30 can enable data and control communication between the host controller 20 and each memory chip 25 via a data bus. The host controller 20 can select one of the memory chips 25 according to a chip enable signal.

[0032] FIG. 1B illustrates a top view of a NAND flash memory 100 according to some embodiments of the present disclosure. The NAND flash memory 100 can be a memory die (or dies) or any portion of a memory die. In some embodiments, each memory chip 25 of FIG. 1A can include one or more memory dies, such as one or more NAND flash memories 100. In some embodiments, each NAND flash memory 100 can include one or more memory planes 101, each of which can include multiple memory blocks 103. Identical and simultaneous operations can be performed on each memory plane 101. The memory blocks 103, which can be megabytes (MB) in size, are the minimum size for performing an erase operation. As shown in FIG. 1B, the exemplary NAND flash memory 100 includes four memory planes 101, each of which includes six memory blocks 103. Each memory block 103 can include multiple memory cells, where each memory cell can be addressed through interconnects such as bit lines and word lines. The bit lines and word lines can be laid out vertically (e.g., as rows and columns, respectively) to form an array of metal lines. The bit line and word line directions are labeled as "BL" and "WL" in FIG. 1B. In this disclosure, the memory block 103 is also referred to as a "memory array" or "array." The memory array is the core area on a memory die that performs storage functions.

[0033] NAND flash memory 100 also includes a peripheral region 105, which is the area surrounding memory plane 101. Peripheral region 105 houses many digital, analog, and / or mixed-signal circuits to support the functionality of the memory array, such as page buffer 50, row decoder 40, column decoder 60, peripheral circuits 70, and sense amplifiers 80. Peripheral circuits 70 include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0034] It should be noted that the layout of electronic components in SSD 10 and NAND flash memory 100 of Figures 1A and 1B are shown as examples. SSD 10 and NAND flash memory 100 may have other layouts and may include additional components. For example, NAND flash memory 100 may also include a high voltage charge pump, I / O circuitry, etc. SSD 10 may also include firmware, a data scrambler, etc.

[0035] 2 illustrates a peak power management system 200 for a memory chip 25 according to some embodiments of the present disclosure. The peak power management (PPM) system 200 may be implemented within each memory chip 25 of the NAND storage system 10 of FIG. 1A, where each memory chip 25 may include multiple memory dies 100-1, 100-2, 100-3, ..., 100-n, where each memory die may be similar to the NAND flash memory 100 discussed above with reference to FIG. 1B. In some embodiments, each NAND flash memory 100 may include a peak power management (PPM) circuit 202, where each PPM circuit 202 may include a PPM contact pad 204 (also referred to as a PPM pin). The PPM circuits 202-1, 202-2, 202-3, ..., 202-n on different NAND flash memories 100-1, 100-2, 100-3, ..., 100-n of the memory chip 25 can communicate with each other through PPM pins 204-1, 204-2, 204-3, ..., 204-n. In some embodiments, the PPM pins between different NAND flash memories 100 can be electrically connected with each other through multiple die-to-die connections 205. For example, the PPM pin 204-2 on the NAND flash memory 100-2 can be electrically connected with the PPM pin 204-1 on the NAND flash memory 100-1 through the die-to-die connection 205-1, and can be electrically connected with the PPM pin 204-3 on the NAND flash memory 100-3 through the die-to-die connection 205-2. In some embodiments, the die-to-die connections 205 can be metal wires formed through wire bonding. In some embodiments, die-to-die connections 205 may be metal wires or any suitable metallic or conductive material formed through flip-chip bonding or any suitable die-to-die bonding. In some embodiments, die-to-die connections 205 may be formed by through-silicon VIAs (e.g., through-array structures).

[0036] By using the above-mentioned inter-die connections, communication can be established between different memory dies (i.e., NAND flash memories 100-1, 100-2, 100-3, ..., 100-n) within the memory chip 25. Thus, the NAND storage system 10 can send operational commands to any number of memory dies at any time, and at the same time, the PPM circuit 202 can control the power consumption of the system by selecting one or more memory dies.

[0037] 3 illustrates an example PPM circuit 202 on a NAND flash memory 100 in accordance with some embodiments of the present disclosure. The PPM circuit 202 may include a pull-up driver 314, where one terminal of the pull-up driver 314 is connected to a voltage V dd In some embodiments, the pull-up driver 314 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In some embodiments, the pull-up driver 314 may be a p-channel MOSFET (i.e., pFET), where a source terminal of the pFET 314 may be connected to the power supply 312 and a drain terminal of the pFET 314 may be connected to the power supply 312 with a resistance R ppm The input signal can be connected to a PPM resistor 318 having a

[0038] In some embodiments, the PPM circuit 202 also includes a pull-down driver 336. In some embodiments, the pull-down driver 336 may be a MOSFET. In some embodiments, the pull-down driver 336 may be an n-channel MOSFET (i.e., nFET). A source terminal of the nFET 336 may be connected to ground, and a drain terminal of the nFET 336 may be connected to the PPM resistor 318.

[0039] In some embodiments, the drain terminal of the PPM resistor 318 and the nFET 336 are also electrically connected to the PPM contact pad 204 at node 322. Some or all of the PPM contact pads (e.g., PPM pins 204) may be electrically connected through die-to-die connections 205 (see FIG. 2). Thus, those PPM contact pads 204 of the memory chips 25 are electrically connected to the potential V ppm It is possible for the data to be held in a constant state.

[0040] In some embodiments, the PPM circuit 202 is configured such that the first input terminal 324 receives a reference voltage V ref and having a second input terminal 326 connected to node 322. The comparator 328 is connected to the input voltage V in at the first input terminal 324. ref In this case, the output voltage V at the output terminal 330 may be an operational amplifier used to compare out is the input voltage V in is the reference voltage V ref For example, it can indicate whether the output voltage V out is the input voltage V in is the reference voltage V ref On the other hand, when the output voltage V out is the input voltage V in is the reference voltage V ref When the voltage is less than 1 V, it can be a negative voltage.

[0041] In some embodiments, the PPM circuit 202 may further include an inverter 332 having an input terminal connected to an output terminal 330 of the comparator 328. The inverter 332 may invert the input signal. For example, the output voltage V out When V is a positive voltage, the PPM enablement signal enPPM generated by the inverter 332 at the output terminal 334 can be zero, i.e., the PPM enablement signal enPPM=0. On the other hand, when the output voltage V of the comparator 328 outWhen the potential V at node 322 is negative, the PPM enablement signal enPPM=1. ppm is the reference voltage V ref is greater (or higher) than (i.e., V ppm >V ref When the potential V at node 322 is V, the PPM enablement signal enPPM=0. ppm is the reference voltage V ref is smaller (or lower) than (i.e., V ppm <V ref , the PPM enablement signal enPPM=1.

[0042] In some embodiments, there may be an optional RC filter 344 connected between the node 322 and the second input terminal 326 of the comparator 328. The RC filter 344 can be used to filter out undesired signals within a certain frequency range.

[0043] As discussed above, the PPM pins on the same memory chip are electrically connected together, i.e., all PPM pins in the same PPM group are at the same potential V ppm Thus, each memory chip only needs to have one comparator 328 electrically connected to the PPM contact pad 204 at node 322. The PPM enablement signal enPPM also has a potential V ppm Shows.

[0044] 3, during operation, a first control signal 340 can be sent to the gate terminal 316 of the pFET 314 to switch the pFET 314 on or off. For example, when the first control signal 340 has a voltage less than the threshold voltage of the pFET 314, the pFET 314 can be switched on and a conductive path can be formed from the power supply 312 to the PPM resistor 318. The current flowing through the pull-up driver 314 and the PPM resistor 318 is referred to as a pull-up current I pull_upWhen the first control signal 340 has a voltage higher than the threshold voltage of the pFET 314, the pFET 314 can be switched off.

[0045] When a second control signal 342 is sent to the gate terminal 338 of nFET 336, nFET 336 may be switched on or off. For example, if the second control signal 342 has a voltage higher than the threshold voltage of nFET 336, nFET 336 may be switched on and a conductive path may be formed from node 322 to ground. If the second control signal 342 has a voltage less than the threshold voltage of nFET 336, nFET 336 may be switched off.

[0046] In some embodiments, the pull-down driver 336 can operate as a current controller. In this example, when the pull-down driver 336 is switched on, a current flows through the pull-down driver 336 from the node 322 to ground (pull-down current I pull_dn The magnitude of the pull-down current I pull_dn may depend on the voltage level of the second control signal 342 and the transconductance of the nFET 336. According to some embodiments of the present disclosure, the current profile I cc may correspond to the voltage level of the second control signal 342, thereby causing the pull-down current I pull_dn Therefore, the pull-down current I pull_dn is the current profile of the memory die, I cc It can function as a current mirror of the

[0047] In some embodiments, the pull-down current I pull_dn is the current profile I cc The pull-down current I pull_dn is the current profile Icc For example, if the memory die is operating at a current of 200 mA, the pull-down current I pull_dn can be 200 μA. Therefore, the memory operation and corresponding current are pull_dn Additionally, through die-to-die connections at the PPM contact pads, the peak power behavior across the entire memory chip can be coordinated between different memory dies.

[0048] FIG. 4 illustrates an example current profile I of a memory die (e.g., the NAND flash memory 100 of FIG. 2) according to some embodiments of the present disclosure. cc The current profile I cc is the peak current I cp and the base current I cb The peak current I cp corresponds to the current level when the memory die is performing peak power operation. cb corresponds to the average current level when the memory die is performing normal operation. cc is the base current I cb When the current rises to , the memory die reaches a breakpoint 450. Due to the increasing trend of the current, a PPM scheme can be implemented to control the total current consumed by the memory chip among multiple memory dies.

[0049] Referring again to FIG. 3, in some embodiments, the pull-down current I pull_dn has two current levels: high current level I H (or the first current level) and the low current level I L (or a second current level). pull_dn High current level I H is the peak current I for a particular memory die. cp The pull-down current I pull_dn Low current level IL is the base current I of a particular memory die. cb Corresponds to.

[0050] During operation, according to some embodiments of the present disclosure, only one pull-up driver 314 in a memory chip is switched on (i.e., enabled), while the remaining pull-up drivers 314 on different memory dies of the same memory chip can be switched off. Thus, on each memory chip, current flows only through one PPM resistor 318 from the power supply 312. That is, the PPM circuits 202 on the same memory chip share a shared pull-up driver 314 and a shared PPM resistor 318.

[0051] During operation, the pull-down drivers 336 can be switched on or off depending on the state of the memory die and can be independently controlled according to the PPM management scheme discussed below. For example, the NAND flash memory 100-1 (of FIG. 2) has the pull-down driver 336 of the PPM circuit 202-1 switched on, with a pull-down current I pull_dn is high current level I H When a conductive path is allowed to form through the pull-down driver 336 to ground, the peak current I cp The NAND flash memory 100-1 is prevented from performing any peak power operation when the pull-down driver 336 of the PPM circuit 202-1 is switched off, such that no current can flow through the pull-down driver 336 on the NAND flash memory 100-1.

[0052] The potential V of node 322 (or each PPM pin 204) ppm depends on the number of pull-down drivers 336 that are switched on and the pull-down current I pull_dn The pull-down driver 336 is switched on and the pull-down current I pull_dn is high current level I HPeak power operation can be performed on the memory die when the potential V ppm By monitoring the total current I total , thereby regulating the number of peak power operations performed in a memory chip having multiple memory dies.

[0053] FIG. 5 illustrates an equivalent PPM circuit 500 on a memory chip consisting of multiple memory dies according to some embodiments of the present disclosure. The equivalent PPM circuit 500 represents the PPM circuit 202 across different memory dies as shown in FIG. 2 and FIG. 3. In FIG. 5, the pull-up drivers 314 and pull-down drivers 336 that are switched off are omitted because only the pull-up drivers 314 and pull-down drivers 336 that are switched on can form a conductive path. As discussed above, the node 322 is electrically connected to the PPM pins 204 on the memory dies (see FIG. 3), and all the PPM pins 204 in the same memory chip are electrically connected across different memory dies (see FIG. 2). Thus, the node 322 is connected to the same potential V across different memory dies on the same memory chip. ppm , which is shown in FIG. 5 as a single node leading to PPM resistor 318.

[0054] In some embodiments, for peak power management across multiple memory dies on the same memory chip, only one pull-up driver 314 may be switched on. In some embodiments, peak power operation (i.e., peak current I cp A pull-down driver 336 in the PPM circuit corresponding to the memory die implementing the PPM control (using

[0055] In one example, there may be m pull-down drivers 336 switched on in a memory chip, where m can be any integer. These pull-down drivers 336 are from the PPM circuits 202 of the memory die, e.g., NAND flash memories 100-1, 100-2, ..., 100-m in FIG. 2. The pull-down drivers 336 are connected in parallel with each other. In this configuration, the pull-up current I flows through the pulled-up drivers 314 that are switched on. pull_up is the pull-down current I pull_dn It is the sum of

[0056]

number

[0057] where I pull_dn-1 , I pull_dn-2 , ..., I pull_dn-m is the pull-down current flowing through each of the pull-down drivers 336 that are switched on. The pull-down current I pull_dn Depending on the operations being performed on a particular memory die, the high level current I H and low-level current I L It can be set to either.

[0058] The pull-up driver 314 in FIG. 5 is a shared pull-up driver for the PPM circuit on the memory chip, so the pull-up current I pull_up may be the total current of the PPM circuits on the same memory chip. In some embodiments, the pull-up current I pull_up is the total current of the memory chip, I total The pull-up current I pull_up , and the total current of the memory chip I total is the pull-down current I pull_dn (For example, at high current levels I H and low current level I L ), and the current profile of the memory chip I cc (For example, the peak current Icp and the base current I cb ) can be scaled in the same way as for the total current I total is 1000mA, the pull-up current I pull_up can be 1000 μA.

[0059] The potential V of node 322 ppm teeth, V ppm =V dd -(R ppm I pull_up ) (2) where R ppm is the resistance of PPM resistor 318, and V dd is the voltage of the power supply 312.

[0060] As discussed above, the reference voltage V for comparator 328 (of FIG. 3) ref is the potential V ppm is the reference voltage V ref In this example, it can be selected that the PPM enablement signal enPPM can be set to enPPM=0 when the reference voltage V ref teeth, V ref =V dd -(R ppm I pull_up_max ) (3) where I pull_up_max is the maximum pull-up current through the pull-up driver 314 in the PPM circuit 202, and the maximum total current I total_max In some embodiments, the maximum pull-up current I pull_up_max , and the maximum total current I total_max is the pull-down current I pull_dn (For example, at high current levels I H and low current level I L ), and the current profile of the memory chip I cc (For example, the peak current I cpand the base current I cb ) follows the same scaling ratio as for the maximum total current I total_max is 1000mA, the maximum pull-up current I pull_up_max can be 1000 μA.

[0061] In this example, the pull-up current I pull_up is the maximum pull-up current I pull_up_max When the potential V is less than 1 V, the potential V ppm is the reference voltage V ref Therefore, the PPM enablement signal enPPM can be set to enPPM=0. Meanwhile, the pull-up current I pull_up is the maximum pull-up current I pull_up_max When the potential V ppm is the reference voltage V ref Also, the PPM enablement signal enPPM can be set to enPPM=1. Thus, by adjusting the pull-down driver 336 of the PPM circuit 202, the pull-down current I pull_dn The pull-up current I pull_up can be adjusted accordingly. The total current I total The pull-up current I pull_up is the maximum total current I allowed for the memory chips. total_max The maximum pull-up current I pull_up_max By comparing the reference voltage V with the reference voltage V, the PPM enablement signal enPPM can be set to 0 or 1. In other words, ref is the maximum total current I allowed for the memory chips total_max The PPM enablement signal enPPM can also be used to indicate whether there is still a current or power budget to perform additional peak power operations. For example, when the PPM enablement signal enPPM=0, the maximum pull-up current Ipull_up_max , and therefore the maximum total current I total_max It is shown that the memory chip 25 does not reach the peak current I cp , i.e., has enough power (or current) to supply at least one additional memory die to perform peak power operation. On the other hand, when the PPM enablement signal enPPM=1, the maximum pull-up current I pull_up_max , which results in a maximum total current I total_max It is shown that the memory chip 25 has reached its power (or current) limit and requires additional peak current I cp cannot supply.

[0062] 6 illustrates a peak power check routine 600 associated with the peak power management system 200 of FIG. 2 and the PPM circuit 202 of FIG. 3 in accordance with some embodiments of the present disclosure. ref and determining the maximum total current I that the NAND storage system 10 will allow to the memory chips 25. total_max 2-5 is used to generate a PPM enablement signal enPPM to indicate whether the power supply is operating at a current level below 100 V. It should be understood that the peak power check (PPC) routine 600 is not exhaustive and that other operational steps may be performed before, after, or between any of the illustrated operational steps. In some embodiments, some operational steps of the PPC routine 600 may be omitted or other operational steps may be included, which will not be described here for simplicity. In some embodiments, the operational steps of the PPC routine 600 may be performed in a different order and / or may be changed.

[0063] The PPC routine 600 provides an exemplary method of managing peak power usage for a memory chip with one or more memory dies, each of which includes at least one PPM circuit. The example below is shown for a memory chip, such as memory chip 25 of FIG. 2, where each memory die includes a PPM circuit 202 for checking and adjusting the peak power operation performed by those memory dies. However, the method can also be extended to memory chips where each memory die includes more than one PPM circuit.

[0064] The PPC routine 600 determines whether the total power (or current) consumed by the memory chips is adjusted to a predetermined value, e.g., a maximum total current I total_max This can be done before the memory die begins to perform peak power operations so that the power consumption can be controlled lower.

[0065] The PPC routine 600 begins at operation step S605 when a NAND storage system (e.g., NAND storage system 10 of FIG. 1) determines that one of the memory dies (e.g., NAND flash memory 100-1) on the memory chip 25 has reached a breakpoint (e.g., breakpoint 450 shown in FIG. 4). An increase in current consumption on the memory die compared to the current level prior to breakpoint 450 indicates that the memory die may subsequently undergo peak power operation.

[0066] Before the breakpoint 450, the PPM circuit 202-1 on the NAND flash memory 100-1 may be in a reset state. In the reset state, the pull-down driver 336-1 is switched off. In the operation step S605, one of the pull-up drivers 314 of the PPPM circuit 202 may be switched on as a shared pull-up driver among multiple memory dies on the memory chip.

[0067] In operation step S610, the pull-down driver 336-1 on the NAND flash memory 100-1 can be switched on.

[0068] In operation step S615, a pull-down current I flows through the pull-down driver 336-1 on the NAND flash memory 100-1. pull_dn-1 At high current level I H It can be set to a high current level I H is the peak current I required to perform a peak power operation on the NAND flash memory 100-1. cp Corresponds to.

[0069] In operation step S620, the PPM enablement signal enPPM is verified. If the PPM enablement signal enPPM=0, the pull-up current I pull_up is the maximum pull-up current I pull_up_max Therefore, the NAND flash memory 100-1 can be supplied with a maximum total current I total_max The total current of the memory chips exceeds I total without causing the peak current I cp It is shown that peak power operation using

[0070] In operation step S625, the NAND flash memory 100-1 generates a peak current I cp In some embodiments, the NAND flash memory 100-1 implements a peak power operation that operates at a peak current I cp Any operation that operates at a current level below may also be performed.

[0071] In operation step S620, if the PPM enablement signal enPPM is not zero (e.g., enPPM=1), the PPC routine 600 proceeds to operation step S630, where the pull-down driver 336-1 on the NAND flash memory 100-1 may be switched off. In operation step S635, the PPC routine 600 is paused for a delay period t dl In some embodiments, the delay period t dlis random. In some embodiments, the delay period t dl may be any suitable period within the range between 0.1 μs and 100 μs. In some embodiments, the delay period t dl may be different for each memory die. dl Thereafter, the PPC routine 600 returns via loop L1 to action step S620 where the PPM enablement signal enPPM is checked again.

[0072] Delay period t dl is introduced because multiple memory dies enter the PPC routine 600 at the same time, causing multiple pull-down drivers to be switched on at the same time, resulting in a high current level I H If there is no available current / power budget to simultaneously perform the peak power operation of these memory dies, the PPM enablement signal enPPM is asserted to the multiple memory dies in operation step S620. Then, in operation step S630, the corresponding pull-down drivers on the multiple memory dies can be switched off simultaneously. The delay period t dl By introducing the maximum total current I , the multiple memory dies can return to the operation step S620 one by one, i.e., the requests for peak power operation from the multiple memory dies can be asynchronous. Thus, the multiple memory dies can be configured to operate at the maximum total current I , which is allowed for the memory chips. total_max Peak power operation can be implemented in sequence without exceeding

[0073] In operation step S640, after completing the peak power operation, the pull-down current I flows through the pull-down driver 336-1. pull_dn-1 at low current level I L Therefore, the NAND flash memory 100-1 can be set to a peak current I cp It is possible to continue operation with a current less than 100 mA.

[0074] In some embodiments, the PPC routine 600 may return again to action step S605 via loop L2, for example, when another breakpoint is detected after completion of the current peak power operation.

[0075] In operation step S645, for example, the current level of the NAND flash memory 100-1 is the base current I cb When the voltage drops below 1 V, the pull-down driver 336-1 of the PPM circuit 202-1 on the NAND flash memory 100-1 may be disabled (e.g., switched off). The PPC routine 600 may be terminated and restarted if the NAND storage system 10 determines that one of the memory dies on the memory chip has entered one of the breakpoints.

[0076] The pull-down current I of a particular memory die pull_dn is high current level I H When set to , a current / power budget can be temporarily set aside for this particular memory die. Any other memory dies on the same memory chip that run the PPC routine 600 will consume the total current I total is the maximum total current I total_max As long as it is not less than or until a current / power budget is available on the memory chip (which can be verified in operation step S620), it can be queued in a loop consisting of operation steps S620, S630, and S635.

[0077] Memory die current profile I cc The upper two current levels (e.g., peak current I cp and the base current I cb ), and the pull-down current I of the pull-down driver 336 in the PPM circuit 202 on the memory die. pull_dn Adjust the current accordingly (e.g. by switching on / off the high current level I H and low current level I L, the potential V of the PPM contact pads 204 across the multiple memory dies on the memory chip. ppm can be adjusted because the PPM contact pads 204 on different memory dies can be electrically connected through die-to-die connections 205 and are at the same potential V ppm This is because the potential V ppm is the maximum total current I allowed for the memory chips. total_max A predetermined reference voltage V ref By comparing the total current I total can be controlled.

[0078] However, the PPM circuit and PPM scheme are not limited to the examples shown in Figures 3-6. Variations of the PPM circuit 202 and PPC routine 600 can achieve similar peak power management for memory chips with multiple memory dies.

[0079] 7 illustrates another exemplary PPM circuit 202′ on a NAND flash memory 100, according to some embodiments of the present disclosure. The PPM circuit 202′ is similar to the PPM circuit 202. The main difference is that a PPM resistor 318 can be connected between node 322 and a pull-down driver 336. In this example, during operation, only one pull-down driver 336 is switched on among multiple memory dies on the same memory chip, while the pull-up driver 314 provides a current profile I cc Here, the pull-up current I pull_up is the peak current I cp and the base current I cb Two current levels, e.g., high current level I H and low current level I LIn this example, during operation, when there may be m pull-up drivers 314 switched on within the memory chip, the pull-down current I pull_dn is the pull-up current I pull_up It is the sum of

[0080]

number

[0081] The potential V of the node 322 can be expressed as ppm teeth, V ppm =R ppm I pull_dn (5) and the reference voltage V ref teeth, V ref =R ppm I pull_dn_max (6) where I pull_dn_max is the maximum pull-down current through the pull-down driver 336, and the maximum total current I allowed for the memory chip total_max Therefore, the pull-down current I pull_dn is the maximum pull-down current I pull_dn_max When the potential V ppm is the reference voltage V ref is higher than the output voltage V out In the PPM circuit 202′, the output voltage V out can be sent directly to the PPM enablement signal enPPM without an inverter. Therefore, I pull_dn >I pull_dn_max When I pull_dn pull_dn_max If so, then enPPM=0. In this example, the PPC routine 600 can be modified by changing the pull-down driver / pull-down current to a pull-up driver / pull-up current.​

[0082] The devices and configurations used in the example PPM circuit 202 of FIG. 3 and the PPM circuit 202′ of FIG. 7 are merely for illustrative purposes and to simply illustrate the functionality of the PPM circuits and PPM schemes. In some embodiments, the pull-down driver 336 of FIG. 3 is configured with a pull-down current I pull_dn can be replaced by a suitable current source to set the current level.

[0083] The dynamic peak power management of the memory chip discussed above is based on the current profile I cc For example, the current profile I cc Based on this, the PPM scheme can be divided into multiple stages, where each stage P i is the peak current I i (i=1, 2, ..., 6). In this example, when the pull-down driver 336 is switched on, the pull-down current I pull_dn At each stage P i Peak current I i The breakpoint 450 is set at the beginning of phase P1 and at the peak current I i The previous stage P i-1 Peak current I i-1 If it is greater than P i For example, breakpoints 450 can be inserted at the beginning of stages P1, P2, and P4 of FIG.

[0084] Using something similar to the PPC routine 600 of FIG. 6, operational step S605 may be initiated when the memory die reaches a breakpoint 450, e.g., the beginning of phase P2. In operational step S610, the pull-down driver 336 on the memory die may be enabled, causing a pull-down current I to flow through the pull-down driver 336. pull_dnmay be set to a current level reflecting the peak current I2 in stage P2. In operational step S620, the PPM enablement signal enPPM is checked. If the PPM enablement signal enPPM=0, a peak power operation corresponding to the peak current I2 may be performed by the memory die. If not, the pull-down driver 336 on the memory die may be switched off, and the memory die may wait for a delay period in operational step S635 before checking the PPM enablement signal enPPM again in operational step S620.

[0085] Peak current I i The previous stage P i-1 Peak current I i-1 If it is smaller than, step P i For example, in the example shown in Figure 8, the current profile I cc No breakpoints are inserted at the beginning of steps P3, P5, and P6 in the

[0086] When the peak power operation is completed in operation step S640, the pull-down current I pull_dn can be adjusted to a lower level proportional to the next peak current of the memory die. For example, when the peak power operation for phase P2 is completed, the pull-down current I pull_dn can be adjusted to be proportional to the peak current I3 and continues to operate in phase P3.

[0087] At the beginning of phase P4, another breakpoint 450 is detected. The PPC routine 600 returns to action step S605 where the PPM enablement signal enPPM is again checked at action step S620.

[0088] In summary, the present disclosure provides a peak power management (PPM) system for a memory chip with multiple memory dies. The PPM system includes a PPM circuit on each of the multiple memory dies. Each PPM circuit includes a pull-up driver electrically connected to a power source and a PPM resistor, a pull-down driver electrically connected to the PPM resistor, and a PPM contact pad connected to the PPM resistor. The PPM contact pads of the multiple memory dies are electrically connected to each other. The PPM system is also configured to manage peak power operation based on a potential of the PPM contact pad.

[0089] The present disclosure also provides a method of peak power management (PPM) for a memory chip with multiple memory dies, each of the multiple memory dies including a PPM circuit having PPM contact pads. The PPM contact pads of the multiple memory dies are electrically connected to each other. The PPM method includes the steps of: switching on a pull-down driver of a PPM circuit on a selected memory die of the memory chip, verifying a PPM enablement signal regulated by a pull-down current flowing through the pull-down driver, and implementing a peak power operation on the selected memory die when the PPM enablement signal indicates that a total current of the memory chip is less than a maximum total current allowed for the memory chip.

[0090] The above description of specific embodiments sufficiently reveals the general nature of the present disclosure so that others can easily modify and / or adapt such specific embodiments to various applications by applying knowledge within the skill of the art without undue experimentation and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments based on the present disclosure and guidance presented herein. It should be understood that the expressions or terms in this specification are intended to be descriptive rather than limiting, and therefore the terms or terms in this specification should be interpreted by those skilled in the art in light of the present disclosure and guidance.

[0091] The embodiments of the present disclosure have been described above using functional building blocks that illustrate implementations of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for convenience of description. Alternative boundaries can be defined so long as the specified functions and relationships thereof are appropriately implemented.

[0092] The Summary and Abstract sections may describe one or more exemplary embodiments of the disclosure contemplated by the inventor(s), but may not describe all exemplary embodiments, and thus, these sections are not intended to be in any way limiting of the disclosure and the appended claims.

[0093] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0094] 10 NAND storage systems, solid-state drives (SSDs) 15 Host Computer 20 Host Controller 25 Semiconductor memory chips 25-1 Memory chip 25-2 Memory chip 25-3 Memory chip 25-n memory chip 30 memory channels 30-1 Memory Channel 30-2 Memory Channel 30-3 Memory Channel 30-n memory channels 40 Row Decoder 50 page buffer 60 Column Decoder 70 Peripheral circuits 80 Sense Amplifier 100 NAND Flash Memory 100-1 Memory die, NAND flash memory 100-2 Memory die, NAND flash memory 100-3 Memory die, NAND flash memory 100-n memory die, NAND flash memory 101 Memory Plane 103 Memory Blocks 200 Peak Power Management (PPM) System 202 Peak Power Management (PPM) Circuit 202-1 PPM circuit 202-2 PPM circuit 202-3 PPM circuit 202-n PPM circuit 202' PPM circuit 204 PPM contact pads, PPM pins 204-1 PPM pin 204-2 PPM pin 204-3 PPM pin 204-n PPM pin 205 Die to die connections 205-1 Die to die connections 205-2 Die to die connections 312 Power supply 314 Pull-up driver, pFET 316 Gate terminal 318 ppm resistor 322 nodes 324 1st input terminal 326 Second input terminal 328 Comparator 330 Output terminal 332 Inverter 334 Output terminal 336 Pull-down driver, nFET 336-1 Pull-down driver 338 Gate terminal 340 First control signal 342 Second Control Signal 450 Breakpoint 500 equivalent PPM circuit 600 Peak Power Check (PPC) Routine enPPM PPM enablement signal I2 Peak Current I3 Peak Current I cb Base Current I cc Current Profile I cp Peak Current I H High current level, high level current I i Peak Current I i-1 Peak Current I L Low current level, low level current I pull_dn Pull-down Current I pull_dn-1 Pull-down Current I pull_dn_max Maximum Pull-Down Current I pull_up Pull-up Current I pull_up_max Maximum Pull-Up Current I total Total Current Itotal_max Maximum Total Current L1 Loop L2 Loop P1 stage P2 stage P3 stage P4 stage P5 stage P6 stage P i step P i-1 step R ppm Resistance Value t dl Delay Period V dd Voltage V in Input voltage V out Output Voltage V ppm potential V ref Reference Voltage

Claims

1. A system having a plurality of memory dies, a PPM circuit on each of the plurality of memory dies, the PPM circuit comprising a first pull driver, a second pull driver, and a PPM contact pad connected between the first pull driver and the second pull driver; the PPM contact pads of the plurality of memory dies are electrically connected to each other; the PPM circuits of the plurality of memory dies are configured to manage peak power operation according to a first pull current flowing through a particular first pull driver of a particular PPM circuit, the first pull current being a sum of second pull currents flowing through second pull drivers of the PPM circuits, each of the second pull currents being proportional to a current level of a corresponding memory die.

2. The method of claim 1, wherein the first pull driver is a pull-up driver electrically connected between a power source and the PPM contact pad; 2. The system of claim 1, wherein the second pull driver is a pull-down driver electrically connected between ground and the PPM contact pad, and the PPM circuit further comprises a PPM resistor electrically connected between the power supply and the PPM contact pad, the PPM contact pad and the PPM resistor in series with the pull-up driver.

3. The method of claim 2, wherein the first pull driver is a pull-down driver electrically connected between ground and the PPM contact pad; 2. The system of claim 1, wherein the second pull driver is a pull-up driver electrically connected between a power source and the PPM contact pad, and the PPM circuit further comprises a PPM resistor electrically connected between the ground and the PPM contact pad, the PPM resistor in series with the pull-down driver.

4. The system of claim 1, wherein the PPM circuit further comprises a comparator having a first input terminal electrically connected to the PPM contact pads of the multiple memory dies and a second input terminal electrically connected to a reference voltage.

5. The system of claim 4, wherein the reference voltage is based on a maximum total current allowed for the multiple memory dies.

6. The system of claim 1, wherein each of the plurality of memory dies has a current profile, the current level of the current profile of the corresponding memory die has a peak current for peak power operation, and the second pull current of the corresponding memory die is proportional to the peak current.

7. The system of claim 6, wherein the current level of the current profile of the corresponding memory die has a base current lower than the peak current, and the second pull current of the corresponding memory die is proportional to the base current.

8. The system described in claim 6, wherein the second pull driver is a metal-oxide semiconductor field effect transistor (MOSFET) and the second pull current is determined according to a gate voltage applied to a gate terminal of the second pull driver.

9. A method of peak power management (PPM) for a system having a plurality of memory dies, each of the plurality of memory dies comprising a PPM circuit having a PPM contact pad, the PPM contact pads of the plurality of memory dies being electrically connected, the method comprising: adjusting a second pull current flowing through a second pull driver of a PPM circuit on the plurality of memory dies; managing peak power operation of the plurality of memory dies according to first pull currents flowing through a particular first pull driver of a particular PPM circuit, the first pull current being a sum of the second pull currents, each of the second pull currents being proportional to a current level of a corresponding memory die.

10. The method of claim 9, wherein the step of adjusting the second pull current includes a step of adjusting a second pull current flowing through a second pull driver of a PPM circuit on the memory die in accordance with the current level of a current profile of the memory die.

11. The method of claim 9, wherein the current level has a base current of the corresponding memory die, and adjusting the second pull current includes setting the second pull current at a low current level proportional to the base current.

12. The method of claim 9, wherein the current level has a peak current of peak power operation on the corresponding memory die, and adjusting the second pull current includes setting the second pull current at a high current level proportional to the peak current.

13. The method of claim 12, wherein the step of managing the peak power operation includes a step of enabling the memory die to perform the peak power operation when the first pull current is less than or equal to a maximum first pull current, the maximum first pull current being proportional to a maximum current allowed for the plurality of memory dies.

14. The method of claim 13, further comprising switching off the second pull driver of the PPM circuit on the memory die when the first pull current is greater than the maximum first pull current.

15. The method of claim 14, further comprising a step of waiting for a delay period after switching off the second pull driver to check whether the memory die is allowed to perform the peak power operation.

16. The method of claim 13, further comprising the step of generating a PPM enablement signal based on a potential of the PPM contact pad, the potential of the PPM contact pad being determined according to the first pull current.

17. The method of claim 16, further comprising: dividing the current profile of the memory die into two or more stages, each of the two or more stages having a peak current; repeating the steps of adjusting the second pull current and managing the peak power operation for each of the two or more stages; The method of claim 10, further comprising:

18. The method of claim 17, wherein if a peak current of a current stage is greater than a peak current of a previous stage, a breakpoint is inserted at the beginning of the current stage, the method comprising:

20. The method of claim 17, further comprising: switching on the second pull driver of the PPM circuit on the memory die when the breakpoint is detected.

19. The method of claim 9, wherein adjusting the second pull current flowing through the second pull driver includes adjusting a pull-down current flowing through a pull-down driver of the PPM circuits on the multiple memory dies, each of the pull-down drivers being electrically connected between ground and a respective PPM contact pad of a respective PPM circuit on a respective memory die, and each of the first pull drivers being a pull-up driver electrically connected between a power supply and the respective PPM contact pad.

20. The method of claim 9, wherein adjusting the second pull current flowing through the second pull driver includes adjusting a pull-up current flowing through a pull-up driver of the PPM circuits on the multiple memory dies, each of the pull-up drivers being electrically connected between a power supply and a respective PPM contact pad of each PPM circuit on each memory die, and each of the first pull drivers being a pull-down driver electrically connected between ground and the respective PPM contact pad.

21. A storage system comprising: A memory controller; a plurality of memory dies coupled to the memory controller, each of the plurality of memory dies comprising a PPM circuit, each PPM circuit comprising: A first pull driver; A second pull driver; a PPM contact pad connected between the first pull driver and the second pull driver; PPM contact pads of PPM circuits on the plurality of memory dies are electrically connected to each other; 11. A storage system comprising: a first pull current generating unit configured to generate a first pull current for each of the plurality of memory dies; a first pull current generating unit configured to generate a first pull current for each of the plurality of memory dies; a second pull current generating unit configured to generate a second pull current for each of the plurality of memory dies;

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