Reconfigurable circuit device

Abstract

A reconfigurable circuit device (10) is provided with a first circuit (20) and a second circuit (30) that allow for partial reconfiguration of an arithmetic circuit. The first circuit (20) comprises: a plurality of first partial circuits (21) arrayed spaced apart along the Y-direction; and first wiring (22) for connecting the plurality of first partial circuits (21) so that adjacent first partial circuits (21) are mutually connected. The second circuit (30) comprises a plurality of second partial circuits (31) arrayed spaced apart along the Y-direction, and second wiring (32) for connecting the plurality of second partial circuits (31) so that adjacent second partial circuits (31) are mutually connected. The plurality of first partial circuits (21) and the plurality of second partial circuits (31) are arrayed alternately along the Y-direction. The first wiring (22) directly connects adjacent first partial circuits (21) together. The second wiring (32) directly connects adjacent second partial circuits (31) together. Due to this configuration, it is possible to load bitstreams of the same format with less processing load.

Description

[Technical field]

[0001] The present invention relates to a reconfigurable circuit device such as an FPGA (Field Programmable Gate Array). [Background technology]

[0002] Circuit devices capable of reconfiguring arithmetic circuits, such as FPGAs, are sometimes used in data centers as accelerators to improve calculation speed. In these data centers, virtualization is required to switch processing contents. To achieve such virtualization, partial reconfiguration, which reconfigures only a partial area of ​​a circuit, as disclosed in Non-Patent Document 1, is sometimes used in FPGAs. This partial reconfiguration is performed by loading a bitstream file into a partial area. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Yohei Hori and 2 others, “The Present and Future of Partial Reconfiguration of FPGAs”, Design Wave Magazine, September 2007, p.129-130 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional partial reconfiguration, even when bitstreams using the same number of switch cells and logic cells, i.e., bitstreams of the same format, are to be loaded, logic synthesis and placement and wiring, especially placement and wiring, are required individually for each bitstream. This is because, in conventional partial reconfiguration, the position where the bitstream is loaded changes depending on the position of the written (configured) arithmetic circuit, etc.

[0005] An object of the present invention is to load bitstreams of the same format with a small processing burden. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, a reconfigurable circuit device according to a first aspect of the present invention comprises a first circuit and a second circuit capable of reconfiguring an arithmetic circuit, the first circuit includes a plurality of first partial circuits arranged at intervals along a predetermined direction, and a first wiring connecting adjacent first partial circuits of the plurality of first partial circuits to each other, the second circuit includes a plurality of second partial circuits arranged at intervals along the predetermined direction, and a second wiring connecting adjacent second partial circuits of the plurality of second partial circuits to each other, the plurality of first partial circuits and the plurality of second partial circuits are arranged alternately along the predetermined direction, each pair of the plurality of first partial circuits and each pair of the adjacent second partial circuits along the predetermined direction of each of the plurality of first partial circuits have a plurality of switch cells and a plurality of logic cells arranged in the same manner for each pair, the first wiring is configured to directly connect the adjacent first partial circuits to each other, and the second wiring is configured to directly connect the adjacent second partial circuits to each other.

[0007] A reconfigurable circuit device according to a second aspect of the present invention includes first to Nth circuits (N is a natural number equal to or greater than 2) that reconfigure an arithmetic circuit, and the nth circuit among the first to Nth circuits includes a plurality of nth partial circuits arranged at intervals along a predetermined direction and an nth wiring that connects adjacent nth partial circuits of the plurality of nth partial circuits to each other (n is a value from 1 to N), a plurality of mth partial circuits and an m+1th partial circuit among the plurality of nth partial circuits are arranged alternately along the predetermined direction (m is a value from 1 to N-1), the plurality of mth partial circuits and the plurality of m+1th partial circuits are arranged alternately along the predetermined direction, each pair of the plurality of mth partial circuits and each of the m+1th partial circuits adjacent to each other along the predetermined direction of the plurality of mth partial circuits has a plurality of switch cells and a plurality of logic cells in the same arrangement for each pair, and the nth wiring is configured to directly connect the adjacent nth partial circuits to each other. Effect of the Invention

[0008] According to the present invention, bitstreams of the same format can be loaded with less processing load. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit configuration diagram of a reconfigurable circuit device according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a configuration diagram focusing on the first circuit in FIG. [Diagram 3] FIG. 3 is a configuration diagram focusing on the second circuit in FIG. [Figure 4] FIG. 4 is a circuit configuration diagram of a reconfigurable circuit device according to another example of the first embodiment of the present invention. [Diagram 5] FIG. 5 is a circuit configuration diagram of a reconfigurable circuit device according to another example of the first embodiment of the present invention. [Figure 6] FIG. 6 is a circuit configuration diagram of a reconfigurable circuit device according to another example of the first embodiment of the present invention. [Figure 7] FIG. 7 is a circuit configuration diagram of a reconfigurable circuit device according to another example of the first embodiment of the present invention. [Figure 8] FIG. 8 is an explanatory diagram illustrating a reconfigurable circuit device according to the second embodiment. [Figure 9] FIG. 9 is a configuration diagram of a reconfigurable circuit device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, a reconfigurable circuit device according to an embodiment of the present invention will be described with reference to the drawings, in which the same or corresponding elements are designated by the same reference numerals.

[0011] (Embodiment 1) As shown in Fig. 1, a reconfigurable circuit device 10 according to this embodiment includes a circuit 10A that combines a plurality of switch cells 11 and a plurality of logic cells 12. The circuit device 10 is configured using an FPGA (Field Programmable Gate Array). Note that Fig. 1 illustrates only a portion of the circuit 10A. Also, Fig. 1 omits I / O (Input / Output) and the like. The same is true for Fig. 2, which will be referred to later.

[0012] If the switch cells 11 and the logic cells 12 are not distinguished from each other and are treated as one circuit element, the circuit elements are arranged in a matrix in the X and Y directions as a whole. The switch cells 11 and the logic cells 12 are arranged periodically in the X and Y directions. Here, unit circuits U, each of which is a set of three switch cells 11 and one logic cell 12, are arranged in a matrix in the X and Y directions.

[0013] The three switch cells 11 included in each unit circuit U are also referred to as switch cells 11A, 11B, or 11C depending on their relative positions with respect to one logic cell 12. Specifically, the switch cell 11 adjacent to the switch cell 11 in the opposite direction to the X direction (the left side of the paper) is also referred to as switch cell 11A. The switch cell 11 adjacent to the switch cell 11 in the opposite direction to the Y direction (the upper side of the paper) is also referred to as switch cell 11B. The switch cell 11 connected to switch cell 11A and switch cell 11B is also referred to as switch cell 11C. The number of switch cells and logic cells constituting the unit circuit U and their relative positions are arbitrary.

[0014] The logic cells 12 are logic circuits configured to include a look-up table (LUT) or a calculation element. By loading a bit stream into the reconfigurable circuit device 10, the contents of the LUT of the logic cells 12 and the states of the switch cells 11 are updated, and an arithmetic circuit is configured in the circuit 10A. The configuration of the arithmetic circuit can be performed multiple times, that is, the circuit device 10 is reconfigurable.

[0015] In the reconfigurable circuit 10A, a first circuit 20 and a second circuit 30 are configured by a combination of a plurality of switch cells 11 and a plurality of logic cells 12, more specifically, a plurality of unit circuits U. The first circuit 20 and the second circuit 30 are configured such that the arithmetic circuit is reconfigurable (writable).

[0016] As shown in FIG. 1 and FIG. 2, the first circuit 20 includes a plurality of first partial circuits 21-1 to 21-p (p is an integer of 2 or more) arranged at intervals along the Y direction. In the following description, the first partial circuits 21-1 to 21-p are also collectively referred to as the first partial circuits 21. The first circuit 20 further includes first wiring 22 (see FIG. 2 in particular) including wiring 22-1 to 22q (where q=p-1) that connects the plurality of first partial circuits 21-1 to 21-p with adjacent first partial circuits 21. In FIG. 2, second partial circuits 31-1 to 31-p of the second circuit 30, which will be described later, are drawn with dotted lines for the sake of coordination of the first circuit 20, and second wiring 32, which will be described later, is omitted.

[0017] 1 and 3, the second circuit 30 includes a plurality of second partial circuits 31-1 to 31-p arranged at intervals along the Y direction. In the following description, the second partial circuits 31-1 to 31-p are also collectively referred to as the second partial circuits 31. The second circuit 30 further includes second wiring 32 (see FIG. 3 in particular) including wiring 32-1 to 32-q that connects the plurality of second partial circuits 31-1 to 31-p with adjacent second partial circuits 31. In FIG. 3, the first partial circuit 21 of the first circuit 20 is drawn with dotted lines and the first wiring 22 is omitted for the sake of coordination of the second circuit 30.

[0018] As shown in FIG. 1 to FIG. 3, the first partial circuits 21 and the second partial circuits 31 are arranged alternately along the Y direction. Each of the first partial circuits 21 and the second partial circuits 31 is composed of a plurality of unit circuits U arranged in a row in the X direction perpendicular to the Y direction. Therefore, each pair of the first partial circuits 21 and the second partial circuits 31 adjacent to each of the first partial circuits 21 along the Y direction (for example, the second partial circuit 31-1 for the first partial circuit 21-1) has a plurality of switch cells 11 and a plurality of logic cells 12 arranged in the same arrangement for each pair. Here, in particular, each of the first partial circuits 21 and the second partial circuits 31 has a plurality of switch cells 11 and a plurality of logic cells 12 arranged in the same arrangement. In other words, the first partial circuits 21 and the second partial circuits 31 have the same circuit configuration. The first partial circuits 21 and the second partial circuits 31 may be composed of unit circuits U arranged in a plurality of rows in the X direction.

[0019] 2, the first wiring 22 directly connects adjacent first partial circuits 21 among the multiple first partial circuits 21 arranged in the Y direction without passing through the second partial circuit 31. For example, the wiring 22-1 of the first wiring 22 directly connects the first partial circuit 21-1 and the first partial circuit 21-2 through the second partial circuit 31-1. The wiring 22-1 of the first wiring 22 includes a line connecting the switch cell 11A of the unit circuit U of the first partial circuit 21 to the switch cell 11B of the unit circuit U of the adjacent first partial circuit 21, and a line connecting the logic cell 12 of the unit circuit U of the first partial circuit 21 to the switch cell 11C of the unit circuit U of the adjacent first partial circuit 21.

[0020] 3, the second wiring 32 directly connects adjacent second partial circuits 31 among the multiple second partial circuits 31 arranged in the Y direction without passing through the first partial circuit 21. For example, the wiring 32-1 of the second wiring 32 directly connects the second partial circuit 31-1 and the second partial circuit 31-2 by passing through the first partial circuit 21-1.

[0021] As described above, in the reconfigurable circuit device 10 according to the present embodiment, each pair of the multiple first partial circuits 21 and the second partial circuits 31 adjacent to each of the multiple first partial circuits 21 along the Y direction has the same array of multiple switch cells 11 and multiple logic cells 12 for each pair. The first wiring 22 connecting the multiple first partial circuits 21 to each other passes through adjacent first partial circuits 21 of the multiple first partial circuits 21 directly, without passing through the second partial circuits 31 between them. Furthermore, the second wiring 32 connecting the multiple second partial circuits 31 to each other passes through adjacent second partial circuits 31 of the multiple second partial circuits 31 directly, without passing through the first partial circuits 21 between them. With this configuration, when the first circuit 20 is shifted in the Y direction, the first circuit 20 becomes substantially the same as the second circuit 30. Strictly speaking, the two circuits are different due to the presence of the first wiring 22 and the second wiring 32, but this can be ignored since it can be designed with an error that does not impede logic synthesis and placement and wiring.

[0022] With the above-mentioned configuration, for example, a bitstream that has been logically synthesized and placed and wired for the first circuit 20 can also be loaded into the second circuit 30. Furthermore, a bitstream that has only changed the contents of the bitstream for the first circuit 20 (the state of the switch cells 11 and the contents of the logic cells 12) can also be loaded into the second circuit 30. Therefore, when loading bitstreams of the same format, such as the number of switch cells 11 and the number of logic cells 12 used being the same and the states of the switch cells 11 and the contents of the logic cells 12 being the same or different, into the first circuit 20 and the second circuit 30, for example, by performing logical synthesis and placement and wiring (compilation) once for the first circuit 20, the bitstream can be diverted for use in the second circuit 30 (recompilation is not required). For this reason, in this embodiment, the bitstreams for the first circuit 20 and the second circuit 30 can be made compatible with each other, and the processing load of placement and wiring before loading when loading a bitstream of the same format can be reduced. Furthermore, by making the bitstreams for the first circuit 20 and the second circuit 30 compatible with each other, virtualization of the circuit device 10 can be realized in "bitstream units (almost the same as task units)".

[0023] Furthermore, in the above configuration, when arithmetic circuits using the same format of bit stream are loaded into the first circuit 20 and the second circuit 30, the delay times due to the wiring of each arithmetic circuit can be made closer to each other, thereby enabling synchronized parallel processing in each arithmetic circuit.

[0024] Furthermore, the circuit device 10 of this embodiment is advantageous for dynamic partial reconfiguration. In a method using dynamic partial reconfiguration, it is necessary to reconfigure (rewrite) a certain arithmetic circuit (function) while operating other arithmetic circuits (functions). In a conventional reconfigurable circuit device, since the circuits are not separated, when performing dynamic partial reconfiguration, it is necessary to write a new arithmetic circuit while avoiding other arithmetic circuits that are in operation, which places a large burden on the hardware. In the circuit device according to this embodiment, since the area in which the arithmetic circuits are reconfigured is separated into the first circuit 20 and the second circuit 30, processing to avoid other arithmetic circuits that are in operation is not required, and the burden is reduced accordingly.

[0025] In addition, each pair (the pair of the first partial circuit 21-1 and the second partial circuit 31-1, the pair of the first partial circuit 21-2 and the second partial circuit 31-2, etc.) of each of the multiple first partial circuits 21 and the adjacent second partial circuit 31 along the Y direction of each of the multiple first partial circuits 21 may have the same arrangement of multiple switch cells 11 and multiple logic cells 12 for each pair. For example, the first partial circuit 21-1 and the second partial circuit 31-1 may have the same arrangement of multiple switch cells 11 and multiple logic cells 12. The first partial circuit 21-2 and the second partial circuit 31-2 may have the same arrangement of multiple switch cells 11 and multiple logic cells 12 (the same applies to the first partial circuit 21-3 and subsequent circuits). Therefore, all of the first partial circuits 21 and all of the second partial circuits 31 do not have to have the same arrangement of the switch cells 11 and the logic cells 12. For example, the first partial circuit 21-1 may have the same arrangement of the switch cells 11 and the logic cells 12 as the adjacent second partial circuit 31-1 in the Y direction, but may have a different arrangement of the switch cells 11 and the logic cells 12 from the second partial circuit 31-2 that is not adjacent. However, it is easier to design the circuit if all of the first partial circuits 21 and all of the second partial circuits 31 are the same.

[0026] If the first circuit and the second circuit are expressed as a first layer and a second layer as execution units of a task, the reconfigurable circuit device may be provided with reconfigurable circuits from the first layer to the Nth layer (N is a natural number of 2 or more). For this reason, the circuit device 10 may include partially reconfigurable first to Nth circuits. The nth circuit among the first to Nth circuits may include a plurality of nth partial circuits arranged at intervals along a predetermined direction, and an nth wiring that connects the plurality of nth partial circuits with adjacent nth partial circuits (n is 1 to N, respectively). A plurality of mth partial circuits and an m+1th partial circuit among the plurality of nth partial circuits may be arranged alternately along a predetermined direction (m is 1 to N-1, respectively). A plurality of mth partial circuits and a plurality of m+1th partial circuits may be arranged alternately along a predetermined direction. Each pair of a plurality of m-th partial circuits and a respective one of the m-th partial circuits adjacent to the m+1-th partial circuits along the predetermined direction may have the same arrangement of switch cells and logic cells for each pair. Furthermore, the n-th wiring may directly connect adjacent n-th partial circuits among the plurality of n-th partial circuits.

[0027] With the above-described configuration, it is possible to manufacture a circuit device according to the required number of layers.

[0028] As an example of the above configuration, an example when N=4 will be described with reference to Fig. 4. As shown in Fig. 4, in the circuit 10B of the reconfigurable circuit device 10 when N=4, the first plurality of first partial circuits 21-1 to 21-p constituting the first circuit 20 and the second plurality of second partial circuits 31-1 to 31-p constituting the second circuit 30 are arranged alternately along the Y direction. Furthermore, the second plurality of second partial circuits 31-1 to 31-p and the third plurality of third partial circuits 41-1 to 41-p constituting the third circuit 40 are arranged alternately along the Y direction. The third plurality of third partial circuits 41-1 to 41-p and the fourth plurality of fourth partial circuits 51-1 to 51-p constituting the fourth circuit 50 are arranged alternately along the Y direction. Furthermore, the first partial circuit 21-r, the second partial circuit 31-r, the third partial circuit 41-r, and the fourth partial circuit 51-r arranged in the Y direction have a plurality of switch cells and a plurality of logic cells in the same arrangement (r is each of 1 to p). Here, in particular, each of the first partial circuit 21-p, the second partial circuit 31-p, the third partial circuit 41-p, and the fourth partial circuit 51-p has a plurality of switch cells and a plurality of logic cells in the same arrangement. The first wiring 22 includes wirings 22-1 to 21-p, and directly connects adjacent first partial circuits 21 to each other by passing through the second to fourth partial circuits therebetween. The second wiring 32 includes wirings 32-1 to 31-p, and directly connects adjacent second partial circuits 31 to each other by passing through the first, third, and fourth partial circuits therebetween. The third wiring 42 includes wirings 42-1 to 41-p, and directly connects adjacent third partial circuits 41 by passing through the first, second, and fourth partial circuits therebetween. The fourth wiring 52 includes wirings 52-1 to 51-p, and directly connects adjacent fourth partial circuits 51 by passing through the first to third partial circuits therebetween.

[0029] The first wiring 22 in the above-mentioned FIG. 1 to FIG. 4 is configured to directly connect the first partial circuits 21 to each other, and the second wiring 32 is configured to directly connect the second partial circuits 31 to each other. However, the first wiring 22 may be provided so as to be connectable to each second partial circuit 31 between the first partial circuits 21 to be connected. FIG. 5 shows, as a modification of FIG. 1, a state in which the first wiring 22 is connected (wired) to the second partial circuits 31 between each of the first partial circuits 21. In FIG. 5, the first wiring 22 is shown to be connected to the circuit elements (switch cell 11 and logic cell 12) of the second partial circuit 31 by not passing through the second partial circuit 31 as shown by a dotted line. In the case of FIG. 5, the arithmetic circuit can be reconfigured by treating the first circuit 20 and the second circuit 30 as one circuit (one-layer reconfigurable circuit). In this case, the second wiring 32 does not need to be used. In this way, when the arithmetic circuit is reconfigured, the first wiring 22 is either in a first state in which adjacent first partial circuits 21 of the multiple first partial circuits 21 are directly connected to each other, or in a second state in which adjacent first partial circuits 21 are connected to each other via a second partial circuit 31 located between them. This makes it possible to reconfigure the arithmetic circuit by separating the first circuit 20 and the second circuit 30 (second layer in FIG. 2 and FIG. 3), or to reconfigure the arithmetic circuit by treating the first circuit 20 and the second circuit 30 as one circuit (first layer in FIG. 4). This allows the arithmetic circuit to be reconfigured more flexibly. In addition to or instead of the first wiring 22, the second wiring 32 may be configured to be either in a first state in which adjacent second partial circuits 31 are directly connected to each other, or in a second state in which adjacent second partial circuits 31 are connected to each other via a first partial circuit 21 located between them, when the arithmetic circuit is reconfigured.

[0030] Similarly, as a modification of FIG. 4, the first wiring 22 may be provided so as to be connectable to each second partial circuit 31 between adjacent first partial circuits 21 to which the first wiring 22 is connected, and the third wiring 42 may be provided so as to be connectable to adjacent fourth partial circuits 51 to which the third wiring 42 is connected. FIG. 6 shows a state in which the first wiring 22 is connected to each second partial circuit 31, and the third wiring 42 is connected to each fourth partial circuit 51. In the case of such wiring, the first partial circuit 21 and the second partial circuit 31 constitute a first-layer circuit, and the third partial circuit 41 and the fourth partial circuit 51 constitute a second-layer circuit. In the case of FIG. 6, the second wiring 32 and the fourth wiring 52 are not used. That is, due to the above connection relationship, when the first wiring 22 directly connects the first partial circuits 21 and the third wiring 42 directly connects the third partial circuits 31 (see FIG. 4), a four-layer reconfigurable circuit is realized. When the first wiring 22 connects the first partial circuit 21 via the second partial circuit 31 and the third wiring 42 connects the third partial circuit 41 via the fourth partial circuit 51 (see FIG. 7), a two-layer reconfigurable circuit is realized.

[0031] As shown in FIG. 7, each of the wires constituting the first wiring 22 and the like may be formed to be selectable between connecting and passing through each circuit element such as the switch cell 11 and the logic cell 12. Whether the connection or passing is adopted is determined when the arithmetic circuit is reconfigured (written). In FIG. 7, the wires pass through the circuit elements as thin dashed lines, thereby indicating that the wires can connect to or pass through the circuit elements. N wires, which is the number of desired layers, may be prepared to connect the circuit elements arranged in the Y direction. In the example of FIG. 7, four wires are prepared for each type of wire, and thus a reconfigurable circuit in which the circuit configurations of the layers are the same is realized in a maximum of four layers (first partial circuit 21 to fourth partial circuit 51). As shown in the example of Figure 7, the nth wiring such as the first wiring 22 may be configured to be capable of being in one of a number of states (particularly connection states) including a first state in which adjacent nth partial circuits among a plurality of nth partial circuits are directly connected to each other when the arithmetic circuit is reconfigured, and a second state in which the adjacent nth partial circuits are connected to each other via at least some of the kth partial circuits (where k = a value other than n among 1 to N) located between them (note that the examples of Figures 5 and 6 are also examples of this configuration).

[0032] (Embodiment 2) If the first circuit 20 or the like is made too large, the design burden of the LUT and the switch cell may increase. It is also possible to divide the circuit of the reconfigurable circuit device 10 into a plurality of regions and apply the above configuration (circuit 10A or 10B) to each of them. For example, as shown in FIG. 8, the entire circuit H of the circuit device 10 may be divided into 12 regions, and the 12 regions may be divided into 5 sections, as if they were divided by a pattern such as dots. If the circuit 10B is applied to each section, a circuit device capable of loading 20 bit streams (20 arithmetic circuits that process 20 tasks in parallel) with 5 sections x 4 layers is realized. In this way, by dividing the entire circuit in which the first to Nth circuits are provided into a plurality of sections and providing the first to Nth circuits for each of the plurality of sections, it becomes possible to execute a large number of tasks at a reasonable implementation cost. In addition, this idea of ​​division can be introduced when a plurality of chips such as chiplets are integrated on a single interposer and designed to behave as an FPGA such as a single circuit device 10. Normally, when spanning chips, it is difficult to control the amount of delay, so each chip may be regarded as one region. Each chip may be further divided into multiple regions.

[0033] (Embodiment 3) A data input circuit that inputs input data to each of the first to Nth arithmetic circuits configured in the first to Nth circuits, and a data synthesis circuit that synthesizes output data output from each of the first to Nth arithmetic circuits may be provided. For example, as shown in FIG. 9, a data distribution circuit 91 that distributes input data input via a communication IF (Interface) (not shown) to each of the first to fourth arithmetic circuits configured (written) in the first to fourth circuits may be provided in the front stage of the circuit 10B of the circuit device 10 as a data input circuit. Furthermore, a data synthesis circuit 92 that synthesizes output data from each of the first to fourth arithmetic circuits and outputs the data to the outside via a communication IF (not shown) may be provided in the rear stage of the circuit 10B of the circuit device 10 as a data synthesis circuit. The number of layers and the number of areas are values ​​that are determined at the stage when the circuit device 10 is made, and data processing is facilitated by incorporating the data input circuit and the data synthesis circuit in advance. At least one of the data input circuit and the data synthesis circuit may be configured to be reconfigurable, may be configured to be non-reconfigurable, or may be configured to be a hybrid.

[0034] (Scope of the present invention) Although the present invention has been described above with reference to the embodiment and its modified examples, the present invention is not limited to the above embodiment and modified examples. For example, the present invention includes various modifications to the above embodiment and modified examples that can be understood by a person skilled in the art within the scope of the technical concept of the present invention. The configurations listed in the above embodiment can be appropriately combined within a range without contradiction. [Explanation of symbols]

[0035] 10...circuit device, 10A, 10B...circuit, 11...switch cell, 12...logic cell, 20...first circuit, 21, 21-1 to 21-p...first partial circuit, 22...first wiring, 30...second circuit, 31, 31-1 to 31-p...second partial circuit, 32...second wiring, 40...third circuit, 41, 41-1 to 41-p...third partial circuit, 42...third wiring, 50...fourth circuit, 51, 51-1 to 51-p...fourth partial circuit, 52...fourth wiring, 91...data distribution circuit, 92...data synthesis circuit, H...whole, U...unit circuit.

Claims

1. The present invention provides a first circuit and a second circuit that are capable of reconfiguring an arithmetic circuit, the first circuit includes a plurality of first partial circuits arranged at intervals along a predetermined direction, and first wiring that connects adjacent first partial circuits of the plurality of first partial circuits to each other; the second circuit includes a plurality of second partial circuits arranged at intervals along the predetermined direction, and second wiring that connects adjacent second partial circuits of the plurality of second partial circuits to each other; the plurality of first partial circuits and the plurality of second partial circuits are arranged alternately along the predetermined direction, each pair of the plurality of first partial circuits and the adjacent second partial circuits along the predetermined direction of each of the plurality of first partial circuits includes a plurality of switch cells and a plurality of logic cells arranged in the same manner for each pair; the first wiring is configured to directly connect the adjacent first partial circuits to each other; the second wiring is configured to directly connect the adjacent second partial circuits to each other; Reconfigurable circuit device.

2. the first wiring is configured to be in any one of a plurality of states including a first state in which the adjacent first partial circuits are directly connected to each other and a second state in which the adjacent first partial circuits are connected to each other via the second partial circuit located therebetween when the arithmetic circuit is reconfigured. The reconfigurable circuit device according to claim 1 .

3. an entire circuit in which the first circuit and the second circuit are provided is divided into a plurality of sections; Each of the plurality of sections includes the first circuit and the second circuit.

3. The reconfigurable circuit device according to claim 1 or 2.

4. a data input circuit that inputs input data to a first arithmetic circuit configured in the first circuit and a second arithmetic circuit configured in the second circuit; a data synthesis circuit that synthesizes the output data from the first arithmetic circuit and the output data from the second arithmetic circuit; The reconfigurable circuit device according to claim 1 , further comprising:

5. The present invention includes first to Nth circuits (N is a natural number of 2 or more) that can reconfigure an arithmetic circuit, The n-th circuit among the first to N-th circuits includes a plurality of n-th partial circuits arranged at intervals along a predetermined direction, and an n-th wiring that connects adjacent n-th partial circuits of the plurality of n-th partial circuits (n is an integer from 1 to N), a plurality of m-th and (m+1)-th partial circuits among the plurality of n-th partial circuits are arranged alternately along the predetermined direction (m is 1 to N-1, respectively); the mth partial circuits and the m+1th partial circuits are arranged alternately along the predetermined direction, each pair of the mth partial circuits and an m+1th partial circuit adjacent to each of the mth partial circuits along the predetermined direction includes a plurality of switch cells and a plurality of logic cells arranged in the same manner for each pair; the nth wiring is configured to directly connect the adjacent nth sub-circuits to each other; Reconfigurable circuit device.

6. the nth wiring is configured to be in one of a plurality of states including a first state in which the adjacent nth partial circuits are directly connected to each other, and a second state in which the adjacent nth partial circuits are connected to each other via at least a part of the kth partial circuits (where k=a value other than n among 1 to N) located therebetween, when the arithmetic circuit is reconfigured; The reconfigurable circuit device according to claim 5 .

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