Encoding method and apparatus, decoding method and apparatus, and device

Abstract

An encoding method and apparatus, a decoding method and apparatus, and a device are provided. The encoding method includes a step (S301) of obtaining K bits to be encoded, where K is a positive integer, a step (S302) of determining a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed based on a predetermined positional relationship, the sub-blocks including a plurality of first generator matrix cores, a step (S303) of generating a second generator matrix based on the first generator matrix, where the second generator matrix includes T sub-blocks, where the positional relationship between two adjacent sub-blocks among the T sub-blocks is determined based on the predetermined positional relationship, where T is a positive integer, and a step (S304) of polar-coding the K bits to be encoded based on the second generator matrix to obtain coded bits. This can reduce the complexity of encoding / decoding.

Description

[Technical field]

[0001] This application claims priority to Chinese Patent Application No. 202010323605.X, entitled “ENCODER METHOD AND APPARATUS, DECODING METHOD AND APPARATUS, AND DEVICE,” filed with the State Intellectual Property Office of the People's Republic of China on April 22, 2020, which is incorporated herein by reference in its entirety.

[0002] This application relates to the field of communication technology, and in particular to an encoding method and apparatus, a decoding method and apparatus, and a device. [Background technology]

[0003] In the field of communication technology, a communication device (eg, a terminal device or a base station) may perform channel encoding and decoding using polar codes.

[0004] When decoding is performed by using polar codes, the complexity of encoding / decoding (encoding and / or decoding) is usually related to the code length. A larger code length indicates a higher encoding / decoding complexity. When the code length is very large (e.g., the code length is larger than 16384), the complexity of performing encoding / decoding by using polar codes is very high, resulting in a decrease in the encoding / decoding performance. Summary of the Invention

[0005] SUMMARY OF THE PRESENT APPLICATION The embodiments of this application provide an encoding method and apparatus, a decoding method and apparatus, and a device to reduce the encoding / decoding complexity. [Means for solving the problem]

[0006] According to a first aspect, an embodiment of the present application provides an encoding method, which includes the steps of: obtaining K bits to be encoded, where K is a positive integer; determining a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed based on a preset positional relationship, where the sub-blocks include a plurality of first generator matrix cores; generating a second generator matrix based on the first generator matrix, where the second generator matrix includes T sub-blocks, where a positional relationship between two adjacent sub-blocks among the T sub-blocks is determined based on a preset positional relationship, where T is a positive integer; and polar-encoding the K bits to be encoded based on the second generator matrix to obtain encoded bits.

[0007] In the above process, when K bits to be encoded need to be encoded, a first generator matrix is ​​first determined, then a second generator matrix is ​​generated based on the first generator matrix, and the K bits to be encoded are polar-encoded based on the second generator matrix. The first generator matrix includes at least two sub-blocks distributed based on a preset positional relationship, each sub-block includes a plurality of first generator matrix cores, and the second generator matrix includes T sub-blocks, and the positional relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset positional relationship. Therefore, it can be seen that the second generator matrix includes a plurality of sub-blocks arranged according to the above-mentioned preset positional relationship, and each sub-block includes a plurality of first generator matrix cores. Therefore, the step of polar-encoding the K bits to be encoded based on the second generator matrix is ​​equivalent to the step of polar-encoding a plurality of short codes and combining the plurality of short codes to obtain an encoding result. This can reduce the complexity of encoding.

[0008] In a possible implementation, the positional relationship between two adjacent sub-blocks among the T sub-blocks is the same as a preset positional relationship.

[0009] In the above process, the position relationship between two adjacent sub-blocks among the T sub-blocks in the second generator matrix is ​​the same as the preset position relationship, so that the short code has the same combination scheme and the encoding complexity is low.

[0010] In a possible implementation, there is an overlap in at least two of the sub-blocks.

[0011] In the above process, there is an overlap between two sub-blocks so that different short codes can be combined.

[0012] In a possible implementation, the first generator matrix core is included in the first diagonal of the sub-block.

[0013] In a possible implementation, the multiple first generator matrix cores within a sub-block are distributed in a lower triangular fashion.

[0014] In a possible implementation, the distribution of the first generator matrix core within the sub-block is the same as the distribution of the first elements within the second generator matrix core, the number of elements contained in the second generator matrix core is the same as the number of sub-matrices contained in the sub-block, and the sub-matrix contained in the sub-block is the first generator matrix core or a zero matrix.

[0015] In the above process, since the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, the combination manner of the short code is similar to the existing encoding method, and therefore the encoding complexity is low.

[0016] In a possible implementation, the first generator matrix includes two sub-blocks.

[0017] In the above process, the second generator matrix contains a small amount of sub-blocks, and the second generator matrix is ​​easy to construct.

[0018] In a possible implementation, the number of sub-matrices included in the sub-block is 2*2, and the sub-matrix included in the sub-block is the first generator matrix core or a zero matrix.

[0019] In a possible implementation, a first generator matrix includes a first sub-block and a second sub-block, a first sub-matrix in the first sub-block overlaps with a second sub-matrix in the second sub-block, the coordinates of the first sub-matrix in the first sub-block are (2, 2), and the coordinates of the second sub-matrix in the second sub-block are (1, 1).

[0020] In the above process, since the second generator matrix is ​​symmetric in the direction of the secondary diagonal of the second generator matrix, the encoding complexity is low and the decoding complexity is also low.

[0021] In a possible implementation, the number of sub-matrices included in the sub-block is 4*4, and the sub-matrix included in the sub-block is the first generator matrix core or a zero matrix.

[0022] In a possible implementation, the first generator matrix includes a first sub-block and a second sub-block, and four first sub-matrices in the first sub-block overlap with four second sub-matrices in the second sub-block, the coordinates of the four first sub-matrices in the first sub-block are (3, 3), (3, 4), (4, 3), and (4, 4), and the coordinates of the four second sub-matrices in the second sub-block are (1, 1), (1, 2), (2, 1), and (2, 2).

[0023] In the above process, since the second generator matrix is ​​symmetric in the direction of the secondary diagonal of the second generator matrix, the encoding complexity is low and the decoding complexity is also low.

[0024] In a possible implementation, the K bits to be coded are information bits. The step of polar coding the K bits to be coded based on the second generator matrix to obtain coded bits includes the steps of: determining K subchannels having the highest reliability among a plurality of subchannels corresponding to the K bits to be coded, determining positions of the K bits to be coded based on the K subchannels having the highest reliability, determining a sequence to be coded based on the positions of the K bits to be coded, where the sequence to be coded includes the K bits to be coded and a frozen bit, and polar coding the sequence to be coded based on the second generator matrix to obtain coded bits.

[0025] In the above process, the subchannel with the highest reliability is selected to transmit the information bits, and therefore the coding performance is high.

[0026] In a possible implementation, the plurality of subchannels includes P groups of subchannels, where P is a positive integer. The step of determining the K most reliable subchannels among the plurality of subchannels corresponding to the K bits to be coded includes: selecting X from the i-th group of subchannels based on the reliability of the i-th group of subchannels. i determining X first sub-channels; i The first subchannel is the one with the highest reliability in the i-th group of subchannels, X i subchannels, i is an integer, 1≦i≦P, and X i is a positive integer,

number

[0027] According to a second aspect, an embodiment of the present application provides a decoding method, the method includes receiving polar-encoded bit information, and polar-decoding the bit information based on a second generator matrix to obtain polar-decoded bits. The second generator matrix is ​​generated based on a first generator matrix, the first generator matrix includes at least two sub-blocks distributed based on a preset positional relationship, the sub-blocks include a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and a positional relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset positional relationship, where T is a positive integer.

[0028] In the above-mentioned decoding process, the first generator matrix includes at least two sub-blocks distributed based on a preset positional relationship, each sub-block includes a plurality of first generator matrix cores, and the second generator matrix includes T sub-blocks, and the positional relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset positional relationship. Therefore, it can be seen that the second generator matrix includes a plurality of sub-blocks arranged according to the above-mentioned preset positional relationship, and each sub-block includes a plurality of first generator matrix cores. Therefore, the step of polar decoding the bit information based on the second generator matrix is ​​equivalent to the step of separating a plurality of short codes and decoding the separated short codes. Due to the complexity of decoding the short codes, the complexity of decoding is low.

[0029] In a possible implementation, the positional relationship between two adjacent sub-blocks among the T sub-blocks is the same as a preset positional relationship.

[0030] In the above process, the position relationship between two adjacent sub-blocks among the T sub-blocks in the second generator matrix is ​​the same as the preset position relationship, so that the short code has the same combination scheme and the decoding complexity is low.

[0031] In a possible implementation, there is an overlap in at least two of the sub-blocks.

[0032] In the above process, there is an overlap between two sub-blocks so that different short codes can be combined.

[0033] In a possible implementation, the first generator matrix core is included in the first diagonal of the sub-block.

[0034] In a possible implementation, the multiple first generator matrix cores within a sub-block are distributed in a lower triangular fashion.

[0035] In a possible implementation, the distribution of the first generator matrix core within the sub-block is the same as the distribution of the first elements within the second generator matrix core, the number of elements contained in the second generator matrix core is the same as the number of sub-matrices contained in the sub-block, and the sub-matrix contained in the sub-block is the first generator matrix core or a zero matrix.

[0036] In the above process, since the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first element in the second generator matrix core, the combining manner of the short code is similar to the existing decoding manner, and therefore the decoding complexity is low.

[0037] In a possible implementation, the first generator matrix includes two sub-blocks.

[0038] In the above process, the second generator matrix contains a small amount of sub-blocks, and the second generator matrix is ​​easy to construct.

[0039] In a possible implementation, the number of sub-matrices included in the sub-block is 2*2, and the sub-matrix included in the sub-block is the first generator matrix core or a zero matrix.

[0040] In a possible implementation, a first generator matrix includes a first sub-block and a second sub-block, a first sub-matrix in the first sub-block overlaps with a second sub-matrix in the second sub-block, the coordinates of the first sub-matrix in the first sub-block are (2, 2), and the coordinates of the second sub-matrix in the second sub-block are (1, 1).

[0041] In the above process, the second generator matrix is ​​symmetric in the direction of the secondary diagonal of the second generator matrix, and therefore the decoding complexity is low.

[0042] In a possible implementation, the number of sub-matrices included in the sub-block is 4*4, and the sub-matrix included in the sub-block is the first generator matrix core or a zero matrix.

[0043] In a possible implementation, the first generator matrix includes a first sub-block and a second sub-block, and four first sub-matrices in the first sub-block overlap with four second sub-matrices in the second sub-block, the coordinates of the four first sub-matrices in the first sub-block are (3, 3), (3, 4), (4, 3), and (4, 4), and the coordinates of the four second sub-matrices in the second sub-block are (1, 1), (1, 2), (2, 1), and (2, 2).

[0044] In the above process, the second generator matrix is ​​symmetric in the direction of the secondary diagonal of the second generator matrix, and therefore the decoding complexity is low.

[0045] In a possible implementation, the bit information comprises N' first log-likelihood ratio (LLR) sequences, where N' is a positive integer.

[0046] In a possible implementation, the N′ first LLRs include T first LLR sequences, where the first LLR sequences include at least two first LLRs. The polar decoding includes determining T second LLR sequences corresponding to the T first LLR sequences, where one of the first LLR sequences corresponds to one or more groups of uncoded bits and one of the second LLR sequences corresponds to one group of uncoded bits, and performing polar decoding based on the T second LLR sequences.

[0047] In the above process, firstly, the T combined first LLR sequences are separated to obtain T separated second LLR sequences, and then the T separated second LLR sequences are decoded. Because the length of the second LLR sequence is short, the decoding complexity of the second LLR sequence is low, and the decoding complexity is low.

[0048] In a possible implementation, the step of determining T second LLR sequences corresponding to the T first LLR sequences includes a step of determining the i-th second LLR sequence based on the i-th first LLR sequence and at least one of the first (i-1) second LLR sequences, where i is an integer from 2 to T.

[0049] In the above process, once the i-th second LLR sequence is determined, the first LLR sequence is separated based on the i-th first LLR sequence and at least one of the separated first (i-1) second LLR sequences to obtain the i-th second LLR sequence.

[0050] In a possible implementation, the degree of combination of the code blocks is 2. Determining the i-th second LLR sequence based on the i-th first LLR sequence and at least one of the first (i-1) second LLR sequences includes determining the i-th second LLR sequence based on the i-th first LLR sequence and the (i-1)-th second LLR sequence.

[0051] In a possible implementation, the first second LLR sequence is the same as the first first LLR sequence.

[0052] In a possible implementation, the degree of combination of the code blocks is 4. Determining the i-th second LLR sequence based on the i-th first LLR sequence and at least one of the first (i-1) second LLR sequences includes determining the i-th second LLR sequence based on the i-th first LLR sequence and the (i-2)-th second LLR sequence, where i is an integer from 3 to T.

[0053] In a possible implementation, the first second LLR sequence is the same as the first first LLR sequence and the second second LLR sequence is the same as the second first LLR sequence.

[0054] In a possible implementation, polar decoding may be performed based on T second LLR sequences in the following manner, namely: determine to obtain a Tth decoding result based on the Tth second LLR sequence; and determine the ith decoding result based on the ith second LLR sequence and at least one of the (i+1)th decoding result to the Tth decoding result, where i is an integer from 1 to T-1.

[0055] In the above process, the second LLR sequence (short code) is decoded to obtain the decoding result, and therefore the decoding complexity is low.

[0056] In a possible implementation, the degree of coupling of the code blocks is 2. The step of determining the i-th decoding result based on the i-th second LLR sequence and at least one of the (i+1)-th decoding result to the T-th decoding result includes the step of determining the i-th decoding result based on the (i+1)-th decoding result, the (i+1)-th first LLR sequence, and the i-th second LLR sequence.

[0057] According to a third aspect, an embodiment of the present application provides an encoding method, the method including the steps of: obtaining K bits to be encoded, where K is a positive integer; and determining a first generator matrix, the first generator matrix including a first matrix block and a second matrix block, the first matrix block being located at an upper left corner of the first generator matrix and the second matrix block being located at a lower right corner of the first generator matrix, the first matrix block being equal to the second matrix block, and a distance between a first element in the first matrix block and a second element in the second matrix block in a diagonal direction of the first generator matrix is ​​u, where u is an integer equal to or greater than 1. , a step of determining a second generator matrix based on the coding length and the first generator matrix, where the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along a diagonal of the second generator matrix, a first matrix block of an (a+1)th first generator matrix among the T first generator matrices overlaps with a second matrix block of an ath first generator matrix, a is an integer greater than or equal to 1, and T is an integer greater than or equal to 2; and a step of polar-encoding the K bits to be encoded based on the second generator matrix to obtain encoded bits.

[0058] In the foregoing process, when K bits to be encoded need to be encoded, a first generator matrix is first determined, then a second generator matrix is generated based on the first generator matrix, and the K bits to be encoded are polar encoded based on the second generator matrix. Since the first generator matrix has self-similarity and the second generator matrix includes a plurality of first matrix blocks, the step of polar encoding K bits to be encoded based on the second generator matrix is equivalent to the steps of polar encoding a plurality of short codes to obtain an encoding result and combining the plurality of short codes. Thereby, the encoding complexity can be reduced.

[0059] In an imaginable implementation, there are no overlapping elements in the first matrix block and the second matrix block.

[0060] In an imaginable implementation, the size of the first generator matrix is v*v, and the elements in the first generator matrix are a i,j =a i+u,j+u satisfies, where i is an integer, j is an integer, v is a positive integer, u is an integer, 1≦i<v, 1≦j<v, 1<i+u≦v, and 1<j+u≦v.

[0061] In the foregoing process, when the first generator matrix satisfies a i,j =a i+u,j+u the first generator matrix satisfies self-similarity. The step of polar encoding K bits to be encoded based on the second generator matrix is equivalent to the steps of polar encoding a plurality of short codes and combining the plurality of short codes to obtain an encoding result. Thereby, the encoding complexity can be reduced.

[0062] In an imaginable implementation, the elements in the first generator matrix are symmetric along the secondary diagonal of the first generator matrix.

[0063] In the foregoing process, since the elements in the first generator matrix are symmetric along the secondary diagonal of the first generator matrix, the encoding complexity is low.

[0064] In a possible implementation, T is the smallest integer that enables a first condition to be satisfied, the first condition being that the size of the second generator matrix is ​​greater than or equal to the coding length.

[0065] In a possible implementation, T satisfies the following relationship: v+(T-1)*u <N ’ ≦v+T*u, where v is the size of the first generator matrix, N′ is the coding length, and N′ is an integer greater than 1.

[0066] In the above process, an excessively large or small size of the second generator matrix can be avoided, and therefore the encoding complexity is low.

[0067] According to a fourth aspect, an embodiment of the present application provides a decoding method, the method includes: receiving polar-encoded bit information; and polar-decoding the bit information based on a second generator matrix to obtain polar-decoded bits. The second generator matrix is ​​generated based on a first generator matrix, the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at an upper left corner of the first generator matrix, the second matrix block is located at a lower right corner of the first generator matrix, the first matrix block is the same as the second matrix block, and a distance between a first element in the first matrix block and a second element in the second matrix block is u in a diagonal direction of the first generator matrix, where u is an integer equal to or greater than 1. The second generator matrix includes T first generator matrices, the T first generator matrices are distributed along a diagonal of the second generator matrix, a first matrix block of an (a+1)th first generator matrix in the T first generator matrices overlaps with a second matrix block of an ath first generator matrix, a is an integer greater than or equal to 1, and T is an integer greater than or equal to 2.

[0068] In the foregoing process, since the first generation matrix has self-similarity, the second generation matrix includes a plurality of first matrix blocks. Therefore, the step of polar decoding bit information based on the second generation matrix is equivalent to the step of separating a plurality of short codes and decoding the separated short codes. Due to the complexity of decoding the short codes, the decoding complexity is low.

[0069] In an imaginable implementation, there are no overlapping elements in the first matrix block and the second matrix block.

[0070] In an imaginable implementation, the size of the first generation matrix is v*v, and the elements in the first generation matrix are a i,j =a i+u,j+u is satisfied, where i is an integer, j is an integer, v is a positive integer, u is an integer, 1≦i<v, 1≦j<v, 1<i+u≦v, and 1<j+u≦v.

[0071] In the foregoing process, when the first generation matrix satisfies a i,j =a i+u,j+u the first generation matrix satisfies self-similarity. The step of polar decoding K decoding target bits based on the second generation matrix is equivalent to the step of polar decoding a plurality of short codes, combining the plurality of short codes, and obtaining a decoding result. Thereby, the decoding complexity can be reduced.

[0072] In an imaginable implementation, the elements in the first generation matrix are symmetric along the secondary diagonal of the first generation matrix.

[0073] In the foregoing process, since the elements in the first generation matrix are symmetric along the secondary diagonal of the first generation matrix, the decoding complexity is low.

[0074] In an imaginable implementation, T is the smallest integer that enables the first condition to be satisfied, and the first condition is that the size of the second generation matrix is greater than or equal to the decoding length.

[0075] In a possible implementation, T is determined by the following relationship: v+(T-1)*u <N ’ ≦v+T*u, where v is the size of the first generator matrix, N′ is the decoding length, and N′ is an integer greater than 1.

[0076] In the above process, an excessively large or small size of the second generator matrix can be avoided, and therefore the decoding complexity is low.

[0077] In a possible implementation, the bit information comprises N' first log-likelihood ratio (LLR) sequences, where N' is a positive integer.

[0078] In a possible implementation, the N′ first LLRs include T first LLR sequences, where the first LLR sequences include at least two first LLRs. The polar decoding includes determining T second LLR sequences corresponding to the T first LLR sequences, where one of the first LLR sequences corresponds to one or more groups of uncoded bits and one of the second LLR sequences corresponds to one group of uncoded bits, and performing polar decoding based on the T second LLR sequences.

[0079] In the above process, first, the T combined first LLR sequences are first separated to obtain T separated second LLR sequences, and then the T separated second LLR sequences are decoded. Because the length of the second LLR sequence is short, the decoding complexity of the second LLR sequence is low, and the decoding complexity is low.

[0080] In a possible implementation, the step of determining T second LLR sequences corresponding to the T first LLR sequences includes a step of determining the i-th second LLR sequence based on the i-th first LLR sequence and at least one of the first (i-1) second LLR sequences, where i is an integer from 2 to T.

[0081] In the above process, once the i-th second LLR sequence is determined, the first LLR sequence is separated based on the i-th first LLR sequence and at least one of the separated first (i-1) second LLR sequences to obtain the i-th second LLR sequence.

[0082] In a possible implementation, the degree of combination of the code blocks is 2. Determining the i-th second LLR sequence based on the i-th first LLR sequence and at least one of the first (i-1) second LLR sequences includes determining the i-th second LLR sequence based on the i-th first LLR sequence and the (i-1)-th second LLR sequence.

[0083] In a possible implementation, the first second LLR sequence is the same as the first first LLR sequence.

[0084] In a possible implementation, the degree of combination of the code blocks is 4. Determining the i-th second LLR sequence based on the i-th first LLR sequence and at least one of the first (i-1) second LLR sequences includes determining the i-th second LLR sequence based on the i-th first LLR sequence and the (i-2)-th second LLR sequence, where i is an integer from 3 to T.

[0085] In a possible implementation, the first second LLR sequence is the same as the first first LLR sequence and the second second LLR sequence is the same as the second first LLR sequence.

[0086] In a possible implementation, polar decoding may be performed based on T second LLR sequences in the following manner, namely: determine to obtain a Tth decoding result based on the Tth second LLR sequence; and determine the ith decoding result based on the ith second LLR sequence and at least one of the (i+1)th decoding result to the Tth decoding result, where i is an integer from 1 to T-1.

[0087] In the above process, the second LLR sequence (short code) is decoded to obtain the decoding result, and therefore the decoding complexity is low.

[0088] In a possible implementation, the degree of coupling of the code blocks is 2. The step of determining the i-th decoding result based on the i-th second LLR sequence and at least one of the (i+1)-th decoding result to the T-th decoding result includes the step of determining the i-th decoding result based on the (i+1)-th decoding result, the (i+1)-th first LLR sequence, and the i-th second LLR sequence.

[0089] According to a fifth aspect, an embodiment of the present application provides an encoding device, including an obtaining module, a determining module, a generating module, and an encoding module.

[0090] The obtaining module is configured to obtain K bits to be encoded, where K is a positive integer.

[0091] The determination module is configured to determine a first generator matrix, the first generator matrix including at least two sub-blocks distributed based on a preset positional relationship, the sub-block including a plurality of first generator matrix cores.

[0092] The generating module is configured to generate a second generating matrix based on the first generating matrix, the second generating matrix including T sub-blocks, and a positional relationship between two adjacent sub-blocks among the T sub-blocks is determined based on a preset positional relationship, where T is a positive integer.

[0093] The encoding module is configured to polar-encode the K bits to be encoded based on a second generator matrix to obtain encoded bits.

[0094] In a possible implementation, the positional relationship between two adjacent sub-blocks among the T sub-blocks is the same as a preset positional relationship.

[0095] In a possible implementation, there is an overlap in at least two of the sub-blocks.

[0096] In a possible implementation, the first diagonal of the sub-block contains the first generator matrix core.

[0097] In a possible implementation, the multiple first generator matrix cores within a sub-block are distributed in a lower triangular fashion.

[0098] In a possible implementation, the distribution of the first generator matrix core within the sub-block is the same as the distribution of the first elements within the second generator matrix core, the number of elements contained in the second generator matrix core is the same as the number of sub-matrices contained in the sub-block, and the sub-matrix contained in the sub-block is the first generator matrix core or a zero matrix.

[0099] In a possible implementation, the first generator matrix includes two sub-blocks.

[0100] In a possible implementation, the number of sub-matrices included in the sub-block is 2*2, and the sub-matrix included in the sub-block is the first generator matrix core or a zero matrix.

[0101] In a possible implementation, the first generator matrix includes a first sub-block and a second sub-block, a first sub-matrix in the first sub-block overlaps with a second sub-matrix in the second sub-block, and the coordinates of the first sub-matrix in the first sub-block are (2, 2) and the coordinates of the second sub-matrix in the second sub-block are (1, 1).

[0102] In a possible implementation, the number of sub-matrices included in the sub-block is 4*4, and the sub-matrix included in the sub-block is the first generator matrix core or a zero matrix.

[0103] In a possible implementation, the first generator matrix includes a first sub-block and a second sub-block, and four first sub-matrices in the first sub-block overlap with four second sub-matrices in the second sub-block.

[0104] The coordinates of the four first sub-matrices in the first sub-block are (3, 3), (3, 4), (4, 3), and (4, 4), and the coordinates of the four second sub-matrices in the second sub-block are (1, 1), (1, 2), (2, 1), and (2, 2).

[0105] In a possible implementation, the K bits to be coded are information bits, and the coding module is particularly configured to: determine K sub-channels with the highest reliability among the multiple sub-channels corresponding to the K bits to be coded, determine positions of the K bits to be coded according to the K sub-channels with the highest reliability, determine a sequence to be coded according to the positions of the K bits to be coded, the sequence to be coded includes the K bits to be coded and a frozen bit, and polar-code the sequence to be coded according to a second generator matrix to obtain coded bits, thereby obtaining coded bits.

[0106] In a possible implementation, the plurality of subchannels includes P groups of subchannels, where P is a positive integer. The encoding module may further include a coding module for coding X from the i-th group of subchannels based on the reliability of the i-th group of subchannels. iDetermine the first subchannels, X i The first subchannels X have the highest reliability in the i-th group of subchannels. i subchannels, i is an integer, 1≦i≦P, and X i is a positive integer,

number

[0107] The K subchannels with the highest reliability include the first subchannel.

[0108] According to a sixth aspect, an embodiment of the present application provides a decoding device, including a receiving module and a decoding module.

[0109] The receiving module is configured to receive the polar encoded bit information.

[0110] The decoding module is configured to polar-decode the bit information based on the second generator matrix to obtain polar-decoded bits.

[0111] The second generator matrix is ​​generated based on the first generator matrix, the first generator matrix includes at least two sub-blocks distributed based on a predetermined positional relationship, the sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and a positional relationship between two adjacent sub-blocks among the T sub-blocks is determined based on the predetermined positional relationship, where T is a positive integer.

[0112] In a possible implementation, the positional relationship between two adjacent sub-blocks among the T sub-blocks is the same as a preset positional relationship.

[0113] In a possible implementation, there is an overlap in at least two of the sub-blocks.

[0114] In a possible implementation, the first diagonal of the sub-block contains the first generator matrix core.

[0115] In a possible implementation, the multiple first generator matrix cores within a sub-block are distributed in a lower triangular fashion.

[0116] In a possible implementation, the distribution of the first generator matrix core within the sub-block is the same as the distribution of the first elements within the second generator matrix core, the number of elements contained in the second generator matrix core is the same as the number of elements contained in the sub-block, and the elements contained in the sub-block are the first generator matrix core or a zero matrix.

[0117] In a possible implementation, the first generator matrix includes two sub-blocks.

[0118] In a possible implementation, the number of elements contained in the sub-block is 2*2, and the elements contained in the sub-block are the first generator matrix core or zero matrices.

[0119] In a possible implementation, a first generator matrix includes a first sub-block and a second sub-block, a first element in the first sub-block overlaps with a second element in the second sub-block, and the coordinates of the first element in the first sub-block are (2, 2) and the coordinates of the second element in the second sub-block are (1, 1).

[0120] In a possible implementation, the number of elements contained in the sub-block is 4*4, and the elements contained in the sub-block are the first generator matrix core or zero matrix.

[0121] In a possible implementation, the first generator matrix includes a first sub-block and a second sub-block, and four first elements in the first sub-block overlap with four second elements in the second sub-block.

[0122] The coordinates of the four first elements in the first sub-block are (3, 3), (3, 4), (4, 3), and (4, 4), and the coordinates of the four second elements in the second sub-block are (1, 1), (1, 2), (2, 1), and (2, 2).

[0123] In a possible implementation, the bit information comprises N' first log-likelihood ratio (LLR) sequences, where N' is a positive integer.

[0124] In a possible implementation, the N′ first LLRs include T first LLR sequences, where the first LLR sequences include at least two first LLRs. The decoding module is particularly configured to determine T second LLR sequences corresponding to the T first LLR sequences, where one of the first LLR sequences corresponds to one or more groups of uncoded bits and one of the second LLR sequences corresponds to one group of uncoded bits, and to perform polar decoding based on the T second LLR sequences.

[0125] In a possible implementation, the decoding module is particularly configured to determine an i-th second LLR sequence based on the i-th first LLR sequence and at least one of the first (i-1) second LLR sequences, where i is an integer from 2 to T.

[0126] In a possible implementation, the degree of coupling of the code blocks is 2. The decoding module is particularly configured to determine the i-th second LLR sequence based on the i-th first LLR sequence and the (i-1)-th second LLR sequence.

[0127] In a possible implementation, the first second LLR sequence is the same as the first first LLR sequence.

[0128] In a possible implementation, the degree of coupling of the code block is 4. The decoding module is particularly configured to determine an i-th second LLR sequence based on the i-th first LLR sequence and the (i-2)-th second LLR sequence, where i is an integer from 3 to T.

[0129] In a possible implementation, the first second LLR sequence is the same as the first first LLR sequence, and the second second LLR sequence is the same as the second first LLR sequence.

[0130] In a possible implementation, the decoding module is particularly configured to: determine to obtain a Tth decoding result based on the Tth second LLR sequence; and determine an ith decoding result based on the ith second LLR sequence and at least one of the (i+1)th decoding result to the Tth decoding result, where i is an integer from 1 to T-1.

[0131] In a possible implementation, the degree of coupling of the code blocks is 2. The decoding module is particularly configured to determine an i-th decoding result based on the (i+1)-th decoding result, the (i+1)-th first LLR sequence, and the i-th second LLR sequence.

[0132] According to a seventh aspect, an embodiment of the present application provides an encoding device, including an obtaining module, a determining module, a generating module, and an encoding module.

[0133] The obtaining module is configured to obtain K bits to be encoded, where K is a positive integer.

[0134] The decision module is configured to determine a first generator matrix. The first generator matrix includes a first matrix block and a second matrix block. The first matrix block is located at the upper left corner of the first generator matrix, and the second matrix block is located at the lower right corner of the first generator matrix. The first matrix block is the same as the second matrix block, and the distance between the first element in the first matrix block and the second element in the second matrix block is u in the diagonal direction of the first generator matrix, where u is an integer greater than or equal to 1.

[0135] The generation module is configured to generate a second generator matrix based on the coding length and the first generator matrix. The second generator matrix includes T first generator matrices, and the T first generator matrices are distributed along the diagonal of the second generator matrix. The first matrix block of the (a + 1)-th first generator matrix within the T first generator matrices overlaps with the second matrix block of the a-th first generator matrix, where a is an integer greater than or equal to 1 and T is an integer greater than or equal to 2.

[0136] The encoding module is configured to perform polar encoding on K bits to be encoded based on the second generator matrix to obtain encoded bits.

[0137] In a possible implementation, there are no overlapping elements in the first matrix block and the second matrix block.

[0138] In a possible implementation, the size of the first generator matrix is v * v, and the elements within the first generator matrix satisfy a i,j =a i+u,j+u where i is an integer, j is an integer, v is a positive integer, u is an integer, 1 ≤ i < v, 1 ≤ j < v, 1 < i + u ≤ v, and 1 < j + u ≤ v.

[0139] In a possible implementation, the elements within the first generator matrix are symmetric along the secondary diagonal of the first generator matrix.

[0140] In a possible implementation, T is the smallest integer that enables a first condition to be satisfied, the first condition being that the size of the second generator matrix is ​​greater than or equal to the coding length.

[0141] In a possible implementation, T satisfies the following relationship: v+(T-1)*u <N ’ ≦v+T*u, where v is the size of the first generator matrix, N′ is the coding length, and N′ is an integer greater than 1.

[0142] According to an eighth aspect, an embodiment of the present application provides a decoding device, including a receiving module and a decoding module.

[0143] The receiving module is configured to receive the polar encoded bit information.

[0144] The decoding module is configured to polar-decode the bit information based on a second generator matrix to obtain polar-decoded bits, The second generator matrix is ​​generated based on the first generator matrix.

[0145] The first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at an upper left corner of the first generator matrix, the second matrix block is located at a lower right corner of the first generator matrix, the first matrix block is the same as the second matrix block, and a distance between a first element in the first matrix block and a second element in the second matrix block is u in a diagonal direction of the first generator matrix, where u is an integer greater than or equal to 1.

[0146] The second generator matrix includes T first generator matrices, the T first generator matrices are distributed along a diagonal of the second generator matrix, a first matrix block of an (a+1)th first generator matrix in the T first generator matrices overlaps with a second matrix block of an ath first generator matrix, a is an integer greater than or equal to 1, and T is an integer greater than or equal to 2.

[0147] In a possible implementation, there are no duplicated elements in the first matrix block and the second matrix block.

[0148] In a possible implementation, the size of the first generator matrix is v*v, and the elements in the first generator matrix are a i,j =a i+u,j+u satisfies, i is an integer, j is an integer, v is a positive integer, u is an integer, 1≦i<v, 1≦j<v, 1<i+u≦v, and 1<j+u≦v.

[0149] In a possible implementation, the elements in the first generator matrix are symmetric along the secondary diagonal of the first generator matrix.

[0150] In a possible implementation, T is the smallest integer that enables the first condition to be satisfied, and the first condition is that the size of the second generator matrix is greater than or equal to the coding length.

[0151] In a possible implementation, T satisfies the following relationship, that is, v+(T-1)*u<N ’ ≦v+T*u, where v is the size of the first generator matrix, N’ is the coding length, and N’ is an integer greater than 1.

[0152] In a possible implementation, the bit information includes N’ first log-likelihood ratio (LLR) sequences, and N’ is a positive integer.

[0153] In a possible implementation, the N’ first LLRs include T first LLR sequences, and each first LLR sequence includes at least two first LLRs. The decoding module is specifically configured to determine T second LLR sequences corresponding to the T first LLR sequences, where one of the first LLR sequences corresponds to one or more groups of uncoded bits, one of the second LLR sequences corresponds to one group of uncoded bits, and perform polar decoding based on the T second LLR sequences.

[0154] In a possible implementation, the decoding module is particularly configured to determine an i-th second LLR sequence based on the i-th first LLR sequence and at least one of the first (i-1) second LLR sequences, where i is an integer from 2 to T.

[0155] In a possible implementation, the degree of coupling of the code blocks is 2. The decoding module is particularly configured to determine the i-th second LLR sequence based on the i-th first LLR sequence and the (i-1)-th second LLR sequence.

[0156] In a possible implementation, the first second LLR sequence is the same as the first first LLR sequence.

[0157] In a possible implementation, the degree of coupling of the code block is 4. The decoding module is particularly configured to determine an i-th second LLR sequence based on the i-th first LLR sequence and the (i-2)-th second LLR sequence, where i is an integer from 3 to T.

[0158] In a possible implementation, the first second LLR sequence is the same as the first first LLR sequence, and the second second LLR sequence is the same as the second first LLR sequence.

[0159] In a possible implementation, the decoding module is particularly configured to: determine to obtain a Tth decoding result based on the Tth second LLR sequence; and determine an ith decoding result based on the ith second LLR sequence and at least one of the (i+1)th decoding result to the Tth decoding result, where i is an integer from 1 to T-1.

[0160] In a possible implementation, the degree of coupling of the code blocks is 2. The decoding module is particularly configured to determine an i-th decoding result based on the (i+1)-th decoding result, the (i+1)-th first LLR sequence, and the i-th second LLR sequence.

[0161] According to a ninth aspect, an embodiment of the present application provides an encoding device including a memory, a processor, and a computer program, the computer program being stored in the memory, and executed by the processor to perform the encoding method according to any implementation of the first aspect.

[0162] According to a tenth aspect, an embodiment of the present application provides an encoding device including a memory, a processor, and a computer program, the computer program being stored in the memory, and the processor executing the computer program to perform a decoding method according to any implementation of the second aspect.

[0163] According to an eleventh aspect, an embodiment of the present application provides an encoding device including a memory, a processor, and a computer program, the computer program being stored in the memory, and executed by the processor to perform the encoding method according to any implementation of the third aspect.

[0164] According to a twelfth aspect, an embodiment of the present application provides an encoding device including a memory, a processor, and a computer program, the computer program being stored in the memory, and executed by the processor to perform a decoding method according to any implementation of the fourth aspect.

[0165] According to a thirteenth aspect, an embodiment of the present application provides a storage medium, the storage medium including a computer program, the computer program being used to perform the encoding method according to any implementation of the first aspect.

[0166] According to a fourteenth aspect, an embodiment of the present application provides a storage medium, the storage medium including a computer program, the computer program being used to perform the decoding method according to any implementation of the second aspect.

[0167] According to a fifteenth aspect, an embodiment of the present application provides a storage medium, the storage medium including a computer program, the computer program being used to perform the encoding method according to any implementation of the third aspect.

[0168] According to a sixteenth aspect, an embodiment of the present application provides a storage medium, the storage medium including a computer program, the computer program being used to perform the decoding method according to any implementation of the fourth aspect.

[0169] According to a seventeenth aspect, an embodiment of the present application provides an encoding device. The encoding device may include an input interface and a logic circuit.

[0170] The input interface is configured to receive K bits to be encoded, where K is a positive integer.

[0171] The logic circuit is configured to: determine a first generator matrix, the first generator matrix including at least two sub-blocks distributed based on a predetermined positional relationship, the sub-block including a plurality of first generator matrix cores; generate a second generator matrix based on the first generator matrix, the second generator matrix including T sub-blocks, a positional relationship between two adjacent sub-blocks among the T sub-blocks being determined based on a predetermined positional relationship, T is a positive integer; and polar-encode the K bits to be encoded based on the second generator matrix to obtain encoded bits.

[0172] In a possible implementation, the logic circuitry may further execute an encoding method according to any implementation of the first aspect.

[0173] According to an eighteenth aspect, an embodiment of the present application provides a decoding device. The decoding device may include an input interface and a logic circuit.

[0174] The input interface is configured to receive the polar encoded bit information.

[0175] The logic circuit is configured to polar-decode the bit information based on a second generator matrix to obtain polar-decoded bits, where the second generator matrix is ​​generated based on a first generator matrix, the first generator matrix includes at least two sub-blocks distributed based on a preset positional relationship, the sub-blocks include a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and a positional relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset positional relationship, where T is a positive integer.

[0176] In a possible implementation, the logic circuitry may further perform a decoding method according to any implementation of the second aspect.

[0177] According to a nineteenth aspect, an embodiment of the present application provides a schematic diagram of a structure of an encoding device. The encoding device may include an input interface and a logic circuit.

[0178] The input interface is configured to receive K bits to be encoded, where K is a positive integer.

[0179] the logic circuit is configured to: determine a first generator matrix, the first generator matrix including a first matrix block and a second matrix block, the first matrix block being located in an upper left corner of the first generator matrix and the second matrix block being located in a lower right corner of the first generator matrix, the first matrix block being the same as the second matrix block, a distance between a first element in the first matrix block and a second element in the second matrix block is u in a diagonal direction of the first generator matrix, u being an integer greater than or equal to 1; determine a second generator matrix based on the coding length and the first generator matrix, the second generator matrix including T first generator matrices, the T first generator matrices being distributed along a diagonal of the second generator matrix, a first matrix block of an (a+1)th first generator matrix in the T first generator matrices overlaps with a second matrix block of an ath first generator matrix, a is an integer greater than or equal to 1, T is an integer greater than or equal to 2;

[0180] In a possible implementation, the logic circuitry may further perform an encoding method according to any implementation of the third aspect.

[0181] According to a twentieth aspect, an embodiment of the present application provides a decoding device. The decoding device may include an input interface and a logic circuit.

[0182] The input interface is configured to receive the polar encoded bit information.

[0183] The logic circuit is configured to polar-decode the bit information based on the second generator matrix to obtain polar-decoded bits. The second generator matrix is ​​generated based on the first generator matrix, the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at an upper left corner of the first generator matrix, the second matrix block is located at a lower right corner of the first generator matrix, the first matrix block is the same as the second matrix block, and a distance between a first element in the first matrix block and a second element in the second matrix block is u in a diagonal direction of the first generator matrix, where u is an integer equal to or greater than 1. The second generator matrix includes T first generator matrices, the T first generator matrices are distributed along a diagonal of the second generator matrix, and a first matrix block of an (a+1)th first generator matrix in the T first generator matrices overlaps with a second matrix block of an ath first generator matrix, where a is an integer equal to or greater than 1, and T is an integer equal to or greater than 2.

[0184] In a possible implementation, the logic circuitry may further perform a decoding method according to any implementation of the fourth aspect.

[0185] The embodiments of this application provide an encoding method and apparatus, a decoding method and apparatus, and a device. When K bits to be encoded need to be encoded, a first generator matrix is ​​first determined, and then a second generator matrix is ​​generated based on the first generator matrix, and the K bits to be encoded are polar-encoded based on the second generator matrix. The first generator matrix includes at least two sub-blocks distributed based on a preset positional relationship, each sub-block includes a plurality of first generator matrix cores, and the second generator matrix includes T sub-blocks, and the positional relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset positional relationship. Therefore, it can be seen that the second generator matrix includes a plurality of sub-blocks arranged according to the above-mentioned preset positional relationship, and each sub-block includes a plurality of first generator matrix cores. Therefore, the step of polar-encoding the K bits to be encoded based on the second generator matrix is ​​equivalent to the step of polar-encoding a plurality of short codes and combining the plurality of short codes to obtain an encoding result. This can reduce the complexity of encoding. When the codeword obtained by encoding based on the above-mentioned encoding method is decoded, the complexity of decoding can be reduced. [Brief description of the drawings]

[0186] [Figure 1] FIG. 1 is an architecture diagram of a communication system according to the present application. [Diagram 2] FIG. 2 is a diagram of an encoding according to an embodiment of the present application. [Diagram 3] 1 is a schematic flowchart of an encoding method according to an embodiment of the present application; [Figure 4] FIG. 2 is a schematic diagram of a sub-block according to an embodiment of the present application. [Figure 5A] FIG. 2 is a schematic diagram of a first generator matrix according to an embodiment of the present application. [Figure 5B] FIG. 13 is a schematic diagram of another first generator matrix according to an embodiment of the present application. [Figure 5C] FIG. 13 is a schematic diagram of yet another first generator matrix according to an embodiment of the present application. [Figure 6A] FIG. 2 is a schematic diagram of a second generator matrix according to an embodiment of the present application. [Figure 6B] FIG. 13 is a schematic diagram of another second generator matrix according to an embodiment of the present application. [Figure 6C] FIG. 13 is a schematic diagram of yet another second generator matrix according to an embodiment of the present application. [Figure 7A] FIG. 2 is a schematic diagram of a third generator matrix according to an embodiment of the present application. [Figure 7B] FIG. 13 is a schematic diagram of another third generator matrix according to an embodiment of the present application. [Figure 8A] FIG. 2 is a schematic diagram of a decoding process according to an embodiment of the present application; [Figure 8B] FIG. 2 is a schematic diagram of another decoding process according to an embodiment of the present application; [Figure 9A] FIG. 2 is another diagram of the encoding according to an embodiment of the present application. [Figure 9B] FIG. 2 is yet another diagram of encoding according to an embodiment of the present application. [Figure 9C] FIG. 2 is yet another diagram of encoding according to an embodiment of the present application. [Figure 10] 4 is a schematic flowchart of another encoding method according to an embodiment of the present application; [Figure 11A] FIG. 13 is a schematic diagram of yet another first generator matrix according to an embodiment of the present application. [Figure 11B] FIG. 13 is a schematic diagram of yet another first generator matrix according to an embodiment of the present application. [Figure 11C] FIG. 2 is a schematic diagram of a further first generator matrix according to an embodiment of the present application; [Figure 12A] FIG. 13 is a schematic diagram of yet another first generator matrix according to an embodiment of the present application. [Figure 12B] FIG. 13 is a schematic diagram of yet another first generator matrix according to an embodiment of the present application. [Figure 13] FIG. 13 is a schematic diagram of yet another second generator matrix according to an embodiment of the present application. [Figure 14]FIG. 2 is a schematic diagram of a process for generating a second generator matrix according to an embodiment of the present application. [Figure 15A] FIG. 13 is a schematic diagram of yet another second generator matrix according to an embodiment of the present application. [Figure 15B] FIG. 2 is a schematic diagram of a further second generator matrix according to an embodiment of the present application; [Figure 15C] FIG. 13 is a schematic diagram of yet another second generator matrix according to an embodiment of the present application. [Figure 16] FIG. 2 is a schematic diagram of a decoding according to an embodiment of the present application; [Figure 17] FIG. 2 is a schematic diagram of a decoding process according to an embodiment of the present application; [Figure 18] FIG. 2 is a schematic diagram of another decoding process according to an embodiment of the present application; [Figure 19] FIG. 2 is a schematic diagram of the decoding performance according to an embodiment of the present application; [Figure 20A] FIG. 2 is another schematic diagram of the decoding performance according to an embodiment of the present application; [Figure 20B] FIG. 13 is yet another schematic diagram of the decoding performance according to an embodiment of the present application. [Figure 21] 1 is a schematic diagram of the structure of an encoding device according to an embodiment of this application; [Figure 22] FIG. 2 is a schematic diagram of the structure of a decoding device according to an embodiment of this application; [Figure 23] FIG. 2 is a schematic diagram of the structure of another encoding device according to an embodiment of this application; [Figure 24] FIG. 2 is a schematic diagram of the structure of another decoding device according to an embodiment of this application; [Diagram 25] FIG. 13 is a schematic diagram of a hardware structure of yet another encoding device according to an embodiment of the present application. [Figure 26] FIG. 13 is a schematic diagram of a hardware structure of yet another decoding device according to an embodiment of the present application. [Figure 27] FIG. 2 is a schematic diagram of the structure of yet another encoding device according to an embodiment of the present application; [Figure 28] FIG. 2 is a schematic diagram of the structure of yet another decoding device according to an embodiment of the present application; [Figure 29] FIG. 1 is a schematic diagram of the structure of yet another encoding device according to an embodiment of this application; [Diagram 30] FIG. 2 is a schematic diagram of the structure of yet another decoding device according to an embodiment of the present application; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0187] The embodiments of this application may be used in various fields in which polar coding is used, such as data storage, optical network communication, and wireless communication. The wireless communication systems referred to in the embodiments of this application include, but are not limited to, a narrow band-internet of things (NB-IoT) system, a Wimax system, a long term evolution (LTE) system, and three application scenarios of the next generation 5G mobile communication system new radio (NR), namely enhanced mobile broadband (eMBB), ultra reliable low latency communication (URLLC), and massive machine-type communications (mMTC). Of course, there may be other fields in which polar coding is used, which is not particularly limited in this application. The embodiments of this application are applicable to communication scenarios with long code lengths, including but not limited to, for example, high throughput service scenarios, high definition video service scenarios, large file transfer service scenarios, and multimedia services such as virtual reality (VR) / augmented reality (AR for short) for wireless communication, and hybrid automatic repeat request (HARQ).

[0188] For ease of understanding, the following describes, with reference to FIG. 1, an architecture diagram of a communication system to which the embodiments of this application are applicable.

[0189] 1 is an architecture diagram of a communication system according to this application. Please refer to Fig. 1. A transmitting device 101 and a receiving device 102 are included.

[0190] Optionally, when the transmitting device 101 is a terminal device, the receiving device 102 is a network device. When the transmitting device 101 is a network device, the receiving device 102 is a terminal device.

[0191] Please refer to Fig. 1. The transmitting device 101 includes an encoder, so that the transmitting device 101 can perform polar encoding and output an encoded sequence. After being rate-matched, interleaved, and modulated, the encoded sequence is transmitted to the receiving device 102 through a channel. The receiving device 102 includes a decoder. The receiving device 102 can receive the signal transmitted by the transmitting device 101 and decode the received signal.

[0192] Note that FIG. 1 is merely an example of an architecture diagram of a communication system, and is not intended to limit the scope of the architecture diagram of a communication system.

[0193] For ease of understanding, the following describes the concepts in the embodiments of this application.

[0194] Terminal devices include, but are not limited to, mobile stations (MS), mobile terminals (MT), mobile telephones (MT), handsets, portable equipment, etc. Terminal devices can communicate with one or more core networks via radio access networks (RANs). For example, terminal devices may be mobile phones (also called "cell" phones), computers with wireless communication capabilities, etc. Alternatively, terminal devices may be portable, pocket-sized, handheld, computer-embedded, or vehicle-mounted mobile equipment or devices.

[0195] The network device is an evolved Node B ( evolved The network device may be a gNB, a transmission reception point (TRP), a micro base station, etc. in a 5G communication system, and the network device may be a relay station, an access point, an in-vehicle device, a wearable device, or a network device of a future evolved public land mobile network (PLMN), a base station of another network that integrates multiple technologies, a base station of various other evolved networks, etc.

[0196] Polar coding: Polar coding may alternatively be polar encoding / decoding, and polar coding may be described in the following two aspects.

[0197] In one aspect, the encoding process comprises generating a generator matrix, i.e.

number

[0198]

number

number

number

[0199] G N is the generator matrix, and G N is an N*N matrix,

number

number

number

[0200] In another aspect, the encoding process may be represented using an encoding diagram.

[0201] The encoding diagram will now be described with reference to FIG.

[0202] FIG. 2 is an encoding diagram according to one embodiment of this application. Please refer to FIG. 2. The encoding length corresponding to the encoding diagram is 8, and each circle in the first column represents one information bit or frozen bit, and u1, u2, ..., u8 shown in the first column are uncoded bits (information bits or frozen bits), where u4, u6, u7, u8 are information bits, and u1, u2, u3, u5 are frozen bits. Each circle in columns other than the first column represents one partial sum bit. x1, x2, ..., x8 in the last column are coding bits. Each butterfly diagram (shown on the right side of the figure) represents one polarization of 2 bits, i.e.

number

[0203] In the polar encoding process, a larger code length indicates a higher encoding complexity. For example, the complexity of polar encoding in current technology is O(N*log 2( N). To solve this technical problem, an embodiment of this application provides an encoding method. In the encoding process, a generator matrix corresponding to a short code can be processed to obtain a final generator matrix, and polar encoding is performed based on the final generator matrix. This is equivalent to polar encoding multiple short codes and combining the multiple short codes to obtain an encoding result. This can reduce the encoding complexity.

[0204] When the encoding is performed based on the final generator matrix, the encoding complexity can be reduced.

[0205] It should be noted that in this embodiment of the application, an example in which the starting coordinate (the coordinate of the upper left corner) of the matrix is ​​(1, 1) is used for explanation. Of course, the starting coordinate in the matrix may alternatively be (0, 0). This is not particularly limited in this embodiment of the application.

[0206] Figure 3 is a schematic flow chart of an encoding method according to an embodiment of this application. Please refer to Figure 3. The method may include the following steps.

[0207] S301: K bits to be coded are obtained.

[0208] K is a positive integer.

[0209] Optionally, the K bits to be encoded include information bits and frozen bits, or all of the K bits to be encoded are information bits.

[0210] S302: A first generator matrix is ​​determined.

[0211] The first generator matrix includes at least two sub-blocks distributed based on a preset positional relationship, and the sub-block includes a plurality of first generator matrix cores.

[0212] The first generator matrix core is G N and N=2 n where n is a positive integer. In the actual application process, the value of N can be set according to the actual requirements. For example, N may be a preset value.

[0213] The sub-block includes the first generator matrix core and the zero matrix (0 N (which can be expressed as: ). The size of the first generator matrix core is the same as the size of the zero matrix. For example, if the size of the first generator matrix core is N*N, the size of the zero matrix is ​​also N*N. For ease of explanation, in the following, the first generator matrix core or the zero matrix is ​​referred to as a sub-matrix.

[0214] In this embodiment of the application, it should be noted that the size of a matrix means that the matrix includes the number of rows and the number of columns, and the size of a matrix can be expressed as M*N (M is the number of rows of the matrix, and N is the number of columns of the matrix). If the matrix is ​​a square matrix, the size of the matrix may be expressed as the number of rows or the number of columns. For example, if the matrix has N rows and N columns, the size of the matrix may be expressed as N*N, or the size of the matrix may be expressed as N.

[0215] The sub-blocks will now be described with reference to FIG.

[0216] FIG. 4 is a schematic diagram of a sub-block according to this embodiment of this application. Please refer to FIG. 4. The sub-block includes multiple sub-matrices. In FIG. 4, an example in which the number of sub-matrices is 16 is used for explanation. Each sub-matrix includes N*N elements. For example, the elements may be 0 or 1. The sub-matrix is ​​G N or 0 N If N is equal to 2,

number

[0217] Optionally, a first generator matrix core (G N ) is included in the first diagonal of the sub-block. The first diagonal may be the main diagonal of the sub-block. For example, see FIG. 4. The sub-matrix located on the main diagonal of the sub-block is G N For example, the submatrices for coordinates (1, 1), (2, 2), (3, 3), and (4, 4) are G N It is.

[0218] Optionally, the multiple first generator matrix cores in the sub-block are distributed in a lower triangular manner. For example, see FIG. 4. N is distributed in the lower triangle.

[0219] Optionally, the distribution of the first generator matrix core in the sub-block is the same as the distribution of the first elements in the second generator matrix core. The first elements may be 1. The distribution of the elements in the second generator matrix core is

number

number

[0220] The sub-blocks will be described below using a concrete example.

[0221] Example 1: The second generator matrix core is

number

number

[0222] For N=2,

number

number

number

[0223] For N=4,

number

number

number

[0224] Example 2: The second generator matrix core is

number

number

[0225] For N=2,

number

number

number

[0226] The first generator matrix includes at least two sub-blocks that are distributed based on a preset positional relationship. Optionally, the number of sub-blocks included in the first generator matrix may be two.

[0227] Optionally, there is an overlap for at least two sub-blocks in the first generator matrix. For example, there is an overlap for every two adjacent sub-blocks in the first generator matrix. If the two adjacent sub-blocks are sub-block 1 and sub-block 2, an element in the lower right corner region of sub-block 1 overlaps with an element in the upper left corner region of sub-block 2.

[0228] For example, when the first generator matrix includes two sub-blocks (called sub-block 1 and sub-block 2), the preset positional relationship may be such that sub-block 1 is located in the upper left portion of the first generator matrix, sub-block 2 is located in the lower right portion of the first generator matrix, and the lower right corner region of sub-block 1 overlaps with the upper left corner region of sub-block 2.

[0229] Next, the first generator matrix will be described with reference to FIGS. 5A to 5C.

[0230] Figure 5A is a schematic diagram of a first generator matrix according to this embodiment of the present application. Figure 5B is a schematic diagram of another first generator matrix according to this embodiment of the present application. Figure 5C is a schematic diagram of yet another first generator matrix according to this embodiment of the present application.

[0231] Please refer to FIG. 5A. The first generator matrix includes two sub-blocks, which are indicated as the first sub-block and the second sub-block. The first sub-block is the same as the second sub-block. The first sub-block is located in the upper left part of the first generator matrix, and the second sub-block is located in the lower right part of the first generator matrix. The lower right corner region of the first sub-block overlaps with the upper left corner region of the second sub-block, and the distribution of elements in the lower right corner region of the first sub-block is the same as the distribution of elements in the upper left corner region of the second sub-block.

[0232] Refer to FIG. 5B. The first generator matrix includes a first sub-block and a second sub-block, and each of the first sub-block and the second sub-block is

number

number

[0233] Refer to FIG. 5C. The first generator matrix includes a first sub-block and a second sub-block, and each of the first sub-block and the second sub-block is

number

number

[0234] For ease of explanation and viewing, in Figs. 5B and 5C, NThe marks are omitted, i.e., all blank submatrices in Fig. 5B to Fig. 5C are 0 N It should be noted that

[0235] S303: A second generator matrix is ​​generated based on the first generator matrix.

[0236] The second generator matrix includes T sub-blocks, and a positional relationship between two adjacent sub-blocks among the T sub-blocks is determined based on a preset positional relationship, where T is a positive integer. Optionally, the positional relationship between two adjacent sub-blocks among the T sub-blocks is the same as the preset positional relationship.

[0237] The number T of sub-blocks included in the second generator matrix may be determined based on the first generator matrix, the size of the sub-blocks, and the coding length N', and the second generator matrix is ​​generated based on the first generator matrix and the number T.

[0238] Optionally, T is the smallest integer that enables a first condition to be satisfied, and the first condition is that the size of the second generator matrix is ​​equal to or greater than the coding length. The second generator matrix is ​​a square matrix, and the size of the second generator matrix may be represented by the number of rows or columns included in the second generator matrix, i.e., the size of the second generator matrix is ​​the number of rows or columns included in the second generator matrix.

[0239] For example, T satisfies the following relationship: v+(T-2)*u <N ’ ≦v+(T−1)*u, During the ceremony, v is the size of a subblock (the subblock is a square matrix, and v represents the number of rows or columns of elements contained in the subblock), N' is the coding length, N' is an integer greater than 1, and u is the distance between two adjacent subblocks. The distance between two adjacent subblocks may be represented by the distance (difference in row numbers or difference in column numbers) between the first elements in the two adjacent subblocks (e.g., the first element may be the element having coordinates (1, 1) in the subblock).

[0240] For example, if the size v of a sub-block is 512, the coding length N′ is 2048, and the distance u between two adjacent sub-blocks is 256, then T is 7.

[0241] For example, if the size v of a sub-block is 512, the coding length N′ is 1500, and the distance u between two adjacent sub-blocks is 256, then T is 5.

[0242] Hereinafter, the second generator matrix will be described using a specific example with reference to FIGS. 6A to 6C.

[0243] 6A is a schematic diagram of a second generator matrix according to this embodiment of the present application. Referring to FIG. 6A, the first generator matrix includes two sub-blocks, each of which includes 16 sub-matrices, and some of the sub-matrices are G N and some of the submatrices are 0 N FIG. 6A shows the positional relationship between the two sub-blocks.

[0244] When the size of each sub-matrix is ​​128 (including 128 rows and 128 columns), the size of the sub-block is 512, and the distance between two sub-blocks in the first generator matrix is ​​256. When the coding length N' is 2048, the second generator matrix includes seven sub-blocks, denoted as sub-block 1, sub-block 2, ..., sub-block 6, and sub-block 7. The positional relationship between every two adjacent sub-blocks in the seven sub-blocks is the same as the positional relationship between two sub-blocks in the first generator matrix. The size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 2048.

[0245] FIG. 6B is a schematic diagram of another second generator matrix according to this embodiment of the present application. Please refer to FIG. 6B. The first generator matrix includes two sub-blocks, each of which includes 16 sub-matrices, and some of the sub-matrices are G N and some of the submatrices are 0 N It is assumed that: Figure 6B shows the relative positions of the two sub-blocks.

[0246] When the size of each sub-matrix is ​​128 (including 128 rows and 128 columns), the size of the sub-block is 512, and the distance between two sub-blocks in the first generator matrix is ​​256. When the coding length N' is 1500, the second generator matrix includes five sub-blocks denoted as sub-block 1, sub-block 2, sub-block 3, sub-block 4, and sub-block 5, and the positional relationship between every two adjacent sub-blocks in the five sub-blocks is the same as the positional relationship between two sub-blocks in the first generator matrix. The size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 1536.

[0247] FIG. 6C is a schematic diagram of yet another second generator matrix according to this embodiment of the present application. Please refer to FIG. 6C. The first generator matrix includes two sub-blocks, each of which includes four sub-matrices, and some of the sub-matrices are G N and some of the submatrices are 0 N It is assumed that: Figure 6C shows the relative positions of the two sub-blocks.

[0248] When the size of each sub-matrix is ​​128 (including 128 rows and 128 columns), the size of the sub-block is 256, and the distance between two sub-blocks in the first generator matrix is ​​128. When the coding length N' is 1024, the second generator matrix includes seven sub-blocks, denoted as sub-block 1, sub-block 2, ..., sub-block 6, and sub-block 7. The positional relationship between every two adjacent sub-blocks in the seven sub-blocks is the same as the positional relationship between two sub-blocks in the first generator matrix. The size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 1024.

[0249] In FIG. 6A to FIG. 6C, N All submatrices except N For ease of explanation and viewing, the figures are N The marks are omitted, i.e., all blank submatrices in Figures 6A to 6C are 0 N It is.

[0250] 6A to 6C merely show an example of the second generator matrix, and do not limit the second generator matrix. Of course, there may be another second generator matrix as an alternative. This is not particularly limited in this embodiment of the present application.

[0251] S304: The K bits to be encoded are polar-encoded based on the second generator matrix to obtain encoded bits.

[0252] When the size of the second generator matrix is ​​equal to the coding length, the K bits to be coded are polar coded based on the second generator matrix to obtain coded bits.

[0253] When the size of the second generator matrix is ​​larger than the coding length, a third generator matrix is ​​first determined in the second generator matrix, and the K bits to be coded are polar coded based on the third generator matrix to obtain coded bits. The third generator matrix is ​​a matrix taken from the upper left corner area of ​​the second generator matrix, or the third generator matrix is ​​a matrix taken from the lower right corner area of ​​the second generator matrix. The third generator matrix is ​​a square matrix.

[0254] Next, the third generator matrix will be described with reference to FIGS. 7A and 7B.

[0255] Figure 7A is a schematic diagram of the third generator matrix according to this embodiment of this application. Please refer to Figure 7A. If the coding length is 1500 and the size of the second generator matrix is ​​1536, the matrix with size 1500 can be taken as the third generator matrix from the upper left corner area of ​​the second generator matrix.

[0256] Figure 7B is a schematic diagram of another third generator matrix according to this embodiment of this application. Please refer to Figure 7B. If the coding length is 1500 and the size of the second generator matrix is ​​1536, the matrix with size 1500 can be taken as the third generator matrix from the lower right corner area of ​​the second generator matrix.

[0257] When the K bits to be coded are polar coded, the K most reliable sub-channels may be determined from a plurality of sub-channels corresponding to the K bits to be coded, the positions of the K bits to be coded may be determined based on the K most reliable sub-channels, and the sequence to be coded may be determined based on the positions of the K bits to be coded, in which case the sequence to be coded includes the K bits to be coded and a frozen bit, and the sequence to be coded may be polar coded based on a second generator matrix to obtain the coded bits.

[0258] Optionally, the positions of the K bits to be coded are positions corresponding to the K subchannels with the highest reliability. After the positions of the K bits to be coded are determined, information bits (bits to be coded) are filled into the positions of the K bits to be coded, and frozen bits are filled into other positions to obtain a coded sequence. The coded sequence includes N' bits, where N' bits include K information bits and N'-K frozen bits.

[0259] For example, if the coding length is 8, the number of bits to be coded is 4, and the subchannels with the highest reliability among the 8 subchannels are subchannel 4, subchannel 6, subchannel 7, and subchannel 8, then the positions corresponding to subchannel 4, subchannel 6, subchannel 7, and subchannel 8 are used to carry information bits, and the other subchannels are used to carry frozen bits. In this case, the sequence to be coded may be 00010111, where 1 represents an information bit and 0 represents a frozen bit.

[0260] The K subchannels with the highest reliability may be determined in the following manner.

[0261] Method 1: P groups of subchannels are determined from the plurality of subchannels, where P is a positive integer. i The first subchannels are determined from the i-th group of subchannels based on the reliability of the i-th group of subchannels, and the K subchannels having the highest reliability include the first subchannels determined in each group of subchannels, and X i The first subchannels are the ones with the highest reliability in the i-th group of subchannels, i subchannels, i is an integer, 1≦i≦P, and X i is a positive integer,

number

[0262] Optionally, the number of subchannels included in a group of subchannels may be the same as the size of the submatrix, for example, if the size of the submatrix is ​​16, then the group of subchannels includes 16 subchannels.

[0263] Optionally, the number of subchannels included in the group of subchannels may be the same as the size of the subblock, for example, if the size of the subblock is 64, then the group of subchannels includes 64 subchannels.

[0264] The reliability of each group of sub-channels may be pre-calculated and stored. The reliability of each group of sub-channels may be stored in the following two ways.

[0265] Method 1: The ranking sequence of stored confidences is r = {r1, r2, ..., r N}, where r i represents the subchannel sequence number of a group of subchannels, and r in the r sequence i The position of is the subchannel r i , where a higher ranking may indicate a higher degree of trustworthiness.

[0266] For example, if a group of subchannels includes 8 subchannels, the sequence numbers of the 8 subchannels are 1, 2, ..., 7, and 8, and the reliability ranking sequence is r = {4, 5, 3, 6, 7, 2, 1, 8}, it indicates that the reliability of the 8 subchannels satisfies: subchannel 4 > subchannel 5 > subchannel 3 > subchannel 6 > subchannel 7 > subchannel 2 > subchannel 1 > subchannel 8.

[0267] Method 2: The stored confidence ranking sequence is w = {w1, w2, ..., w N}, wherein w i represents the reliability value of the i-th subchannel in the group of subchannels, and wi The larger the value of w, the higher the reliability of the i-th subchannel. i >w j If i i = 1 , it indicates that the reliability of the i th subchannel is greater than the reliability of the j th subchannel.

[0268] For example, if a group of subchannels contains eight subchannels and the ranking sequence of the confidence levels satisfies w={2.1, 3, 4.5, 5, 3.2, 2, 2.6, 7}, it indicates that the confidence levels of the eight subchannels are shown separately in Table 1.

[0269] [Table 1]

[0270] Optionally, the reliability rankings of the sub-channels in different groups may be the same or different. If the reliability rankings of the sub-channels in different groups are the same, the reliability of only one group of sub-channels may be stored.

[0271] Second method: The reliabilities of all subchannels corresponding to the coding length are calculated, the subchannels are sorted in descending order of the reliabilities of all subchannels, and the first K subchannels of the sorted subchannels are determined as the K subchannels with the highest reliabilities.

[0272] Optionally, the reliabilities of all subchannels corresponding to the coding length can be pre-computed and the sequences of the reliabilities are stored. If the maximum coding length supported by the protocol is N*T, T reliability sequences may be pre-computed and stored, where N is the size of the sub-matrix, and the lengths of the T reliability sequences are T, 2T, 3T, ..., and N*T.

[0273] In the actual application process, when the coding length N’ satisfies the following condition: t’ - 1 < N’ < t’, a pre-stored reliability sequence with a length of t’ * N can be selected, and K sub-channels with the highest reliability can be determined from the reliability sequence with a length of t’ * N.

[0274] The calculation of the sub-channel reliability shown in this embodiment of this application includes in-short-code reliability calculation and inter-short-code reliability calculation. The calculation of the reliability within the short code is the same as the existing calculation method.

[0275] Optionally, when the second generator matrix is different, the method for calculating the sub-channel reliability is also different. Hereinafter, with reference to FIGS. 8A to 8 FIG. B, a method for calculating the sub-channel reliability will be described using a specific example.

[0276] Example 1: Assume that the second generator matrix is the second generator matrix shown in FIG. 6C, and the coding corresponding to the second generator matrix can also be called 2 - combined coding.

[0277] Hereinafter, with reference to FIG. 8A, the sub-channel reliability determination process will be described.

[0278] FIG. 8A is a schematic diagram of a decoding process according to an embodiment of this application. Please refer to FIG. 8A.

Number

Number

Number

[0279] Please refer to FIG. 8A. First, the second reliability m1 of the first group of sub-channels is the first reliability m2 of the first group of sub-channels.

number

number

number

number

[0280] See FIG. 8A. Third reliability of the eighth group of sub-channels

number

number

number

number

number

number

[0281] Figure 8B is a schematic diagram of another decoding process according to an embodiment of this application. Please refer to Figure 8B.

number

[0282] first,

number

number

number

[0283] Next, m i but

number

number

[0284] Then, based on the above calculated parameters

number

number

[0285] Next, the final reliability of the subchannel

number

number

[0286] The encoding method in this application will now be described with reference to the encoding diagram.

[0287] Figure 9A is another diagram of the encoding according to this embodiment of the application. The second generator matrix corresponding to the encoding diagram is the second generator matrix of Figure 6C.

[0288] Please refer to Fig. 9A. Compared with the encoding diagram shown in Fig. 2, the leftmost block of Fig. 9A represents a diagram of encoding a short code, instead of representing one information bit or one frozen bit. For example, the code length of the short code may be the size N of the sub-matrix. The circles in each column except the first column represent one part and one bit vector, instead of one part and one bit.

[0289] In the encoding / decoding diagram above, the number of polarizations (the number of columns at each stage of the encoding / decoding diagram) for each short code of length N is log 2( Based on this, the short code is polarized twice more to obtain a long code of code length N'. Therefore, the number of polarizations of the long code of code length N' is log 2( N)+2, and the total encoding / decoding complexity is N'*(log 2(N' can be set to a constant that does not change with N', so when N' is very large, the constant term may be ignored and the encoding / decoding complexity is O(N').

[0290] The polar codes presented in this application may be referred to as combined polar codes. From the viewpoint of the encoding diagram, the diagram for encoding the combined polar code may be considered as a recombination or clipping of the original diagram for encoding the long polar code. The encoding diagram is described in detail below with reference to Figures 9B and 9C.

[0291] Figure 9B is yet another diagram of the encoding according to this embodiment of the present application, see Figure 9B. Several columns from the original diagram encoding the long polar code may be extracted and then combined to obtain a diagram encoding the combined polar code.

[0292] Figure 9C is yet another diagram of the encoding according to this embodiment of the application. Please refer to Figure 9C. Some rows and some columns may be extracted from the original diagram encoding the long polar code and then combined to obtain a diagram encoding the combined polar code.

[0293] After obtaining the coded bits, the transmitting end transmits the coded bits, which are then transmitted to the receiving end through a channel after being rate matched, interleaved and modulated.

[0294] According to the encoding method provided in this embodiment of the application, when K bits to be encoded need to be encoded, first, a first generator matrix is ​​determined, then a second generator matrix is ​​generated based on the first generator matrix, and the K bits to be encoded are polar-encoded based on the second generator matrix. The first generator matrix includes at least two sub-blocks distributed based on a preset positional relationship, each sub-block includes a plurality of first generator matrix cores, and the second generator matrix includes T sub-blocks, and the positional relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset positional relationship. Therefore, it can be seen that the second generator matrix includes a plurality of sub-blocks arranged according to the aforementioned preset positional relationship, each sub-block includes a plurality of first generator matrix cores. Therefore, the step of polar-encoding the K bits to be encoded based on the second generator matrix is ​​equivalent to the step of polar-encoding a plurality of short codes and combining the plurality of short codes to obtain an encoding result. This can reduce the complexity of encoding.

[0295] Next, another encoding method will be described with reference to FIG.

[0296] Figure 10 is a schematic flow chart of another encoding method according to an embodiment of this application. Please refer to Figure 10. The method may include the following steps.

[0297] S1001: K bits to be coded are obtained.

[0298] K is a positive integer.

[0299] For the process of step S1001, see step S301, and the details will not be repeated here.

[0300] S1002: A first generator matrix is ​​determined.

[0301] It should be noted that the first generator matrix in the embodiment of Figure 10 is equivalent to the sub-blocks in the embodiment of Figure 3, and the description of the sub-blocks in the embodiment of Figure 3 is applicable to the first generator matrix in the embodiment of Figure 10. Details will not be repeated here.

[0302] The first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located in the upper left corner of the first generator matrix, the second matrix block is located in the lower right corner of the first generator matrix, the first matrix block is the same as the second matrix block, and the distance between a first element in the first matrix block and a second element in the second matrix block (hereinafter, may be abbreviated to the distance between the first matrix block and the second matrix block) is u in the diagonal direction of the first generator matrix, where u is an integer greater than or equal to 1.

[0303] Optionally, the first element may be an upper left corner element of the first matrix block, and the second element may be an upper left corner element of the second generator matrix. The distance between the first element and the second element is the difference between the row numbers of the first element and the second element, or the difference between the column numbers of the first element and the second element. For example, the first element is 0 or 1.

[0304] All elements in the first generator matrix may be zero elements, except for the first matrix block and the second matrix block.

[0305] Optionally, the first matrix block and the second matrix block may include one or more sub-matrices, the sub-matrices being G N or 0 N Each of the first matrix block and the second matrix block may be a square matrix. G N and 0 N For an explanation, please refer to the embodiment shown in FIG.

[0306] The first generation matrix satisfies self-similarity (or what is called shift self-similarity). Self-similarity means that after the first matrix block within the first generation matrix moves by a preset distance (for example, moves along the main diagonal of the first generation matrix), the first matrix block can move to the position of the second matrix block, and the content within the first matrix block is the same as the content within the second matrix block. When the first generation matrix has self-similarity, the elements of the first generation matrix satisfy a i,j =a i+u,j+u where i is an integer, j is an integer, v is the size of the first generation matrix, u is an integer, 1 ≤ i < v, 1 ≤ j < v, 1 < i + u ≤ v, and 1 < j + u ≤ v.

[0307] Hereinafter, with reference to FIGS. 11A to 11C, it will be described that the first generation matrix includes a first matrix block and a second matrix block.

[0308] FIG. 11A is a schematic diagram of still another first generation matrix according to this embodiment of this application. Refer to FIG. 11A. The first generation matrix includes a first matrix block and a second matrix block. The first matrix block is located at the upper left corner (or what is called the upper left corner region) of the first generation matrix, and the second matrix block is located at the lower right corner (or what is called the lower right corner region) of the first generation matrix. The first matrix block is the same as the second matrix block. The first generation matrix and the second generation matrix overlap with each other.

[0309] FIG. 11B is a schematic diagram of yet another first generator matrix according to this embodiment of this application. Please refer to FIG. 11B. The first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner (or called upper left corner region) of the first generator matrix, and the second matrix block is located at the lower right corner (or called lower right corner region) of the first generator matrix. The first matrix block is the same as the second matrix block. There is a certain distance between the first generator matrix and the second generator matrix, that is, there is a certain distance between the element at the lower right corner (element 1 for short) of the first generator matrix and the element at the upper left corner (element 2 for short) of the second generator matrix. For example, the difference between the row numbers of element 2 and element 1 is greater than 1.

[0310] FIG. 11C is a schematic diagram of a further first generator matrix according to this embodiment of this application. Please refer to FIG. 11C. The first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner (or called the upper left corner region) of the first generator matrix, and the second matrix block is located at the lower right corner (or called the lower right corner region) of the first generator matrix. The first matrix block is the same as the second matrix block. The first generator matrix is ​​adjacent to the second generator matrix, that is, the element at the lower right corner (element 1 for short) of the first generator matrix is ​​adjacent to the element at the upper left corner (element 2 for short) of the second generator matrix. For example, the row number of element 2 is one greater than the row number of element 1, and the column number of element 2 is one greater than the column number of element 1.

[0311] Optionally, the elements of the first generator matrix are symmetric along a secondary diagonal of the first generator matrix.

[0312] The following illustrates the first generator matrix using a concrete example.

[0313] FIG. 12A is a schematic diagram of yet another first generator matrix according to this embodiment of the present application. Please refer to FIG. 12A. The first generator matrix includes a first matrix block and a second matrix block, and each of the first matrix block and the second matrix block is a G NIf N is 128, the distance between the first matrix block and the second matrix block is 128.

[0314] Figure 12B is a schematic diagram of yet another first generator matrix according to this embodiment of the present application. Referring to Figure 12B, the first generator matrix includes a first matrix block and a second matrix block, and each of the first matrix block and the second matrix block includes four sub-matrices. When N is 128, the distance between the first matrix block and the second matrix block is 256.

[0315] For ease of explanation and viewing, in FIGS. 12A and 12B, the N The marks are omitted, i.e., all blank submatrices in Fig. 12A and Fig. 12B are set to 0. N It should be noted that Figures 12A and 12B merely show an example of the first generator matrix, and do not limit the first generator matrix.

[0316] S1003: A second generator matrix is ​​determined based on the coding length and the first generator matrix.

[0317] The second generator matrix includes T first generator matrices, the T first generator matrices are distributed along a diagonal (which may be a main diagonal) of the second generator matrix, a first matrix block of an (a+1)th first generator matrix among the T first generator matrices overlaps with a second matrix block of an ath first generator matrix, a is an integer greater than or equal to 1, and T is an integer greater than or equal to 2.

[0318] Next, the second generator matrix will be described with reference to FIG.

[0319] FIG. 13 is a schematic diagram of yet another second generator matrix according to this embodiment of this application. Please refer to FIG. 13. The second generator matrix includes five first generator matrices. The five first generator matrices are distributed along the main diagonal of the second generator matrix, and the reference numbers of the first generator matrices increase continuously in the downward and rightward extension direction of the main diagonal of the second generator matrix, and the matrix in the upper left corner of the second generator matrix is ​​the first first generator matrix. For example, please refer to FIG. 13. The first generator matrix indicated by reference number 1 is the first first generator matrix, the first generator matrix indicated by reference number 2 is the second first generator matrix, and the method is applied by analogy. The first generator matrix indicated by reference number 5 is the fifth first generator matrix.

[0320] See Figure 13. The second matrix block of the first first generator matrix overlaps with the first matrix block of the second first generator matrix. The second matrix block of the second first generator matrix overlaps with the first matrix block of the third first generator matrix. The second matrix block of the third first generator matrix overlaps with the first matrix block of the fourth first generator matrix. The second matrix block of the fourth first generator matrix overlaps with the first matrix block of the fifth first generator matrix.

[0321] T is the smallest integer that enables the first condition to be satisfied, and the first condition is that the size of the second generator matrix is ​​greater than or equal to the coding length.

[0322] For example, T satisfies the following relationship: v+(T-2)*u <N ’ ≦v+(T-1)*u, in the formula, v is the size of the first generator matrix, and N′ is the coding length, where N′ is an integer greater than 1.

[0323] For example, if the size v of the first generator matrix is ​​512, the coding length N′ is 2048, and the distance u between two adjacent sub-blocks is 256, then T is 7.

[0324] For example, if the size v of the first generator matrix is ​​512, the coding length N′ is 1500, and the distance u between two adjacent sub-blocks is 256, then T is 5.

[0325] Optionally, the number T of first generator matrices included in the second generator matrix may be determined based on the coding length and the first generator matrix, and then the second generator matrix is ​​generated based on the first generator matrix and the number T. For example, the first generator matrix may be copied and moved T-1 times in the direction of the main diagonal of the first generator matrix to obtain the second generator matrix. The distance moved once is u, and the moving distance is the number of moved rows or columns. For example, if three rows are moved, the moving distance is 3.

[0326] Next, a process of generating a second generator matrix based on a first generator matrix will be described with reference to FIG.

[0327] FIG. 14 is a schematic diagram of a process for generating a second generator matrix according to this embodiment of the present application. Please refer to FIG. 14. The first generator matrix includes 16 sub-matrices, some of the sub-matrices are G N and some of the submatrices are 0 N The first generator matrix satisfies self-similarity, and the distance (row interval or column interval) between the first matrix block and the second matrix block in the first generator matrix is ​​u. If it is determined that the second generator matrix contains three first generator matrices, the first generator matrix needs to be copied and moved twice.

[0328] Please refer to Figure 14. In the first copy and move process, the first generator matrix 1 is copied, and the copied first generator matrix 1 is shifted by u rows in the main diagonal direction (the diagonal distance corresponding to the u rows is

number

[0329] Please refer to FIG. 14. In the second copy and shift process, the first generator matrix 2 is copied, and the copied first generator matrix 2 is shifted by u rows in the diagonal direction (the diagonal distance corresponding to the u rows is

number

[0330] The second generator matrix is ​​determined to include first generator matrix 1, first generator matrix 2, and first generator matrix 3.

[0331] It should be noted that FIG. 14 merely illustrates an exemplary method for generating a second generator matrix based on a first generator matrix, and is not intended to limit the method. In FIG. 14, G N All submatrices except N For ease of explanation and viewing, the figure shows N The marks are omitted, i.e., all blank submatrices in Fig. 14 are 0 N It is.

[0332] Hereinafter, the second generator matrix will be described using a specific example with reference to FIGS. 15A to 15C.

[0333] FIG. 15A is a schematic diagram of yet another second generator matrix according to this embodiment of the present application. Please refer to FIG. 15A. The first generator matrix includes 16 sub-matrices, some of the sub-matrices are G N and some of the submatrices are 0 N The first generator matrix satisfies the self-similarity property.

[0334] When the size of each sub-matrix is ​​128 (including 128 rows and 128 columns), the size of the sub-block is 512, and the distance between two sub-blocks in the first generator matrix is ​​256. When the coding length N' is 2048, the second generator matrix includes seven first generator matrices, and for every two adjacent generator matrices of the seven first generator matrices, a first matrix block of the latter first generator matrix overlaps with a second matrix block of the former first generator matrix, and the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 2048.

[0335] FIG. 15B is a schematic diagram of a further second generator matrix according to this embodiment of the present application. See FIG. 15B. The first generator matrix includes 16 sub-matrices, some of which are G N and some of the submatrices are 0 N The first generator matrix satisfies the self-similarity property.

[0336] When the size of each sub-matrix is ​​128 (including 128 rows and 128 columns), the size of the sub-block is 512, and the distance between two sub-blocks in the first generator matrix is ​​256. When the coding length N' is 1500, the second generator matrix includes five first generator matrices, and for every two adjacent generator matrices of the five first generator matrices, a first matrix block of the latter first generator matrix overlaps with a second matrix block of the former first generator matrix, and the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 1536.

[0337] FIG. 15C is a schematic diagram of yet another second generator matrix according to this embodiment of the present application. See FIG. 15C. The first generator matrix includes 16 sub-matrices, some of which are G N and some of the submatrices are 0 N The first generator matrix satisfies the self-similarity property.

[0338] When the size of each sub-matrix is ​​128 (including 128 rows and 128 columns), the size of the sub-block is 256, and the distance between two sub-blocks in the first generator matrix is ​​128. When the coding length N' is 1024, the second generator matrix includes seven first generator matrices, and for every two adjacent generator matrices of the seven first generator matrices, a first matrix block of the latter first generator matrix overlaps with a second matrix block of the former first generator matrix, and the size of the second generator matrix (the number of rows or columns included in the second generator matrix) is 1024.

[0339] In FIG. 15A to FIG. 15C, G N All submatrices except N For ease of explanation and viewing, the figures are N The marks are omitted, that is, all blank submatrices in Figures 15A to 15C are 0 N It is.

[0340] S1004: The K bits to be encoded are polar-encoded based on the second generator matrix to obtain encoded bits.

[0341] For the process of performing step S1004, please refer to step S304, and the details will not be repeated here.

[0342] According to the encoding method provided in this embodiment of the present application, when K bits to be encoded need to be encoded, a first generator matrix is ​​first determined, then a second generator matrix is ​​generated according to the first generator matrix, and the K bits to be encoded are polar-encoded according to the second generator matrix. Since the first generator matrix has self-similarity and the second generator matrix includes a plurality of first matrix blocks, polar-encoding the K bits to be encoded according to the second generator matrix is ​​equivalent to polar-encoding a plurality of short codes and combining the plurality of short codes to obtain an encoding result. This can reduce the complexity of encoding.

[0343] Based on any one of the above encoding methods, the following describes a decoding method based on the above encoding methods.

[0344] Figure 16 is a schematic diagram of decoding according to one embodiment of this application. Please refer to Figure 16. The method may include the following steps.

[0345] S1601: Polar-encoded bit information is received.

[0346] The bit information includes a sequence of N' first log-likelihood ratios (LLRs), where N' is a positive integer. For example, after receiving a signal, the receiving end performs processing such as demodulation on the signal to obtain N' first LLRs, and performs polar decoding based on the received N' first LLRs. Whether the transmitting end transmits bit 1 or bit 0, the receiving end may make an incorrect decision. Given a signal r, the likelihood ratio is the ratio of the probability p(r|b=0) of correctly determining 0 by the receiving end to the probability p(r|b=1)] of correctly determining 1 by the receiving end. To facilitate the computation process, the likelihood ratio is a natural logarithm. In this case, the log-likelihood ratio can be calculated, i.e., LLR=ln [p(r|b=0) / p(r|b=1)]. The LLR may be a floating-point number.

[0347] S1602: Polar-decode bit information based on the second generator matrix to obtain polar-decoded bits.

[0348] Optionally, the second generator matrix is ​​a polar encoding matrix in the embodiment of Figure 3. For a related description of the second generator matrix, please refer to the embodiment shown in Figure 3. Details are not repeated here.

[0349] Optionally, the second generator matrix is ​​a polar encoding matrix in the embodiment of Figure 10. For a related description of the second generator matrix, please refer to the embodiment shown in Figure 10. Details are not repeated here.

[0350] In the embodiment shown in Figure 3 or Figure 10, the coded sequence includes N' uncoded bits, which include K information bits and N'-K frozen bits. The N' bits may include T groups of uncoded bits, each group of uncoded bits includes N uncoded bits, i.e., N'=N*T.

[0351] The N′ first LLRs include T first LLR sequences. In other words, the N′ first LLRs may be divided into T first LLR sequences, where one of the first LLR sequences includes N LLRs.

[0352] One of the first LLR sequences may be associated with two or more groups of uncoded bits. For example, if the coded sequence includes eight groups of uncoded bits and FIG. 6C shows the second generator matrix, the N′ first LLRs include eight first LLR sequences, and Table 2 shows the relationship between the eight first LLR sequences and the groups of uncoded bits.

[0353] [Table 2]

[0354] See Table 2. The first LLR sequence 1 is associated with a first group of uncoded bits and a second group of uncoded bits, the first LLR sequence 2 is associated with a second group of uncoded bits and a third group of uncoded bits, and the method is applied by analogy.

[0355] To perform accurate decoding, the first LLR sequence may be separated to obtain second LLR sequences corresponding to each first LLR sequence, so that each 1 / 2 LLR sequence corresponds to one group of uncoded bits. For example, the first LLR sequence shown in Table 2 is separated to obtain eight second LLR sequences. Table 3 shows the relationship between the eight second LLR sequences and the groups of uncoded bits.

[0356] [Table 3]

[0357] See Table 2. The first LLR sequence 1 is associated with a first group of uncoded bits, and the first LLR sequence 2 is associated with a second group of uncoded bits, and the method is applied by analogy.

[0358] Optionally, the second LLR sequence may be determined based on the first LLR sequence in the following manner, namely, by determining the i-th second LLR sequence based on the i-th first LLR sequence and at least one of the first (i-1) second LLR sequences, where i is an integer from 2 to T.

[0359] Optionally, polar decoding may be performed based on T second LLR sequences in the following manner: determining to obtain a Tth decoding result based on the Tth second LLR sequence; and determining the ith decoding result based on the ith second LLR sequence and at least one of the (i+1)th decoding result to the Tth decoding result, where i is an integer from 1 to T-1.

[0360] A specific example will now be used to describe the process of determining second LLR sequences and performing polar decoding based on the T second LLR sequences.

[0361] Example 1: It is assumed that the second generator matrix is ​​the second generator matrix shown in FIG. 6C, and the coding corresponding to the second generator matrix may also be called 2-joint coding.

[0362] The i-th second LLR sequence may be determined in the following manner, i.e., by determining the i-th second LLR sequence based on the i-th first LLR sequence and the (i-1)-th second LLR sequence, where the 1-th second LLR sequence is the same as the 1-th first LLR sequence.

[0363] The i-th decoding result may be determined in the following manner: determining the i-th decoding result based on the (i+1)-th decoding result, the (i+1)-th first LLR sequence, and the i-th second LLR sequence.

[0364] Hereinafter, with reference to FIG. 17, a decoding process corresponding to the above-mentioned second generator matrix will be described.

[0365] Figure 17 is a schematic diagram of the decoding process according to this embodiment of the present application.

number

number

[0366] After receiving the N'LLR, the receiving end divides the received N'LLR into eight first LLR sequences, and the eight first LLR sequences are represented as:

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[0367] Refer to FIG. 17. First, the first secondary LLR sequence l1 is determined, and the first secondary LLR sequence l1 and the second primary LLR sequence l2 are

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[0368] Referring to FIG. 17, to obtain an eighth decoded result u8, an eighth second LLR sequence l8 is first input to the decoder for decoding, where u8 includes N decoded bits. u8 is coded to obtain an eighth coded bit sequence c8. c8,

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[0369] Example 2: It is assumed that the second generator matrix is ​​the second generator matrix shown in FIG. 14, and the coding corresponding to the second generator matrix may also be called 4-joint coding.

[0370] The i-th second LLR sequence may be determined in the following manner: determining the i-th second LLR sequence based on the i-th first LLR sequence and the (i-2)-th second LLR sequence, where i is an integer from 3 to T. The 1st second LLR sequence is the same as the 1st first LLR sequence, and the 2nd second LLR sequence is the same as the 2nd first LLR sequence.

[0371] Hereinafter, with reference to FIG. 18, a decoding process corresponding to the above-mentioned second generator matrix will be described.

[0372] 18 is a schematic diagram of another decoding process according to this embodiment of the present application. The f operation in FIG. 18 may be the same as the g operation in FIG.

[0373] Please refer to Figure 17.

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[0374] first,

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[0375] Next, l i but

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[0376] Then, decoding is performed based on the above calculated parameters, and l8 is input to a decoder for decoding to obtain an eighth decoding result u8, where u8 includes N decoded bits. u8 is coded to obtain an eighth coded bit sequence c8.

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[0377] The decoding performance of the decoding method in this application will be described below with reference to FIG.

[0378] 19 is a schematic diagram of the decoding performance according to one embodiment of this application. Please refer to FIG 19. The horizontal axis represents the signal to noise ratio (SNR), and the vertical axis represents the Block Error Rate (BLER).

[0379] Please refer to Figure 19. When the code length is 2048, the number of information bits is 1024, and no combining is performed (existing method), the dashed line shows the performance curve. When the code length is 16384, the number of information bits K is 8129, and two combining operations are performed (for example, Figure 6C shows the second generator matrix), the solid line shows the performance curve. It can be seen from Figure 19 that the performance gain can be about 1 dB with the method shown in this application.

[0380] In the practical application process, compared with the long polar code, the combined polar code has less complexity without performance loss. When the code length increases to a certain value, the combination in the wider range cannot bring about a large performance gain. The following description will be given with reference to FIG. 20A.

[0381] Figure 20A is another schematic diagram of the decoding performance according to this embodiment of this application. Please refer to Figure 20A. When code length is 65536, the number of information bits K is 32768, and no combining is performed (existing method), the solid line shows the performance curve. When code length is 65536, the number of information bits K is 32768, and two combining operations are performed (for example, Figure 6C shows the second generator matrix), the dashed line shows the performance curve. When code length is 65536, the number of information bits K is 32768, and four combining operations are performed (for example, Figure 14 shows the second generator matrix), another dashed line shows the performance curve.

[0382] Figure 20B is yet another schematic diagram of the decoding performance according to this embodiment of this application. Please refer to Figure 20B. When code length is 131072, the number K of information bits is 65536, and no combining is performed (existing method), the solid line shows the performance curve. When code length is 131072, the number K of information bits is 65536, and two-combining operation is performed (for example, Figure 6C shows the second generator matrix), the dashed line shows the performance curve. When code length is 131072, the number K of information bits is 65536, and four-combining operation is performed (for example, Figure 14 shows the second generator matrix), another dashed line shows the performance curve.

[0383] When the coupling range is larger, the coding / decoding complexity is higher.Furthermore, it can be seen from Figures 20A and 20B that the coupling range or width can be limited to a certain extent, or an appropriate coupling degree can be selected, so that the complexity of software and hardware implementation can be reduced as much as possible without performance loss.

[0384] Figure 21 is a schematic diagram of the structure of an encoding device according to an embodiment of this application. Please refer to Figure 21. The encoding device 10 can include: an acquisition module 11, a decision module 12, a generation module 13, and an encoding module 14.

[0385] The obtaining module 11 is configured to obtain K bits to be coded, where K is a positive integer.

[0386] The determination module 12 is configured to determine a first generator matrix, the first generator matrix including at least two sub-blocks distributed based on a preset positional relationship, and the sub-blocks including a plurality of first generator matrix cores.

[0387] The generating module 13 is configured to generate a second generating matrix based on the first generating matrix, the second generating matrix including T sub-blocks, and a positional relationship between two adjacent sub-blocks among the T sub-blocks is determined based on a preset positional relationship, where T is a positive integer.

[0388] The encoding module 14 is configured to polar-code the K bits to be encoded based on the second generator matrix to obtain coded bits.

[0389] Optionally, the acquisition module 11 may perform step S301 in the embodiment of FIG.

[0390] Optionally, the decision module 12 may perform step S302 in the embodiment of FIG.

[0391] Optionally, the generation module 13 may perform step S303 in the embodiment of FIG.

[0392] Optionally, the encoding module 13 may perform step S304 in the embodiment of FIG.

[0393] It should be noted that the encoding device shown in this embodiment of this application can implement the technical solution shown in the above method embodiment. The implementation principle and its beneficial effects are similar to those of the method embodiment. Details are not repeated here.

[0394] In a possible implementation, the positional relationship between two adjacent sub-blocks among the T sub-blocks is the same as a preset positional relationship.

[0395] In a possible implementation, there is an overlap in at least two of the sub-blocks.

[0396] In a possible implementation, the first diagonal of the sub-block contains the first generator matrix core.

[0397] In a possible implementation, the multiple first generator matrix cores within a sub-block are distributed in a lower triangular fashion.

[0398] In a possible implementation, the distribution of the first generator matrix core within the sub-block is the same as the distribution of the first elements within the second generator matrix core, the number of elements contained in the second generator matrix core is the same as the number of sub-matrices contained in the sub-block, and the sub-matrix contained in the sub-block is the first generator matrix core or a zero matrix.

[0399] In a possible implementation, the first generator matrix includes two sub-blocks.

[0400] In a possible implementation, the number of sub-matrices included in the sub-block is 2*2, and the sub-matrix included in the sub-block is the first generator matrix core or a zero matrix.

[0401] In a possible implementation, the first generator matrix includes a first sub-block and a second sub-block, a first sub-matrix in the first sub-block overlaps with a second sub-matrix in the second sub-block, and the coordinates of the first sub-matrix in the first sub-block are (2, 2) and the coordinates of the second sub-matrix in the second sub-block are (1, 1).

[0402] In a possible implementation, the number of sub-matrices included in the sub-block is 4*4, and the sub-matrix included in the sub-block is the first generator matrix core or a zero matrix.

[0403] In a possible implementation, the first generator matrix includes a first sub-block and a second sub-block, and four first sub-matrices in the first sub-block overlap with four second sub-matrices in the second sub-block.

[0404] The coordinates of the four first sub-matrices in the first sub-block are (3,3), (3,4), (4,3), and (4,4); and The coordinates of the four second sub-matrices in the second sub-block are (1,1), (1,2), (2,1), and (2,2).

[0405] In a possible implementation, the K bits to be coded are information bits. The coding module 14: determining K sub-channels having the highest reliability among a plurality of sub-channels corresponding to the K bits to be coded; determining positions of the K bits to be coded based on the K most reliable subchannels; determining a sequence to be coded based on the positions of the K bits to be coded; The encoding target sequence includes K encoding target bits and frozen bits, and the encoding target sequence is polar-encoded based on a second generator matrix to obtain encoded bits; The device is specifically configured as follows.

[0406] In a possible implementation, the plurality of subchannels includes P groups of subchannels, where P is a positive integer. From the i-th group of subchannels, X is calculated based on the confidence of the i-th group of subchannels. i determining a first sub-channel; X i The first subchannels X have the highest reliability in the i-th group of subchannels. i subchannels, i is an integer, 1≦i≦P, and X i is a positive integer,

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[0407] The K subchannels with the highest reliability include the first subchannel.

[0408] It should be noted that the encoding device shown in this embodiment of this application can implement the technical solution shown in the above method embodiment. The implementation principle and its beneficial effects are similar to those of the method embodiment. Details are not repeated here.

[0409] 22 is a schematic diagram of a structure of a decoding device according to an embodiment of this application, please refer to FIG 22. The decoding device 20 may include: a receiving module 21 and a decoding module 22.

[0410] The receiving module 21 is configured to receive the polar encoded bit information.

[0411] The decoding module 22 is configured to polar decode the bit information based on the second generator matrix to obtain polar decoded bits.

[0412] The second generator matrix is ​​generated based on the first generator matrix, the first generator matrix includes at least two sub-blocks distributed based on a predetermined positional relationship, the sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and a positional relationship between two adjacent sub-blocks among the T sub-blocks is determined based on the predetermined positional relationship, where T is a positive integer.

[0413] Optionally, the receiving module 21 may perform step S1601 in the embodiment of FIG.

[0414] Optionally, the decoding module 22 may perform step S1602 in the embodiment of FIG.

[0415] As shown in this embodiment of the present application Decryption It should be noted that the device can implement the technical solutions shown in the above method embodiments. The implementation principles and its beneficial effects are similar to those of the method embodiments. Details are not repeated here.

[0416] In a possible implementation, the positional relationship between two adjacent sub-blocks among the T sub-blocks is the same as a preset positional relationship.

[0417] In a possible implementation, there is an overlap in at least two of the sub-blocks.

[0418] In a possible implementation, the first diagonal of the sub-block contains the first generator matrix core.

[0419] In a possible implementation, the multiple first generator matrix cores within a sub-block are distributed in a lower triangular fashion.

[0420] In a possible implementation, the distribution of the first generator matrix core within the sub-block is the same as the distribution of the first elements within the second generator matrix core, the number of elements contained in the second generator matrix core is the same as the number of elements contained in the sub-block, and the elements contained in the sub-block are the first generator matrix core or a zero matrix.

[0421] In a possible implementation, the first generator matrix includes two sub-blocks.

[0422] In a possible implementation, the number of elements contained in the sub-block is 2*2, and the elements contained in the sub-block are the first generator matrix core or zero matrices.

[0423] In a possible implementation, the first generator matrix includes a first sub-block and a second sub-block, a first element in the first sub-block overlaps with a second element in the second sub-block, and The coordinates of the first element in the first sub-block are (2, 2), and the coordinates of the second element in the second sub-block are (1, 1).

[0424] In a possible implementation, the number of elements contained in the sub-block is 4*4, and the elements contained in the sub-block are the first generator matrix core or zero matrices.

[0425] In a possible implementation, the first generator matrix includes a first sub-block and a second sub-block, and four first elements in the first sub-block overlap with four second elements in the second sub-block.

[0426] The coordinates of the four first elements in the first sub-block are (3,3), (3,4), (4,3), and (4,4); and The coordinates of the four second elements in the second sub-block are (1,1), (1,2), (2,1), and (2,2).

[0427] In a possible implementation, the bit information comprises N' first log-likelihood ratio (LLR) sequences, where N' is a positive integer.

[0428] In a possible implementation, the N′ first LLRs include a sequence of T first LLRs, and the sequence of first LLRs includes at least two first LLRs. determining T second LLR sequences corresponding to the T first LLR sequences, one of the first LLR sequences corresponding to one or more groups of uncoded bits and one of the second LLR sequences corresponding to one group of uncoded bits; and performing polar decoding based on the T second LLR sequences; The device is specifically configured as follows.

[0429] In a possible implementation, the decoding module 22: determining an i-th second LLR sequence based on the i-th first LLR sequence and at least one of the first (i-1) second LLR sequences, where i is an integer from 2 to T; The device is specifically configured as follows.

[0430] In a possible implementation, the degree of connectivity of the code blocks is 2. The decoding module 22: determining an i-th second LLR sequence based on the i-th first LLR sequence and the (i-1)-th second LLR sequence; The device is specifically configured as follows.

[0431] In a possible implementation, the first second LLR sequence is the same as the first first LLR sequence.

[0432] In a possible implementation, the degree of connectivity of the code blocks is 4. The decoding module 22: Determine an i-th second LLR sequence based on the i-th first LLR sequence and the (i-2)-th second LLR sequence, where i is an integer from 3 to T; The device is specifically configured as follows.

[0433] In a possible implementation, the first second LLR sequence is the same as the first first LLR sequence; The second second LLR sequence is the same as the second first LLR sequence.

[0434] In a possible implementation, the decoding module 22: Determine to obtain a T-th decoding result based on the T-th second LLR sequence; and determining an i-th decoding result based on the i-th second LLR sequence and at least one of the (i+1)-th decoding result to the T-th decoding result, where i is an integer from 1 to T-1. The device is specifically configured as follows.

[0435] In a possible implementation, the degree of connectivity of the code blocks is 2. The decoding module 22: determining an i-th decoding result based on the (i+1)-th decoding result, the (i+1)-th first LLR sequence, and the i-th second LLR sequence; The device is specifically configured as follows.

[0436] As shown in this embodiment of the present application Decryption It should be noted that the device can implement the technical solutions shown in the above method embodiments. The implementation principles and its beneficial effects are similar to those of the method embodiments. Details are not repeated here.

[0437] Figure 23 is a schematic diagram of the structure of another encoding device according to an embodiment of this application. Please refer to Figure 23. The encoding device 30 can include: an acquisition module 31, a decision module 32, a generation module 33, and an encoding module 34.

[0438] The obtaining module 31 is configured to obtain K bits to be coded, where K is a positive integer.

[0439] The determination module 32 is configured to determine a first generator matrix, the first generator matrix including a first matrix block and a second matrix block, the first matrix block being located at an upper left corner of the first generator matrix, the second matrix block being located at a lower right corner of the first generator matrix, the first matrix block being equal to the second matrix block, and a distance between a first element in the first matrix block and a second element in the second matrix block is u in a diagonal direction of the first generator matrix, where u is an integer equal to or greater than 1.

[0440] The generating module 33 is configured to generate a second generator matrix based on the coding length and the first generator matrix, where the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along a diagonal of the second generator matrix, a first matrix block of an (a+1)-th first generator matrix in the T first generator matrices overlaps with a second matrix block of an a-th first generator matrix, a is an integer equal to or greater than 1, and T is an integer equal to or greater than 2.

[0441] The encoding module 34 is configured to polar encode the K bits to be encoded based on the second generator matrix to obtain encoded bits.

[0442] Optionally, the acquisition module 31 may perform step S1001 in the embodiment of FIG.

[0443] Optionally, the determination module 32 may perform step S1002 in the embodiment of FIG.

[0444] Optionally, the generation module 33 may perform step S1003 in the embodiment of FIG.

[0445] Optionally, encoding module 34 may perform step S1004 in the embodiment of FIG.

[0446] It should be noted that the encoding device shown in this embodiment of this application can implement the technical solutions shown in the embodiments of the foregoing method. The implementation principle and its beneficial effects are the same as those of the method embodiments. Details are not repeated here.

[0447] In an imaginable implementation, there are no duplicate elements in the first matrix block and the second matrix block.

[0448] In an imaginable implementation, the size of the first generating matrix is v*v, and the elements in the first generating matrix are a i,j =a i+u,j+u satisfies where i is an integer, j is an integer, v is a positive integer, u is an integer, 1≦i<v, 1≦j<v, 1<i+u≦v, and 1<j+u≦v.

[0449] In an imaginable implementation, the elements in the first generating matrix are symmetric along the secondary diagonal of the first generating matrix.

[0450] In an imaginable implementation, T is the smallest integer that enables the first condition to be satisfied, and the first condition is that the size of the second generating matrix is greater than or equal to the encoding length.

[0451] In an imaginable implementation, T satisfies the following relationship, that is, v+(T-1)*u<N ’ ≦v+T*u, where v is the size of the first generating matrix, N’ is the encoding length, and N’ is an integer greater than 1.

[0452] It should be noted that the encoding device shown in this embodiment of this application can implement the technical solutions shown in the embodiments of the foregoing method. The implementation principle and its beneficial effects are the same as those of the method embodiments. Details are not repeated here.

[0453] 24 is a schematic diagram of the structure of another decoding device according to an embodiment of this application, please refer to FIG 24. The decoding device 40 may include: a receiving module 41 and a decoding module 42.

[0454] The receiving module 41 is configured to receive the polar encoded bit information.

[0455] The decoding module 42 is configured to polar decode the bit information based on a second generator matrix to obtain polar decoded bits. The second generator matrix is ​​generated based on the first generator matrix.

[0456] The first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at an upper left corner of the first generator matrix, the second matrix block is located at a lower right corner of the first generator matrix, the first matrix block is the same as the second matrix block, and a distance between a first element in the first matrix block and a second element in the second matrix block is u in a diagonal direction of the first generator matrix, where u is an integer greater than or equal to 1.

[0457] The second generator matrix includes T first generator matrices, the T first generator matrices are distributed along a diagonal of the second generator matrix, a first matrix block of an (a+1)th first generator matrix in the T first generator matrices overlaps with a second matrix block of an ath first generator matrix, a is an integer greater than or equal to 1, and T is an integer greater than or equal to 2.

[0458] Optionally, the receiving module 41 can execute S1601 of the embodiment of FIG.

[0459] Optionally, the decoding module 42 may perform step S1602 in the embodiment of FIG.

[0460] As shown in this embodiment of the present application DecryptionIt should be noted that the device can implement the technical solutions shown in the foregoing method embodiments. The implementation principle and its beneficial effects are the same as those of the method embodiments. Details are not repeated here.

[0461] In an imaginable implementation, there are no duplicate elements in the first matrix block and the second matrix block.

[0462] In an imaginable implementation, the size of the first generator matrix is v*v, and the elements in the first generator matrix are a i,j =a i+u,j+u satisfies i is an integer, j is an integer, v is a positive integer, u is an integer, 1≦i<v, 1≦j<v, 1<i+u≦v, and 1<j+u≦v.

[0463] In an imaginable implementation, the elements in the first generator matrix are symmetric along the secondary diagonal of the first generator matrix.

[0464] In an imaginable implementation, T is the smallest integer that enables the first condition to be satisfied, and the first condition is that the size of the second generator matrix is greater than or equal to the coding length.

[0465] In an imaginable implementation, T satisfies the following relationship, that is, v+(T-1)*u<N ’ ≦v+T*u, where v is the size of the first generator matrix, N’ is the coding length, and N’ is an integer greater than 1.

[0466] In an imaginable implementation, the bit information includes N’ first log-likelihood ratio LLR sequences, and N’ is a positive integer.

[0467] In an imaginable implementation, the N’ first LLRs include T first LLR sequences, and the first LLR sequence includes at least two first LLRs. The decoding module 42 determining T second LLR sequences corresponding to the T first LLR sequences, one of the first LLR sequences corresponding to one or more groups of uncoded bits and one of the second LLR sequences corresponding to one group of uncoded bits; and performing polar decoding based on the T second LLR sequences; The device is specifically configured as follows.

[0468] In a possible implementation, the decoding module 42 comprises: determining an i-th second LLR sequence based on the i-th first LLR sequence and at least one of the first (i-1) second LLR sequences, where i is an integer from 2 to T; The device is specifically configured as follows.

[0469] In a possible implementation, the degree of connectivity of the code blocks is 2. The decoding module 42: determining an i-th second LLR sequence based on the i-th first LLR sequence and the (i-1)-th second LLR sequence; The device is specifically configured as follows.

[0470] In a possible implementation, the first second LLR sequence is the same as the first first LLR sequence.

[0471] In a possible implementation, the degree of connectivity of the code blocks is 4. The decoding module 42: Determine an i-th second LLR sequence based on the i-th first LLR sequence and the (i-2)-th second LLR sequence, where i is an integer from 3 to T; The device is specifically configured as follows.

[0472] In a possible implementation, the first second LLR sequence is the same as the first first LLR sequence; The second second LLR sequence is the same as the second first LLR sequence.

[0473] In a possible implementation, the decoding module 42 comprises: Determine to obtain a Tth decoding result based on the Tth second LLR sequence; and determining an i-th decoding result based on the i-th second LLR sequence and at least one of the (i+1)-th decoding result to the T-th decoding result, where i is an integer from 1 to T-1; The device is specifically configured as follows.

[0474] In a possible implementation, the degree of connectivity of the code blocks is 2. The decoding module 42: determining an i-th decoding result based on the (i+1)-th decoding result, the (i+1)-th first LLR sequence, and the i-th second LLR sequence; The device is specifically configured as follows.

[0475] As shown in this embodiment of the present application Decryption It should be noted that the device can implement the technical solutions shown in the above method embodiments. The implementation principles and its beneficial effects are similar to those of the method embodiments. Details are not repeated here.

[0476] 25 is a schematic diagram of a hardware structure of yet another encoding device according to an embodiment of this application. Please refer to FIG. 25. The encoding device 50 may include a processor 51 and a memory 52.

[0477] The memory 52 is configured to store computer programs and may further be configured to store intermediate data.

[0478] The processor 51 is configured to execute a computer program stored in the memory to perform the steps of the aforementioned encoding method, for details, please refer to the relevant descriptions of the aforementioned method embodiments.

[0479] Optionally, the memory 52 may be separate or integrated with the processor 51. In some implementations, the memory 52 may be located external to the encoding device 50.

[0480] In the case where the memory 52 is a component separate from the processor 51 , the encoding device 50 may further include a bus 53 configured to connect the memory 52 and the processor 51 .

[0481] Optionally, the encoding device 50 may further include a transmitter, for example configured to transmit the coded bits.

[0482] The encoding device 50 provided in this embodiment may be a terminal device or a network device, and may be configured to perform the above-mentioned encoding method. Its implementation form and technical effect are similar to those of the encoding method. In this embodiment, details are not repeated here.

[0483] 26 is a schematic diagram of a hardware structure of yet another decoding device according to an embodiment of this application. Please refer to FIG. 26. The decoding device 60 may include a processor 61 and a memory 62.

[0484] The memory 62 is configured to store computer programs and may further be configured to store intermediate data.

[0485] The processor 61 is configured to execute a computer program stored in the memory to implement the steps of the aforementioned decoding method, for details, please refer to the relevant descriptions of the aforementioned method embodiments.

[0486] Optionally, the memory 62 may be separate or integrated with the processor 61. In some implementations, the memory 62 may be located outside the decoding device 60.

[0487] In the case where the memory 62 is a device independent of the processor 61 , the decoding device 60 may further include a bus 63 configured to connect the memory 62 and the processor 61 .

[0488] Optionally, the decoding device 60 may further include a receiver, for example, configured to receive the polar encoded bit information.

[0489] The decoding device 60 provided in this embodiment may be a terminal device or a network device, and may be configured to execute the above-mentioned decoding method. Its implementation form and technical effect are similar to those of the decoding method. In this embodiment, details are not repeated here.

[0490] 27 is a schematic diagram of the structure of yet another encoding device according to an embodiment of this application. Please refer to FIG. 27. The encoding device 70 may include an input interface 71 and a logic circuit 72.

[0491] The input interface 71 is configured to receive K bits to be coded, where K is a positive integer.

[0492] The logic circuit 72 is configured to: determine a first generator matrix, the first generator matrix including at least two sub-blocks distributed based on a predetermined positional relationship, the sub-block including a plurality of first generator matrix cores; generate a second generator matrix based on the first generator matrix, the second generator matrix including T sub-blocks, a positional relationship between two adjacent sub-blocks among the T sub-blocks being determined based on a predetermined positional relationship, T being a positive integer; and polar-encode the K bits to be encoded based on the second generator matrix to obtain encoded bits.

[0493] Optionally, the input interface 71 may have the functionality of the acquisition module 11 in the embodiment of Figure 21. The logic circuit 72 may have the functionality of the determination module 11, the generation module 13, and the encoding module 14 in the embodiment of Figure 21.

[0494] Optionally, logic circuitry 72 may have the functionality of processor 61 in the embodiment of Figure 25. Logic circuitry 72 may further perform other steps in the encoding method.

[0495] Optionally, the encoding device 70 may further include an output interface, for example, the output interface may output the encoded bits.

[0496] The encoding device 70 provided in this embodiment of the present application can implement the technical solutions shown in the above method embodiment. The implementation principle and its beneficial effects are similar to those of the method embodiment. Details are not repeated here.

[0497] 28 is a schematic diagram of the structure of yet another decoding device according to an embodiment of this application. Please refer to FIG. 28. The decoding device 80 may include an input interface 81 and a logic circuit 82.

[0498] The input interface 81 is configured to receive polar encoded bit information.

[0499] The logic circuit 82 is configured to polar-decode the bit information based on the second generator matrix to obtain polar-decoded bits. The second generator matrix is ​​generated based on the first generator matrix, the first generator matrix includes at least two sub-blocks distributed based on a preset positional relationship, the sub-block includes a plurality of first generator matrix cores, the second generator matrix includes T sub-blocks, and a positional relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset positional relationship, where T is a positive integer.

[0500] Optionally, the input interface 81 may have the function of the receiving module 21 in the embodiment of Figure 22. The logic circuit 82 may have the function of the decoding module 22 in the embodiment of Figure 22.

[0501] Optionally, the input interface 81 may have the functionality of the receiver in the embodiment of Fig. 26. The logic circuit 82 may have the functionality of the processor 61 in the embodiment of Fig. 26. The logic circuit 82 may further perform other steps in the decoding method.

[0502] Optionally, the decoding device 80 may further include an output interface. For example, the output interface may output the decoding result.

[0503] The decoding device 80 provided in this embodiment of the present application can implement the technical solutions shown in the above method embodiment. The implementation principle and its beneficial effects are similar to those of the method embodiment. Details are not repeated here.

[0504] 29 is a schematic diagram of the structure of yet another encoding device according to an embodiment of this application. Please refer to FIG. 29. The encoding device 90 may include an input interface 91 and a logic circuit 92.

[0505] The input interface 91 is configured to receive K bits to be coded, where K is a positive integer.

[0506] The logic circuit 92 determines a first generator matrix, the first generator matrix including a first matrix block and a second matrix block, the first matrix block being located at an upper left corner of the first generator matrix and the second matrix block being located at a lower right corner of the first generator matrix, the first matrix block being the same as the second matrix block, a distance between a first element in the first matrix block and a second element in the second matrix block is u in a diagonal direction of the first generator matrix, u being an integer equal to or greater than 1, and a coding length and the first generator matrix and a second generator matrix based on T, wherein the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along a diagonal of the second generator matrix, a first matrix block of an (a+1)th first generator matrix in the T first generator matrices overlaps with a second matrix block of an a-th first generator matrix, a is an integer greater than or equal to 1, and T is an integer greater than or equal to 2; and polar-encoding the K bits to be encoded based on the second generator matrix to obtain encoded bits.

[0507] Optionally, the input interface 91 may have the functionality of the acquisition module 31 in the embodiment of Figure 23. The logic circuit 92 may have the functionality of the determination module 32, the generation module 33, and the encoding module 34 in the embodiment of Figure 23.

[0508] Optionally, the logic circuitry 92 may have the functionality of the processor 61 in the embodiment of Figure 25. The logic circuitry 92 may further perform other steps in the encoding method.

[0509] Optionally, the encoding device 90 may further include an output interface, for example, the output interface may output the encoded bits.

[0510] The encoding device 90 provided in this embodiment of the present application can implement the technical solutions shown in the above method embodiment. The implementation principle and its beneficial effects are similar to those of the method embodiment. Details are not repeated here.

[0511] 30 is a schematic diagram of the structure of yet another decoding device according to an embodiment of this application. Please refer to FIG. 30. The decoding device 100 may include an input interface 101 and a logic circuit 102.

[0512] The input interface 101 is configured to receive polar encoded bit information.

[0513] The logic circuit 102 is configured to polar-decode the bit information based on the second generator matrix to obtain polar-decoded bits. The second generator matrix is ​​generated based on the first generator matrix, the first generator matrix includes a first matrix block and a second matrix block, the first matrix block is located at the upper left corner of the first generator matrix, the second matrix block is located at the lower right corner of the first generator matrix, the first matrix block is the same as the second matrix block, and a distance between a first element in the first matrix block and a second element in the second matrix block is u in a diagonal direction of the first generator matrix, where u is an integer equal to or greater than 1. The second generator matrix includes T first generator matrices, the T first generator matrices are distributed along a diagonal of the second generator matrix, and the first matrix block of the (a+1)th first generator matrix in the T first generator matrices overlaps with the second matrix block of the ath first generator matrix, where a is an integer equal to or greater than 1, and T is an integer equal to or greater than 2.

[0514] Optionally, the input interface 101 may have the functionality of the receiving module 41 in the embodiment of Figure 24. The logic circuit 102 may have the functionality of the decoding module 42 in the embodiment of Figure 24.

[0515] Optionally, the input interface 101 may have the functionality of the receiver in the embodiment of Fig. 26. The logic circuit 102 may have the functionality of the processor 61 in the embodiment of Fig. 26. The logic circuit 102 may further perform other steps in the decoding method.

[0516] Optionally, the decoding device 100 may further include an output interface. For example, the output interface may output the decoding result.

[0517] The decoding device 100 provided in this embodiment of this application can implement the technical solutions shown in the above method embodiment. The implementation principle and its beneficial effects are similar to those of the method embodiment. Details are not repeated here.

[0518] An embodiment of the present application further provides a storage medium, which includes a computer program, and the computer program is used to execute the aforementioned encoding method.

[0519] An embodiment of the present application further provides a storage medium, which includes a computer program, and the computer program is used to perform the aforementioned decoding method.

[0520] An embodiment of the present application further provides a chip or integrated circuit including a memory and a processor.

[0521] The memory is configured to store program instructions, and may be further configured to store intermediate data.

[0522] The processor is configured to invoke program instructions stored in the memory in order to carry out the encoding method described above.

[0523] Optionally, the memory may be separate or integrated with the processor, and in some implementations, the memory may alternatively be located outside the chip or integrated circuit.

[0524] An embodiment of the present application further provides a chip or integrated circuit including a memory and a processor.

[0525] The memory is configured to store program instructions, and may be further configured to store intermediate data.

[0526] The processor is configured to invoke program instructions stored in the memory in order to carry out the above-mentioned decoding method.

[0527] Optionally, the memory may be separate or integrated with the processor, and in some implementations, the memory may alternatively be located outside the chip or integrated circuit.

[0528] An embodiment of the present application further provides a program product, which includes a computer program, the computer program being stored in a storage medium, and the computer program being used to execute the aforementioned encoding method.

[0529] An embodiment of the present application further provides a program product, the program product including a computer program, the computer program being stored in a storage medium, the computer program being used to execute the aforementioned decoding method.

[0530] The method or algorithm steps described with reference to the contents disclosed in the embodiments of the present invention may be implemented by hardware or by a processor by executing software instructions. The software instructions may include corresponding software modules. The software modules may be stored in a Random Access Memory (RAM), a flash memory, a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a register, a hard disk, a removable hard disk, a Compact Disk Read Only Memory (CD-ROM), or any other form of storage medium known in the art. For example, the storage medium is coupled to the processor, such that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium may be components of the processor. The processor and the storage medium may be located in an ASIC. In addition, the ASIC may be located in a base station or a terminal. Indeed, the processor and the storage medium may exist as separate components in the receiving device.

[0531] It is to be understood that the processor may be a Central Processing Unit (in short CPU) or another general-purpose processor, a Digital Signal Processor (in short DSP), an Application Specific Integrated Circuit (in short ASIC), etc. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. The steps of the methods disclosed with reference to the invention may be performed and achieved directly by using a hardware processor or by using a combination of hardware and software modules in a processor.

[0532] The memory may include high-speed RAM memory, may include non-volatile memory NVM, for example at least one magnetic disk memory, or may be a USB flash drive, a removable hard disk, a read-only memory, a magnetic disk, an optical disk, etc.

[0533] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be categorized as an address bus, a data bus, a control bus, etc. For ease of presentation, the buses in the accompanying drawings of this application are not limited to only one bus or only one type of bus.

[0534] The storage medium may be implemented by any type of volatile or non-volatile storage device or combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), or an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a disk, or an optical disk. The storage medium may be any available medium that can be accessed by a general purpose or special purpose computer.

[0535] In this application, "at least one" means one or more, and "multiple" means two or more. The term "and / or" describes an association relationship to describe associated objects and indicates that three relationships may exist. For example, A and / or B may represent the following cases: only A is present, both A and B are present, and only B is present, where A and B may be singular or plural. In addition, the symbol " / " in this specification generally indicates an "or" relationship between associated objects. At least one of the following or similar expressions refer to any combination of these, including any combination of singular or plural items. For example, at least one piece of a, b, or c may represent a, b, c, ab, ac, bc, or abc, where a, b, and c may be singular or plural.

[0536] In one or more of the foregoing examples, those skilled in the art should understand that the functions described in the embodiments of the present invention may be implemented using hardware, software, firmware, or any combination thereof. If the functions are implemented using software, the functions may be stored on or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media includes computer storage media and communication media. Communication media includes any medium that facilitates the transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0537] In some embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the described apparatus embodiments are merely examples. For example, the division into modules is merely a logical division of functions, and may be other divisions in actual implementation. For example, multiple modules may be incorporated into or integrated into another system, or some features may be ignored or not implemented. In addition, the shown or discussed mutual couplings or direct couplings or communication connections may be implemented through some interfaces. Indirect couplings or communication connections between devices or modules may be implemented in electrical, mechanical, or other forms.

[0538] The modules described as separate parts may or may not be physically separate, and the parts shown as modules may or may not be physical units, and may be located in one location or distributed over multiple network units. Some or all of the modules may be selected according to the actual requirements for achieving the objectives of the solutions of the embodiments.

[0539] In addition, the functional modules in the embodiments of the present invention may be integrated into one processing unit, or each of the modules may exist physically alone, or two or more modules may be integrated into one module. The units integrated by the modules may be implemented in the form of hardware, or may be implemented in the form of hardware and software functional units. [Explanation of symbols]

[0540] 10 Encoding device 11 Acquisition Module 12 Decision Module 13 Generation Module 14 Encoding Module 20 Decryption device 21 Receiving module 22 Decryption module 30 Encoding device 31 Acquisition Module 32 Decision Module 33 Generation Module 34 Encoding Module 40 Decryption device 41 Receiver module 42 Decryption module 50 Encoding device 51 Processors 52 Memory 53 Bus 60 Decryption Device 61 processors 62 Memory 70 Encoding device 71 Input Interface 72 Logic Circuits 80 Decryption Device 81 Input Interface 82 Logic Circuits 90 Encoding device 9 91 Input Interface 92 Logic Circuits 100 Decryption device 1 101 Input Interface 101 Sending Device 102 Logic Circuit 102 Receiving Device

Claims

1. obtaining K bits to be coded, where K is a positive integer; determining a first generator matrix, the first generator matrix including at least two sub-blocks distributed in a diagonal direction based on a first positional relationship, each of the sub-blocks including a plurality of first generator matrix cores and at least one zero matrix, the first generator matrix core being a matrix G Ｎ and G Ｎ is an N×N matrix, where N=2 ｎ where n is a positive integer equal to or greater than 1; generating a second generator matrix based on the first generator matrix, the second generator matrix including T sub-blocks, the T sub-blocks being distributed along a diagonal of the second generator matrix, and a positional relationship in the diagonal direction between two sub-blocks having overlapping portions among the T sub-blocks in the second generator matrix being determined based on the first positional relationship, where T is an integer equal to or greater than 2; polar-encoding the K bits to be encoded based on the second generator matrix to obtain encoded bits; 13. An encoding method comprising:

2. The method of claim 1 , wherein a first diagonal of the sub-block includes the first generator matrix core.

3. The method according to claim 1 , wherein the first generator matrix cores within the sub-block are distributed in a lower triangular fashion.

4. 4. The method according to claim 1, wherein a distribution of the first generator matrix core in the sub-block is the same as a distribution of first elements in a second generator matrix core, a number of elements included in the second generator matrix core is the same as a number of sub-matrices included in the sub-block, and a sub-matrix included in the sub-block is the first generator matrix core or a zero matrix.

5. The method of claim 4, wherein the number of sub-matrices included in the sub-block is 2*2, and the sub-matrix included in the sub-block is the first generator matrix core or the zero matrix.

6. the first generator matrix includes a first sub-block and a second sub-block, a first sub-matrix in the first sub-block overlaps with a second sub-matrix in the second sub-block; The coordinates of a first sub-matrix in the first sub-block are (2, 2) and the coordinates of a second sub-matrix in the second sub-block are (1, 1). The method of claim 5.

7. The method of claim 4, wherein the number of sub-matrices included in the sub-block is 4*4, and the sub-matrix included in the sub-block is the first generator matrix core or the zero matrix.

8. the first generator matrix includes a first sub-block and a second sub-block, and four first sub-matrices in the first sub-block overlap with four second sub-matrices in the second sub-block; The coordinates of the four first sub-matrices in the first sub-block are (3,3), (3,4), (4,3), and (4,4); The coordinates of the four second sub-matrices in the second sub-block are (1,1), (1,2), (2,1), and (2,2). The method of claim 7.

9. receiving polar encoded bit information; polar-decode the bit information based on a second generator matrix to obtain polar-decoded bits; Including, The second generator matrix is ​​generated based on a first generator matrix, and the first generator matrix includes at least two sub-blocks distributed in a diagonal direction based on a first positional relationship, and the sub-blocks include a plurality of first generator matrix cores, each of the sub-blocks includes a plurality of first generator matrix cores and at least one zero matrix, and the first generator matrix core is a matrix G Ｎ and G Ｎ is an N×N matrix, where N=2 ｎ wherein n is a positive integer equal to or greater than 1, the second generator matrix includes T sub-blocks, the T sub-blocks are distributed along a diagonal of the second generator matrix, and within the second generator matrix, a positional relationship in the diagonal direction between two sub-blocks having an overlapping portion among the T sub-blocks is determined based on the first positional relationship, and T is an integer equal to or greater than 2. Decryption method.

10. The method of claim 9 , wherein the bit information includes N′ first log-likelihood ratio (LLR) sequences, where N′ is a positive integer.

11. The N′ first LLRs include a sequence of T first LLRs, the sequence of T first LLRs includes at least two first LLRs, and the polar decoding includes: determining T second LLR sequences corresponding to the T first LLR sequences, one of the first LLR sequences corresponding to one or more groups of uncoded bits and one of the second LLR sequences corresponding to one group of uncoded bits; performing polar decoding based on the T second LLR sequences; The method of claim 10, comprising:

12. obtaining K bits to be coded, where K is a positive integer; determining a first generator matrix, the first generator matrix includes a first matrix block and a second matrix block that are distributed based on a first positional relationship in a diagonal direction, the first matrix block is located at an upper left corner of the first generator matrix, the second matrix block is located at a lower right corner of the first generator matrix, the first matrix block is the same as the second matrix block, a distance between a first element in the first matrix block and a first element in the second matrix block is u in a diagonal direction of the first generator matrix, u is an integer equal to or greater than 1, each of the first matrix block and the second matrix block includes a plurality of first generator matrix cores and at least one zero matrix, the first generator matrix core is a matrix G Ｎ and G Ｎ is an N*N matrix, where N=2 ｎ , n is a positive integer equal to or greater than 1; determining a second generator matrix based on a coding length and the first generator matrix, the second generator matrix including T first generator matrices, the T first generator matrices being distributed along a diagonal of the second generator matrix, a first matrix block of an (a+1)th first generator matrix in the T first generator matrices overlapping with a second matrix block of an ath first generator matrix, a being an integer equal to or greater than 1, T being an integer equal to or greater than 2, and a positional relationship in the diagonal direction between two first generator matrices having overlapping portions of the T first generator matrices in the second generator matrix is ​​determined based on the first positional relationship; polar-encoding the K bits to be encoded based on the second generator matrix to obtain encoded bits; 13. An encoding method comprising:

13. The size of the first generator matrix is ​​v*v, and the elements in the first generator matrix are a i，j = a i＋u，j＋u Fulfilling i is an integer, j is an integer, v is a positive integer, u is an integer, and 1≦i<v, 1≦j<v, 1<i+u≦v, and 1<j+u≦v; The method of claim 12.

14. 14. The method of claim 12 or 13, wherein T is the smallest integer that enables a first condition to be satisfied, the first condition being that the size of the second generator matrix is ​​greater than or equal to the coding length.

15. receiving polar encoded bit information; polar-decode the bit information based on a second generator matrix to obtain polar-decoded bits, the second generator matrix being generated based on a first generator matrix; Including, The first generator matrix includes a first matrix block and a second matrix block that are distributed based on a first positional relationship in a diagonal direction, the first matrix block is located at an upper left corner of the first generator matrix, the second matrix block is located at a lower right corner of the first generator matrix, the first matrix block is the same as the second matrix block, a distance between a first element in the first matrix block and a first element in the second matrix block is u in a diagonal direction of the first generator matrix, u is an integer equal to or greater than 1, each of the first matrix block and the second matrix block includes a plurality of first generator matrix cores and at least one zero matrix, and the first generator matrix core is a matrix G Ｎ and G Ｎ is an N*N matrix, where N=2 ｎ , n is a positive integer equal to or greater than 1; the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along a diagonal of the second generator matrix, a first matrix block of an (a+1)-th first generator matrix in the T first generator matrices overlaps with a second matrix block of an a-th first generator matrix, a is an integer equal to or greater than 1, T is an integer equal to or greater than 2, and in the second generator matrix, a positional relationship in the diagonal direction between two first generator matrices having overlapping portions among the T first generator matrices is determined based on the first positional relationship. Decryption method.

16. The size of the first generator matrix is ​​v*v, and the elements in the first generator matrix are a i，j = a i＋u，j＋u Fulfilling i is an integer, j is an integer, v is a positive integer, u is an integer, and 1≦i<v, 1≦j<v, 1<i+u≦v, and 1<j+u≦v; The method of claim 15.

17. 17. The method according to claim 15 or 16, wherein T is the smallest integer that enables a first condition to be satisfied, the first condition being that the size of the second generator matrix is ​​greater than or equal to a coding length.

18. An encoding device comprising an input interface and a logic circuit, The input interface is configured to receive K bits to be encoded, where K is a positive integer; The logic circuit determines a first generator matrix, the first generator matrix including at least two sub-blocks distributed in a diagonal direction based on a first positional relationship, each of the sub-blocks including a plurality of first generator matrix cores and at least one zero matrix, the first generator matrix core being a matrix G Ｎ and G Ｎ is an N×N matrix, where N=2 ｎ wherein n is a positive integer equal to or greater than 1; generating a second generator matrix based on the first generator matrix, the second generator matrix including T sub-blocks, the T sub-blocks being distributed along a diagonal of the second generator matrix; a positional relationship in the diagonal direction between two sub-blocks having an overlapping portion among the T sub-blocks in the second generator matrix is ​​determined based on the first positional relationship, T is an integer equal to or greater than 2; and polar-coding the K bits to be encoded based on the second generator matrix to obtain encoded bits. Encoding device.

19. 19. The apparatus of claim 18, wherein the logic circuitry is further configured to perform an encoding method according to any one of claims 1 to 8.

20. An encoding device comprising an input interface and a logic circuit, The input interface is configured to receive K bits to be encoded, where K is a positive integer; The logic circuit determines a first generator matrix, the first generator matrix including a first matrix block and a second matrix block that are distributed based on a first positional relationship in a diagonal direction, the first matrix block is located at an upper left corner of the first generator matrix and the second matrix block is located at a lower right corner of the first generator matrix, the first matrix block is the same as the second matrix block, a distance between a first element in the first matrix block and a first element in the second matrix block is u in a diagonal direction of the first generator matrix, u is an integer equal to or greater than 1, each of the first matrix block and the second matrix block includes a plurality of first generator matrix cores and at least one zero matrix, the first generator matrix core is a matrix G Ｎ and G Ｎ is an N*N matrix, where N=2 ｎ , n is a positive integer equal to or greater than 1; determining a second generator matrix based on a coding length and the first generator matrix, the second generator matrix including T first generator matrices, the T first generator matrices being distributed along a diagonal of the second generator matrix, a first matrix block of an (a+1)th first generator matrix in the T first generator matrices overlapping with a second matrix block of an ath first generator matrix, a is an integer equal to or greater than 1, T is an integer equal to or greater than 2; in the second generator matrix, a positional relationship in the diagonal direction between two first generator matrices having overlapping portions among the T first generator matrices is determined based on the first positional relationship; and polar-coding the K bits to be encoded based on the second generator matrix to obtain coded bits. Encoding device.

21. 21. The apparatus of claim 20, wherein the logic circuitry is further configured to perform an encoding method according to any one of claims 12 to 14.

22. An encoding device comprising a memory, a processor and a computer program, the computer program being stored in the memory, and the processor executing the computer program to perform the encoding method according to any one of claims 1 to 8 or any one of claims 12 to 14.

23. 15. A computer readable storage medium, the storage medium comprising a computer program, the computer program being used to perform the encoding method according to any one of claims 1 to 8 or the encoding method according to any one of claims 12 to 14.

24. A computer program, which when executed on a computer, The coding method according to any one of claims 1 to 8 is carried out, or The encoding method according to any one of claims 12 to 14 is carried out Computer program.

25. An encoding device comprising an acquisition module, a determination module, a generation module, and an encoding module, The obtaining module is configured to obtain K bits to be coded, where K is a positive integer; the determining module is configured to determine a first generator matrix, the first generator matrix includes at least two sub-blocks that are distributed in a diagonal direction based on a first positional relationship, each of the sub-blocks includes a plurality of first generator matrix cores and at least one zero matrix, and the first generator matrix core is a matrix G Ｎ and G Ｎ is an N×N matrix, where N=2 ｎ where n is a positive integer equal to or greater than 1; the generating module is configured to generate a second generator matrix based on the first generator matrix, the second generator matrix including T sub-blocks, the T sub-blocks being distributed along a diagonal of the second generator matrix, and a positional relationship in the diagonal direction between two sub-blocks having overlapping portions among the T sub-blocks in the second generator matrix is ​​determined based on the first positional relationship, where T is an integer equal to or greater than 2; and the encoding module is configured to polar-encode the K encoding target bits based on the second generator matrix to obtain encoded bits. Encoding device.

26. 26. The apparatus of claim 25, wherein a first diagonal of the sub-block comprises the first generator matrix core.

27. 27. The apparatus of claim 25 or 26, wherein the plurality of first generator matrix cores within the sub-block are distributed in a lower triangular fashion.

28. 28. The apparatus of claim 25, wherein a distribution of the first generator matrix core within the sub-block is the same as a distribution of first elements within a second generator matrix core, a number of elements included in the second generator matrix core is the same as a number of sub-matrices included in the sub-block, and a sub-matrix included in the sub-block is the first generator matrix core or a zero matrix.

29. The apparatus of claim 28, wherein the number of sub-matrices included in the sub-block is 2*2, and the sub-matrix included in the sub-block is the first generator matrix core or the zero matrix.

30. the first generator matrix includes a first sub-block and a second sub-block, a first sub-matrix in the first sub-block overlaps with a second sub-matrix in the second sub-block; The coordinates of a first sub-matrix in the first sub-block are (2, 2) and the coordinates of a second sub-matrix in the second sub-block are (1, 1).

30. The apparatus of claim 29.

31. The apparatus of claim 28, wherein the number of sub-matrices included in the sub-block is 4*4, and the sub-matrix included in the sub-block is the first generator matrix core or the zero matrix.

32. the first generator matrix includes a first sub-block and a second sub-block, and four first sub-matrices in the first sub-block overlap with four second sub-matrices in the second sub-block; The coordinates of the four first sub-matrices in the first sub-block are (3,3), (3,4), (4,3), and (4,4); The coordinates of the four second sub-matrices in the second sub-block are (1,1), (1,2), (2,1), and (2,2).

32. The apparatus of claim 31.

33. A decoding device comprising a receiving module and a decoding module, the receiving module is configured to receive polar encoded bit information; the decoding module is configured to polar-decode the bit information based on a second generator matrix to obtain polar-decoded bits; The second generator matrix is ​​generated based on a first generator matrix, and the first generator matrix includes at least two sub-blocks distributed in a diagonal direction based on a first positional relationship, and each of the sub-blocks includes a plurality of first generator matrix cores and at least one zero matrix, and the first generator matrix core is a matrix G Ｎ and G Ｎ is an N×N matrix, where N=2 ｎ wherein n is a positive integer equal to or greater than 1, the second generator matrix includes T sub-blocks, the T sub-blocks are distributed along a diagonal of the second generator matrix, and a positional relationship in the diagonal direction between two sub-blocks having an overlapping portion among the T sub-blocks in the second generator matrix is ​​determined based on the first positional relationship, and T is an integer equal to or greater than 2. Decryption device.

34. 34. The apparatus of claim 33, wherein the bit information comprises N' first log-likelihood ratio (LLR) sequences, where N' is a positive integer.

35. The N′ first LLRs include a sequence of T first LLRs, the sequence of first LLRs includes at least two first LLRs, and the decoding module is determining T second LLR sequences corresponding to the T first LLR sequences, one of the first LLR sequences corresponding to one or more groups of uncoded bits and one of the second LLR sequences corresponding to one group of uncoded bits; performing polar decoding based on the T second LLR sequences.

35. The apparatus of claim 34, specifically configured for:

36. An encoding device comprising an acquisition module, a determination module, a generation module, and an encoding module, The obtaining module is configured to obtain K bits to be encoded, where K is a positive integer; The determination module is configured to determine a first generator matrix, the first generator matrix includes a first matrix block and a second matrix block that are distributed according to a first positional relationship in a diagonal direction, the first matrix block is located at an upper left corner of the first generator matrix, the second matrix block is located at a lower right corner of the first generator matrix, the first matrix block is the same as the second matrix block, a distance between a first element in the first matrix block and a first element in the second matrix block is u in a diagonal direction of the first generator matrix, u is an integer equal to or greater than 1, each of the first matrix block and the second matrix block includes a plurality of first generator matrix cores and at least one zero matrix, the first generator matrix core is a matrix G Ｎ and G Ｎ is an N*N matrix, where N=2 ｎ , n is a positive integer equal to or greater than 1; the generating module is configured to determine a second generator matrix based on a coding length and the first generator matrix, the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along a diagonal of the second generator matrix, a first matrix block of an (a+1)-th first generator matrix in the T first generator matrices overlaps with a second matrix block of an a-th first generator matrix, a is an integer equal to or greater than 1, and T is an integer equal to or greater than 2; and in the second generator matrix, a positional relationship in the diagonal direction between two first generator matrices having overlapping portions of the T first generator matrices is determined based on the first positional relationship; the encoding module is configured to polar-encode the K encoding target bits based on the second generator matrix to obtain encoded bits. Encoding device.

37. The size of the first generator matrix is ​​v*v, and the elements in the first generator matrix are a i，j = a i＋u，j＋u Fulfilling i is an integer, j is an integer, v is a positive integer, u is an integer, and 1≦i<v, 1≦j<v, 1<i+u≦v, and 1<j+u≦v; 37. The apparatus of claim 36.

38. 38. The apparatus of claim 36 or 37, wherein T is the smallest integer that enables a first condition to be satisfied, the first condition being that the size of the second generator matrix is ​​greater than or equal to the coding length.

39. A decoding device comprising a receiving module and a decoding module, the receiving module is configured to receive polar encoded bit information; The decoding module is configured to polar-decode the bit information based on a second generator matrix to obtain polar-decoded bits, the second generator matrix being generated based on a first generator matrix; The first generator matrix includes a first matrix block and a second matrix block that are distributed based on a first positional relationship in a diagonal direction, the first matrix block is located at an upper left corner of the first generator matrix, the second matrix block is located at a lower right corner of the first generator matrix, the first matrix block is the same as the second matrix block, a distance between a first element in the first matrix block and a first element in the second matrix block is u in a diagonal direction of the first generator matrix, u is an integer equal to or greater than 1, each of the first matrix block and the second matrix block includes a plurality of first generator matrix cores and at least one zero matrix, and the first generator matrix core is a matrix G Ｎ and G Ｎ is an N*N matrix, where N=2 ｎ , n is a positive integer equal to or greater than 1; the second generator matrix includes T first generator matrices, the T first generator matrices are distributed along a diagonal of the second generator matrix, a first matrix block of an (a+1)-th first generator matrix of the T first generator matrices overlaps with a second matrix block of an a-th first generator matrix, a is an integer equal to or greater than 1, T is an integer equal to or greater than 2, and in the second generator matrix, a positional relationship in the diagonal direction between two first generator matrices having overlapping portions among the T first generator matrices is determined based on the first positional relationship. Decryption device.

40. The size of the first generator matrix is ​​v*v, and the elements in the first generator matrix are a i，j = a i＋u，j＋u Fulfilling i is an integer, j is an integer, v is a positive integer, u is an integer, and 1≦i<v, 1≦j<v, 1<i+u≦v, and 1<j+u≦v; 40. The apparatus of claim 39.

41. 41. The apparatus of claim 39 or 40, wherein T is the smallest integer that enables a first condition to be satisfied, the first condition being that the size of the second generator matrix is ​​greater than or equal to a coding length.

42. A decoding device comprising a memory, a processor and a computer program, the computer program being stored in the memory, the processor executing the computer program to perform the decoding method according to any one of claims 9 to 11 or to perform the decoding method according to any one of claims 15 to 17. Decryption device.

43. 1. A computer-readable storage medium, comprising: The storage medium contains a computer program, the computer program being used to perform the decoding method according to any one of claims 9 to 11 or to perform the decoding method according to any one of claims 15 to 17. A computer-readable storage medium.

44. A computer program, which when executed on a computer, A method for decoding according to any one of claims 9 to 11 is carried out, or A decoding method according to any one of claims 15 to 17 is carried out, Computer program.

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