Grouping of power sources for power saving modes

Abstract

Methods, systems, and devices for grouping power supplies for power saving modes are described that configure a memory device with groups of internal power supplies whose voltage levels may be changed sequentially according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, the individual voltage levels of a first group of internal power supplies may be changed to individual external power supply voltage levels at a first time, the individual voltage levels of a second group of internal power supplies may be changed to individual external power supply voltage levels at a second time, etc. When the memory device exits deep sleep mode, the groups of internal voltage supplies may be changed from individual external power supply voltage levels to individual operating voltage levels in a group order opposite to the group order of entry.

Description

[Technical field]

[0001] [Cross Reference] This patent application claims priority to U.S. patent application Ser. No. 16 / 890,819, entitled “GROUPING POWER SUPPLIES FOR A SLEEP MODE,” by Nam et al., filed Jun. 20, 2020, which is assigned to the assignee of the present application and expressly incorporated by reference herein.

[0002] [Technical field] The following relates generally to one or more memory systems, and more specifically to grouping power sources for power saving modes. [Background technology]

[0003] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells in the memory device to various states. For example, a binary memory cell may be programmed to one of two supported states, often represented by a logical one or a logical zero. In some instances, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, a component of the device may read or sense at least one stored state in the memory device. To store information, a component of the device may write or program a state in the memory device.

[0004] There are various types of memory devices including magnetic hard disks, random access memories (RAMs), read-only memories (ROMs), dynamic RAMs (DRAMs), synchronous dynamic RAMs (SDRAMs), ferroelectric RAMs (FeRAMs), magnetic RAMs (MRAMs), resistive RAMs (RRAMs), flash memories, and phase change memories (PCMs). Memory devices can be volatile or non-volatile. Non-volatile memories, such as FeRAMs, can maintain their stored logic states for long periods of time even in the absence of an external power source. Volatile memory devices, such as DRAMs, can lose their stored states when disconnected from an external power source. FeRAMs can achieve similar densities as volatile memories, but have non-volatile characteristics due to the use of ferroelectric capacitors as storage devices. [Brief description of the drawings]

[0005] [Figure 1] An example of a system that supports grouping of power sources for power saving modes according to examples as disclosed herein is described. [Diagram 2] 1 illustrates an example of a memory die that supports grouping of power sources for power saving modes in accordance with the examples disclosed herein. [Figure 3A] An example of non-linear electrical characteristics of ferroelectric memory cells that supports grouping of power supplies for power saving modes according to the examples as disclosed herein is described. [Figure 3B] An example of non-linear electrical characteristics of ferroelectric memory cells that supports grouping of power supplies for power saving modes according to the examples as disclosed herein is described. [Figure 4] 1 illustrates an example of a timing diagram supporting grouping of power sources for power saving modes according to examples as disclosed herein. [Diagram 5] 1 illustrates an example of a timing diagram supporting grouping of power sources for power saving modes according to examples as disclosed herein. [Figure 6]An example of a voltage change configuration that supports grouping of power sources for power saving modes according to examples as disclosed herein is described. [Figure 7] 1 illustrates an example of a circuit diagram that supports grouping of power sources for power saving modes according to examples as disclosed herein. [Figure 8] 1 illustrates a block diagram of a memory device that supports grouping of power sources for power saving modes in accordance with an aspect of the present disclosure. [Figure 9] 1 shows a flowchart illustrating one or more methods for supporting grouping of power sources for power saving modes according to examples as disclosed herein. [Figure 10] 1 shows a flowchart illustrating one or more methods for supporting grouping of power sources for power saving modes according to examples as disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] Some memory devices (e.g., ferroelectric memory devices) use multiple internal power supplies to generate higher voltages for use in memory cell write and / or read procedures. In some cases, the memory device may enter a standby or sleep mode (e.g., deep sleep mode), for example, to conserve power or to prevent overuse. When entering deep sleep mode, the memory device (e.g., a controller of the memory device) may change the individual voltage levels of the internal power supplies to individual lower voltage levels and may maintain the internal power supplies at individual different voltage levels (e.g., lower voltage levels) during deep sleep mode. In some cases, if the individual voltage levels of the internal power supplies are changed without regard to the sequence or order of the changes, the change in voltage may cause data loss in some ferroelectric memory cells and may cause latch-up in one or more components of the memory device (e.g., due to forward biasing of junctions in one or more components that create a low impedance path between a positive supply voltage and a lower supply voltage or ground).

[0007] To mitigate possible effects associated with latch-up or forward bias in components of the memory device during entry or exit from deep sleep, the memory device may be configured with groups of internal power supplies whose voltage levels may be changed sequentially according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, the individual voltage levels of a first group of internal power supplies may be changed to individual external power supply voltage levels at a first time, the individual voltage levels of a second group of internal power supplies may be changed to individual external power supply voltage levels at a second time, etc. When the memory device exits deep sleep mode, the groups of internal voltage supplies may be changed from individual external power supply voltage levels to individual operating voltage levels in a group order opposite to the deep sleep entry group order.

[0008] The voltage alteration mechanism may include one or more bleeder circuits and one or more clamp circuits, where the clamp circuits may be enabled by comparing respective internal power supply voltage levels to thresholds associated with respective external power supply voltages (e.g., such that the clamp circuits are enabled once the internal power supply voltage is within the threshold of the external power supply voltage). Sequencing and altering the internal voltage supplies according to groups in this manner may support power savings, reduce or prevent damaging effects from forward bias or latch-up, reduce data loss in memory cells (e.g., improving cell safety and reliability), and reduce peak currents when exiting deep sleep modes.

[0009] The disclosed features are first described in the context of memory systems and dies, as described with reference to Figures 1-2. The disclosed features are described in the context of non-linear electrical characteristics of ferroelectric memory cells, timing diagrams, voltage change configurations, and circuit diagrams, as described with reference to Figures 3-7. These and other disclosed features are further illustrated by and with reference to apparatus diagrams and flow charts relating to grouping of power sources for power saving modes, as described with reference to Figures 8-10.

[0010] 1 illustrates an example of a system 100 that supports grouping of power sources for power saving modes according to examples as disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling host device 105 with memory device 110. Although system 100 may include one or more memory devices, aspects of one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0011] System 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a mobile phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. Memory device 110 may be a component of the system operable to store data for one or more other components of system 100.

[0012] At least a portion of the system 100 may be an example of a host device 105. The host device 105 may be an example of a processor or other circuitry in a device that uses memory to execute a process, such as in a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a mobile phone, a wearable device, an Internet-connected device, a vehicle controller, or any other fixed or portable electronic device, among other examples. In some examples, the host device 105 may refer to the hardware, firmware, software, or combination thereof that implements the functionality of the external memory controller 120. In some examples, the external memory controller 120 may be referred to as a host or host device 105.

[0013] Memory device 110 may be an independent device or component operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configurable to operate with one or more different types of host device 105. Signaling between host device 105 and memory device 110 may be operable to support one or more of modulation schemes for modulating signals, various pin configurations for communicating signals, various types of factors for the physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing rules, or other factors.

[0014] The memory device 110 may be operable to store data for components of the host device 105. In some examples, the memory device 110 may act as a slave-type device to the host device 105 (e.g., executing in response to commands provided by the host device 105 through the external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands. In some cases, a command from the host device 105 may indicate that the memory device 110 is to enter a sleep mode. For example, the host device 105 may indicate that the memory device 110 is to enter a sleep mode in which some memory device functions are shut down and some other memory device functions are still operational. Additionally or alternatively, the host device 105 may indicate that the memory device 110 is to enter a deep sleep mode in which all but the most critical memory device functions, power supplies, and voltages are shut down.

[0015] The host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components, such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using a bus 135.

[0016] The processor 125 may be operable to provide control or other functionality to at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, the processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a system on a chip (SoC), among other examples. In some examples, the external memory controller 120 may be implemented by the processor 125 or may be part of the processor 125.

[0017] BIOS component 130 may be a software component including a BIOS operating as firmware, which may initialize and execute various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0018] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sections), each memory cell operable to store at least one bit of data. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package. The memory die may include an on-die timer, in some cases, that may generate timing or clock pulses that may be used by components of the memory die (e.g., when executing one or more procedures).

[0019] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and may be operable to receive, send, or execute commands, data, or control information related to components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 as described herein in conjunction with a local memory controller 165 of the memory die 160. The device memory controller 155 (e.g., or other memory controller) may control the operation of one or more components of the memory device 110 when entering a sleep mode, such as a deep sleep mode (e.g., based on a command received from the host device 105).

[0020] In some examples, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command indicating that memory device 110 should store data for host device 105, or a read command indicating that memory device 110 should provide data stored in memory die 160 to the host device.

[0021] A local memory controller 165 (e.g., local to memory die 160) may be operable to control the operation of memory die 160. In some examples, local memory controller 165 may be operable to communicate (e.g., receive or send data or commands, or both) with device memory controller 155. In some examples, memory device 110 may not include device memory controller 155 and local memory controller 165, or external memory controller 120 may perform various functions described herein. Thus, local memory controller 165 may be operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120, or processor 125, or a combination thereof. Examples of components that may be included within the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating transmitted signals, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0022] The external memory controller 120 may be operable to facilitate communication of one or more of information, data, or commands between a component of the system 100 or the host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may replace or translate communications exchanged between the components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or the host device 105, or the functionality thereof described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or the host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some examples, external memory controller 120, or its functionality described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0023] Components of the host device 105 may exchange information with the memory device 110 using one or more channels 115. The channels 115 may be operable to support communication between the external memory controller 120 and the memory device 110. Each channel 115 may be an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. A signal path may be an example of a conductive path operable to carry a signal. For example, the channel 115 may include a first terminal that includes one or more pins or pads at the host device 105 and one or more pins or pads at the memory device 110. A pin may be an example of a conductive input or output point of a device of the system 100, and the pin may be operable to function as part of a channel.

[0024] Channels 115 (and associated signal paths and terminals) may be dedicated to communicating one or more types of information. For example, channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling may be communicated over channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be recorded every clock cycle (e.g., on a rising edge or a falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be recorded every clock cycle (e.g., on both the rising edge and the falling edge of a clock signal).

[0025] In some examples, CA channel 186 may be operable to communicate commands between host device 105 and memory device 110, including control information (e.g., address information) associated with the commands. For example, CA channel 186 may include a read command having an address of desired data. In some examples, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) for decoding one or more of the address or command data.

[0026] In some examples, the clock signal channel 188 may be operable to communicate one or more clock signals between the host device 105 and the memory device 110. Each clock signal may be operable to oscillate between a high state and a low state and may support coordination (e.g., in time) between operations of the host device 105 and the memory device 110. In some examples, the clock signals may be single-ended. In some examples, the clock signals may provide a timing reference for command and addressing operations for the memory device 110 or other system-wide operations for the memory device 110. The clock signals may therefore be referred to as control clock signals, command clock signals, or system clock signals. The system clock signals may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors).

[0027] To mitigate possible effects associated with latch-up or forward bias in components of memory device 110 during entry or exit from deep sleep, memory device 110 may be configured with groups of internal power supplies whose voltage levels may be changed sequentially according to a group order signaled by an on-die timer. For example, when memory device 110 enters deep sleep mode, the individual voltage levels of a first group of internal power supplies may be changed to individual external power supply voltage levels at a first time, the individual voltage levels of a second group of internal power supplies may be changed to individual external power supply voltage levels at a second time, etc. When memory device 110 exits deep sleep mode, the groups of internal voltage supplies may be changed from individual external power supply voltage levels to individual operating voltage levels in a group order opposite to the deep sleep entry group order.

[0028] The voltage alteration mechanism may include one or more bleeder circuits and one or more clamp circuits, where the clamp circuits may be enabled by comparing respective internal power supply voltage levels to thresholds associated with respective external power supply voltages (e.g., such that the clamp circuits are enabled once the internal power supply voltage is within the threshold of the external power supply voltage). Sequencing and altering the internal voltage supplies according to groups in this manner may support power savings, reduce or prevent damaging effects from forward bias or latch-up, reduce data loss in memory cells (e.g., improving cell safety and reliability), and reduce peak currents when exiting deep sleep modes.

[0029] FIG. 2 illustrates an example of a memory die 200 that supports grouping of power sources for power saving modes according to examples as disclosed herein. The memory die 200 may be an example of the memory die 160 described with reference to FIG. 1. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmable to store a different logical state (e.g., may be programmed to one state of a set of two or more possible states). For example, the memory cells 205 may be operable to store one bit of information at a time (e.g., a logical 0 or a logical 1). In some examples, the memory cells 205 (e.g., a multi-level memory cell) may be operable to store multiple bits of information at a time (e.g., a logical 00, a logical 01, a logical 10, a logical 11). In some examples, the memory cells 205 may be arranged in an array, such as the memory array 170 described with reference to FIG. 1.

[0030] The memory cell 205 may store a state (e.g., a polarization state or a dielectric charge) that represents a programmable state in a capacitor. In an FeRAM architecture, the memory cell 205 may include a capacitor 240 that includes a ferroelectric material for storing a charge and / or polarization that represents a programmable state. The memory cell 205 may include a logic storage component, such as the capacitor 240, and a switching component 245. The capacitor 240 may be an example of a ferroelectric capacitor. A first node of the capacitor 240 may be coupled to the switching component 245, and a second node of the capacitor 240 may be coupled to the plate line 220. The switching component 245 may be an example of a transistor or any other type of switch device that selectively establishes or de-establishes electronic communication between two components.

[0031] The memory die 200 may include access lines (e.g., word lines 210, digit lines 215, and plate lines 220) arranged in a pattern, such as a grid-like pattern. The access lines may be conductive lines coupled to the memory cells 205 and may be used to perform access operations on the memory cells 205. In some examples, the word lines 210 may be referred to as row lines. In some examples, the digit lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, bit lines, or plate lines, or the like, may be interchangeable without loss of understanding or operation. The memory cells 205 may be located at the intersections of the word lines 210, digit lines 215, and / or plate lines 220.

[0032] By activating or selecting access lines, such as word line 210, digit line 215, and / or plate line 220, operations such as read and write may be performed on memory cells 205. By biasing word line 210, digit line 215, and plate line 220 (e.g., applying a voltage to word line 210, digit line 215, or plate line 220), a single memory cell 205 may be accessed at their intersection. Activating or selecting a word line 210, digit line 215, or plate line 220 may include applying a voltage to the individual lines.

[0033] Access to memory cells 205 may be controlled through row decoder 225, column decoder 230, and plate driver 235. For example, row decoder 225 may receive a row address from local memory controller 265 and activate word line 210 based on the received row address. Column decoder 230 may receive a column address from local memory controller 265 and activate digit line 215 based on the received column address. Plate driver 235 may receive a plate address from local memory controller 265 and activate plate line 220 based on the received plate address.

[0034] Selecting or deselecting memory cell 205 may be accomplished by activating or deactivating switching component 245. Capacitor 240 may be in electronic communication with digit line 215 using switching component 245. For example, capacitor 240 may be isolated from digit line 215 when switching component 245 is deactivated and capacitor 240 may be coupled to digit line 215 when switching component 245 is activated.

[0035] The sense component 250 may determine a state (e.g., a polarization state or charge) stored on the capacitor 240 of the memory cell 205 and may determine a logic state of the memory cell 205 based on the detected state. The sense component 250 may include one or more sense amplifiers for amplifying a signal output of the memory cell 205. The sense component 250 may compare a signal received from the memory cell 205 via the digit line 215 to a reference 255 (e.g., a reference voltage). The detected logic state of the memory cell 205 may be provided as an output of the sense component 250 (e.g., to an input / output 260) to indicate the detected logic state to another component of the memory device 110 including the memory die 200.

[0036] The local memory controller 265 may control operation of the memory cells 205 through various components (e.g., row decoder 225, column decoder 230, plate driver 235, and sense component 250). The local memory controller 265 may be one example of the local memory controller 165 described with reference to FIG. 1. In some examples, one or more of the row decoder 225, column decoder 230, plate driver 235, and sense component 250 may be co-located with the local memory controller 265. The local memory controller 265 may be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), convert the commands or data (or both) into information usable by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 265 may generate row and column address signals to activate the word line 210 of interest, the digit line 215 of interest, and the plate line 220 of interest. The local memory controller 265 may also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may be modified and may be different for the various operations discussed in the operation of the memory die 200.

[0037] The local memory controller 265 may be operable to perform one or more access operations to one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 265 in response to various access commands (e.g., from the host device 105). The local memory controller 265 may be operable to perform other access operations not listed here, or other operations associated with the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0038] For example, a controller (e.g., local memory controller 265) may be configured to sequentially change the voltage levels of different groups of internal power supplies according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, the controller may begin changing the individual voltage levels of a first group of internal power supplies to individual external power supply voltage levels at a first time, and may begin changing the individual voltage levels of a second group of internal power supplies to individual external power supply voltage levels at a second time, etc. Similarly, when the memory device exits a deep sleep mode, the controller may change the groups of internal voltage supplies from individual external power supply voltage levels to individual operating voltage levels in a group order opposite to the deep sleep entry group order.

[0039] 3A and 3B illustrate examples of nonlinear electrical characteristics of a ferroelectric memory cell having hysteresis curves 300-a and 300-b according to various examples as disclosed herein. The hysteresis curves 300-a and 300-b respectively illustrate the write and read processes of an exemplary ferroelectric memory cell. The hysteresis curves 300-a and 300-b depict the charge Q stored in a ferroelectric capacitor (e.g., the capacitor 240 described with reference to FIG. 2) as a function of the voltage difference V.

[0040] A ferroelectric material is characterized by spontaneous electric polarization, i.e., it maintains a non-zero electric polarization in the absence of an electric field. Exemplary ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconate titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. The electric polarization in a ferroelectric capacitor results in a net charge on the surface of the ferroelectric material, which attracts an opposite charge through the capacitor terminals. Thus, charge accumulates at the interface between the ferroelectric material and the capacitor terminals. Because the electric polarization can be maintained in the absence of an externally applied electric field for a relatively long time, even indefinitely, charge leakage can be significantly reduced, for example, compared to capacitors used in DRAM arrays. This can reduce the need to perform refresh operations.

[0041] The hysteresis curves 300-a and 300-b may be understood from the perspective of a single terminal of a capacitor. As an example, if the ferroelectric material has a negative polarization, a positive charge is stored at the terminal. Similarly, if the ferroelectric material has a positive polarization, a negative charge is stored at the terminal. Also, the voltages in the hysteresis curves 300-a and 300-b represent the voltage difference across the capacitor and are directional. For example, a positive voltage may be achieved by applying a positive voltage to the terminal (e.g., the cell plate) and maintaining a second terminal (e.g., the cell bottom) at ground (or about zero volts (0V)). A negative voltage may be applied by maintaining the terminal at ground and applying a positive voltage to the second terminal, i.e., a positive voltage may be applied to negatively polarize the terminal. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages can be applied to the appropriate capacitor terminals to generate the voltage differences shown in hysteresis curves 300-a and 300-b.

[0042] As depicted in hysteresis curve 300-a, the ferroelectric material can maintain a positive or negative polarization with zero voltage difference, resulting in two possible charge states: charge state 305 and charge state 310. Following the example of Figures 3A and 3B, charge state 305 represents a logic 0 and charge state 310 represents a logic 1. In some examples, the logic values ​​of the individual charge states may be reversed to accommodate other schemes for operating the memory cell.

[0043] A logic 0 or 1 can be written to a memory cell by controlling the electric polarization of the ferroelectric material, and therefore the charge on the capacitor terminals, through the application of voltages. For example, applying a net positive voltage 315 across the capacitor results in the accumulation of charge until a charge state 305-a is reached. Upon removal of the voltage 315, the charge state 305-a follows a path 320 until a charge state 305 at zero voltage is reached. Similarly, the charge state 310 is written by applying a net negative voltage 325, which results in a charge state 310-a. After removing the negative voltage 325, the charge state 310-a follows a path 330 until a charge state 310 at zero voltage is reached. The charge states 305-a and 310-a may also be referred to as remnant polarization (Pr) values, i.e., the polarization (or charge) that remains upon removal of the external bias (e.g., voltage). The coercive voltage is the voltage at which the charge (or polarization) is zero.

[0044] To read or sense the stored state of a ferroelectric capacitor, a voltage can be applied across the capacitor. In response, the stored charge Q changes, the extent of which depends on the initial charge state, i.e., the final stored charge (Q) depends on whether charge state 305-b or 310-b was initially stored. For example, hysteresis curve 300-b illustrates two possible stored charge states 305-b and 310-b. A voltage 335 can be applied across capacitor 240 as discussed with reference to FIG. 2. In other cases, a fixed voltage can be applied to the cell plate, and although depicted as a positive voltage, voltage 335 can be negative. In response to voltage 335, charge state 305-b can follow path 340. Similarly, if charge state 310-b was initially stored, it follows path 345. The final location of charge state 305-c and charge state 310-c depends on one or more factors, including the particular sensing scheme and circuitry.

[0045] In some examples, the final charge may depend on the intrinsic capacitance of the digit line connected to the memory cell. For example, if a capacitor is electrically connected to a digit line and a voltage 335 is applied, the voltage of the digit line may rise due to its intrinsic capacitance. The voltage measured at the sense component may not be equal to voltage 335 and may instead depend on the voltage of the digit line. The location of the final charge states 305-c and 310-c on the hysteresis curve 300-b may therefore depend on the capacitance of the digit line and may be determined through a load line analysis, i.e., the charge states 305-c and 310-c may be defined with respect to the capacitance of the digit line. As a result, the voltage of the capacitor, voltage 350 or voltage 355, may differ and may depend on the initial state of the capacitor.

[0046] By comparing the digit line voltage to a reference voltage, the initial state of the capacitor can be determined. The digit line voltage can be the difference between voltage 335 and the final voltage across the capacitor, voltage 350 or voltage 355, i.e., the difference between voltage 335 and voltage 350, or the difference between voltage 335 and voltage 355. To determine the stored logic state, i.e., whether the digit line voltage is higher or lower than the reference voltage, the reference voltage can be generated such that its magnitude is between the two possible digit line voltages. When compared by the sense component, the sensed digit line voltage can be determined to be higher or lower than the reference voltage, and the stored logic value of the ferroelectric memory cell (i.e., logic 0 or 1) can be determined. In some cases, the sense component can integrate the charge read from the capacitor and output the integrated charge level to determine the stored logic value of the ferroelectric memory cell.

[0047] In some cases, the ferroelectric memory cell may maintain its initial logic state after a read operation. For example, if charge state 305-b is accumulated, the charge state may follow path 340 to charge state 305-c during a read operation, and after removing voltage 335, the charge state may return to the initial charge state 305-b by following path 340 in the opposite direction. In some examples, the ferroelectric memory cell may lose its initial logic state after a read operation. For example, if charge state 310-b is accumulated, the charge state may follow path 345 to charge state 305-c during a read operation, and after removing voltage 335, the charge state may relax to charge state 305-b by following path 340.

[0048] In some examples, the voltages used to read or write logic states associated with memory cells (e.g., ferroelectric capacitors) may be higher than one or more voltages supplied by one or more external power sources coupled to the memory device (e.g., memory array). For example, one or more of voltages 315, 325, or 335, etc., may be higher than any voltages available to be supplied by any external power sources associated with the memory device. Thus, a memory device may be associated with or include an internal power supply (e.g., an analog power supply) that may be configured to provide the higher voltages used in the ferroelectric memory device.

[0049] The internal power supply may provide a voltage, a current, or a combination thereof, such as by charge pumping or voltage regulation (e.g., via a regulator). In some cases, the internal power supply may be configured to generate separate voltages that may generate a fixed amount of current (e.g., a controlled current) in one or more components of the memory device. For example, the one or more power supplies may provide or generate separate voltages for one or more memory cells (e.g., read or write operations to a ferroelectric capacitor), one or more sense amplifiers, sense amplifier control logic, voltage level converters, other peripheral circuitry, or any combination thereof.

[0050] A memory device may read or write logic states to memory cells in an operational or active mode in which one or more internal voltage supplies are available to provide voltages for operation of the memory device. For example, one or more internal voltage supplies may be powered up (e.g., held at an operating voltage) during the operational mode to reduce the time it takes to power up one or more internal voltage supplies before performing a read function, a write function, or other memory device function. In some cases, a memory device may enter a standby or sleep mode (e.g., a deep sleep mode), for example, to conserve power or prevent data loss. When entering the deep sleep mode, the memory device (e.g., or one or more controllers thereof) may change the individual voltage levels of the internal power supplies to individual lower voltage levels and may maintain the internal power supplies at the individual lower voltage levels during the deep sleep mode.

[0051] In some cases, if the individual voltage levels of the internal power supplies are changed simultaneously or in some sequence, the voltage changes may cause data loss in some ferroelectric memory cells or may cause latch-up in one or more components of the memory device. Latch-up may occur when a low impedance path is created between parts of a circuit, such as between a combination of well structures (e.g., P-type well and N-type well) and the substrate. If latch-up occurs in one or more components of the memory device, the one or more components may experience parasitic currents or voltages that may cause the one or more components to lose function (e.g., temporarily) or may cause permanent loss of function in the one or more components. In some cases, latch-up may be associated with forward biasing, where a component may allow continuous current flow that may disrupt or destroy the function of the component. In some cases, high voltage transistors (e.g., P-type metal oxide semiconductor (PMOS) transistors) in the memory device may be associated with latch-up when the internal voltage supplies are changed to individual lower voltage levels in a sequence that forward biases the junctions.

[0052] To mitigate possible effects associated with latch-up or forward bias in components of a memory device during entry or exit from deep sleep, a memory device may be configured with groups of internal power supplies whose voltage levels may be changed sequentially according to a group order controlled by an on-die timer. For example, when a memory device enters a deep sleep mode, the individual voltage levels of a first group of internal power supplies may be changed to individual lower voltage levels at a first time, the individual voltage levels of a second group of internal power supplies may be changed to individual lower voltage levels at a second time, etc. When a memory device exits a deep sleep mode, the groups of internal voltage supplies may be changed from the individual lower voltage levels to the individual operating voltage levels in a group order opposite to the deep sleep entry group order.

[0053] Sequencing and varying internal power supplies according to groups may support power savings, reduce or prevent damaging effects from forward bias or latch-up, reduce data loss in ferroelectric cells (e.g., improving the safety and reliability of the cells), and reduce peak currents when exiting deep sleep modes.

[0054] 4 illustrates an example of a timing diagram 400 supporting grouping of power sources for power saving modes according to examples as disclosed herein. As described with reference to FIGs. 3A and 3B, the internal power sources of a memory device may be grouped for voltage change operations (e.g., powering down and powering up the internal power sources) when entering or exiting a deep sleep mode. The timing diagram 400 may illustrate examples of different timing of voltage change operations when entering or exiting a deep sleep mode for various groups of the internal power sources.

[0055] According to various aspects, the internal power supplies of a memory device may be divided into groups according to the relationships of the power supplies within the circuits of the memory device. Constraints may be defined for the various power supplies based on the circuit relationships, and the power supplies may be assigned to the groups according to the constraints. For example, a memory device may include power supplies A, B, C, D, and E, and constraints may be determined from the circuit elements as B>A, C>B, D>A, and E>B. Thus, power supply A may be assigned to a first group, power supplies B and D may be assigned to a second group, and power supplies C and E may be assigned to a third group. In general, the groups of power supplies may include supplies of similar voltage ranges, but some internal power supplies may be assigned (e.g., according to constraints) to groups with other power supplies of different voltage ranges. Additionally or alternatively, a risk of latch-up may also be evaluated, and power supplies may be assigned to the same or different groups according to the risk of latch-up. For example, if power supplies A and B have a constraint that B>A, then if the risk of latch-up based on circuit elements supplied by A and B is low, they may be assigned to the same group, while higher risk circuits supplied by A or B may lead to a decision to have power supplies A and B in different groups.

[0056] In one example, the internal power sources of the first group of internal power sources may correspond to internal power supply voltages 405-a, 405-b, 405-c, 405-d, and 405-e, respectively. Similarly, in one example, the internal power sources of the second group of internal power sources may correspond to internal power supply voltages 410-a, 410-b, 410-c, 410-d, 410-e, and 410-f, respectively, and one or more of the internal power sources of the third group of internal power sources may correspond to internal power supply voltage 415-a. The internal power sources (e.g., regardless of grouping of the internal power sources) may be powered up according to a power-up sequence following boot-up of the device, such as represented by 450. At 450 (e.g., at device power-up), one or more external power sources, such as those represented by external power supply voltages 420 and 425, respectively, may reach an external power supply operating voltage level. Thereafter, or simultaneously, the internal power sources may begin to increase their respective voltage levels (e.g., above the voltage levels of the external power sources, such as external power supply voltages 420 or 425) to their respective operating voltage levels (e.g., using charge pump circuits, etc.).

[0057] 4 includes three groups of internal power sources, the examples may apply to any number of groups of internal power sources. The number of groups of internal power sources may be adjustable or configurable, may be based on operating conditions or power requirements, etc.

[0058] A host device associated with a memory device may provide or couple one or more external power sources to the memory device. The host device may, in some cases, send a command to the memory device indicating that the memory device is to enter or exit a deep sleep mode. For example, at 455, the host device may send a first command indicating that the memory device is to enter a deep sleep mode. The first command may generate a latch signal 430 (e.g., in the memory device) indicating to an internal power source that the memory device is entering a deep sleep mode. The latch signal 430 may be received, for example, by an on-die timer of the memory device, which may then generate one or more signals to indicate that individual groups of the internal power sources are to power down for the deep sleep mode. The on-die timer may program the order of entry and / or exit of the deep sleep mode for the individual groups of the internal power sources. The on-die timer may be generated based on an internal clock of the memory device and may be coupled, for example, to a stable voltage or power source to maintain operation during the deep sleep mode.

[0059] For example, after 455, the on-die timer may change the state of the first signal 435 to represent a flag indicating that the first group of internal power supplies are powered down for the deep sleep mode. The internal power supplies of the first group of internal power supplies may be powered down by changing their respective voltages to respective external supply voltages. For example, the internal power supply voltages 405-a, 405-b, and 405-c may be changed to the external power supply voltage 425, and the internal power supply voltage 405-e may be changed to a zero voltage or a steady state voltage, starting after 455. In some cases, the internal power supply voltage 405 may be changed via one or more bleeder circuits, which are further described herein with reference to FIGS. 6 and 7. In some cases, the voltage of one or more of the groups of power supplies (e.g., the internal power supply voltage 405-d) may not be changed and may be held at a stable voltage based on, for example, one or more settings of the deep sleep mode. Once the modified internal power supply voltage 405 reaches the respective external power supply voltage, the internal power supply voltage 405 may be clamped to (e.g., maintained at) the external power supply voltage. Clamping operations and circuits are further described herein with reference to Figures 6 and 7.

[0060] At 460, the on-die timer may change the state of the second signal 440 to represent a flag indicating that a second group of internal power supplies are to be powered down for the deep sleep mode by changing their respective voltages to respective external power supply voltages. For example, the internal power supply voltages 410-a through 410-e may be changed to the external power supply voltage 420 and the internal power supply voltage 410-f may be changed to the external power supply voltage 425, starting at 460. As with the first group of internal power supplies, the internal power supply voltage 410 may be changed via one or more bleeder circuits and maintained at the respective external power supply voltages via one or more clamper circuits.

[0061] At 465, the on-die timer may change the state of the third signal 445 to represent a flag indicating that the third group of internal power supplies are powered down for the deep sleep mode by changing their respective voltages to the respective external power supply voltages. For example, the internal power supply voltage 415-a may be changed to the external power supply voltage 420 starting after 465. Each of the internal power supply voltages may reach the respective external power supply voltage before 470 such that the power down procedure may be completed before 470 and the entry time for the deep sleep mode may be represented by the time between 455 and 470. As with the first and second groups of internal power supplies, the internal power supply voltage 415 may be changed via one or more bleeder circuits and maintained at the respective external power supply voltages via one or more clamper circuits.

[0062] At 475, the host device may send a second command indicating that the memory device is to exit the deep sleep mode. The second command may change the latch signal 430 (e.g., at the memory device) so that the latch signal 430 may indicate to the internal power supply that the memory device is exiting the deep sleep mode. The latch signal 430 may be received, for example, by an on-die timer of the memory device, which may then generate or change one or more signals to indicate that a respective group of the internal power supplies is to power up for the deep sleep mode. For example, after 475, the on-die timer may change the third signal 445 to represent a flag indicating that a third group of the internal power supplies is to power up to exit the deep sleep mode. The internal power supplies of the third group of the internal power supplies may be powered down by changing their respective voltages from the respective external supply voltages to the respective operating voltages of the internal power supplies. For example, the internal power supply voltage 415-a may be changed (eg, increased) from the external power supply voltage 420 starting at 475 onwards.

[0063] At 480, the on-die timer may change the second signal 440 to represent a flag indicating that the second group of internal power supplies power up to exit the deep sleep mode. The internal power supplies of the second group of internal power supplies may be powered down by changing their respective voltages from the respective external power supply voltages to the respective operating voltages of the internal power supplies. For example, the internal power supply voltages 410-a through 410-d may be changed (e.g., increased) from the external power supply voltage 420, and the internal power supply voltage 410-f may be changed (e.g., increased) from the external power supply voltage 425, starting at 480 onward.

[0064] At 485, the on-die timer may change the first signal 435 to represent a flag indicating that a first group of internal power supplies are powering up to exit the deep sleep mode. For example, the internal power supply voltages 405-a, 405-b, and 405-c may be changed (e.g., increased) from the external power supply voltage 425, and the internal power supply voltage 405-e may be changed (e.g., decreased) from a zero voltage or steady state voltage, beginning after 485. Each of the internal power supply voltages may have completed a power-up procedure before 490 and may reach a respective operating voltage before 490, as the exit time for deep sleep mode is represented by the time between 475 and 490. In some cases, beginning at 490 (e.g., after each internal power supply has reached an operating voltage level), the memory device may resume operation in an awake mode (e.g., from a deep sleep mode).

[0065] In some cases, the sequence for a group of internal power supplies to exit a deep sleep mode may be the opposite of the sequence for a group of internal power supplies to enter a deep sleep mode. In some cases, the interval for changing the voltage for successive groups of internal power supplies (e.g., for entry or exit from deep sleep) may support changing the individual voltage of one group of internal power supplies before beginning to change the individual voltage of another group of internal power supplies.

[0066] 4 and described herein, several internal power sources within the same group may be changed and clamped to different external voltage levels (e.g., different external power sources). The external voltage level to which the internal power sources are clamped may be based on the operating voltage level of the internal power sources, how close the internal power source voltage level is to the respective external power source voltage level, a safety factor for clamping the internal power sources to the respective external power source voltage level, or a combination thereof, among other factors.

[0067] FIG. 5 illustrates an example of a timing diagram 500 supporting grouping of power sources for a power saving mode according to examples as disclosed herein. As described with reference to FIGS. 3 and 4, the internal power sources of a memory device may be grouped for voltage change operations (e.g., powering down and powering up the internal power sources) when entering or exiting a deep sleep mode. Timing diagram 500 may illustrate an example of different timing of voltage change operations when entering or exiting a deep sleep mode for various groups of the internal power sources. In some cases, different groups of the internal power sources may or may not enter a deep sleep mode (e.g., may or may not be changed to an external power supply voltage level) based on, for example, the duration of the deep sleep mode.

[0068] In one example, the internal power supplies of a memory device may be divided into three groups, for example, as described with reference to Figure 4. Although the example described herein with reference to Figure 5 describes three groups of internal power supplies, the example may apply equally to any number of groups of internal power supplies. The number of groups of internal power supplies may be adjustable or configurable, may be based on operating conditions or power requirements, etc.

[0069] As described with reference to FIG. 4, the host device may in some cases send a command to the memory device indicating that the memory device is to enter or exit a deep sleep mode. For example, prior to 525, the host device may send a first command indicating that the memory device is to enter a deep sleep mode. The first command may generate (e.g., at the memory device) a latch signal 505 that may indicate that the internal power supply is to enter the deep sleep mode. The latch signal 505 may be received, for example, by an on-die timer of the memory device, which may then generate one or more signals to indicate that individual groups of the internal power supply are to power down for the deep sleep mode. The host device may also send a second command indicating that the memory device is to exit the deep sleep mode, and in some cases the latch signal may terminate or change based on the second command (e.g., to indicate that the on-die timer is to exit the deep sleep mode). The on-die timer may program an order for entry and / or exit of deep sleep mode for distinct groups of internal power supplies.

[0070] For example, the on-die timer may generate a first signal 510 that may represent a flag indicating that a first group of internal power sources power down for a deep sleep mode (e.g., upon a transition from a first state to a second state), a second signal 515 that may represent a flag indicating that a second group of internal power sources power down for a deep sleep mode (e.g., upon a transition from a first state to a second state), and a third signal 520 that may represent a flag indicating that a third group of internal power sources power down for a deep sleep mode (e.g., upon a transition from a first state to a second state). In some cases, one or more signals generated by the on-die timer may be based on the duration of a latch signal 505 associated with a deep sleep mode. For example, if the latch signal 505 changes or ends (e.g., to indicate an exit from deep sleep mode) before the on-die timer generates the second signal 515 and / or the third signal 520, the deep sleep mode may be exited without powering down the second and / or third groups of internal power supplies. In this manner, higher voltage power supplies (e.g., associated with the second and / or third groups) may not be powered down during the shorter deep sleep mode, which may conserve power and reduce voltage disturbances.

[0071] In a first example, at 525, the on-die timer may receive the latch signal 505-a and thereafter may change the first signal 510-a to a state indicating that a first group of internal power supplies enter a deep sleep mode based on the latch signal 505-a. In response to the first signal 510-a, the individual voltage levels of the first group of internal power supplies may be changed to individual external power supply voltage levels. At 530, based on the latch signal 505-a, the on-die timer may change the second signal 515-a to a state indicating that a second group of internal power supplies enter a deep sleep mode. In response to the second signal 515-a, the individual voltage levels of the second group of internal power supplies may be changed to individual external power supply voltage levels. At 535, based on the latch signal 505-a, the on-die timer may change the third signal 520-a to a state indicating that a third group of internal power supplies enter a deep sleep mode. In response to the third signal 520-a, the respective voltage levels of the third group of internal power supplies may be changed to the respective external power supply voltage levels.

[0072] Prior to 540, the host device may send a second command to the memory device indicating that the memory device is to exit the deep sleep mode. At 540, the latched signal 505-a may change state, indicating that the memory device is to exit the deep sleep mode. After 540, based on the latched signal 505-a, the on-die timer may change the third signal 520-a to a state indicating that the third group of internal power supplies is to exit the deep sleep mode. In response to the change in the third signal 520-a, the individual voltage levels of the third group of internal power supplies may be changed from the individual external power supply voltage levels to the individual operating voltage levels.

[0073] At 545, based on the latch signal 505-a, the on-die timer may change the second signal 515-a to a state indicating that the second group of internal power supplies are to exit the deep sleep mode. In response to the change in the second signal 515-a, the individual voltage levels of the second group of internal power supplies may be changed from the individual external power supply voltage levels to the individual operating voltage levels. At 550, based on the latch signal 505-a, the on-die timer may change the first signal 510-a to a state indicating that the first group of internal power supplies are to exit the deep sleep mode. In response to the change in the first signal 510-a, the individual voltage levels of the second group of internal power supplies may be changed from the individual external power supply voltage levels to the individual operating voltage levels.

[0074] In a second example, at 525, the on-die timer may receive the latch signal 505-b and after 525, may change the first signal 510-b to a state indicating that the first group of internal power supplies enter a deep sleep mode based on the latch signal 505-b. In response to the first signal 510-b, the individual voltage levels of the first group of internal power supplies may be changed to individual external power supply voltage levels. At 530, based on the latch signal 505-b, the on-die timer may change the second signal 515-b to a state indicating that the second group of internal power supplies enter a deep sleep mode. In response to the second signal 515-b, the individual voltage levels of the second group of internal power supplies may be changed to individual external power supply voltage levels. Prior to 555, the host device may send a second command to the memory device indicating that the memory device exits the deep sleep mode. For example, the host device may send a second command before the third group of internal power supplies enters the deep sleep mode such that the on-die timer may refrain from changing the third signal 520-b.

[0075] At 555, the latch signal 505-b may change state, indicating that the memory device is to exit the deep sleep mode. After 555, based on the latch signal 505-b, the on-die timer may change the second signal 515-b to a state indicating that the second group of internal power supplies are to exit the deep sleep mode. In response to the change in the second signal 515-b, the individual voltage levels of the second group of internal power supplies may be changed from the individual external power supply voltage levels to the individual operating voltage levels. At 560, based on the latch signal 505-b, the on-die timer may change the first signal 510-b to a state indicating that the first group of internal power supplies are to exit the deep sleep mode. In response to the change in the first signal 510-b, the individual voltage levels of the second group of internal power supplies may be changed from the individual external power supply voltage levels to the individual operating voltage levels.

[0076] In a third example, at 525, the on-die timer may receive the latch signal 505-c and after 525 may change the first signal 510-c to a state indicating that the first group of internal power supplies enter a deep sleep mode based on the latch signal 505-c. In response to the first signal 510-c, the respective voltage levels of the first group of internal power supplies may be changed to the respective external power supply voltage levels. Before 565, the host device may send a second command to the memory device indicating that the memory device exits the deep sleep mode. For example, the host device may send the second command before either the second group or the third group of internal power supplies enter the deep sleep mode such that the on-die timer may refrain from changing the second signal 515-c and the third signal 520-c.

[0077] At 565, the latched signal 505-c may change state, indicating that the memory device is to exit the deep sleep mode. After 565, based on the latched signal 505-c, the on-die timer may change the first signal 510-c to a state indicating that the first group of internal power supplies is to exit the deep sleep mode. In response to the change in the first signal 510-c, the individual voltage levels of the second group of internal power supplies may be changed from the individual external power supply voltage levels to the individual operating voltage levels.

[0078] FIG. 6 illustrates an example of a voltage change configuration 600 supporting grouping of power supplies for power saving modes according to examples as disclosed herein. As described with reference to FIGS. 3-5, the internal power supplies of the memory device may be grouped for voltage change operations (e.g., powering down and powering up the internal power supplies) when entering or exiting a deep sleep mode. The voltage change configuration 600 may illustrate circuitry and associated operation timing for changing (e.g., bleeding) and maintaining (e.g., clamping) the internal power supply voltage 645 to a separate external power supply voltage 650. The internal power supply voltage 645 and the external power supply voltage 650 may correspond to the internal power supply 615 (e.g., a voltage pump and / or oscillator) of the memory device and the external power supply of the memory device, respectively.

[0079] The voltage change configuration 600 may include a bleeder circuit 605 for changing the internal power supply voltage 645 from an operating voltage 655 to an external power supply voltage 650, and a clamper circuit 610 for maintaining the internal power supply voltage 645 at the external power supply voltage. As described herein, at 685, an on-die timer of the memory device may change a signal 660 to a state indicating that the internal power supply is to enter a deep sleep mode. The signal 660 may reset a latch 630 associated with the circuit for changing the internal power supply voltage 645. In response to the signal 660, the internal power supply signal 665 may switch to an “off” state, for example, indicating that the pump of the internal power supply 615 is turned off. Similarly, in response to the signal 660, the bleeder signal 670 may be changed to activate the bleeder circuit 605 to change the internal power supply voltage 645 to the external power supply voltage 650 via leakage current and current in the bleeder circuit 605. For example, one or more switching components 640 of the bleeder circuit may be engaged in response to the bleeder signal 670.

[0080] In some cases, the bleeder circuit 605 may include one or more resistors 635 or one or more current sources that may support modifying the internal power supply voltage 645 by bleeding power from the internal power supply 615 and other signal traces or components connected to the internal power supply voltage 645. In some cases, the current and associated power consumption of the bleeder circuit 605 may be less than the current and associated power consumption of the external power supply voltage 650 such that the bleeder circuit 605 may not affect the external power supply voltage 650. For example, the current of the bleeder circuit 605 may inject substantially less charge than is consumed by other components connected to the external power supply voltage 650.

[0081] In response to signal 660, comparator signal 680 may change to a state indicating that comparator 625 associated with internal power supply 615 is activated to compare internal power supply voltage 645 with external power supply voltage 650 (e.g., or with a threshold from external power supply voltage 650). If internal power supply voltage 645 reaches a voltage within a threshold from external power supply voltage 650 (e.g., a defined threshold for a deep sleep mode voltage), e.g., at 690, comparator 625 may deactivate bleeder circuit 605 (e.g., deactivate bleeder signal 670, which may deactivate one or more switching components 640) and activate clamper circuit 610 (e.g., activate or generate clamper signal 675). After deactivating bleeder circuit 605 and activating clamper circuit 610, comparator 625 may be deactivated (e.g., based on comparator signal 680 being deactivated).

[0082] The clamper circuit 610 may be configured to clamp one or more instances of the internal power supply voltage 645 at the external power supply voltage 650 to clamp or maintain the internal power supply voltage 645 at the external power supply voltage 650. For example, the clamper circuit 610 may include one or more transistors (e.g., PMOS or N-type metal oxide semiconductor (NMOS) transistors) that may be enabled by changing the state of a clamp signal 675 to couple the internal power supply voltage 645 to the external power supply voltage 650.

[0083] Prior to 695, the on-die timer may change signal 660 to a state indicating that the internal power supply 615 is to exit the deep sleep mode. In response to signal 660, the internal power supply signal 665 may switch to an “on” signal, for example, indicating that the pumps of the internal power supply 615 are to turn back on. Similarly, in response to signal 660, the clamp signal 675 may switch off, which may power down the clamper circuit 610 so that the internal power supply voltage 645 may return to the operating voltage 655 and the internal power supply 615 may exit the deep sleep mode.

[0084] 7 illustrates an example circuit diagram 700 supporting grouping of power sources for power saving modes according to examples as disclosed herein. As described with reference to FIGS. 3-6, the internal power sources of a memory device may be grouped for voltage change operations (e.g., powering down and powering up the internal power sources) when entering or exiting a deep sleep mode. Circuit diagram 700 may illustrate an example of voltage change (e.g., bleeding) and maintenance (e.g., clamping) operations, for example, as described with reference to FIG. 6.

[0085] In one example, the internal power supplies of the first group of internal power supplies 702-a may correspond to the internal power supply nodes 705-a, 705-b, and 705-c, respectively. Similarly, in one example, the internal power supplies of the second group of internal power supplies 702-b may correspond to the internal power supply nodes 710-a, 710-b, and 710-c, respectively, and one or more of the internal power supplies of the third group of internal power supplies 702-c may correspond to the internal power supply nodes 715-a and 715-b. In some cases, one or more of the voltages (e.g., voltages at a node) described herein may represent multiple voltages of the same group of internal power supplies sharing the same node in the circuit diagram 700 for purposes of illustration. Although the example described herein with reference to FIG. 7 includes three groups of internal power supplies, the example may apply to any number of groups of internal power supplies.

[0086] The voltages described herein may be combined with a separate bleeder circuit 740, a clamping circuit 745, or a combination thereof. In some cases, the separate bleeder circuit 740 and / or clamping circuit 745 may be combined with a separate comparator 750, for example, to compare the voltage of the internal power supply to the voltage of the external power supply (e.g., external power supply voltages 725, 730, and / or 735). The bleeder circuit 740 and comparator 750 may function, for example, as described with reference to FIG. 6.

[0087] A first group of internal power supplies 702-a (e.g., and the corresponding internal power supply node 705) may be changed to a respective external voltage based on a first signal 755, which may, for example, activate one or more transistors and a corresponding bleeder circuit 740. For example, the voltage on the internal power supply node 705-a may be changed to an external power supply voltage 725, the voltage on the internal power supply node 705-b may be changed to an external power supply voltage 730 (e.g., coupled via a bleeder circuit 740), and the voltage on the internal power supply node 705-c may be changed to an external power supply voltage 735. Similarly, a second group of internal power supplies 702-b (e.g., and the voltage at the corresponding internal power supply node 710) may be changed to a respective external voltage based on a second signal 760 (which may, for example, be generated by an on-die timer), which may, for example, activate a corresponding bleeder circuit 740 and a comparator 750. The respective voltages at the internal power supply nodes 710-a, 710-b, and 710-c may be changed to the external power supply voltage 725, for example, using the respective bleeder circuits 740 and clamper circuits 745. Activation of the signal 760 (e.g., transitioning to a logic state corresponding to a change in the second group 702-b of internal power supplies) may, for example, enable the bleeder circuits 740-d, 740-e, and 740-f and enable the comparators 750-a, 750-b, and 750-c. The bleeder circuits 740-d, 740-e, and 740-f may be enabled until the respective comparators 750-a, 750-b, or 750-c determine that the voltage at the respective internal power supply node 710 is within the threshold of the external power supply node 710. If the voltage at the individual internal power supply node 710 is within a threshold of the external power supply voltage 725 (e.g., or in some cases a different external power supply voltage), the individual internal power supply node 710 may be clamped (e.g., maintained) using clamps 745-a, 745-b, and 745-c, respectively (e.g., and bleeder circuit 740 may be disabled).

[0088] In some examples, the completion signal 770 may be generated by the group of internal power supplies 702 when at least one of the internal power supplies of the group is clamped to a respective external power supply voltage. For example, the completion signal 770 may be generated when at least one of the internal power supplies of the second group of internal power supplies 702-c is modified and clamped. Alternatively, the completion signal 770 may be generated when at least one of the internal power supplies of the second group of internal power supplies 702-c is modified and clamped (e.g., using an AND gate). In such a case, the third group of internal power supplies 702-c (e.g., and the corresponding internal power supply voltage 715) may be modified to a respective external voltage based on a fourth signal 775 generated from a third signal 765 (e.g., which may be generated by an on-die timer) and the completion signal 770 (e.g., an AND operation of the third signal and the completion signal 770). Activation of signal 775 (e.g., transitioning to a logic state corresponding to a change in the third group of internal power supplies 702-c) may, for example, enable bleeder circuits 740-g and 740-h and enable comparators 750-d and 750-e.

[0089] The bleeder circuits 740-g and 740-h may be enabled until the respective comparators 750-d or 750-e determine that the voltage at the respective internal power supply node 715 is within a threshold of the external power supply voltage 725. If the voltage at the respective internal power supply node 715 is within a threshold of the external power supply voltage 725 (e.g., or in some cases of a different external power supply voltage), the respective internal power supply node 715 may be clamped (e.g., maintained) using clamps 745-d and 745-e (e.g., and the bleeder circuit 740 may be disabled). Although FIG. 7 illustrates the completion signal 770 being generated using the same comparator 750 used to enable the clamping circuit 745, in some cases separate comparators with separate thresholds may be used. For example, in some cases, the completion signal 770 may use a higher threshold than the clamping circuit 745 so that the bleeder circuit for the next group (e.g., the third group) may be enabled before the clamps of one or more of the internal power supplies of the second group 702-b of internal power supplies.

[0090] Although the first group of internal power supplies 702-a is illustrated using a bleeder circuit 740 and without a clamping circuit 745 or a comparator 750 (e.g., due to a lower voltage resulting in a more defined bleeding time), one or more of the internal power supplies of the first group of internal power supplies 702-a may include a clamping circuit 745 or a comparator 750. A completion signal may also be generated from the first group of internal power supplies 702-a and the second group of internal power supplies 702-b (e.g., using the comparator 750).

[0091] 8 illustrates a block diagram 800 of a memory device 805 supporting grouping of power sources for power saving modes according to examples as disclosed herein. The memory device 805 may be an example of an embodiment of a memory device as described with reference to FIGS. 1-7. The memory device 805 may include a sleep command component 810, a voltage change component 815, an internal voltage maintenance component 820, a voltage restore component 825, and an external voltage maintenance component 830. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0092] The sleep command component 810 may receive a command at a first time at a memory device indicating that the memory device is to enter a sleep mode, the memory device including a set of internal power supplies associated with a set of distinct voltage levels. In some examples, the sleep command component 810 may receive a second command at a third time, a fourth time, or a fifth time at the memory device indicating that the memory device is to exit the sleep mode.

[0093] The voltage changing component 815 may change the individual voltage levels for the first subset of the set of internal power sources at a second time point based on receiving the command, where at least one internal power source of the first subset of the set of internal power sources is associated with a first voltage level that is different from the external power source voltage level. In some examples, the voltage changing component 815 may change the individual voltage levels for the second subset of the set of internal power sources at a third time point based on receiving the command. In some examples, the voltage changing component 815 may change the individual voltage levels for the third subset of the set of internal power sources at a fourth time point based on receiving the command.

[0094] In some cases, a first subset of the set of internal power sources is associated with a first threshold for forward voltage bias, a first voltage level threshold for power supply operation, or a combination thereof. In some cases, a second subset of the set of internal power sources is associated with a second threshold for forward voltage bias, a second voltage level threshold for power supply operation, or a combination thereof.

[0095] In some examples, the voltage modifying component 815 may activate individual bleeder circuits to modify the individual voltage levels of the first subset of the set of internal power sources from the individual first operating voltage levels to individual threshold voltage levels from the individual first external power supply voltage levels. In some examples, the voltage modifying component 815 may compare the individual voltage levels of the first subset of the set of internal power sources to the individual first external power supply voltage levels via individual comparators coupled to the individual bleeder circuits. In some examples, the voltage modifying component 815 may deactivate the individual bleeder circuits based on comparing the individual voltage levels of the first subset of the set of internal power sources to the individual first external power supply voltage levels. In some cases, each individual first voltage level of the first subset of the set of internal power sources is higher than each individual first external power supply voltage level.

[0096] Based on receiving the command, the internal voltage maintenance component 820 may maintain individual voltage levels for a second subset of the set of internal power sources at a second time point, where at least one internal power source of the second subset of the set of internal power sources is associated with a second voltage level that is different from the external power source voltage level. In some examples, based on receiving the command, the internal voltage maintenance component 820 may maintain individual voltage levels for a third subset of the set of internal power sources at the second time point and a third time point, where at least one internal power source of the third subset of the set of internal power sources is associated with a third voltage level that is different from the external power source voltage level.

[0097] In some examples, the internal voltage maintenance component 820 may activate a respective clamper circuit based at least in part on the respective voltage levels of the respective internal power supplies of the first subset of the set of internal power supplies reaching respective threshold voltage levels from the respective first external power supply voltage levels.

[0098] The voltage restoration component 825 may change the individual voltage levels for the first subset of the set of internal power sources at a fourth time point based on receiving the second command, the changing including restoring at least one internal power source of the first subset of the set of internal power sources to the first voltage level. In some examples, the voltage restoration component 825 may change the individual voltage levels for the second subset of the set of internal power sources at a fifth time point based on receiving the second command, the changing including restoring at least one internal power source of the second subset of the set of internal power sources to the second voltage level.

[0099] In some examples, the voltage restoration component 825 may change the individual voltage levels for the first subset of the set of internal power sources at a sixth time point based on receiving the second command, the changing including restoring at least one internal power source of the first subset of the set of internal power sources to the first voltage level. In some examples, the voltage restoration component 825 may change the individual voltage levels for the third subset of the set of internal power sources at a sixth time point based on receiving the second command, the changing including restoring at least one internal power source of the third subset of the set of internal power sources to a third voltage level.

[0100] In some examples, the voltage restoration component 825 may change the individual voltage levels for the second subset of the set of internal power sources at a seventh time point based on receiving the second command, the changing including restoring at least one internal power source of the second subset of the set of internal power sources to the second voltage level. In some examples, the voltage restoration component 825 may change the individual voltage levels for the first subset of the set of internal power sources at an eighth time point based on receiving the second command, the changing including restoring at least one internal power source of the first subset of the set of internal power sources to the first voltage level.

[0101] The external voltage maintenance component 830 may maintain the individual voltage levels for the first subset of the set of internal power sources at a fifth time point based on receiving the second command. In some examples, the external voltage maintenance component 830 may maintain the individual voltage levels for the second and first subsets of the set of internal power sources at a sixth time point based on receiving the second command. In some examples, the external voltage maintenance component 830 may maintain the individual voltage levels for the first subset of the set of internal power sources at a seventh time point based on receiving the second command.

[0102] In some examples, the external voltage maintenance component 830 may activate respective clamper circuits coupled with respective comparators to maintain the respective voltage levels of the first subset of the set of internal power sources at respective threshold voltage levels from the respective first external power source voltage levels based on comparing the respective voltage levels of the first subset of the set of internal power sources to the respective first external power source voltage levels.

[0103] FIG. 9 shows a flow chart illustrating one or more methods 900 of supporting grouping of power sources for power saving modes according to aspects of the disclosure. The operations of method 900 may be implemented by a memory device as described herein or components thereof. For example, the operations of method 900 may be performed by a memory device as described with reference to FIG. 8. In some examples, the memory device may execute a set of instructions to control functional elements of the memory device to perform the described functionality. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functionality.

[0104] At 905, the memory device may receive a command at a first time at the memory device indicating that the memory device is to enter a sleep mode, the memory device including a set of internal power supplies associated with a set of distinct voltage levels. The operations of 905 may be performed according to methods described herein. In some examples, aspects of the operations of 905 may be performed by a sleep command component such as described with reference to FIG.

[0105] At 910, the memory device may change individual voltage levels for a first subset of the set of internal power sources at a second time based on receiving the command, where at least one internal power source of the first subset of the set of internal power sources is associated with a first voltage level that is different from the external power source voltage level. The operations of 910 may be performed according to methods described herein. In some examples, aspects of the operations of 910 may be performed by a voltage modification component such as described with reference to FIG.

[0106] At 915, based on receiving the command, the memory device may maintain individual voltage levels for a second subset of the set of internal power sources at a second time, where at least one internal power source of the second subset of the set of internal power sources is associated with a second voltage level that is different from the external power source voltage level. The operations of 915 may be performed according to methods described herein. In some examples, aspects of the operations of 915 may be performed by an internal voltage maintenance component such as described with reference to FIG.

[0107] In some examples, an apparatus as described herein may perform one or more methods, such as method 900. The apparatus may include mechanisms, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a command at a first time at a memory device indicating that the memory device enters a sleep mode, the memory device including a set of internal power supplies associated with a set of individual voltage levels, changing the individual voltage levels for a first subset of the set of internal power supplies at a second time based on receiving the command, where at least one internal power supply source of the first subset of the set of internal power supplies is associated with a first voltage level that is different from the external power supply voltage level, and maintaining the individual voltage levels for a second subset of the set of internal power supplies at the second time based on receiving the command, where at least one internal power supply source of the second subset of the set of internal power supplies is associated with a second voltage level that is different from the external power supply voltage level.

[0108] Some examples of the methods 900 and apparatus described herein may further include operations, mechanisms, means, or instructions for receiving a second command at the memory device at a third time indicating that the memory device is to exit the sleep mode, and modifying individual voltage levels for the first subset of the set of internal power supply sources at a fourth time based on receiving the second command, the modifying including restoring at least one internal power supply source of the first subset of the set of internal power supply sources to a first voltage.

[0109] Some examples of the methods 900 and apparatus described herein may further include operations, mechanisms, means, or instructions for changing individual voltage levels for a second subset of the set of internal power sources at a third time based on receiving the command.

[0110] Some examples of the methods 900 and apparatus described herein may further include operations, mechanisms, means, or instructions for receiving a second command at the memory device at a fourth time point indicating that the memory device exits the sleep mode; altering individual voltage levels for a second subset of the set of internal power supply sources at a fifth time point based on receiving the second command, the altering including restoring at least one internal power supply source of the second subset of the set of internal power supply sources to a second voltage level; maintaining individual voltage levels for a first subset of the set of internal power supply sources at the fifth time point based on receiving the second command; and altering individual voltage levels for the first subset of the set of internal power supply sources at a sixth time point based on receiving the second command, the altering including restoring at least one internal power supply source of the first subset of the set of internal power supply sources to a first voltage level.

[0111] Some examples of the methods 900 and apparatus described herein may further include an operation, mechanism, means, or instruction for maintaining individual voltage levels for a third subset of the set of internal power sources at the second time point and a third time point based on receiving a command, where at least one internal power source of the third subset of the set of internal power sources may be associated with a third voltage level that is different from the external power source voltage level.

[0112] Some examples of the methods 900 and apparatus described herein may further include an operation, mechanism, means, or instruction for altering individual voltage levels for a third subset of the set of internal power sources at a fourth time based on receiving the command.

[0113] Some examples of the methods 900 and apparatus described herein include receiving a second command at the memory device at a fifth time point indicating that the memory device is to exit a sleep mode, altering individual voltage levels for a third subset of the set of internal power supply sources at a sixth time point based on receiving the second command, the altering including restoring at least one internal power supply source of the third subset of the set of internal power supply sources to a third voltage level, maintaining individual voltage levels for the second subset and the first subset of the set of internal power supply sources at the sixth time point based on receiving the second command, and restoring at least one internal power supply source of the third subset of the set of internal power supply sources to a third voltage level based on receiving the second command. the first subset of the set of internal power sources at a seventh time point, the changing including restoring at least one internal power source of the second subset of the set of internal power sources to a second voltage level; maintaining the individual voltage levels for the first subset of the set of internal power sources at the seventh time point based on receiving the second command; and changing the individual voltage levels for the first subset of the set of internal power sources at an eighth time point, the changing including restoring at least one internal power source of the first subset of the set of internal power sources to the first voltage level based on receiving the second command.

[0114] In some examples of the methods 900 and apparatus described herein, a first subset of the set of internal power sources may be associated with a first threshold for forward voltage bias, a first voltage level threshold for power supply operation, or a combination thereof, and a second subset of the set of internal power sources may be associated with a second threshold for forward voltage bias, a second voltage level threshold for power supply operation, or a combination thereof.

[0115] In some examples of the methods 900 and apparatus described herein, changing the individual voltage levels for the first subset of the set of internal power sources may include acts, mechanisms, means, or instructions for activating individual bleeder circuits to change the individual voltage levels of the first subset of the set of internal power sources from the individual first operating voltage levels to individual threshold voltage levels from the individual first external power supply voltage levels.

[0116] In some examples of the methods 900 and apparatus described herein, altering the individual voltage levels for the first subset of the set of internal power sources may include operations, mechanisms, means, or instructions for comparing, via individual comparators coupled with individual bleeder circuits, the individual voltage levels of the first subset of the set of internal power sources to the individual first external power source voltage level, deactivating the individual bleeder circuits based on comparing the individual voltage levels of the first subset of the set of internal power sources to the individual first external power source voltage level, and activating individual clamper circuits coupled with the individual comparators to maintain the individual voltage levels of the first subset of the set of internal power sources at individual threshold voltage levels from the individual first external power source voltage level based on comparing the individual voltage levels of the first subset of the set of internal power sources to the individual first external power source voltage level.

[0117] Some examples of the methods 900 and apparatus described herein may further include operations, mechanisms, means, or instructions for which activating the individual clamper circuits may be based at least in part on the individual voltage levels of the individual internal power supplies of the first subset of the set of internal power supplies reaching individual threshold voltage levels from the individual first external power supply voltage level.

[0118] In some examples of the methods 900 and apparatus described herein, each respective first voltage level of the first subset of the set of internal power supplies may be higher than each respective first external power supply voltage level.

[0119] FIG. 10 shows a flow chart illustrating one or more methods 1000 of supporting grouping of power sources for power saving modes according to aspects of the disclosure. The operations of method 1000 may be implemented by a memory device as described herein or components thereof. For example, the operations of method 1000 may be performed by a memory device as described with reference to FIG. 8. In some examples, the memory device may execute a set of instructions to control functional elements of the memory device to perform the described functionality. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functionality.

[0120] At 1005, a memory device may receive a command at a first time at the memory device indicating that the memory device is to enter a sleep mode, the memory device including a set of internal power supplies associated with a set of distinct voltage levels. The operations of 1005 may be performed according to methods described herein. In some examples, aspects of the operations of 1005 may be performed by a sleep command component such as described with reference to FIG.

[0121] At 1010, the memory device may change individual voltage levels for a first subset of the set of internal power sources at a second time based on receiving the command, where at least one internal power source of the first subset of the set of internal power sources is associated with a first voltage level that is different from the external power source voltage level. The operations of 1010 may be performed according to methods described herein. In some examples, aspects of the operations of 1010 may be performed by a voltage modification component such as described with reference to FIG.

[0122] At 1015, based on receiving the command, the memory device may maintain individual voltage levels for a second subset of the set of internal power sources at a second time, where at least one internal power source of the second subset of the set of internal power sources is associated with a second voltage level that is different from the external power source voltage level. The operations of 1015 may be performed according to methods described herein. In some examples, aspects of the operations of 1015 may be performed by an internal voltage maintenance component such as described with reference to FIG.

[0123] At 1020, the memory device may receive a second command at a third time at the memory device indicating that the memory device is to exit the sleep mode. The operations of 1020 may be performed according to methods described herein. In some examples, aspects of the operations of 1020 may be performed by a sleep command component such as described with reference to FIG.

[0124] At 1025, the memory device may change individual voltage levels for the first subset of the set of internal power supplies at a fourth time based on receiving the second command, the changing including restoring at least one internal power supply of the first subset of the set of internal power supplies to a first voltage level. The operations of 1025 may be performed according to methods described herein. In some examples, aspects of the operations of 1025 may be performed by a voltage restoration component such as described with reference to FIG.

[0125] It should be noted that the methods described herein are possible implementations, that acts and steps may be rearranged or otherwise modified, and that other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0126] An apparatus is described. The apparatus may include a set of internal power sources including a set of internal power sources associated with a set of individual voltage levels, a first subset of the internal power sources including a first internal power source associated with a first voltage level different from the external power source voltage level, and a second subset of the internal power sources including a second internal power source associated with a second voltage level different from the external power source voltage level. The apparatus may also include a controller configured to receive a command at a first time point indicating that the apparatus enters a sleep mode, change the individual voltage levels for the first subset of the set of internal power sources at a second time point based on receiving the command, and maintain the individual voltage levels for the second subset of the set of internal power sources at the second time point based on receiving the command.

[0127] Some examples of the controller may be further configured to receive a second command at the device at a third time indicating that the device is to exit the sleep mode, and based on receiving the second command, modify individual voltage levels for the first subset of the set of internal power supplies at a fourth time, the modifying including restoring the first internal power supply to the first voltage level.

[0128] Some examples of the controller may be further configured to, based on receiving the command, change individual voltage levels for a second subset of the set of internal power supplies at a third time.

[0129] Some examples of the controller may be further configured to receive a second command at the device at a fourth time point indicating that the device exits the sleep mode, and, based on receiving the second command, modifying individual voltage levels for a second subset of the set of internal power supplies at a fifth time point, where the modifying includes restoring the second internal power supply to the second voltage level. The controller may be further configured to maintain the individual voltage levels for the first subset of the set of internal power supplies at the fifth time point, based on receiving the second command, and, based on receiving the second command, modifying individual voltage levels for the first subset of the set of internal power supplies at a sixth time point, where the modifying includes restoring the first internal power supply to the first voltage level.

[0130] In some examples, a first subset of the set of internal power sources may be associated with a first threshold for forward voltage bias, a first voltage level threshold for power supply operation, or a combination thereof, and a second subset of the set of internal power sources may be associated with a second threshold for forward voltage bias, a second voltage level threshold for power supply operation, or a combination thereof.

[0131] In some examples, the device may further include a set of bleeder circuits including a first subset of bleeder circuits configured to change the individual voltage levels of a first subset of the set of internal power sources from a first individual operating voltage level to a first individual threshold value from a first individual external power supply voltage level, and a second subset of bleeder circuits configured to change the individual voltage levels of a second subset of the set of internal power sources from a second individual operating voltage level to a second individual threshold value from a second individual external power supply voltage level. The device may further include a set of comparator circuits including a first subset of comparator circuits coupled to the individual bleeder circuits of the first subset of bleeder circuits and configured to compare the individual voltage levels of the first subset of the set of internal power sources to the first individual external power supply voltage level, and a second subset of comparator circuits coupled to the individual bleeder circuits of the second subset of bleeder circuits and configured to compare the individual voltage levels of the second subset of the set of internal power sources to the second individual external power supply voltage level.

[0132] In some examples, each individual first operating voltage level of a first subset of the set of internal power supply sources may be higher than each individual first external power supply voltage level, and each individual second operating voltage level of a second subset of the set of internal power supply sources may be higher than each individual second external power supply voltage level.

[0133] In some examples, the apparatus may further include a set of clamper circuits including a first subset of clamper circuits coupled with respective comparator circuits of the first subset of comparator circuits and configured to maintain respective voltage levels of the first subset of the set of internal power supply sources at respective first threshold levels from a respective first external power supply voltage level based on the respective comparator circuits of the first subset, and a second subset of clamper circuits coupled with respective comparator circuits of the second subset of comparator circuits and configured to maintain respective voltage levels of the second subset of the set of internal power supply sources at respective second threshold levels from a respective second external power supply voltage level based on the respective comparator circuits of the second subset.

[0134] Some examples of the controller may be further configured to activate individual clamper circuits of the first subset of the clamper circuits based at least in part on individual voltage levels of individual internal power supplies of the first subset of the set of internal power supplies reaching individual voltage level thresholds.

[0135] An apparatus is described that may include a first internal power source associated with a first voltage level different from an external power source voltage level, a second internal power source associated with a second voltage level different from the first voltage level and different from the voltage level of the external power source, a set of bleeder circuits including a first bleeder circuit configured to change the first voltage level of the first internal power source to the first external power source voltage level and a second bleeder circuit configured to change the second voltage level of the second internal power source to the second external power source voltage level, and a set of clamper circuits including a first clamper circuit configured to maintain the first internal power source at the first external power source voltage level and a second clamper circuit configured to maintain the second internal power source at the second external power source voltage level.

[0136] Some examples of the apparatus may include a third internal power supply associated with a third voltage level different from the first voltage level, the second voltage level, and the external power supply voltage level; a third bleeder circuit of the set of bleeder circuits configured to change the third voltage level of the third internal power supply to the voltage level of the third external power supply; and a third clamper circuit of the set of clamper circuits configured to maintain the third internal power supply at the third external power supply voltage level.

[0137] In some examples, the first bleeder circuit may include one or more switching components configured to selectively couple the first internal power source with a first external power source having a first external power source voltage level, and one or more resistors selectively coupleable to the first internal power source or the first external power source via the one or more switching components.

[0138] In some examples, each clamper circuit of the set of clamper circuits may be coupled with a respective comparator circuit configured to compare a respective voltage level of a respective internal power supply with a respective external power supply voltage level.

[0139] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Although some figures may describe signals as a single signal, it will be understood by those skilled in the art that a signal may represent a bus of signals where the bus may have various bit widths.

[0140] The terms "in electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (or conductive contact, or connected, or coupled) with one another if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication (or conductive contact, or connected, or coupled) with one another may be an open circuit or a closed circuit based on the operation of the devices that include the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intervening components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be temporarily interrupted using one or more intervening components such as, for example, switches or transistors.

[0141] The term "couple" refers to the state of transitioning from an open circuit relationship between components, where signals are not currently able to communicate between the components across conductive paths, to a closed circuit relationship between the components, where signals can be communicated between the components across conductive paths. When a component, such as a controller, interconnects other components, it initiates changes that allow signals to flow between the other components across conductive paths that previously did not allow such flow.

[0142] The term "isolated" refers to a relationship between components where signals are not currently allowed to flow between them. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch positioned between them are isolated from each other if the switch is open. When a controller isolates two components from each other, the controller affects a change that prevents signals from flowing between the components using a conductive path that previously allowed signals to flow.

[0143] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate may be controlled through doping using various species, including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping means.

[0144] The switching components or transistors discussed herein may represent field effect transistors (FETs) and may include three terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic elements through conductive materials, e.g., metals. The source and drain may be conductive and may include heavily doped, e.g., degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority of carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority of carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. The conductivity of the channel may be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage equal to or greater than the transistor's threshold voltage is applied to the gate of the transistor. When a voltage less than the threshold voltage of a transistor is applied to the gate of the transistor, the transistor can be turned "off" or "deactivated."

[0145] The description set forth herein with reference to the accompanying drawings describes exemplary configurations and does not represent every example that may be implemented or is within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, illustration, or illustration" rather than "preferred" or "advantageous over other examples." The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques may, however, be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the content of the described examples.

[0146] In the accompanying figures, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. When only a first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label, regardless of the second reference label.

[0147] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0148] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0149] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. When implemented in software executed by a processor, the functions may be stored or transmitted as one or more instructions or codes on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. The mechanism for implementing the functions may also be physically located in various locations, including being distributed such that part(s) of the function are implemented in different physical locations. Also, as used in this specification, including the claims, "or" as used in a list of items (e.g., a list of items prefaced by a phrase such as "at least one" or "one or more of") refers to an inclusive list, such as, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used in this specification, the phrase "based on" shall not be construed as a reference to a closed set of conditions. For example, an example step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" shall be interpreted in the same manner as the phrase "based at least in part on."

[0150] Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. Non-transitory storage media can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and without limitation, computer-readable media can include RAM, ROM, Electrically Erasable Programmable Read-Only Memory (EEPROM), Compact Disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. Also, any connection is properly referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disk and disc include CDs, laser discs, optical disks, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where a disc reproduces data optically with a laser, while a disk typically reproduces data magnetically. Combinations of the above are also included within the scope of computer readable media.

[0151] The description herein is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. receiving a command at a first time at a memory device indicating that the memory device is to enter a sleep mode, the memory device including a set of internal power supplies associated with a plurality of discrete voltage levels; based at least in part on receiving the command, changing individual voltage levels for a first subset of the set of internal power supplies at a second time, wherein at least one internal power supply of the first subset of the set of internal power supplies is associated with a first voltage level that is different from an external power supply voltage level; maintaining, at least in part based on receiving the command, individual voltage levels for a second subset of the set of internal power supplies at the second time point, where at least one internal power supply of the second subset of the set of internal power supplies is associated with a second voltage level that is different from the external power supply voltage level; modifying the individual voltage levels for the second subset of the set of internal power supplies at a third time based at least in part on receiving the command. The method includes:

2. receiving a second command at the memory device indicating that the memory device should exit the sleep mode; modifying the individual voltage levels for the first subset of the set of internal power supplies at a fourth time based at least in part on receiving the second command, the modifying including restoring at least one internal power supply of the first subset of the set of internal power supplies to the first voltage level. The method of claim 1 further comprising:

3. receiving a second command at a fourth time at the memory device indicating that the memory device should exit the sleep mode; and modifying the individual voltage levels for the second subset of the set of internal power supplies at a fifth time based at least in part on receiving the second command, the modifying including restoring the at least one internal power supply of the second subset of the set of internal power supplies to the second voltage level; maintaining the individual voltage levels for the first subset of the set of internal power supplies at a fifth time point based at least in part on receiving the second command; and modifying the individual voltage levels for the first subset of the set of internal power supplies at a sixth time based at least in part on receiving the second command, the modifying including restoring the at least one internal power supply of the first subset of the set of internal power supplies to the first voltage level. The method of claim 1 further comprising:

4. maintaining, at least in part based on receiving the command, individual voltage levels for a third subset of the set of internal power supplies at the second time point and the third time point, wherein at least one internal power supply of the third subset of the set of internal power supplies is associated with a third voltage level different from the external power supply voltage level. The method of claim 1 further comprising:

5. modifying the individual voltage levels for the third subset of the set of internal power supplies at a fourth time based at least in part on receiving the command. The method of claim 4 further comprising:

6. receiving a second command at a fifth time at the memory device indicating that the memory device should exit the sleep mode; and modifying the individual voltage levels for the third subset of the set of internal power supplies at a sixth time based at least in part on receiving the second command, the modifying including restoring the at least one internal power supply of the third subset of the set of internal power supplies to the third voltage level; maintaining the respective voltage levels for the second subset and the first subset of the set of internal power supplies at the sixth time point based at least in part on receiving the second command; modifying the individual voltage levels for the second subset of the set of internal power supplies at a seventh time based at least in part on receiving the second command, the modifying including restoring the at least one internal power supply of the second subset of the set of internal power supplies to the second voltage level; maintaining the individual voltage levels for the first subset of the set of internal power supplies at the seventh time point based at least in part on receiving the second command; modifying the individual voltage levels for the first subset of the set of internal power supplies at an eighth time based at least in part on receiving the second command, the modifying including restoring the at least one internal power supply of the first subset of the set of internal power supplies to the first voltage level. The method of claim 5 further comprising:

7. the first subset of the set of internal power supply sources is associated with a first threshold for forward voltage bias, a first voltage level threshold for power supply operation, or a combination thereof; the second subset of the set of internal power supply sources is associated with a second threshold for forward voltage bias, a second voltage level threshold for power supply operation, or a combination thereof; The method of claim 1.

8. Varying the individual voltage levels for the first subset of the set of internal power supplies includes: activating respective bleeder circuits to change the respective voltage levels of the first subset of the set of internal power supplies from a respective first operating voltage level to a respective threshold voltage level from a respective first external power supply voltage level. The method of claim 1 , comprising:

9. Varying the individual voltage levels for the first subset of the set of internal power supplies includes: comparing the respective voltage levels of the first subset of the set of internal power supplies with the respective first external power supply voltage levels via respective comparators coupled to the respective bleeder circuits; deactivating the respective bleeder circuits based at least in part on comparing the respective voltage levels of the first subset of the set of internal power supplies to the respective first external power supply voltage levels; activating respective clamper circuits coupled to the respective comparators to maintain the respective voltage levels of the first subset of the set of internal power supplies at the respective threshold voltage levels from the respective first external power supply voltage levels based at least in part on comparing the respective voltage levels of the first subset of the set of internal power supplies to the respective first external power supply voltage levels. The method of claim 8 further comprising:

10. activating the respective clamper circuits is based at least in part on the respective voltage levels of the respective internal power supplies of the first subset of the set of internal power supplies reaching respective threshold voltage levels from a respective first external power supply voltage level.

10. The method of claim 9.

11. 9. The method of claim 8, wherein each respective first voltage level of the first subset of the set of internal power supplies is greater than each respective first external power supply voltage level.

12. A set of internal power supplies associated with a plurality of discrete voltage levels, comprising: a first subset of the internal power supplies including a first internal power supply associated with a first voltage level different from the external power supply voltage level; a second subset of internal power supplies including a second internal power supply associated with a second voltage level different from the external power supply voltage level; said set of internal power supplies including: Receiving a command at a first time indicating that the memory device is to enter a sleep mode; changing individual voltage levels for the first subset of the set of internal power supplies at a second time based at least in part on receiving the command; and maintaining individual voltage levels for the second subset of the set of internal power supplies at the second time based at least in part on receiving the command; modifying the individual voltage levels for the second subset of the set of internal power supplies at a third time based at least in part on receiving the command. A controller configured to a memory device.

13. The controller: receiving a second command at the memory device indicating that the memory device should exit the sleep mode; modifying the individual voltage levels for the first subset of the set of internal power supplies at a fourth time based at least in part on receiving the second command, the modifying including restoring the first internal power supply to the first voltage level. The memory device of claim 12 , further configured to:

14. The controller: receiving a second command at a fourth time at the memory device indicating that the memory device should exit the sleep mode; and modifying the individual voltage levels for the second subset of the set of internal power supplies at a fifth time based at least in part on receiving the second command, the modifying including restoring the second internal power supply to the second voltage level; maintaining the individual voltage levels for the first subset of the set of internal power supplies at the fifth time point based at least in part on receiving the second command; modifying the individual voltage levels for the first subset of the set of internal power supplies at a sixth time based at least in part on receiving the second command, the modifying including restoring the first internal power supply to the first voltage level. The memory device of claim 12 , further configured to:

15. the first subset of the set of internal power supply sources is associated with a first threshold for forward voltage bias, a first voltage level threshold for power supply operation, or a combination thereof; the second subset of the set of internal power supply sources is associated with a second threshold for forward voltage bias, a second voltage level threshold for power supply operation, or a combination thereof; The memory device of claim 12.

16. The memory device comprises: a first subset of bleeder circuits configured to change the respective voltage levels of the first subset of the set of internal power supplies from a respective first operating voltage level to a respective first threshold voltage level from a respective first external power supply voltage level; a second subset of bleeder circuits configured to change the respective voltage levels of the second subset of the set of internal power supplies from a respective second operating voltage level to a respective second threshold voltage level from a respective second external power supply voltage level; a set of bleeder circuits, a first subset of comparator circuits coupled to respective bleeder circuits of the first subset of bleeder circuits and configured to compare the respective voltage levels of the first subset of the set of internal power supplies with the respective first external power supply voltage levels; a second subset of comparator circuits coupled to respective bleeder circuits of the second subset of bleeder circuits and configured to compare the respective voltage levels of the second subset of the set of internal power supplies with the respective second external power supply voltage levels; A set of comparator circuits, including The memory device of claim 12 further comprising:

17. each respective first operating voltage level of the first subset of the set of internal power supplies is greater than each respective first external power supply voltage level; each respective second operating voltage level of the second subset of the set of internal power supplies is greater than each respective second external power supply voltage level; 17. The memory device of claim 16.

18. The memory device comprises: a first subset of clamper circuits coupled to respective comparator circuits of the first subset of comparator circuits and configured to maintain the respective voltage levels of the first subset of the set of internal power supply sources at the respective first threshold voltage levels from the respective first external power supply voltage levels based at least in part on the respective comparator circuits of the first subset; a second subset of clamper circuits coupled to respective comparator circuits of the second subset of comparator circuits and configured to maintain the respective voltage levels of the second subset of the set of internal power supply sources at the respective second threshold voltage levels from the respective second external power supply voltage levels based at least in part on the respective comparator circuits of the second subset; 20. The memory device of claim 16, further comprising a set of clamper circuits including:

19. The controller: activating individual clamper circuits of the first subset of clamper circuits based at least in part on the individual voltage levels of individual internal power supplies of the first subset of the set of internal power supplies reaching individual voltage level thresholds. The memory device of claim 18 , further configured to:

20. a first internal power supply associated with a first voltage level different from the external power supply voltage level; a second internal power supply associated with a second voltage level different from the first voltage level and different from the external power supply voltage level; a first bleeder circuit configured to change the first voltage level of the first internal power supply to a first external power supply voltage level; a second bleeder circuit configured to change the second voltage level of the second internal power supply to a second external power supply voltage level; a set of bleeder circuits, a first clamper circuit configured to maintain the first internal power supply at the first external power supply voltage level; a second clamper circuit configured to maintain the second internal power supply at the second external power supply voltage level; A set of clamper circuits including An apparatus comprising:

21. a third internal power supply associated with a third voltage level different from the first voltage level, the second voltage level, and the external power supply voltage level; a third bleeder circuit of the set of bleeder circuits, the third bleeder circuit configured to change the third voltage level of the third internal power supply to a third external power supply voltage level; a third clamper circuit of the set of clamper circuits, the third clamper circuit configured to maintain the third internal power supply at the third external power supply voltage level; 21. The apparatus of claim 20, further comprising:

22. The first bleeder circuit includes: one or more switching components configured to selectively couple the first internal power supply to a first external power supply source having the first external power supply voltage level; one or more resistors selectively coupleable to the first internal power source or the first external power source via the one or more switching components; 21. The apparatus of claim 20, comprising:

23. 21. The apparatus of claim 20, wherein each clamper circuit of the set of clamper circuits is associated with a respective comparator circuit configured to compare a respective voltage level of a respective internal power supply with a respective external power supply voltage level.

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