Transistor Structure

Abstract

To minimize a planar region used for layout isolation between an NMOS and a PMOS in order to avoid latch-up.SOLUTION: A semiconductor substrate exists beside an initial semiconductor surface (OSS) and has a border in a horizontal direction thereof. A more stable (planar) base for growing a second semiconductor region (for example, N+ doped regions 431 and 432) of source / drain regions of an NMOS transistor and a PMOS transistor is provided. A first semiconductor region 430 and a second semiconductor region (for example, N+ doped regions 431 and 432) are formed of selective epitaxial silicon (Si) or silicon / germanium (SiGe) and in the case of SiGe, a compression distortion is applied to the source / drain region and the ions of the NMOS transistor and the PMOS transistor are improved by 10 to 20%.SELECTED DRAWING: Figure 12B

Description

[Technical field]

[0001] The present invention relates to new transistors and / or new complementary MOSFET (CMOS) structures, in particular to new planar transistors and / or new complementary MOSFET (CMOS) structures that may reduce current leakage, reduce short channel effects, and prevent latch-up, for use, for example, in peripheral circuits or sense amplifiers of DRAMs. [Background technology]

[0002] In high-performance computing applications (such as artificial intelligence (AI), CPU, GPU, etc.), advanced technology nodes (such as 3-7 nm) are often used, while mature technology nodes (such as 20-30 nm) are still common in many IC applications such as power management ICs, MCUs, or DRAM chips. Using DRAM as an example, today, most customized DRAMs are still manufactured with mature technology nodes (such as 12-30 nm), and all transistors in DRAM chip 17 (as shown in FIG. 1A), including those in peripheral circuits 171 (including at least data / address I / O circuits, address decoders, command logic, refresh circuits, etc.) and those in array core circuits 172 (including storage memory arrays, sense amplifiers, etc.), are still planar transistors.

[0003] 1B shows a cross-sectional view of a conventional planar complementary metal oxide semiconductor field effect transistor (CMOSFET) 10, which is most widely used in the peripheral circuits of DRAM chips and in the sense amplifiers of the array core circuits of DRAM chips. The CMOSFET 10 includes a planar NMOS transistor 11 and a planar PMOS transistor 12, with a shallow trench isolation (STI) region 13 located between the NMOS transistor 11 and the PMOS transistor 12. The gate structure 14 of the NMOS transistor 11 or the PMOS transistor 12 using a specific conductive material (such as metal, polysilicon, or silicide) on an insulator (such as oxide, oxide / nitride, or a specific high-k dielectric, etc.) is formed on top of the CMOS transistor with sidewalls separated from those of the other transistors by using an insulating material (e.g., oxide or oxide / nitride, or other dielectric). For the planar NMOS transistor 11, there are source and drain regions formed by ion implantation and thermal annealing techniques to implant n-type dopants into a p-type substrate (or p-well), thus resulting in two spaced apart n+ / p junction regions. For the planar PMOS transistor 12, both the source and drain regions are formed by ion implantation of p-type dopants into an n-well, thus resulting in two p+ / n junction regions. In addition, it is common to form a lightly doped drain (LDD) region 15 under the gate structure to reduce impact ionization and hot carrier injection before the heavily doped n+ / p or p+ / n junctions.

[0004] Meanwhile, during the aforementioned thermal annealing process, the implanted n-type or p-type dopants in the CMOSFET 10 inevitably diffuse in different directions to enlarge the area of ​​the source and drain regions. In addition, another thermal annealing process occurs during the formation of a capacitor on the access transistor in the array core circuit of the DRAM chip to reduce the connection resistance between the capacitor and the access transistor. Such a second thermal annealing process again leads to the diffusion of n-type or p-type dopants to increase the area of ​​the source and drain regions. The larger the area of ​​the source and drain regions is due to the thermal annealing process, the shorter the effective channel length (Leff shown in FIG. 1B) between the source and drain regions is, and such a reduced effective channel length Leff leads to short channel effect (SCE). Therefore, in order to reduce the effect of SCE, it is common to ensure a longer gate length to accommodate the diffusion of n-type or p-type dopants due to thermal annealing. Taking a technology node (λ) of 25 nm as an example, the ensured gate length is about 100 nm, which is about four times the technology node λ.

[0005] On the other hand, since NMOS transistor 11 and PMOS transistor 12 are respectively located within adjacent regions of a portion of the p-substrate and n-well formed adjacent to each other in the vicinity, a parasitic junction structure called an n+ / p / n / p+ (the dashed path in FIG. 1B is called an n+ / p / n / p+ latch-up path) parasitic bipolar device is formed with its contour starting from the n+ region of NMOS transistor 11 to the p-well, to the nearby n-well, and further to the p+ region of PMOS transistor 12.

[0006] Once a large noise occurs on the n+ / p junction or p+ / n junction, a very large current may flow abnormally through this n+ / p / n / p+ junction, which may stop the operation of a part of the CMOS circuit and cause the whole chip to malfunction. Such an abnormal phenomenon, called latch-up, is harmful to CMOS operation and must be avoided. One way to improve the resistance to latch-up, which is certainly a weakness of CMOS, is to increase the distance from the n+ region to the p+ region (labeled as latch-up distance in FIG. 1B), and both the n+ and p+ regions must be designed to be separated by a specific vertically oriented oxide (or other suitable insulating material) as an isolation region, which is usually an STI (shallow trench isolation) region 13. Using a technology node (λ) of 25 nm as an example, the latch-up distance ensured is about 500 nm, which is about 20 times the technology node λ. More serious efforts to avoid latch-up must design guard band structures that further increase the distance between n+ and p+ regions, and / or add extra n+ or p+ regions to collect anomalous charges from noise sources. These isolation techniques always increase the extra planar area at the expense of the die size of the CMOS circuit.

[0007] Other problems are introduced or exacerbated in current DRAM designs with planar transistors or CMOSFETs.

[0008] (1) Junction leakage caused by junction formation processes such as the formation of LDD (lightly doped drain) structures in substrate / well regions, n+ source / drain structures in p-substrates, and p+ source / drain structures in n-wells are all becoming more difficult to control because lattice defects caused by ion implantation cause leakage currents through both the periphery and bottom regions where additional damage such as hole and electron vacancy traps are more difficult to repair.

[0009] (2) Furthermore, since the ion implantation for forming the LDD structure (or n+ / p or p+ / n junctions) acts like a bombardment to insert ions straight down from the top of the silicon surface into the substrate, it is difficult to form uniform material interfaces with fewer defects from the source and drain regions to the channel and substrate-body regions because the dopant concentration is non-uniformly distributed vertically from the top surface, where the doping concentration is higher, down to the junction regions, where the doping concentration is lower.

[0010] (3) It is becoming more difficult to align the edge of the LDD junction to the edge of the transistor gate structure in a perfect position only by using the conventional self-alignment method using the formation of the gate, spacer, and ion implantation. Moreover, the thermal annealing process to remove the damage caused by the ion implantation must rely on high temperature processing techniques such as rapid thermal annealing methods by using various energy sources or other thermal processes. One problem that arises is the gate-induced drain leakage (GIDL) current. (Quoted from A. Sen and J. Das, "MOSFET GIDL Current Variation with Impurity Doping Concentration - A Novel Theoretical Approach" IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO. 5, MAY 2017) As shown in Figure 1C, in a MOSFET structure with a thin oxide close to the gate and drain / source region, a parasitic metal gate diode exists, and the problematic GIDL is induced by the parasitic metal gate diode formed in the gate-to-source / drain region and is difficult to control even though it should be minimized to reduce the leakage current. Another problem that arises is that it is difficult to control the effective channel length and therefore difficult to minimize the SCE.

[0011] (4) Because the vertical length of STI structures is harder to make deeper while the planar width of device isolation must be made smaller (otherwise resulting in worse depth-to-opening aspect ratios for the integration processes of etching, filling, and planarizing), the proportional ratio of planar separation distance between n+ and p+ regions of adjacent transistors reserved for preventing latch-up to shrinking λ cannot be reduced but rather increased to the detriment of die area reduction when shrinking CMOS devices. Summary of the Invention

[0012] The present invention discloses several new concepts to realize new planar transistor and planar CMOSFET structures, especially used in the peripheral circuits of DRAM chips and in the sense amplifiers of the array core circuits of DRAM chips, which significantly improves or even solves most of the problems as mentioned above, such as minimizing current leakage, improving channel conduction performance and control, optimizing the functions of source and drain regions such as improving their conductance to metal interconnects and their closest physical contact to the channel region with seamless regular crystal lattice matching, increasing the higher immunity of CMOS circuits to latch-up, and minimizing the planar area used for layout isolation between NMOS and PMOS to avoid latch-up.

[0013] An object of the present disclosure is to provide a transistor structure, comprising: a semiconductor substrate with an initial semiconductor surface (OSS), a first gate region, a first recess formed in the semiconductor substrate below the initial semiconductor surface, a curved or concave opening formed in the first recess along a longitudinal direction of a sidewall of the semiconductor substrate, and a first conductive region formed in the first recess, the first doped region and a second doped region, the first doped region being based on the curved or concave opening along the longitudinal direction of the sidewall of the semiconductor substrate.

[0014] According to one embodiment of the present invention, the upper surface of the second doped region is flat or planar.

[0015] According to one aspect of the invention, the curved or concave shape is a sigma (Σ) shaped undercut.

[0016] According to one aspect of the invention, the transistor structure includes a metal plug contacting a top surface and a lateralmost sidewall of the second doped region, the second doped region being a highly doped region.

[0017] According to one aspect of the invention, the curved or concave opening includes a plurality of non-vertical semiconductor portion sidewalls, and the first doping region is selectively grown based on the plurality of non-vertical semiconductor portion sidewalls.

[0018] According to one aspect of the invention, the transistor structure further includes a first isolation region within the first recess, the first conductive region overlying the first isolation region.

[0019] According to one aspect of the invention, the curved or concave opening underlies the first gate region.

[0020] Another object of the present disclosure is to provide a transistor structure, the transistor structure including a semiconductor substrate with an OSS, a first transistor, and a second transistor. The first transistor includes a first gate region on the OSS, a first recess formed in the semiconductor substrate under the OSS, a curved or concave first undercut formed in the semiconductor substrate under the first gate region and communicating with the first recess, and a first conductive region having a first doping region and a second doping region. At least a portion of the first doping region is within the curved or concave first undercut. The second transistor includes a second gate region on the OSS, a second recess formed in the semiconductor substrate under the OSS, a curved or concave second undercut formed in the semiconductor substrate under the second gate region and communicating with the second recess, and a second conductive region having a third doping region and a fourth doping region. At least a portion of the third doped region is formed in the second curved or concave undercut.

[0021] According to one aspect of the present invention, the transistor structure further includes a first metal plug and a second metal plug, the first metal plug contacting a top surface and a lateral-most sidewall of the second doped region, the second doped region being a heavily doped region, and the second metal plug contacting a top surface and a lateral-most sidewall of the fourth doped region, the fourth doped region being a heavily doped region.

[0022] According to one aspect of the invention, the transistor structure further comprises a first isolation region and a second isolation region, the first isolation region being in the first recess, the first conductive region being over the first isolation region, the second isolation region being in the first recess, and the second conductive region being over the second isolation region.

[0023] According to one embodiment of the present invention, the upper surface of the second doped region is flat or planar, and the upper surface of the fourth doped region is flat or planar.

[0024] According to one aspect of the invention, the curved or concave first undercut includes a plurality of non-vertical semiconductor portion sidewalls, and the first doping region is selectively grown based on the plurality of non-vertical semiconductor portion sidewalls, and the curved or concave second undercut includes another plurality of non-vertical semiconductor portion sidewalls, and the third doping region is selectively grown based on the another plurality of non-vertical semiconductor portion sidewalls.

[0025] According to one aspect of the invention, the doping concentration of the first doped region is different from the doping concentration of the third doped region.

[0026] According to one aspect of the invention, the doping concentration of said second doped region is the same or substantially the same as said concentration of said fourth doped region. [Brief description of the drawings]

[0027] The above and other aspects of the present disclosure will become better understood with regard to the following detailed description of the preferred, but non-limiting, embodiment(s), the following description being made with reference to the accompanying drawings.

[0028] [Figure 1A] FIG. 1 shows a circuit diagram of a DRAM chip according to the prior art. [Figure 1B] FIG. 1 is a cross-sectional view showing a conventional CMOS structure. [Figure 1C] FIG. 1 illustrates a parasitic metal gate diode formed in the gate-to-source / drain region of a MOSFET and the GIDL problem in MOSFETs according to the prior art. [Figure 2A]1 is a top view of the processed structure after a pad nitride layer has been deposited and STI has been formed in the semiconductor substrate to define active areas for the NMOS and PMOS transistors. [Figure 2B] FIG. 2B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 2A. [Figure 3A] FIG. 13 is a top view of the processed structure after the gate length has been defined. [Figure 3B] FIG. 3B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 3A. [Figure 3-1A] FIG. 13 is a top view of the processed structure after shallow trenches are formed to form channel regions. [Figure 3-1B] FIG. 3-1B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 3-1A. [Figure 3-2A] FIG. 2 is a top view of the processed structure after a channel region has been selectively formed. [Figure 3-2B] FIG. 3-2B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 3-2A. [Figure 3-3A] FIG. 13 is a top view of the processed structure after shallow trenches with rounded features have been formed to form channel regions. [Figure 3-3B] FIG. 2 is a cross-sectional view taken along the cutting line (X-axis). [Figure 3-4A] FIG. 13 is a top view of the processed structure after selective formation of channel regions in shallow trenches with rounded features. [Figure 3-4B] FIG. 3-4B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 3-4A. [Figure 4A] FIG. 2 is a top view of the processed structure after a gate conductive region is formed. [Figure 4B] FIG. 4B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 4A. [Figure 5A] FIG. 13 is a top view of the processed structure after the gate cap region is formed. [Figure 5B]FIG. 5B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 5A. [Figure 6A] FIG. 13 is a top view of the processed structure after the pad nitride and pad oxide outside the gate region have been removed. [Figure 6B] FIG. 6B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 6A. [Figure 7A] FIG. 13 is a top view of the processed structure after spacers on the sidewalls of the gate region are formed. [Figure 7B] FIG. 7B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 7A. [Figure 8A] FIG. 13 is a top view of the processed structure after a recess outside the gate region is formed. [Figure 8B] FIG. 8B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 8A. [Figure 9A] FIG. 13 is a top view showing the processed structure after a local isolation layer is formed in the recess. [Figure 9B] FIG. 9B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 9A. [Figure 10A] FIG. 13 is a top view of the processed structure after a portion of the localized isolation layer within the recess has been removed to expose vertical semiconductor sidewalls. [Figure 10B] FIG. 10B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 10A. [Figure 11A] FIG. 13 is a top view of the processed structure after the vertical semiconductor sidewalls have been etched to define multiple sigma (Σ) shaped undercuts. [Figure 11B] FIG. 11B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 11A. [Figure 11B-1] FIG. 13 is a cross-sectional view illustrating a processed structure after vertical semiconductor sidewalls are etched to define a plurality of curved or concave shaped openings, e.g., a plurality of sigma (Σ) shaped undercuts, according to another embodiment of the present disclosure. [Figure 12A]13A is a top view of the processed structure after semiconductor regions have been extended laterally from exposed silicon sidewalls within multiple curved or concave openings, e.g., multiple sigma (Σ) shaped undercuts. [Figure 12B] 12B is a cross-sectional view taken along the cutting line (X-axis) as shown in FIG. 12A. [Figure 12B-1] FIG. 11B-1 is a cross-sectional view showing the processed structure after semiconductor regions have been extended laterally from the exposed silicon sidewalls within multiple curved or concave openings, such as multiple sigma (Σ) shaped undercuts, as shown in FIG. [Figure 12C] 4 is a cross-sectional view illustrating a processed structure after semiconductor regions have been extended laterally from exposed silicon sidewalls within the multiple recesses in accordance with another embodiment of the present disclosure. [Figure 12C-1] 4 is a cross-sectional view illustrating a processed structure after semiconductor regions have grown laterally from exposed silicon sidewalls within the multiple recesses according to yet another embodiment of the present disclosure. [Figure 13A] FIG. 2 is a top view of a new CMOS structure in accordance with one embodiment of the present invention. [Figure 13B] FIG. 13B shows a cross-section of the new CMOS structure along the cutting line (Y-axis) in FIG. 13A. [Figure 14] FIG. 1 shows a conventional CMOS structure with n+ and p+ regions that are not completely separated by an insulator. [Figure 15A] FIG. 1 is a top view of a new CMOS structure with NMOS and PMOS transistors. [Figure 15B] FIG. 15B shows a cross-section of the new CMOS structure along the horizontal dashed cut line in FIG. 15A. [Figure 16] FIG. 2 illustrates a possible latch-up path from an n+ / p junction through a p-well / n-well to an n / p+ junction structure in a conventional CMOS structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] This disclosure describes transistor structures and methods of processing thereof. These and other aspects of the disclosure will become better understood from the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.

[0030] Some embodiments of the present disclosure are disclosed below with reference to the accompanying drawings. However, the structures and contents disclosed in the above embodiments are merely for illustrative and descriptive purposes, and the scope of protection of the present disclosure is not limited to the above embodiments. It should be noted that the present disclosure does not show all possible embodiments, and a person skilled in the art of the present disclosure may make suitable modifications or changes based on the present specification disclosed below to meet actual needs without departing from the spirit of the present disclosure. The present disclosure is also applicable to other implementations not disclosed in the present specification.

[0031] The present invention discloses transistor and CMOSFET structures for use in particular in the peripheral circuits of DRAM chips and in the sense amplifiers of the array core circuits of DRAM chips.The fabrication methods of the proposed NMOS and PMOS transistors are exemplarily illustrated as follows. Step 10: Get started. Step 20: Based on the semiconductor substrate, define active areas of NMOS and PMOS transistors, and form deep shallow trench isolation (STI) structures. Step 30: Form a gate structure on the initial semiconductor surface of the semiconductor substrate. Step 40: Form spacers over the gate structure and form recesses in the semiconductor substrate. Step 50: forming a plurality of localized insulating layers within the recess. Step 60: Exposing the silicon sidewalls in the recesses and growing semiconductor regions laterally from the exposed silicon sidewalls in the recesses to form source and drain regions for the NMOS and PMOS transistors.

[0032] Referring to FIGS. 2A and 2B, step 20 may include: Step 202: A pad oxide layer 22 is formed and a pad nitride layer 23 is deposited. Step 204: A patterned photoresist (PR) is used to define the active areas of the planar NMOS and planar PMOS transistors, and a portion of the silicon material in the semiconductor substrate outside the active area patterns is removed to create temporary trenches. Step 206: An oxide layer is deposited in the created temporary trench, then the oxide layer is etched back and planarized to form shallow trench isolation (STI) 21, with the top surface of STI 21 aligned with the top surface of pad nitride layer 23, as shown in FIG. 2B, which is a cross-sectional view taken along the x-axis cut line in FIG. 2A.

[0033] Referring to FIGS. 3-5, the step 30 of forming a gate structure may include: Step 302: As shown in FIG. 3A and FIG. 3B, which is a cross-sectional view along the x-axis cut line in FIG. 3A, another patterned photoresist (PR) 31 is used to define the gate length (Lgate) of the gate regions of the NMOS and PMOS transistors, and then the portions of the pad oxide layer 302 and the pad nitride layer 304 not covered by the PR are removed to form the gate-accommodating trench 32. Step 304: As shown in FIG. 4A and FIG. 4B, which is a cross-sectional view along the x-axis cut line in FIG. 4A, thereafter, within the gate-receiving trench 32, a gate dielectric layer 331 (such as a thermal oxide or a high dielectric constant (Hi-K) material), a gate conductive layer 332 which may include heavily doped polysilicon (N+ polysilicon for MOS and P+ polysilicon for MOS), a Ti / TiN layer 333, and a tungsten layer 334 are formed. Step 306: As shown in FIG. 5A and FIG. 5B, which is a cross-sectional view taken along the x-axis section line in FIG. 5A, a nitride cap layer 335 and an oxide cap 336 are formed over the tungsten layer 334 to complete the gate regions or gate structures of the NMOS and PMOS transistors.

[0034] Next, referring to FIGS. 6-8, step 40 may include: Step 402: As shown in FIG. 6A and FIG. 6B, which is a cross-sectional view taken along the x-axis cut line in FIG. 6A, the pad oxide layer 22 and the pad nitride layer 23 between the STI layer 21 and the gate region are removed to expose the OSS of the semiconductor substrate. Step 404: As shown in FIG. 7A and FIG. 7B, which is a cross-sectional view along the x-axis cut line in FIG. 7A, form a spacer layer on both sides of the gate region, which may include a thin oxide sub-layer 343 thermally grown on the OSS of the semiconductor substrate, a thin nitride sub-layer 341 on the thin oxide sub-layer 343, and a thin oxide sub-layer 342. Step 406: As shown in Figure 8A and Figure 8B, which is a cross-sectional view along the x-axis cut line in Figure 8A, a portion of the semiconductor substrate is etched to form a plurality of recesses 311-314 in the semiconductor substrate. Each recess 311-314 includes an exposed vertical side 36 with a (110) orientation directly below the spacer layer in step 404 when the semiconductor substrate is a silicon substrate.

[0035] 9A and 9B, step 50 may include: in step 406, thermally growing an oxide-3 layer 41 including a vertical oxide-3V layer 411 covering the sidewalls of said recesses 311-314 and a horizontal oxide-3B layer 412 covering the bottoms of said recesses 311-314; thereafter, depositing a nitride-3 material to a thickness sufficient to completely fill said recesses 311-314, as shown in FIG. 9A and FIG. 9B, which is a cross-sectional view taken along the x-axis cut line in FIG. 9A, and then using an etch-back process to remove unnecessary portions of the nitride-3 material to leave only a suitable nitride-3 layer 42 inside said recesses 311-314; it should be noted that the nitride-3 layer 42 may be replaced by any suitable insulating material.

[0036] It should be noted that the thicknesses of the oxide-3V layer 411 and oxide-3B layer 412 depicted in FIG. 9B and subsequent figures are shown for illustrative purposes only, but it is very important to design this thermally grown oxide-3 layer 41 so that the thickness of the oxide-3V layer 411 is very precisely controlled under precisely controlled thermal oxidation temperature, timing and growth rate. Thermal oxidation on a well-defined silicon surface should result in 40% of the oxide-3V layer 411 thickness removing a portion of the silicon substrate from said exposed (110) vertical side 36, and the remaining 60% of the oxide-3V layer 411 thickness being considered as addition outside said exposed (110) vertical side 36 (such 40% and 60% distribution of the oxide-3V layer 411 is particularly clearly depicted in FIG. 9B). Because the thickness of the oxide-3V layer 411 is very precisely controlled based on the thermal oxidation process, the edge of the oxide-3V layer 411 can be aligned with the edge of the gate region. Of course, depending on the etching conditions and the conditions of the thermal oxide growth, in other embodiments, a portion of the oxide-3V layer 411 (such as less than 5-10%) may underlie the gate structure.

[0037] Referring to FIGS. 10A and 10B, step 60 may include: Step 602: As shown in Figures 10A and 10B, a portion of the oxide-3V layer 411 overlying the nitride-3 layer 42 is removed to expose vertical semiconductor sidewalls 501 and 502 in the recesses 311 and 312, which again have a (110) crystal orientation when the semiconductor substrate is a silicon substrate. The remaining oxide-3 layer 41 and nitride-3 layer 42 may be referred to as Local Isolation Into Silicon Substrate ("LISS"). Step 604: The vertical semiconductor sidewalls 501 and 502 having a (110) crystal orientation are etched to remove portions of the channel regions and define curved or concave openings (such as a plurality of arc-shaped openings, or a plurality of sigma (Σ)-shaped undercuts 512 and 513) along the vertical direction of the sidewalls or under the gate regions of the NMOS and PMOS transistors, e.g., as shown in Figures 11A and 11B, each of the sigma (Σ)-shaped undercuts 512 and 513 communicates with a corresponding recess 311 and 312, respectively, and includes a plurality of non-vertical semiconductor portion sidewalls. Step 606: First semiconductor regions 430 are grown laterally from the exposed non-vertical semiconductor sidewalls 501 and 502 of the sigma (Σ) shaped undercuts 513 and 514, respectively. Each first semiconductor region 430 at least fills the corresponding sigma (Σ) shaped undercut 513 or 514 and may include a lightly doped region (or lightly doped drain, "LDD"), or may include undoped and lightly doped regions. The first semiconductor regions 430 may be formed by a selectively grown method, such as a selective epitaxial growth (SEG) technique or an atomic layer deposition (ALD) technique. Step 608: Second semiconductor regions are grown from the first semiconductor regions 430. Each of the second semiconductor regions includes a heavily doped region, which may also be formed by a selectively grown method. Thus, the drain region of the NMOS transistor includes an N-LDD region and an N+ doped region 431, and the source region of the NMOS transistor includes another N-LDD region and an N+ doped region 432. Similarly, the drain region of the PMOS transistor includes a P-LDD region and a P+ doped region 441, and the source region of the PMOS transistor includes another P-LDD region and a P+ doped region 442. Note that the top surface of the P+ doped region 441 (442) or the N+ doped region 431 (432) may be flat or planar, or substantially parallel to the OSS of the semiconductor substrate.

[0038] It should be noted that in one embodiment, each of the N-LDD and P-LDD regions (e.g., first semiconductor region 430) formed by the SEG or ALD techniques has its horizontal boundary aligned (substantially aligned) with the OSS of the semiconductor substrate, as shown in Figure 12B. Thus, the alignment with the OSS of the semiconductor substrate may provide a more stable (planar) base for growing the second semiconductor regions (e.g., P+ doped regions 441 and 442, or N+ doped regions 431 and 432) of the source / drain regions of the NMOS and PMOS transistors.

[0039] In some embodiments of the present disclosure, the first semiconductor region 430 and the second semiconductor region (e.g., P+ doped regions 441 and 442, or N+ doped regions 431 and 432) may be formed of selective epitaxial silicon (Si) or silicon / germanium (SiGe), which may provide compressive strain to the source / drain regions to improve ion of NMOS and PMOS transistors by 10-20%.

[0040] Moreover, ion implantation and thermal annealing are not required during the formation of the transistor. There is no need to use ion implantation to form the LDD regions or source / drain regions, and no need to use a thermal annealing process to reduce defects. Therefore, the extra defects that are induced and difficult to completely remove even by the annealing process are never caused, so the unexpected leakage current source should be greatly minimized.

[0041] In some embodiments, the source / drain regions of the NMOS and PMOS transistors further include a metal region 351 formed on the N+ doped regions 431 and 432 of the source / drain regions of the NMOS transistor and the P+ doped regions 441 and 442 of the source / drain regions of the PMOS transistor. In this embodiment, as shown in FIG. 12C-1, the N+ doped regions 431 and 432 of the source / drain regions of the NMOS transistor and the P+ doped regions 441 and 442 of the source / drain regions in the PMOS transistor do not completely fill the recesses 311-314, and the metal region 351 is formed on the N+ doped regions 431 and 432 and the P+ doped regions 441 and 442 to completely fill the recesses 311-314 and surround the sidewalls of the N+ doped regions 431 and 432 and the P+ doped regions 441 and 442, respectively.

[0042] Additionally, in some other embodiments of the present disclosure, the LISS (including oxide-3 layer 41 and nitride-3 layer 42) may be omitted. For example, multiple sigma (Σ) shaped undercuts 513′ and 514′ under the gate regions of the NMOS and PMOS transistors may be formed by directly etching the exposed bottom and vertical sides 36 of the recesses 311-314 (as shown in FIG. 11B-1 ).

[0043] The first and second semiconductor regions can then be selectively grown. For example, the N-LDD region 430' of the drain / source region of the NMOS transistor and the P-LDD region (not shown) of the drain / source region of the PMOS transistor can be formed by a selectively grown method based on the non-vertical semiconductor part sidewalls of the sigma (Σ) shaped undercuts (e.g., the sigma (Σ) shaped undercuts 513' and 514' of the NMOS transistor). The N+ doped region 431' of the drain region and the N+ doped region 432' of the source region can then be formed by a selectively grown method based on the N-LDD region 430' of the drain / source region of the NMOS transistor (as shown in FIG. 12B-1). The P-LDD region (not shown) and the P+ doped region (not shown) of the drain / source region of the PMOS transistor can be formed by a similar method.

[0044] On the other hand, in the example of FIG. 12B, the source and drain regions of the transistor according to the present invention are separated by insulating material on the bottom structure (nitride-3 layer 42, and remaining oxide-3 layer 41) and separated along three sidewalls by STI layer 21, and the possibility of junction leakage occurs only in a very small area in first semiconductor region 430 to the channel region (directly below the gate region of the transistor), and may therefore be significantly reduced.

[0045] In another embodiment, the channel region may be formed (such as by ion implantation) under and near the initial silicon surface (OSS) of the semiconductor substrate prior to the formation of the gate structure. However, in addition to the channel region formed by ion implantation, the channel region according to the present invention may be formed by selective growth. For example, prior to forming the gate dielectric layer 331 in FIG. 4B, the exposed silicon surface may be etched to form a shallow trench having a depth of 1.5 nm to 3 nm, as shown in FIGS. 3-1A and 3-1B. Then, the channel region 24 is selectively grown in the shallow trench, as shown in FIGS. 3-2A and 3-2B.

[0046] Thereafter, the processes for forming the gate, source and drain regions shown in Figures 4 / 4B-12A / 12B may be similarly applied to form another transistor structure shown in Figure 12C.

[0047] In yet another embodiment, before forming the gate dielectric layer 331 in FIG. 4B, the exposed silicon surface may be etched to form a shallow trench having a round or curved shape, as shown in FIG. 3-3A and FIG. 3-3B. Then, the semiconductor channel region 24 is selectively grown along the sidewall of the shallow trench, as shown in FIG. 3-4A and FIG. 3-4B. Because the semiconductor channel region 24 is selectively grown along the sidewall of the shallow trench, which is a curved or round shape, the channel length in this embodiment may be longer. Then, the processes for forming the gate region, source region, and drain region shown in FIG. 4A / FIG. 4B-FIG. 12A / FIG. 12B may be similarly applied to form another transistor.

[0048] In another embodiment (e.g., FIG. 12C-1), the source (or drain) region may further comprise a metal plug, such as TiN / tungsten or other suitable metal material, contacting the top surface and lateral-most sidewall of the selectively grown highly doped region of the source (or drain) region. Thus, the source (or drain) region is a composite source (or drain) region. Thus, an external metal contact is connected to the metal region of the composite source (or drain) region, and such metal-to-metal contact has a much lower resistance than a conventional silicon-to-metal contact.

[0049] Further, as shown in Figures 13A-13B, Figure 13A is a top view of the new CMOS structure according to an embodiment of the present invention, and Figure 13B is a cross-sectional view of the new CMOS structure along the cutting line (Y-axis) in Figure 13A. The PMOS and NMOS transistors in Figures 13A-13B are located vertically side by side. In Figure 13A, the new CMOS structure is surrounded by STI 21 on four sides. Furthermore, as shown in Figure 13B, a local composite isolation (including oxide-3 layer 412 and nitride-3 layer 42) exists between the P+ source region 442 (or P+ drain region 441) of the PMOS and the n-type N-well, and another local composite isolation (including oxide-3B layer 412 and nitride-3 layer 42) also exists between the N+ source region 432 (or N+ drain region 431) of the NMOS and the p-type P-well or substrate.

[0050] That is, each of the drain and source regions of the new CMOS structure is surrounded by STI 21 on three sidewalls and by local composite isolation on the bottom wall. Thus, the possible latch-up path from the bottom of the PMOS P+ region to the bottom of the NMOS N+ region is completely blocked by the local isolation. Therefore, the latch-up distance Xp+Xn (measured on the planar surface) can be as small as possible without causing serious latch-up problems. On the other hand, in the conventional CMOS structure, the n+ and p+ regions are not completely separated by an insulator as shown in FIG. 1B or FIG. 14, and the possible latch-up path that exists from the n+ / p junction through the p-well / n-well junction to the n / p+ junction includes length a, length b, and length c.

[0051] Further, please refer to Figures 15A-15B according to another embodiment of the present invention. Figure 15A is a top view of a new CMOS structure with NMOS and PMOS transistors, and Figure 15B is a cross-sectional view of the new CMOS structure along the horizontal dashed cut line in Figure 15A. The PMOS and NMOS transistors in Figures 15A-15B are located side-by-side in the lateral direction. As shown in Figure 15B, it can be simplified that there is a cross-shaped LISS 70 between the PMOS and NMOS transistors. The cross-shaped LISS 70 includes a vertically extending isolation region 71 (e.g., STI 21, the vertical depth of the semiconductor substrate under the OSS as shown in FIG. 15B is about 150-300 nm, e.g., 200 nm), a horizontally extending first isolation region 72 (vertical depth is about 50-120 nm, e.g., 100 nm) on the right side of the vertically extending isolation region 71, and a horizontally extending second isolation region 73 (vertical depth is about 50-120 nm, e.g., 100 nm) on the left side of the vertically extending isolation region 71. Each of the horizontally extending isolation regions may include an oxide-3 layer 41 and a nitride-3 layer 42. The vertical depth of the source / drain regions of the PMOS / NMOS transistors is about 30-50 nm, e.g., 40 nm. The vertical depth of the gate region of the PMOS / NMOS transistor is about 40-60 nm, for example 50 nm as shown in FIG. 15B.

[0052] In this embodiment, the first and second horizontally extending isolation regions 72 / 73 are not directly under the gate structure or channel of the transistor. The first horizontally extending isolation region 72 (to the right of the vertically extending isolation region 71) contacts the bottom of the source / drain region of the PMOS transistor, and the second horizontally extending isolation region 73 (to the left of the vertically extending isolation region 71) contacts the bottom of the source / drain region of the NMOS transistor. Thus, the bottom side of the source / drain region in the PMOS and NMOS transistors is shielded from the semiconductor substrate. Furthermore, the first or second horizontally extending isolation region 72 / 73 may be a composite isolation that includes two or more different insulating materials (e.g., oxide-3 layer 41 and nitride-3 layer 42) or that includes the same two or more insulating materials but formed by separate processes.

[0053] As mentioned above in the text and in Figure 1B, the drawback of traditional CMOS configuration / technology in contrast to pure NMOS technology is that once there are parasitic bipolar structures such as n+ / p-sub / n-well / p+ junctions, unfortunately, some poor designs cannot withstand large current surges caused by noise and will cause latch-up, resulting in the whole chip operation being stopped or permanent damage to the chip function. Traditional CMOS layout and process rules always require a very large space to separate the n+ source / drain region of NMOS from the p+ source / drain region of PMOS, called the latch-up distance (Figure 1B), which uses up a lot of planar surface to prevent any possibility of latch-up. Moreover, if the source / drain n+ / p and p+ / n semiconductor junction areas are too large, once a forward bias accident is induced, a large surge current may be induced to cause latch-up.

[0054] TIFF0007674625000001.tif48164

[0055] On the other hand, in a conventional CMOS structure, the possible latch-up path from the n+ / p junction through the p-well / n-well junction to the n / p+ junction only includes length d, length e, length f, and length g (as shown in FIG. 16). Such possible latch-up path in FIG. 15B is longer than that in FIG. 16. Therefore, from the device layout point of view, the reserved edge distance (X n +X p ) may be smaller than that in FIG. 16. Moreover, in FIG. 15B, the potential latch-up path starts from the LDD-n / p junction to the n / LDD-p junction, not from the n+ / p junction to the n / p+ junction in FIG. 16. Because the doping concentration in the LDD-n or LDD-p region in FIG. 15B is lower than that in the n+ or p+ region in FIG. 16, the amount of electrons or holes emitted from the LDD-n or LDD-p region in FIG. 15B is much lower than that emitted from the n+ or p+ region in FIG. 16. Such a lower emission of carriers not only effectively reduces the possibility of the induced latch-up phenomenon, but also dramatically reduces the current when the latch-up phenomenon is induced. Because both the n+ / p and p+ / n junction areas are greatly reduced, even some sudden forward biasing of these junctions can reduce the magnitude of the abnormal current and reduce the chance of forming latch-up in FIG. 15B.

[0056] 15B again, according to the present invention, the source or drain region of the PMOS is surrounded by the first isolation region 72 extending in the horizontal direction and the isolation region 71 extending in the vertical direction, and only the LDD region (having a vertical length of about 10 to 50 nm) of the source or drain region of the PMOS is in contact with the semiconductor substrate to form an LDD-p / n junction, not a p+ / n junction. Similarly, the source or drain region of the NMOS is surrounded by the second isolation region 73 extending in the horizontal direction and the isolation region 71 extending in the vertical direction, and only the LDD region (having a vertical length of about 40 nm) of the source or drain region of the NMOS is in contact with the substrate to form an LDD-n / p junction, not a p+ / n junction. Therefore, the n+ region of the NMOS and the p+ region of the PMOS are shielded from the substrate or well region. Furthermore, the first or second isolation region 72 / 73 extending in the horizontal direction is composite isolation and thick enough to minimize the parasitic metal gate diode induced between the source (or drain) region and the silicon substrate. It is expected that the planar latch-up distance ensured by adjacent NMOS and PMOS transistors is greatly shortened so that the planar area of ​​the new CMOS can be greatly reduced.

[0057] In summary, the source / drain regions of the transistors in the CMOS structure are grown laterally from the curved or concave openings along the vertical direction of the sidewall of the semiconductor substrate, so that the top surface of the source / drain regions can be flat or planar with good quality. Furthermore, the LDD (lightly doped drain) surface is grown horizontally from both the transistor channel and the substrate body by in-situ doping technique during selective growth, and there is no ion implantation process that can be formed only from the top silicon downward into the source / drain regions, and no thermal annealing process that can make the junction boundary difficult to define and control. Unlike the conventional doped regions formed by ion implantation process, such selectively grown semiconductor regions (e.g., undoped regions, LDD regions, and heavily doped regions) are independent of the semiconductor substrate. The present invention can be applied to not only planar transistor structures, but also fin-like transistor structures.

[0058] Furthermore, in the present invention, SEG formation of LDD into heavily doped regions, including various non-silicon dopants such as germanium or carbon atoms, increases stress and improves channel mobility. The doping concentration profile can be controlled or tailored in the SEG / ALD formation of source / drain regions in accordance with the present invention.

[0059] Those skilled in the art will readily recognize that numerous modifications and variations of the apparatus and methods may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. a semiconductor substrate having an initial semiconductor surface (OSS); a first gate region; a first recess formed in the semiconductor substrate below the initial semiconductor surface; a curved or concave opening formed in the first recess along a vertical direction of a sidewall of the semiconductor substrate; a first conductive region formed in the first recess, the first conductive region including a first doped region and a second doped region; a metal plug contacting a top surface and a lateralmost sidewall of the second doped region; Equipped with the second doped region is a highly doped region; The first doping region is formed based on the curved or concave opening along the vertical direction of the sidewall of the semiconductor substrate. Transistor structure.

2. 2. The transistor structure of claim 1, wherein a top surface of the second doped region is flat or planar.

3. The transistor structure of claim 1 , wherein the curved or concave opening is a sigma (Σ) shaped undercut.

4. 2. The transistor structure of claim 1, wherein the curved or concave opening includes a plurality of non-vertical semiconductor portion sidewalls, and the first doped region is selectively grown based on the plurality of non-vertical semiconductor portion sidewalls.

5. 2. The transistor structure of claim 1, further comprising a first isolation region in the first recess, the first conductive region overlying the first isolation region.

6. The transistor structure of claim 1 , wherein the curved or concave opening underlies the first gate region.

7. A semiconductor substrate having an OSS; A first transistor, a first gate region over the OSS; a first recess formed in the semiconductor substrate below the OSS; a curved or concave first undercut formed in the semiconductor substrate beneath the first gate region and in communication with the first recess; a first conductive region having a first doped region and a second doped region, at least a portion of the first doped region being within the curved or concave first undercut; and a first metal plug contacting a top surface and a lateralmost sidewall of the second doped region, the second doped region being a heavily doped region; A first transistor comprising: a second transistor, a second gate region over the OSS; a second recess formed in the semiconductor substrate below the OSS; a curved or concave second undercut formed in the semiconductor substrate beneath the second gate region and in communication with the second recess; a second conductive region having a third doped region and a fourth doped region, at least a portion of the third doped region being within the curved or concave second undercut; and a second metal plug contacting a top surface and a lateralmost sidewall of the fourth doped region, the fourth doped region being a heavily doped region; A second transistor comprising: A transistor structure comprising:

8. The transistor structure further comprises: a first isolation region in the first recess, the first conductive region overlying the first isolation region; a second isolation region within the first recess, the second conductive region overlying the second isolation region; 8. The transistor structure of claim 7, comprising:

9. 8. The transistor structure of claim 7, wherein a top surface of the second doped region is flat or planar and a top surface of the fourth doped region is flat or planar.

10. 8. The transistor structure of claim 7, wherein the curved or concave first undercut comprises a plurality of non-vertical semiconductor portion sidewalls, the first doping region is selectively grown based on the plurality of non-vertical semiconductor portion sidewalls, and the curved or concave second undercut comprises another plurality of non-vertical semiconductor portion sidewalls, and a third doping region is selectively grown based on the another plurality of non-vertical semiconductor portion sidewalls.

11. A semiconductor substrate having an OSS; A first transistor, a first gate region over the OSS; a first recess formed in the semiconductor substrate below the OSS; a curved or concave first undercut formed in the semiconductor substrate beneath the first gate region and in communication with the first recess; and a first conductive region having a first doped region and a second doped region, at least a portion of the first doped region being within the curved or concave first undercut; A first transistor comprising: a second transistor, a second gate region over the OSS; a second recess formed in the semiconductor substrate below the OSS; a curved or concave second undercut formed in the semiconductor substrate beneath the second gate region and in communication with the second recess; and a second conductive region having a third doped region and a fourth doped region, at least a portion of the third doped region being within the curved or concave second undercut; A second transistor comprising: A transistor structure comprising: A transistor structure, wherein the doping concentration of the first doped region is different from the doping concentration of the third doped region.

12. 8. The transistor structure of claim 7, wherein the doping concentration of the second doped region is the same as the doping concentration of the fourth doped region.

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