Display panel and display device

Abstract

To provide a display panel that can improve the space use rate and resolution.SOLUTION: A display panel includes a first transistor and a second transistor electrically connected to each other. The first transistor includes a first active part formed of a low-temperature polysilicon material. The second transistor includes a second gate and a second active part formed of a metal oxide material. The display panel further includes a substrate. The first active part is disposed on the substrate. The second active part exists on one side of the first active part apart from the substrate. The second gate exists on one side of the second active part apart from the first active part. Here, the orthogonal projection of the second active part in the substrate and the orthogonal projection of the first active part in the substrate overlap with each other at least partially.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to the technical field of displays, and in particular to a display panel and a display device having the display panel. [Background technology]

[0002] In low temperature polycrystalline oxide (LTPO) array substrate, thin film transistors (TFT) are generally manufactured using two materials, low temperature polysilicon (LTPS) and metal oxide such as indium gallium zinc oxide (IGZO), where LTPS is responsible for driving the TFT and metal oxide is responsible for switching the TFT. The LTPO array substrate has the advantages of higher charge mobility and lower off-leakage current, which can reduce the overall power consumption during the screen operation and achieve the purpose of power saving.

[0003] However, in a display panel having an existing LTPO array substrate, an electrode plate is formed above the gate of the low-temperature polysilicon TFT, which requires a large amount of space, and the low-temperature polysilicon TFT and the metal oxide TFT are both independently disposed on the LTPO array substrate, which also requires a large amount of space, which is disadvantageous in improving the space utilization rate and resolution of the display panel. Summary of the Invention

[0004] SUMMARY OF THE DISCLOSURE The embodiments of the present invention provide a display panel and a display device that can reduce the space occupied by the first transistor and the second transistor and improve the space utilization rate and resolution of the display panel.

[0005] An embodiment of the present invention comprises: 1. A display panel including a first transistor and a second transistor electrically connected together, the first transistor including a first active portion made of a low temperature polysilicon material, the second transistor including a second gate and a second active portion made of a metal oxide material, the display panel comprising: A substrate; a first active layer disposed on the substrate and including the first active portion; a second active layer disposed on one side of the first active layer away from the substrate, the second active layer including the second active portion located on one side of the first active portion away from the substrate; a first metal layer disposed on one side of the second active layer away from the first active layer and including the second gate located on one side of the second active portion away from the first active portion, A display panel is provided, wherein an orthogonal projection of the second active portion on the substrate and an orthogonal projection of the first active portion on the substrate at least partially overlap.

[0006] In one embodiment of the present invention, the second transistor further includes a second source and a second drain, the display panel further includes a second metal layer disposed between the second active layer and the first active layer, the second metal layer includes the second source and the second drain, and both ends of the second active portion are connected to the second source and the second drain, respectively.

[0007] In one embodiment of the present invention, the second active portion includes a second sub-source contact portion located on a surface of the second source away from the first active portion, a second sub-drain contact portion located on a surface of the second drain away from the first active portion, and a second sub-trench portion connected between the second sub-source contact portion and the second sub-drain contact portion, and the second sub-trench portion is located between the second source and the second drain.

[0008] In one embodiment of the present invention, the resistivity of a material of the second sub-source contact portion and the resistivity of a material of the second sub-drain contact portion are both equal to the resistivity of a material of the second sub-trench portion.

[0009] In one embodiment of the present invention, the first transistor includes a first source and a first drain connected to both ends of the first active portion, The second metal layer further includes the first source and the first drain, and the second active portion is located between the first source and the first drain.

[0010] In one embodiment of the present invention, the first active portion includes a first sub-source contact connected to the first source and a first sub-drain contact connected to the first drain, and the second source is electrically connected to the first sub-drain contact.

[0011] In one embodiment of the present invention, the first source and the second drain are spaced apart.

[0012] In one embodiment of the present invention, the display panel further includes a light-shielding layer disposed in the substrate, the first active portion further includes a first sub-trench portion connected between the first sub-source contact portion and the first sub-drain contact portion, and a normal projection of the first sub-trench portion on the substrate and a normal projection of the second sub-trench portion on the substrate are both located within a normal projection of the light-shielding layer on the substrate.

[0013] In one embodiment of the present invention, the display panel further includes an anode layer disposed on one side of the first metal layer away from the second active layer, the anode layer including an anode electrically connected to the first transistor; The first metal layer includes a transition portion located between the anode and the first drain, and the anode is connected to the first drain through the transition portion.

[0014] In one embodiment of the present invention, an orthogonal projection of the second sub-trench portion on the substrate is located within an orthogonal projection of the anode on the substrate.

[0015] In one embodiment of the present invention, the display panel further includes an inorganic passivation layer and an organic planarization layer disposed between the second active layer and the anode layer, the inorganic passivation layer covering the second active layer and the organic planarization layer covering the inorganic passivation layer.

[0016] In one embodiment of the present invention, the first transistor further includes a first gate disposed between the first active portion and the second active portion, and an electrode plate disposed between the first gate and the second active portion, The orthogonal projection of the second sub-trench portion on the substrate is located within the orthogonal projection of the first gate on the substrate, and / or the orthogonal projection of the second sub-trench portion on the substrate is located within the orthogonal projection of the electrode plate on the substrate.

[0017] Based on the above objective of the present invention, an embodiment of the present invention further provides a display device including the display panel.

[0018] The beneficial effects of the present invention are as follows: In the present invention, the first active part of the first transistor and the second active part of the second transistor are arranged to be at least partially overlapped with each other, so that the first transistor and the second transistor can be at least partially overlapped with each other, which effectively reduces the occupied space of the first transistor and the second transistor, and improves the space utilization rate and resolution of the display panel. [Brief description of the drawings]

[0019] Hereinafter, specific embodiments of the present invention will be described in detail in conjunction with the drawings to make the technical solutions and other beneficial effects of the present invention clearer. [Figure 1] FIG. 1 is a cross-sectional structural diagram of a display panel according to a related art. [Diagram 2] 1 is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention. [Diagram 3] FIG. 2 is another cross-sectional view of a display panel provided in an embodiment of the present invention. [Figure 4] FIG. 2 is another cross-sectional view of a display panel provided in an embodiment of the present invention. [Diagram 5] FIG. 2 is yet another cross-sectional view of a display panel provided in an embodiment of the present invention. [Figure 6] 2 is a flowchart of a method for manufacturing a display panel provided in an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] In the following, the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention. Of course, the described embodiments are only a part of the embodiments of the present invention, and are not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

[0021] The following disclosure provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the following describes parts and arrangements in specific examples. Of course, they are merely illustrative and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or characters in different examples, and such repetition is for the purpose of brevity and clarity, and does not itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, the present invention provides examples of various specific steps and materials, but those skilled in the art may be aware of the application of other steps and / or the use of other materials.

[0022] Referring to FIG. 1, in the related art, in a display panel having an LTPO array substrate, a low-temperature polysilicon thin film transistor A and a metal oxide thin film transistor B need to be fabricated on the substrate, and a capacitance plate 1 needs to be formed above the gate of the low-temperature polysilicon thin film transistor A, whereby the capacitance plate 1 has a large area and requires a large space, and the low-temperature polysilicon thin film transistor A and the metal oxide thin film transistor B are both independently disposed on the LTPO array substrate, which also requires a large space, which is disadvantageous to improving the space utilization rate and resolution of the display panel.

[0023] Referring to FIG. 2, an embodiment of the present invention provides a display panel, which includes a first transistor T1 and a second transistor T2 electrically connected together, where the first transistor T1 includes a first active portion 21 made of low-temperature polysilicon material, and the second transistor T2 includes a second gate 41 and a second active portion 31 made of metal oxide material.

[0024] The display panel further includes a substrate 10, a first active layer 20, a second active layer 30, and a first metal layer 40, wherein the first active layer 20 is disposed on the substrate 10 and includes a first active portion 21, the second active layer 30 is disposed on one side of the first active layer 20 away from the substrate 10 and includes a second active portion 31 located on one side of the first active portion 21 away from the substrate 10, and the first metal layer 40 is disposed on one side of the second active layer 30 away from the first active layer 20 and includes a second gate 41 located on one side of the second active portion 31 away from the first active portion 21.

[0025] Here, the orthogonal projection of the second active portion 31 onto the substrate 10 and the orthogonal projection of the first active portion 21 onto the substrate 10 at least partially overlap.

[0026] In the process of implementation and application, the embodiment of the present invention arranges the first active part 21 of the first transistor T1 and the second active part 31 of the second transistor T2 to be at least partially overlapped with each other, so that the first transistor T1 and the second transistor T2 can be at least partially overlapped with each other, effectively reducing the space occupied by the first transistor T1 and the second transistor T2, and improving the space utilization rate and resolution of the display panel. In addition, the embodiment of the present invention arranges the second gate 41 of the second transistor T2 on one side away from the first active part 21 of the second active part 31, so that the spatial collision between the second gate 41 and the electrode plate can be avoided compared to the related art shown in FIG. 1, and the occurrence of parasitic capacitance can be reduced, and the reliability and stability of the display panel can be improved.

[0027] Specifically, referring to FIG. 2, the display panel includes a substrate 10, a driving circuit layer disposed on the substrate 10, and a light-emitting functional layer disposed on one side of the driving circuit layer away from the substrate 10.

[0028] Here, the substrate 10 may include a first flexible substrate layer 11, a first water vapor-oxygen barrier layer 12, a second flexible substrate layer 13, a second water vapor-oxygen barrier layer 14 and a third water vapor-oxygen barrier layer 15, which are sequentially stacked, and the material of the first flexible substrate layer 11 and the second flexible substrate layer 13 may include a polyimide material, and the material of the first water vapor-oxygen barrier layer 12, the material of the second water vapor-oxygen barrier layer 14 and the third water vapor-oxygen barrier layer 15 may include at least one of a silicon oxide material and a silicon nitride material.

[0029] The driving circuit layer is disposed on a substrate 10, and the display panel further includes a buffer layer 71 disposed between the substrate 10 and the driving circuit layer, and the driving circuit layer includes a first transistor T1 and a second transistor T2 disposed on the buffer layer 71, where the first transistor T1 and the second transistor T2 are electrically connected, and the first transistor T1 includes a first active portion 21, a first gate 61, an electrode plate 62, a first source 51 and a first drain 52, and the second transistor T2 includes a second active portion 31, a second gate 41, a second source 53 and a second drain 54.

[0030] Further, the driving circuit layer includes a first active layer 20 disposed on the buffer layer 71, a first insulating layer 72 covering the first active layer 20, a first gate 61 disposed on the first insulating layer 72, a gate insulating layer 73 covering the first gate 61, an electrode plate 62 disposed on the gate insulating layer 73, a second insulating layer 74 covering the electrode plate 62, a second metal layer 50 disposed on the second insulating layer 74, a second active layer 30 disposed on the second metal layer 50, an inorganic passivation layer 75 covering the second metal layer 50 and the second active layer 30, a first metal layer 40 disposed on the inorganic passivation layer 75, an organic planar layer 76 covering the first metal layer 40, an anode layer 80 disposed on the organic planar layer 76, and a pixel definition layer 77 disposed on the anode layer 80.

[0031] Specifically, the first active layer 20 includes a first active portion 21, and the material of the first active portion 21 includes a low-temperature polysilicon material, the first gate 61 is disposed on one side of the first active portion 21 away from the substrate 10, the electrode plate 62 is located on one side of the first gate 61 away from the first active portion 21, and the second metal layer 50 includes a first source 51 and a first drain 52, and the first source 51 and the first drain 52 are both connected to both ends of the first active portion 21 through the second insulating layer 74, the gate insulating layer 73 and the first insulating layer 72.

[0032] Correspondingly, the first active portion 21 includes a first sub-source contact portion 211 connected to the first source 51, a first sub-drain contact portion 212 connected to the first drain 52, and a first sub-trench portion 213 connected between the first sub-source contact portion 211 and the first sub-drain contact portion 212.

[0033] In one embodiment, by performing a conductive process on the first sub-source contact portion 211 and the first sub-drain contact portion 212, the resistivity of the material of the first sub-source contact portion 211 and the resistivity of the material of the first sub-drain contact portion 212 can be made smaller than the resistivity of the material of the first sub-trench portion 213.

[0034] The first transistor T1 may be a dual-gate thin film transistor, and the electrode plate 62 and the first gate 61 form a storage capacitance of the sub-pixel unit, so as to improve the continuous display effect of the display device.

[0035] The second metal layer 50 further includes a second source 53 and a second drain 54. The second active layer 30 includes a second active portion 31, a portion of which is located in the second insulating layer 74 and a portion of which extends to one side of the second source 53 and the second drain 54 away from the first active portion 21. Here, the second active portion 31 includes a second sub-source contact portion 311 located on a surface of the second source 53 away from the first active portion 21, a second sub-drain contact portion 312 located on a surface of the second drain 54 away from the first active portion 21, and a second sub-trench portion 313 connected between the second sub-source contact portion 311 and the second sub-drain contact portion 312. The second sub-trench portion 313 is located between the second source 53 and the second drain 54.

[0036] It should be noted that in the process, the second source 53 and the second drain 54 need to be formed first, and then the second active portion 31 needs to be formed; further, by controlling the distance between the second source 53 and the second drain 54, the length of the second sub-trench portion 313 located between the second source 53 and the second drain 54 can be controlled to realize a second transistor T2 having a short trench.

[0037] In the embodiment of the present invention, the orthogonal projection of the second active unit 31 on the substrate 10 and the orthogonal projection of the first active unit 21 on the substrate 10 at least partially overlap, so that the second transistor T2 and the first transistor T1 at least partially overlap, thereby reducing the space occupancy rate of the first transistor T1 and the second transistor T2, and improving the space utilization rate and resolution of the display panel. In addition, the area of ​​the electrode plate 62 is large, and the embodiment of the present invention arranges the second gate 41 of the second transistor T2 on one side away from the first active unit 21 of the second active unit 31, so that the spatial collision between the second gate 41 and the electrode plate 62 can be avoided, the occurrence of parasitic capacitance can be reduced, and the reliability and stability of the display panel can be improved.

[0038] The first metal layer 40 includes a second gate 41 , and the second gate 41 is located on one side of the second active portion 31 away from the first active portion 21 .

[0039] In one embodiment, the second sub-trench portion 313 is connected between the second source 53 and the second drain 54, and when a voltage is applied to the second gate 41, a current channel can be formed in the second sub-trench portion 313, and further, a current channel can be formed directly between the second source 53 and the second drain 54, without requiring a conductor treatment for the second active portion 31.

[0040] In the related art, as shown in FIG. 1, the active layer 2 of the metal oxide thin film transistor B needs to be conductively treated to form an electrical connection with the source and drain, but since the active layer 2 of the metal oxide thin film transistor B adopts a metal oxide process, it is easily affected by a heat process in a subsequent film layer stacking process, which causes carriers to be generated in the conductive portion and diffuse into the trench portion of the active layer, making the metal oxide thin film transistor B unstable. In addition, in the related art, two inorganic insulating layers, an interlayer insulating layer 3 and a passivation layer 4, are disposed above the active layer 2 of the metal oxide thin film transistor B. In contrast, in the embodiment of the present invention, as shown in FIG. 2, the second active portion 31 is disposed above the first transistor T1, and only one inorganic insulating layer, an inorganic passivation layer 75, is disposed above the second active portion 31, which can reduce the number of inorganic insulating layers above the second active portion 31 and further reduce the effect of the heat process on the second active portion 31 in the process of forming the inorganic insulating layer, thereby further improving the stability and yield rate of the second transistor T2.

[0041] Furthermore, as shown in FIG. 2, by disposing the second gate 41 on the second active portion 31 and increasing the covering area of ​​the second gate 41, the second sub-trench portion 313 corresponding to the second gate 41 is connected between the second source 53 and the second drain 54, and a current channel can be formed directly between the second source 53 and the second drain 54. As a result, the second active portion 31 does not need to be conductorized, the conductorization procedure can be omitted, and the phenomenon in which the second active portion 31 is affected by the thermal process and carrier diffusion occurs can be avoided, thereby improving the stability and yield rate of the second transistor T2.

[0042] In one embodiment, since the second active portion 31 does not require a conductive process, the resistivity of the material of the second sub-source contact portion 311 and the resistivity of the material of the second sub-drain contact portion 312 are both equal to the resistivity of the material of the second sub-trench portion 313.

[0043] In an embodiment of the present invention, the first source 51, the first drain 52, the second source 53 and the second drain 54 can be formed in the same process, and the process steps can be omitted; the second active portion 31 is located between the first source 51 and the first drain 52, the second drain 54 and the first source 51 are arranged at an interval, and the second source 53 realizes a connection with the first drain 52 through the first sub-drain contact portion 212, that is, the second source 53 can be connected to the first sub-drain contact portion 212 through the second insulating layer 74, the gate insulating layer 73 and the first insulating layer 72.

[0044] In addition, the display panel further includes a light-shielding layer 17 disposed in the substrate 10 , and the orthogonal projection of the first sub-trench portion 213 on the substrate 10 is located within a coverage area of ​​the orthogonal projection of the light-shielding layer 17 on the substrate 10 .

[0045] It should be noted that in an embodiment of the present invention, a light-shielding layer 17 is formed within the substrate 10, and the light-shielding layer 17 may be located between any two adjacent film layers within the substrate 10, for example, located on the second water vapor and oxygen barrier layer 14 and covered by the third water vapor and oxygen barrier layer 15.

[0046] In one embodiment, the coverage area of ​​the light-shielding layer 17 is increased, i.e., the orthogonal projection of the second sub-trench portion 313 on the substrate 10 is located within the coverage area of ​​the orthogonal projection of the light-shielding layer 17 on the substrate 10, so as to prevent light from being irradiated onto the second sub-trench portion 313 from the side of the second active portion 31 closer to the substrate 10, as shown in FIG. 2, thereby improving the stability of the second transistor T2.

[0047] In one embodiment, the coverage area of ​​the first gate 61 is increased, i.e., the orthogonal projection of the second sub-trench portion 313 on the substrate 10 is located within the coverage area of ​​the orthogonal projection of the first gate 61 on the substrate 10, so as to prevent light from being irradiated onto the second sub-trench portion 313 from the side of the second active portion 31 closer to the substrate 10, as shown in FIG. 3, thereby improving the stability of the second transistor T2.

[0048] In one embodiment, the coverage area of ​​the electrode plate 62 is increased, i.e., the orthogonal projection of the second sub-trench portion 313 on the substrate 10 is located within the coverage area of ​​the orthogonal projection of the electrode plate 62 on the substrate 10, so as to prevent light from being irradiated onto the second sub-trench portion 313 from the side of the second active portion 31 closer to the substrate 10, as shown in FIG. 4, thereby improving the stability of the second transistor T2.

[0049] In one embodiment, the coverage areas of at least two of the light-shielding layer 17, the first gate 61, and the electrode plate 62 can be increased, and the orthogonal projection of the second sub-trench portion 313 on the substrate 10 can be positioned within the coverage areas of at least two of the light-shielding layer 17 on the substrate 10, the orthogonal projection of the first gate 61 on the substrate 10, and the orthogonal projection of the electrode plate 62 on the substrate 10.

[0050] The display panel further includes an anode layer 80 arranged on one side of the first metal layer 40 away from the second active layer 30, the anode layer 80 including an anode 81 electrically connected to the first transistor T1, and the anode 81 electrically connected to the first drain 52.

[0051] In one embodiment, the first metal layer 40 further includes a conversion portion 42, and the anode 81 is connected to the first drain 52 through the conversion portion 42. The embodiment of the present invention can simplify the process steps and reduce the process costs by manufacturing the anode 81 and the conversion portion 42 in the same layer.

[0052] Here, since the orthogonal projection of the second sub-trench portion 313 on the substrate 10 is located within the coverage area of ​​the orthogonal projection of the anode 81 on the substrate 10, light from one side of the second active portion 31 away from the substrate 10 can be prevented from irradiating the second sub-trench portion 313, thereby further improving the stability of the second transistor T2.

[0053] In one embodiment, referring to FIG. 5, the second source 53 and the second drain 54 are connected, i.e., the second source 53 and the second drain 54 are integrally formed and disposed, which can further simplify the process steps and reduce the process cost.

[0054] In view of the above, the embodiment of the present invention arranges the first active part 21 of the first transistor T1 and the second active part 31 of the second transistor T2 to be at least partially overlapped with each other, so that the first transistor T1 and the second transistor T2 can be at least partially overlapped with each other, effectively reducing the space occupied by the first transistor T1 and the second transistor T2, and improving the space utilization rate and resolution of the display panel. In addition, the embodiment of the present invention arranges the second gate 41 of the second transistor T2 on one side away from the first active part 21 of the second active part 31, which can avoid the spatial collision between the second gate 41 and the electrode plate compared to the prior art, and can reduce the occurrence of parasitic capacitance, thereby improving the reliability and stability of the display panel.

[0055] In addition, an embodiment of the present invention further provides a method for manufacturing a display panel, which is the display panel according to the above embodiment, see FIG. 2, the method for manufacturing the display panel includes the following steps:

[0056] A substrate 10 is provided.

[0057] A first active layer 20 is formed on the substrate 10, the first active layer 20 including a first active portion 21 of a first transistor T1, the first active portion 21 being made of a low temperature polysilicon material.

[0058] A second active layer 30 is formed on one side of the first active layer 20 away from the substrate 10, the second active layer 30 including a second active portion 31 of a second transistor T2, the second active portion 31 being formed on one side of the first active portion 21 away from the substrate 10 and made of a metal oxide material, wherein a positive projection of the second active portion 31 on the substrate 10 and a positive projection of the first active portion 21 on the substrate 10 at least partially overlap.

[0059] A first metal layer 40 is formed on one side of the second active layer 30 away from the first active layer 20, and the first metal layer 40 includes a second gate 41 of the second transistor T2, the second gate 41 being formed on one side of the second active portion 31 away from the first active portion 21.

[0060] Specifically, referring to FIG. 2 and FIG. 6, the method for manufacturing the display panel includes the following steps S10, S20, S30, and S40.

[0061] In S10, a substrate 10 is provided.

[0062] In step S10, the substrate 10 may include a first flexible substrate layer 11, a first water vapor-oxygen barrier layer 12, a second flexible substrate layer 13, a second water vapor-oxygen barrier layer 14 and a third water vapor-oxygen barrier layer 15, which are sequentially stacked, and the material of the first flexible substrate layer 11 and the second flexible substrate layer 13 may include a polyimide material, and the material of the first water vapor-oxygen barrier layer 12, the material of the second water vapor-oxygen barrier layer 14 and the third water vapor-oxygen barrier layer 15 may include at least one of a silicon oxide material and a silicon nitride material.

[0063] It should be noted that in an embodiment of the present invention, a light-shielding layer 17 is formed within the substrate 10, and the light-shielding layer 17 may be located between any two adjacent film layers within the substrate 10, for example, located on the second water vapor and oxygen barrier layer 14 and covered by the third water vapor and oxygen barrier layer 15.

[0064] In S20, a first active layer 20 is formed on the substrate 10, the first active layer 20 including a first active portion 21 of a first transistor T1, the first active portion 21 being made of a low temperature polysilicon material.

[0065] In step S20, a buffer layer 71 is formed on the substrate 10.

[0066] Next, a first transistor T1 is formed on one side of the buffer layer 71 away from the substrate 10, specifically including: forming a first active portion 21 on the buffer layer 71 using a low-temperature polysilicon material; forming a first insulating layer 72 on the buffer layer 71 to cover the first active portion 21; forming a first gate 61 located on the one side of the first active portion 21 away from the substrate 10 on the first insulating layer 72; forming a gate insulating layer 73 on the first insulating layer 72 to cover the first gate 61; forming an electrode plate 62 located on the one side of the first gate 61 away from the first active portion 21 on the gate insulating layer 73; forming a second insulating layer 74 on the gate insulating layer 73 to cover the electrode plate 62; and forming a first metal material layer on the second insulating layer 74. Here, the first active portion 21 includes a first sub-trench portion 213 , and a first sub-source contact portion 211 and a first sub-drain contact portion 212 connected to both sides of the first sub-trench portion 213 .

[0067] Next, a patterning process is performed on the first metal material layer to obtain a second metal layer 50, and a first source 51 and a first drain 52 of the first transistor T1 are obtained, and the first source 51 and the first drain 52 are both connected to the first sub-source contact portion 211 and the first sub-drain contact portion 212, respectively, through the second insulating layer 74, the gate insulating layer 73 and the first insulating layer 72.

[0068] In addition, since the second source 53 and the second drain 54 of the second transistor T2 are further formed in the second metal layer 50, and the second transistor T2 needs to be electrically connected to the first transistor T1, the second source 53 may also be connected to the first sub-drain contact 212 through the second insulating layer 74, the gate insulating layer 73 and the first insulating layer 72.

[0069] In S30, a second active layer 30 is formed on one side of the first active layer 20 away from the substrate 10, the second active layer 30 including a second active portion 31 of a second transistor T2, the second active portion 31 being formed on one side of the first active portion 21 away from the substrate 10 and made of a metal oxide material, wherein a positive projection of the second active portion 31 on the substrate 10 and a positive projection of the first active portion 21 on the substrate 10 at least partially overlap.

[0070] In step S30, a metal oxide layer is formed on one side of the second metal layer 50 away from the substrate 10, and the material of the metal oxide layer can be indium gallium zinc oxide.

[0071] Next, a patterning process is performed on the metal oxide layer to obtain a second active layer 30, and the second active layer 30 includes a second active portion 31 formed by patterning, a portion of the second active portion 31 being located in the second insulating layer 74 and a portion of the second active portion 31 extending to one side away from the first active portion 21 of the second source 53 and the second drain 54, wherein the second active portion 31 includes a second sub-source contact portion 311 located on a surface of the second source 53 away from the first active portion 21, a second sub-drain contact portion 312 located on a surface of the second drain 54 away from the first active portion 21, and a second sub-trench portion 313 connected between the second sub-source contact portion 311 and the second sub-drain contact portion 312.

[0072] In an embodiment of the present invention, the orthogonal projection of the second active portion 31 on the substrate 10 and the orthogonal projection of the first active portion 21 on the substrate 10 at least partially overlap, so that the second transistor T2 and the first transistor T1 at least partially overlap, thereby reducing the space occupancy rate of the first transistor T1 and the second transistor T2, and improving the space utilization rate and resolution of the display panel.

[0073] In addition, in an embodiment of the present invention, the second source 53 and the second drain 54 are first fabricated, then the second active portion 31 is fabricated, and the distance between the second source 53 and the second drain 54 is then controlled to control the length of the second sub-trench portion 313 located between the second source 53 and the second drain 54, thereby realizing a second transistor T2 having a short trench.

[0074] An inorganic passivation layer 75 is formed on the second insulating layer 74 covering the second metal layer 50 and the second active layer 30 .

[0075] In S40, a first metal layer 40 is formed on one side of the second active layer 30 away from the first active layer 20, and the first metal layer 40 includes a second gate 41 of the second transistor T2, the second gate 41 being formed on one side of the second active portion 31 away from the first active portion 21.

[0076] In step S40, a second metal material layer is formed on one side of the inorganic passivation layer 75 away from the second active layer 30, and a patterning process is performed on the second metal material layer to obtain a first metal layer 40, wherein the first metal layer 40 includes a second gate 41 formed on one side of the second active portion 31 away from the first active portion 21, and a conversion portion 42 located above the first drain 52, where the conversion portion 42 is connected to the first drain 52 through the inorganic passivation layer 75.

[0077] In an embodiment of the present invention, the second active portion 31 includes a second sub-source contact portion 311 located on a surface of the second source 53 facing away from the first active portion 21, a second sub-drain contact portion 312 located on a surface of the second drain 54 facing away from the first active portion 21, and a second sub-trench portion 313 connected between the second sub-source contact portion 311 and the second sub-drain contact portion 312.

[0078] In one embodiment, the orthogonal projection of the second sub-trench portion 313 on the substrate 10 is located within the coverage range of the orthogonal projection of the light-shielding layer 17 on the substrate 10, which can prevent light from one side of the second active portion 31 close to the substrate 10 from irradiating the second sub-trench portion 313, thereby further improving the stability of the second transistor T2.

[0079] In one embodiment, the second sub-trench portion 313 is connected between the second source 53 and the second drain 54, and when a voltage is applied to the second gate 41, a current channel can be formed in the second sub-trench portion 313, and further, a current channel can be formed directly between the second source 53 and the second drain 54, without requiring a conductor treatment for the second active portion 31.

[0080] It should be noted that in the embodiment of the present invention, the second gate 41 is disposed in the second active portion 31, and the covering area of ​​the second gate 41 is increased, so that the second sub-trench portion 313 corresponding to the second gate 41 is connected between the second source 53 and the second drain 54, and a current channel can be directly formed between the second source 53 and the second drain 54, making it unnecessary for the second active portion 31 to be conductive, eliminating the need for the conductive process work procedure, and avoiding the phenomenon that the second active portion 31 is affected by the thermal process and causes carrier diffusion, thereby improving the stability and yield rate of the second transistor T2.

[0081] In addition, since the area of ​​the electrode plate 62 is large, and in this embodiment of the present invention, the second gate 41 of the second transistor T2 is disposed on one side of the second active unit 31 away from the first active unit 21, spatial collision between the second gate 41 and the electrode plate 62 can be avoided, the occurrence of parasitic capacitance can be reduced, and the reliability and stability of the display panel can be improved.

[0082] Next, an organic planarization layer 76 is formed to cover the first metal layer 40 on one side of the first metal layer 40 that is away from the second active layer 30 .

[0083] Next, an anode layer 80 is formed on one side of the organic planar layer 76 away from the first metal layer 40, the anode layer 80 including an anode 81 electrically connected to the first transistor T1, and the anode 81 is electrically connected to the first drain 52, and the anode 81 is further electrically connected to the first drain 52 via the conversion portion 42.

[0084] Here, since the orthogonal projection of the second sub-trench portion 313 on the substrate 10 is located within the coverage area of ​​the orthogonal projection of the anode 81 on the substrate 10, light from one side of the second active portion 31 away from the substrate 10 can be prevented from irradiating the second sub-trench portion 313, thereby further improving the stability of the second transistor T2.

[0085] Subsequently, a pixel definition layer 77 covering the anode layer 80 is formed on the organic planar layer 76 , and a pixel opening is formed in the pixel definition layer 77 to expose a portion of the upper surface of the anode 81 .

[0086] In view of the above, the embodiment of the present invention arranges the first active part 21 of the first transistor T1 and the second active part 31 of the second transistor T2 to be at least partially overlapped with each other, so that the first transistor T1 and the second transistor T2 can be at least partially overlapped with each other, effectively reducing the space occupied by the first transistor T1 and the second transistor T2, and improving the space utilization rate and resolution of the display panel. In addition, the embodiment of the present invention arranges the second gate 41 of the second transistor T2 on one side away from the first active part 21 of the second active part 31, which can avoid the spatial collision between the second gate 41 and the electrode plate compared to the prior art, and can reduce the occurrence of parasitic capacitance, thereby improving the reliability and stability of the display panel.

[0087] Moreover, an embodiment of the present invention further provides a display device, which includes the display panel and the device body described in the above embodiments, and the display panel and the device body are integrally assembled.

[0088] Here, the device body may include an inner frame, a frame adhesive, etc., and the display device may be a display terminal such as a mobile phone, a tablet, or a television, and is not limited to this in the present invention.

[0089] In the above embodiments, the emphasis of the description for each embodiment is different, and for parts that are not described in detail in one embodiment, reference can be made to related descriptions in other embodiments.

[0090] The display panel and the display device provided in the embodiments of the present invention have been described in detail above. In this specification, the principles and embodiments of the present invention have been described using specific examples, but the description of the above examples is merely for the purpose of easily understanding the technical solutions of the present invention and the main gist thereof, and it is naturally understood that those skilled in the art may modify the technical solutions described in the above embodiments or make equivalent replacements for some of the technical features thereof, and such modifications or equivalent replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. 1. A display panel including a first transistor and a second transistor electrically connected together, the first transistor including a first active portion made of a low temperature polysilicon material, the second transistor including a second gate and a second active portion made of a metal oxide material, the display panel comprising: A substrate; a first active layer disposed on the substrate and including the first active portion; a second active layer disposed on one side of the first active layer away from the substrate, the second active layer including the second active portion located on one side of the first active portion away from the substrate; a first metal layer disposed on one side of the second active layer away from the first active layer and including the second gate located on one side of the second active portion away from the first active portion, an orthogonal projection of the second active portion on the substrate and an orthogonal projection of the first active portion on the substrate at least partially overlap; the second transistor further includes a second source and a second drain, the display panel further includes a second metal layer disposed between the second active layer and the first active layer, the second metal layer includes the second source and the second drain, and both ends of the second active portion are respectively connected to the second source and the second drain, the second active portion includes a second sub-source contact portion located on a surface of the second source away from the first active portion, a second sub-drain contact portion located on a surface of the second drain away from the first active portion, and a second sub-trench portion connected between the second sub-source contact portion and the second sub-drain contact portion, the second sub-trench portion being located between the second source and the second drain, the first transistor further includes a first gate disposed between the first active portion and the second active portion, and an electrode plate disposed between the first gate and the second active portion, A display panel characterized in that the orthogonal projection of the second sub-trench portion on the substrate is located within the orthogonal projection of the first gate on the substrate, and / or the orthogonal projection of the second sub-trench portion on the substrate is located within the orthogonal projection of the electrode plate on the substrate.

2. 2. The display panel according to claim 1, wherein the resistivity of the material of the second sub-source contact portion and the resistivity of the material of the second sub-drain contact portion are both equal to the resistivity of the material of the second sub-trench portion.

3. The first transistor includes a first source and a first drain connected to both ends of the first active portion, The display panel of claim 1 , wherein the second metal layer further includes the first source and the first drain, and the second active portion is located between the first source and the first drain.

4. 4. The display panel of claim 3, wherein the first active portion includes a first sub-source contact connected to the first source and a first sub-drain contact connected to the first drain, and the second source is electrically connected to the first sub-drain contact.

5. The display panel of claim 4 , wherein the first source and the second drain are spaced apart from each other.

6. 2. The display panel of claim 1, further comprising a light-shielding layer disposed in the substrate, the first active portion further comprising a first sub-trench portion connected between a first sub-source contact portion and a first sub-drain contact portion, and a normal projection of the first sub-trench portion on the substrate and a normal projection of the second sub-trench portion on the substrate are both located within a normal projection of the light-shielding layer on the substrate.

7. an anode layer disposed on one side of the first metal layer away from the second active layer, the anode layer including an anode electrically connected to the first transistor; the first metal layer includes a transition portion located between the anode and the first drain; The display panel according to claim 3 , wherein the anode is connected to the first drain through the switching portion.

8. The display panel according to claim 1 , wherein the orthogonal projection of the second sub-trench portion on the substrate is located within the orthogonal projection of the anode on the substrate.

9. 8. The display panel of claim 7, further comprising an inorganic passivation layer and an organic planarization layer disposed between the second active layer and the anode layer, the inorganic passivation layer covering the second active region and the organic planarization layer covering the inorganic passivation layer.

10. A display device comprising the display panel according to claim 1 .

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