Semiconductor Device

Abstract

To provide a semiconductor device capable of reducing malfunction due to current noise and satisfactorily protecting a switching element from overcurrent, and a semiconductor module equipped with the semiconductor device.SOLUTION: A semiconductor device 1 includes a semiconductor substrate 6, a switching element formed on the semiconductor substrate 6, and a temperature sense diode 20 that is provided on the surface side of the semiconductor substrate 6 independently of the switching element and has temperature-dependent characteristics. Further, a semiconductor module equipped with the semiconductor device 1 is provided.SELECTED DRAWING: Figure 5B

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In a switching device, for example, if an overcurrent continues to flow during a short circuit, thermal destruction may occur. In order to prevent this malfunction, for example, Patent Document 1 discloses a semiconductor device including a semiconductor switching element, a semiconductor drive circuit, a sense element formed in the semiconductor switching element, and an overcurrent detection unit formed in the semiconductor drive circuit. The sense element is composed of a sense terminal through which a current proportional to the main current of the semiconductor switching element flows, and a sense resistor connected between the main terminal and the sense terminal of the semiconductor switching element and converts the sense current into a voltage. In addition, the overcurrent detection unit detects the sense current flowing through the above-mentioned sense element, and when the sense current exceeds a predetermined value, turns off the semiconductor switching element to protect the semiconductor switching element from an overcurrent. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-247804 A Summary of the Invention [Problem to be solved by the invention]

[0004] The overcurrent protection method of Patent Document 1 is a method of turning off a semiconductor switching element based on a sense current, so it is susceptible to the effects of noise, and sometimes a sense current containing noise may be mistakenly detected as an overcurrent. To prevent malfunctions caused by such noise, there is a method in which the semiconductor switching element is not turned off immediately even if the sense current exceeds a predetermined threshold, but is turned off after a certain waiting time (mask time) has elapsed.

[0005] However, there are still issues with this method of setting a waiting time. A certain waiting time is necessary to take into account the effects of noise (for example, about 500 ns), but as devices continue to have lower on-resistance, there are cases where the time it takes for an overcurrent to destroy a device becomes shorter than this waiting time, and the overcurrent protection system itself does not work.

[0006] Therefore, one embodiment of the present invention provides a semiconductor device that can reduce malfunctions caused by current noise and effectively protect switching elements from overcurrent. [Means for solving the problem]

[0007] One embodiment of the present invention provides a semiconductor device including a semiconductor substrate, a switching element formed on the semiconductor substrate, and a temperature sensing element provided on a front surface side of the semiconductor substrate independently of the switching element and having temperature-dependent characteristics.

[0008] Moreover, one embodiment of the present invention provides a single-function semiconductor device comprising a semiconductor substrate, a switching element formed on the semiconductor substrate, and a temperature sensing element provided on the front surface side of the semiconductor substrate independently of the switching element and having temperature-dependent characteristics, the temperature sensing element being formed by the switching element.

[0009] According to the above configuration, if a temperature change occurs on the front side of the semiconductor substrate, the characteristics (voltage value, resistance value, etc.) of the temperature sensing element change accordingly. Therefore, by monitoring the change in the characteristics of the temperature sensing element, it is possible to detect the temperature change of the semiconductor substrate. By utilizing this relationship, when an overcurrent flows through a switching element due to, for example, a short circuit, it is possible to detect the temperature rise of the semiconductor substrate caused by the overcurrent, and based on the detection result, it is possible to determine whether or not an overcurrent is flowing through the switching element. Moreover, since the object to be monitored is not the sense current flowing through the switching element, even if noise is introduced into the sense current and superimposed on it, the superimposed current will not be mistakenly detected as an overcurrent. Therefore, it is possible to reduce malfunctions caused by current noise.

[0010] One embodiment of the present invention includes a pair of first and second electrodes on the semiconductor substrate, and an electrical circuit between the first and second electrodes includes only the temperature sensing element as a circuit element.

[0011] In one embodiment of the present invention, the temperature sensing element includes a pn diode made of a polysilicon layer formed on the semiconductor substrate.

[0012] Polysilicon can be easily formed into the desired shape and position using already established semiconductor manufacturing technology. Therefore, by forming a polysilicon layer (pn diode) near the surface, which is the heat generating part of the semiconductor substrate, it is possible to detect temperature changes in the semiconductor substrate with high accuracy. For example, by constantly applying a constant current to a pn diode, the forward voltage V F By monitoring the temperature, it is possible to detect a change in the temperature of the semiconductor substrate.

[0013] In one embodiment of the present invention, the switching element includes a planar gate type MISFET having a gate electrode formed along a surface of the semiconductor substrate, and the polysilicon layer is formed in the same layer as the gate electrode.

[0014] According to this configuration, the polysilicon layer (pn diode) can be formed in the same process as the gate electrode, so that the increase in the number of processes involved in forming the pn diode can be suppressed. Also, since the pn diode can be disposed on the semiconductor substrate via a gate insulating film that is thinner than a relatively thick film such as an interlayer insulating film, the position of the pn diode can be brought close to the current path on the surface side of the semiconductor substrate. This improves the accuracy of detecting temperature changes in the semiconductor substrate.

[0015] In one embodiment of the present invention, the pn diode includes a p-type region and an n-type region surrounding the p-type region in a plan view.

[0016] According to this configuration, the p-type region and the n-type region do not overlap in a plan view, so that no additional wiring is required and contact can be easily made to both the p-type region and the n-type region.

[0017] In one embodiment of the present invention, the switching element includes a trench-gate type MISFET having a gate trench formed in the semiconductor substrate and a gate electrode embedded in the gate trench, and the polysilicon layer is embedded in a second trench formed in the semiconductor substrate independently from the gate trench.

[0018] According to this configuration, the second trench can be formed in the same process as the gate trench, and the polysilicon layer (pn diode) can be formed in the same process as the gate electrode, so that the increase in the number of processes involved in forming the pn diode can be suppressed. Also, since the pn diode is embedded in the surface portion of the semiconductor substrate, the position of the pn diode can be brought close to the current path on the surface side of the semiconductor substrate. This improves the accuracy of detecting temperature changes in the semiconductor substrate.

[0019] In one embodiment of the present invention, the gate trench and the second trench are formed to have the same width.

[0020] According to this configuration, since the etching rates for forming the gate trench and the second trench can be made substantially the same, the gate trench and the second trench can be finally formed to substantially the same depth. By making the depth of the second trench substantially the same as that of the gate trench in which the channel of the MISFET is formed, a temperature rise of the semiconductor substrate due to an overcurrent can be quickly detected.

[0021] In one embodiment of the present invention, the temperature sensing element includes a pn diode made of an impurity region formed in a surface portion of the semiconductor substrate.

[0022] Impurity regions can be easily formed at desired positions using already established semiconductor manufacturing technology. Therefore, by forming an impurity region (pn diode) in close proximity to the current path on the front side of the semiconductor substrate, which is the heat generating part of the semiconductor substrate, it is possible to detect temperature changes in the semiconductor substrate with high accuracy. For example, by constantly applying a constant current to a pn diode, the forward voltage V F By monitoring the temperature, it is possible to detect temperature changes in the semiconductor substrate. In addition, a pn diode made of an impurity region operates well even in high temperature ranges (e.g., 200°C or higher), so it is particularly effective for power devices such as SiC and GaN.

[0023] In one embodiment of the present invention, the pn diode includes a p-type region and an n-type region surrounding the p-type region in a plan view.

[0024] According to this configuration, the p-type region and the n-type region do not overlap in a plan view, so that no additional wiring is required and contact can be easily made to both the p-type region and the n-type region.

[0025] In one embodiment of the present invention, the temperature sensing element includes a series-connected unit in which a plurality of the pn diodes are connected in series.

[0026] With this configuration, the forward voltage V F Since the temperature change increases in proportion to the number of pn diodes connected, the sensitivity to detect temperature changes can be improved. For example, the forward voltage V per pn diode is F When the amplitude of the resistance is XmV / ℃, if five such pn diodes are connected in series to form a series-connected unit, the total amplitude of the series-connected unit can be made 5XmV / ℃.

[0027] In one embodiment of the present invention, the temperature sensing element includes at least a pair of the series-connected units connected in parallel in opposite directions to each other.

[0028] According to this configuration, there is no distinction between the anode and cathode polarities of the terminals of the pn diode assembly, so that the degree of freedom in wiring such as bonding wires can be improved when assembling a module or the like.

[0029] In one embodiment of the present invention, the temperature sensing element includes at least a pair of the pn diodes connected in series in the opposite directions to each other, forming an anti-series connection unit.

[0030] With this configuration, a reverse bias is applied to at least one of the pair of pn diodes, increasing the total resistance of the reverse series connection unit, which in turn reduces the current required to monitor temperature changes and achieves power savings.

[0031] In one embodiment of the present invention, the temperature sensing element includes a configuration in which a plurality of the anti-series connection units are connected in series.

[0032] This configuration makes it possible to achieve further power savings.

[0033] In one embodiment of the present invention, the temperature sensing element includes at least a pair of the pn diodes connected in parallel in opposite directions.

[0034] According to this configuration, there is no distinction between the anode and cathode polarities of the terminals of the pair of pn diodes, so that the degree of freedom in wiring such as bonding wires can be improved when assembling a module or the like.

[0035] In one embodiment of the invention, the temperature sensing element is disposed at the periphery of the semiconductor substrate.

[0036] This configuration allows a relatively large area to be secured in the area other than the area where the temperature sensing element is installed, so that the area of ​​the terminals for the switching elements can be made large. Therefore, even if the chip size is small, wiring members such as bonding plates and relatively thick bonding wires can be connected to the terminals.

[0037] In one embodiment of the invention, the semiconductor substrate comprises a SiC semiconductor substrate.

[0038] According to this configuration, the SiC switching element with low on-resistance can be effectively protected from overcurrent.

[0039] One embodiment of the present invention provides a semiconductor module including the semiconductor device and a second semiconductor device having a circuit electrically connected to the switching element and the temperature sensing element, the circuit cutting off the current path of the switching element when it is determined that an overcurrent is flowing through the switching element based on a characteristic change of the temperature sensing element.

[0040] According to this configuration, since the semiconductor device described above is included, it is possible to realize a semiconductor module that can reduce malfunctions caused by current noise and effectively protect switching elements from overcurrent. [Brief description of the drawings]

[0041] [Figure 1] FIG. 1 is a schematic external view of a semiconductor device according to one embodiment of the present invention. [Diagram 2] FIG. 2 is a circuit diagram of a semiconductor module including the semiconductor device of FIG. [Diagram 3] FIG. 3 is a diagram showing a more specific planar structure of the semiconductor device of FIG. [Figure 4A] FIG. 4A is a schematic plan view showing the structure of a cell region of the semiconductor device of FIG. [Figure 4B] FIG. 4B is a cross-sectional view (cross-sectional view taken along line BB) of FIG. 4A. [Figure 5A]5A is a schematic plan view showing the structure of a temperature sensing region of the semiconductor device of FIG. [Figure 5B] FIG. 5B is a cross-sectional view (cross-sectional view taken along line BB) of FIG. 5A. [Figure 5C] FIG. 5C is a diagram showing a modification of the structure of FIG. 5B. [Figure 6] FIG. 6 is a flow diagram of a manufacturing process of the semiconductor device. [Figure 7A] FIG. 7A is a diagram showing a part of the manufacturing process of the semiconductor device. [Figure 7B] FIG. 7B is a diagram showing the next step of FIG. 7A. [Figure 7C] FIG. 7C is a diagram showing the next step of FIG. 7B. [Figure 7D] FIG. 7D is a diagram showing the next step of FIG. 7C. [Figure 7E] FIG. 7E is a diagram showing the next step of FIG. 7D. [Figure 7F] FIG. 7F is a diagram showing the next step of FIG. 7E. [Figure 7G] FIG. 7G is a diagram showing the next step of FIG. 7F. [Figure 7H] FIG. 7H is a diagram showing the next step of FIG. 7G. [Figure 7I] FIG. 7I is a diagram showing the next step of FIG. 7H. [Figure 7J] FIG. 7J is a diagram showing the next step of FIG. 7I. [Figure 7K] FIG. 7K is a diagram showing the next step of FIG. 7J. [Figure 7L] FIG. 7L is a diagram showing the next step of FIG. 7K. [Figure 8] FIG. 8 is a graph illustrating how the forward voltage of the temperature sensing diode changes with temperature. [Figure 9A] 9A is a schematic plan view showing the structure of a temperature sensing region of the semiconductor device of FIG. [Figure 9B] FIG. 9B is a cross-sectional view (cross-sectional view taken along line BB) of FIG. 9A. [Figure 10]FIG. 10 is a diagram showing an example of a connection form of the temperature sensing diode. [Figure 11] FIG. 11 is a diagram showing an example of a connection form of the temperature sensing diode. [Figure 12] FIG. 12 is a diagram showing an example of a connection form of the temperature sensing diode. [Figure 13] FIG. 13 is a diagram showing an example of a connection form of the temperature sensing diode. [Figure 14] FIG. 14 is a diagram showing an example of a connection form of the temperature sensing diode. [Figure 15A] 4 is a schematic plan view showing the structure of a cell region of the semiconductor device of FIG. 3. [Figure 15B] FIG. 15B is a cross-sectional view (cross-sectional view taken along line BB) of FIG. 15A. [Figure 16A] 16A is a schematic plan view showing the structure of a temperature sensing region of the semiconductor device of FIG. [Figure 16B] FIG. 16B is a cross-sectional view (cross-sectional view taken along line BB) of FIG. 16A. [Figure 16C] FIG. 16C is a cross-sectional view (cross-sectional view taken along line CC) of FIG. 16A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0043] FIG. 1 is a schematic external view of a semiconductor device 1 according to one embodiment of the present invention.

[0044] The semiconductor device 1 is a discrete semiconductor device and has a single function by a switching element SW. The switching element SW may be, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), or may be an IGBT (Insulated Gate Bipolar Transistor), a JFET (Junction Field Effect Transistor), a bipolar transistor, a thyristor, or the like. In this embodiment, the switching element SW is a MISFET. A source pad 2 and a gate pad 3 are formed on the surface of the semiconductor device 1 formed as a square chip in a plan view. The source pad 2 covers almost the entire surface, and the gate pad 3 is disposed in an inner region of the source pad 2. Although not shown, a drain electrode is formed on the back surface of the semiconductor device 1.

[0045] In addition to the switching element SW described above, the semiconductor device 1 is provided with a temperature sensing element TS. The temperature sensing element TS is disposed on the front surface side of the semiconductor device 1. The temperature sensing element TS is independent of the switching element SW and does not directly contribute to the switching operation of the switching element SW.

[0046] Next, an overview of an overcurrent protection method in a semiconductor module 4 including the semiconductor device 1 will be described. 2 is a circuit diagram of the semiconductor module 4 including the semiconductor device 1 of FIG.

[0047] The semiconductor module 4 includes the semiconductor device 1 and a gate driver G / D as an example of a second semiconductor device of the present invention having a short-circuit protection circuit 5. The semiconductor module 4 may include a semiconductor chip (IC, discrete, etc.) other than those shown in FIG.

[0048] The short-circuit protection circuit 5 is electrically connected independently to the gate G of the switching element SW and the temperature sensing element TS. The short-circuit protection circuit 5 constantly monitors the characteristics of the temperature sensing element TS. For example, if a short circuit occurs in the switching element SW and an overcurrent flows, the characteristics of the temperature sensing element TS change due to the associated heat generation. The short-circuit protection circuit 5 detects this change in characteristics as the occurrence of a short circuit in the switching element SW and turns off the gate G of the switching element SW. This blocks the drain current Id flowing between the source and drain (SD) of the switching element SW, protecting the switching element SW.

[0049] FIG. 3 is a diagram showing a more specific planar structure of the semiconductor device 1 of FIG.

[0050] The semiconductor device 1 includes a semiconductor substrate 6 that defines the outer shape of the semiconductor device 1, and has a structure in which a switching element SW and a temperature sensing element TS are formed on the semiconductor substrate 6.

[0051] The semiconductor substrate 6 has a rectangular shape in plan view, and almost the entire surface thereof is covered by a source pad 2 that is generally rectangular in plan view. A cell region 7 constituting a switching element SW is formed in a large part below the source pad 2. A gate pad 3 is disposed on at least one side of the outer periphery of the semiconductor substrate 6. A gate finger 8 is connected to the gate pad 3. The gate finger 8 extends to the center of the semiconductor substrate 6 to divide the cell region 7 into one side and the other side, and also extends to the periphery of the semiconductor substrate 6 to surround the cell region 7.

[0052] A temperature sensing region 9 constituting the temperature sensing element TS is formed in an inner region of the cell region 7. The temperature sensing region 9 is surrounded by the cell region 7. The temperature sensing region 9 may be located, for example, in the peripheral portion of the semiconductor substrate 6. If the temperature sensing region 9 is located in the peripheral portion of the semiconductor substrate 6, a relatively large area can be secured in the portion of the semiconductor substrate 6 other than the temperature sensing region 9, so that the area of ​​the source pad 2 can be made large. Therefore, even if the chip size is reduced, wiring members such as a bonding plate or a relatively thick bonding wire can be connected to the source pad 2.

[0053] In plan view, the first electrode 10 and the second electrode 11 are provided to sandwich the temperature sensing region 9. That is, the pair of the first electrode 10 and the second electrode 11 are arranged on the semiconductor substrate 6 with a gap between them, and the temperature sensing region 9 is formed in the region between the first electrode 10 and the second electrode 11. The first electrode 10 and the second electrode 11 are arranged, for example, side by side along one side of the semiconductor substrate 6 on which the gate pad 3 is arranged. This makes it easier to draw wiring members such as bonding wires from each of the gate pad 3, the first electrode 10, and the second electrode 11 in the same direction (the left direction of the paper in FIG. 3). In addition, the first electrode 10 and the second electrode 11, as well as the source pad 2, the gate pad 3, and the gate finger 8 are made of an electrode film of the same material, and can be formed simultaneously by, for example, forming the electrode film on the semiconductor substrate 6 and then patterning the electrode film. <Cell structure> Fig. 4A is a schematic plan view showing the structure (planar gate structure) of the cell region 7 of the semiconductor device 1 of Fig. 3. Fig. 4B is a cross-sectional view (cross-sectional view taken along line BB) of Fig. 4A.

[0054] The semiconductor substrate 6 may be, for example, a SiC substrate, or may be a GaN substrate, a Si substrate, or the like. The semiconductor substrate 6 may be an epitaxial substrate including a base substrate and an epitaxial layer crystal-grown thereon. In this embodiment, the semiconductor substrate 6 is an n-type SiC epitaxial substrate. The n-type SiC epitaxial substrate is an n-type SiC epitaxial substrate. + A substrate having a mold and the n + n-type substrate - and a type epitaxial layer. + The impurity concentration of the base substrate is, for example, 1.0×10 18 cm -3 ~1.0×10 20 cm -3 and n - The impurity concentration of the epitaxial layer is, for example, 5.0×10 14 cm -3 ~5.0×10 16 cm -3 Examples of n-type impurities include N (nitrogen), As (arsenic), and P (phosphorus).

[0055] As shown in Figures 4A and 4B, a plurality of p-type body regions 12 are formed in the surface portion of the semiconductor substrate 6 in the cell region 7. The plurality of p-type body regions 12 may be formed, for example, in a matrix shape in plan view as shown in Figure 4A, or may be formed in a stripe shape or honeycomb shape. Lines are set between adjacent p-type body regions 12 to partition each unit cell 13 of the switching element SW. The p-type impurity concentration of the p-type body regions 12 is, for example, 1 x 10 15 cm -3 ~1×10 20 cm -3 Examples of p-type impurities include B (boron) and Al (aluminum).

[0056] The surface portion of the inner region of the p-type body region 12 is + A p-type source region 14 is formed at a distance from the periphery of the p-type body region 12. +The n-type impurity concentration of the n-type source region 14 is higher than the impurity concentration of the n-type semiconductor substrate 6, and is, for example, 1×10 18 cm -3 ~5×10 21 cm -3 It may be.

[0057] n + The inner region of the source region 14 is + A body contact region 15 is formed. + The body contact region 15 is an n + The p-type source region 14 is formed so as to penetrate therethrough in the depth direction. + The p-type impurity concentration of the p-type body contact region 15 is higher than that of the p-type body region 12, and is, for example, 1×10 18 cm -3 ~5×10 21 cm -3 It may be.

[0058] A gate insulating film 16 is formed on the surface of the semiconductor substrate 6. The gate insulating film 16 may be made of, for example, silicon oxide (SiO2). The thickness of the gate insulating film 16 may be, for example, 300 Å to 600 Å.

[0059] A gate electrode 17 is formed on the gate insulating film 16. The gate electrode 17 is disposed on the periphery of the p-type body region 12 (n in plan view) with the gate insulating film 16 interposed therebetween. + The gate electrode 17 faces the n-type source region 14 (a portion surrounding the n-type source region 14). The gate electrode 17 is made of, for example, n-type polysilicon (n-type doped polysilicon), but may be made of p-type polysilicon. The thickness of the gate electrode 17 may be, for example, 6000 Å to 12000 Å.

[0060] An interlayer insulating film 18 is formed on the entire surface of the semiconductor substrate 6 to cover the gate electrode 17. The interlayer insulating film 18 may be made of, for example, silicon oxide (SiO2), or may have a structure in which a plurality of films made of silicon oxide are stacked as described later (see FIGS. 7I to 7L). The thickness of the interlayer insulating film 18 (the total thickness when it is made of a plurality of films) may be, for example, 1000 Å to 2000 Å. Although not shown, the interlayer insulating film 18 has a thickness of 1000 Å to 2000 Å. + type source region 14 and p + A wiring electrically connecting the mold body contact region 15 and a wiring electrically connecting the gate pad 3 and the gate electrode 17 are formed penetrating the mold body contact region 15 and the gate electrode 17, respectively. <Temperature sensing element structure> Fig. 5A is a schematic plan view showing the structure of the temperature sensing region 9 of the semiconductor device 1 of Fig. 3. Fig. 5B is a cross-sectional view (cross-sectional view taken along line BB) of Fig. 5A. Fig. 5C is a diagram showing a modified example of the structure of Fig. 5B.

[0061] 5A and 5B, a p-type region 19 is formed in the surface portion of the semiconductor substrate 6 in the temperature sensing region 9. The p-type region 19 may be an impurity region of the same conductivity type as the p-type body region 12, and the p-type impurity concentration and depth may also be the same as those of the p-type body region 12.

[0062] On the surface of the semiconductor substrate 6, the gate insulating film 16 of the cell region 7 is formed to extend to the temperature sensing region 9. A temperature sensing diode 20 (pn diode) as an example of a temperature sensing element TS is formed on the gate insulating film 16 in the temperature sensing region 9. The temperature sensing diode 20 faces the semiconductor substrate 6 with the gate insulating film 16 in between. For example, as shown in FIG. 5B, the entire temperature sensing diode 20 may face a single impurity region of the semiconductor substrate 6 (in this embodiment, the p-type region 19).

[0063] The temperature sensing diode 20 is made of, for example, a single polysilicon layer 21. The temperature sensing diode 20 made of the polysilicon layer 21 may be formed in the same layer as the gate electrode 17 by being formed in the same process as the gate electrode 17. That is, the polysilicon layer 21 may be formed to a thickness of 6000 Å to 12000 Å like the gate electrode 17. Of course, the polysilicon layer 21 may be formed in a process separate from the gate electrode 17, and may have a thickness different from that of the gate electrode 17.

[0064] The temperature sensing diode 20 includes a p-type region 22 and a n-type + The p-type region 22 includes an n-type region 23. + If the n-type region 23 surrounds the p-type region 22, + Since the p-type regions 22 and n-type regions 23 do not overlap each other in a plan view, no separate wiring is required. + Contact can be easily made to either of the mold regions 23 .

[0065] p-type region 22 and n + The p-type regions 23 may be formed so as to extend from the front surface to the rear surface of the polysilicon layer 21 as shown in FIG. 5B, or may be selectively formed in the front surface of the polysilicon layer 21, although this is not shown. + For example, the p-type region 22 and the n-type region 23 may not be surrounded by the p-type region 22. + The p-type regions 23 may be formed adjacent to each other, so that they may have a portion of an unshared periphery. The p-type impurity concentration of the p-type region 22 is, for example, 1×10 15 cm -3 ~1×10 20 cm -3 (same as p-type body region 12). + The n-type impurity concentration of the n-type region 23 is, for example, 1×10 18 cm -3 ~5×10 21 cm -3 (n + The source region 14 may be the same as the source region 14.

[0066] The temperature sensing diode 20 further includes p + The p-type contact region 24 and the p-type peripheral region 25 may be included. + The p-type contact region 24 is formed in the inner region of the p-type region 22 at a distance from the periphery of the p-type region 22, and the p-type peripheral region 25 is + It may be formed so as to surround the mold region 23. + The p-type contact region 24 and the p-type peripheral region 25 may be formed so as to extend from the front surface to the rear surface of the polysilicon layer 21 as shown in FIG. 5B, or may be selectively formed in the front surface of the polysilicon layer 21, although this is not shown. + The p-type impurity concentration of the contact region 24 is, for example, 1×10 18 cm -3 ~5×10 21 cm -3 (p + The p-type impurity concentration of the p-type peripheral region 25 may be, for example, 1×10 15 cm -3 ~1×10 20 cm -3 (the same as the p-type body region 12).

[0067] As shown in FIG. 5C, the temperature sensing diode 20 includes a p-type base layer 26 made of p-type polysilicon (p-type doped polysilicon) of the opposite conductivity type to the gate electrode 17, and a n-type doped polysilicon selectively formed on the surface of the p-type base layer 26. + Type region 23 and p + The semiconductor device may have a structure including a mold contact region 24.

[0068] The temperature sensing diode 20 is covered with an interlayer insulating film 18 on the semiconductor substrate 6. The first electrode 10 is connected to a p + The second electrode 11 is connected to the n-type contact region 24 as a cathode electrode through a contact hole 28 in the interlayer insulating film 18. +The temperature sensing diode 20 is connected to the first region 23. The first electrode 10 and the second electrode 11 connected to both ends of the temperature sensing diode 20 are formed separately from the source pad 2 and the gate pad 3 for the switching element SW, as described above. Therefore, the temperature sensing diode 20 is electrically independent from the switching element SW.

[0069] Polysilicon can be easily formed in a desired shape and position by using already established semiconductor manufacturing technology. Therefore, the temperature sensing diode 20 can be formed near the switching element SW and near the surface of the semiconductor substrate 6, which is a heat generating portion, to detect temperature changes in the semiconductor substrate 6 with high accuracy. For example, when a constant current is applied to the temperature sensing diode 20, the forward voltage V F By monitoring the temperature change of the semiconductor substrate 6, it is possible to detect the temperature change of the semiconductor substrate 6. For example, a constant current of 1 μA is applied, and a forward voltage V F The current may be a constant current in the range of 1 μA to 100 μA.

[0070] The second electrode 11 integrally includes, on the interlayer insulating film 18, a ring-shaped contact portion 30 having an open portion 29 in a portion thereof, and a linear extraction portion 31 extending from the contact portion 30. The contact portion 30 surrounds the p-type region 22 in a plan view. The contact hole 28 is formed in a ring shape with a portion being open along the contact portion 30.

[0071] The first electrode 10 integrally includes, on the interlayer insulating film 18, a contact portion 32 surrounded by the contact portion 30 of the second electrode 11, and a linear extraction portion 33 extending from the contact portion 32 through the open portion 29. The contact portion 32 is p + The contact hole 27 is disposed on the mold contact region 24. The contact hole 27 is formed below the contact portion 32 so as to overlap the contact portion 32.

[0072] Next, a method for manufacturing the semiconductor device 1 will be described. Fig. 6 is a flow diagram of the manufacturing process of the semiconductor device 1. Figs. 7A to 7L are diagrams showing some of the manufacturing process of the semiconductor device 1 in the order of steps. Note that Figs. 7A to 7L do not correspond to each of the steps in Fig. 6. Below, the manufacturing process of the semiconductor device 1 will be described according to the flow in Fig. 6, and Figs. 7A to 7L will be referred to as necessary.

[0073] To manufacture the semiconductor device 1, for example, epitaxial growth is performed on n + n-type substrate - A type epitaxial layer is formed (step S1), thereby forming a semiconductor substrate 6.

[0074] Next, the p-type body region 12 and the p-type region 19 are formed by selectively injecting p-type impurities into the semiconductor substrate 6 (step S2). Similarly, the n-type body region 12 and the p-type region 19 are formed by selectively injecting n-type impurities and p-type impurities into the semiconductor substrate 6 (step S3). + type source region 14 and p + A mold body contact region 15 is formed (steps S3 and S4).

[0075] 7A, the semiconductor substrate 6 is thermally oxidized to form a gate insulating film 16 on the surface of the semiconductor substrate 6 (step S5). Next, the gate electrode 17 and the polysilicon layer 21 serving as the base of the temperature sensing diode 20 are formed by, for example, CVD (step S6). Next, a hard mask 34 (for example, having a thickness of about 9000 Å) made of silicon oxide (SiO2) is formed by, for example, CVD (step S7).

[0076] 7B, a resist film 35 for lithography of the hard mask 34 is formed (step S8). The resist film 35 is formed on the p-type region 22 and the n-type region 23. + It is formed overlying a hard mask 34 over areas 36 where mold regions 23 are to be formed.

[0077] 7C, the hard mask 34 is selectively etched through the resist film 35 (step S9). The etching may be performed by wet etching using hydrofluoric acid. After the etching, the resist film 35 is removed.

[0078] 7D, an n-type impurity (e.g., phosphorus) is deposited in a region 37 of the polysilicon layer 21 exposed from the hard mask 34 (a region other than the region 36 of the polysilicon layer 21) and diffused at about 1000° C., for example, to introduce the n-type impurity into the region 37 (step S10). As a result, the region 37 including the gate electrode 17 of the polysilicon layer 21 becomes n-type polysilicon, while the region 36 remains undoped.

[0079] 7E, the hard mask 34 remaining on the polysilicon layer 21 is removed by etching (step S11). The etching may be performed by wet etching using hydrofluoric acid, for example.

[0080] 7F, while the gate electrode 17 portion of the polysilicon layer 21 is selectively covered with a mask (not shown), boron, which is a p-type impurity, is implanted into the entire surface of the polysilicon layer 21 (step S12). As a result, the region from the surface of the polysilicon layer 21 to the middle of the thickness direction becomes a p-type region 38.

[0081] Next, as shown in FIG. 7G, the n + After a mask (not shown) that selectively exposes the region in which the n-type region 23 is to be formed is formed by lithography, n-type impurities are implanted into the region 36 through the mask (step S13). + A mold region 23 is formed. At this time, n + As shown in FIG. 7G, the mold region 23 may be formed only halfway through the thickness direction of the polysilicon layer 21 from the surface thereof.

[0082] Next, as shown in FIG. 7H, the p+ After a mask (not shown) that selectively exposes the region in which the p-type contact region 24 is to be formed is formed by lithography, p-type impurities are implanted into the region 36 through the mask (step S14). + In this case, the p-type contact region 24 is formed. + As shown in FIG. 7H, the mold contact region 24 may be formed only halfway through the thickness direction of the polysilicon layer 21 from the surface thereof.

[0083] Next, as shown in Fig. 7I, a hard mask 39 is formed to selectively cover the regions of the polysilicon layer 21 where the temperature sensing diode 20 and the gate electrode 17 are to be formed, and then the polysilicon layer 21 is selectively etched through the hard mask 39. As a result, the temperature sensing diode 20 and the gate electrode 17 (not shown in Fig. 7I) are formed.

[0084] Next, as shown in Fig. 7J, a plurality of insulating films are formed by, for example, a CVD method while leaving the hard mask 39. The plurality of insulating films may include, for example, a lower silicon oxide film 40 (for example, a non-doped silicate glass (NSG) film) and an upper silicon oxide film 41 (for example, a phosphorus silicate glass (PSG) film, a boron phosphorus silicate glass (BPSG) film, etc.) as shown in Fig. 7J. In this way, the interlayer insulating film 18 consisting of the hard mask 39, the silicon oxide film 40, and the silicon oxide film 41 is formed (step S15).

[0085] Next, as shown in FIG. 7K, the interlayer insulating film 18 is selectively etched to form the contact holes 27 and 28 (Step S16).

[0086] Next, as shown in FIG. 7L, the semiconductor substrate 6 is heat-treated (reflowed) (step S17). The heat treatment is performed, for example, in a nitrogen (N2) atmosphere at 900° C. to 1200° C. for 5 minutes to 15 minutes. As a result, the p-type regions 38 and n-type regions 39 remaining in the surface portion of the polysilicon layer 21 are + Type region 23 and p + The mold contact region 24 diffuses until it reaches the back surface of the polysilicon layer 21 .

[0087] Thereafter, various wirings, the source pad 2, the gate pad 3, the first electrode 10, the second electrode 11, a passivation film, and the like are formed, and thus the semiconductor device 1 is obtained.

[0088] Next, the operation of the semiconductor device 1 in the semiconductor module 4 and the overcurrent protection method will be described in more detail.

[0089] The electrical circuit configuration of the semiconductor module 4 is as shown in FIG. 2. A voltage is applied to the semiconductor device 1 connected in this manner by the gate driver G / D. Specifically, referring mainly to FIG. 3 and FIG. 4B, a bias voltage is applied between the source pad 2 and the drain electrode (not shown) so that the drain electrode side is positive. As a result, a reverse voltage is applied to the pn junction at the interface between the n-type semiconductor substrate 6 and the p-type body region 12, and as a result, the n + A state is created between the p-type source region 14 and the semiconductor substrate 6, i.e., between the source and drain. In this state, when a predetermined voltage is applied between the source pad 2 and the gate pad 3 so that the gate pad 3 side is positive, a bias is applied to the gate electrode 17 with respect to the p-type body region 12. As a result, electrons are induced in the periphery of the p-type body region 12, forming an inversion channel. Through this inversion channel, n + Electrical conduction occurs between the type source region 14 and the semiconductor substrate 6. Thus, electrical conduction occurs between the source and the drain, and a drain current Id flows.

[0090] 5A and 5B, a constant current is applied to the temperature sensing diode 20 by the gate driver G / D. Also, the short-circuit protection circuit 5 of the gate driver G / D is configured to apply a forward voltage V F In normal operation, the IV characteristics of the temperature sensing diode 20 are, for example, as shown by the solid line in FIG.

[0091] 4A and 4B, when a short circuit occurs in the switching element SW (MISFET) and an overcurrent flows, a temperature rise occurs on the front side of the semiconductor substrate 6. This temperature rise is also transmitted to the temperature sensing region 9 (see FIG. 5B) formed on the semiconductor substrate 6 in common with the cell region 7, and in the temperature sensing region 9, the forward voltage V F For example, as shown by the dashed curve in FIG. 8, the rise voltage of the temperature sensing diode 20 shifts to the low voltage side. The short circuit protection circuit 5 reduces this forward voltage V F The system detects the drop in potential as the occurrence of a short circuit in the switching element SW and turns off the voltage applied to the gate pad 3. This blocks the drain current Id flowing between the source and drain (SD) of the switching element SW, thereby protecting the switching element SW.

[0092] In this way, when an overcurrent flows through the switching element SW due to a short circuit or the like, the temperature rise of the semiconductor substrate 6 caused by the overcurrent is detected by the forward voltage V FBased on the detection result, it is possible to determine whether an overcurrent is flowing through the switching element SW. Moreover, since the object of monitoring is not the sense current flowing through the switching element SW, even if noise is superimposed on the sense current, the sense current will not be erroneously detected as an overcurrent due to the superimposed current. Therefore, it is possible to reduce malfunctions due to current noise. Moreover, unlike conventional overcurrent protection methods, a certain waiting time (mask time) is not required, or if it is required, it is only required for a short time, so that it is very effective for low on-resistance devices (SiC, GaN, etc.) in which the time it takes for the device to be destroyed by an overcurrent is relatively short.

[0093] In this embodiment, as shown in FIG. 5B, the temperature sense diode 20 is made of the polysilicon layer 21 in the same layer as the gate electrode 17, so that an increase in the number of steps involved in forming the temperature sense diode 20 can be suppressed. Furthermore, the temperature sense diode 20 can be disposed on the semiconductor substrate 6 via the gate insulating film 16, which is thinner than a relatively thick film such as the interlayer insulating film 18. Therefore, the position of the temperature sense diode 20 can be brought close to the current path on the front surface side of the semiconductor substrate 6. This improves the accuracy of detecting temperature changes in the semiconductor substrate 6.

[0094] Fig. 9A is a schematic plan view showing the structure of the temperature sensing region 9 of the semiconductor device 1 of Fig. 3. Fig. 9B is a cross-sectional view (cross-sectional view along line BB) of Fig. 9A. Figs. 9A and 9B show another example of the structure of the temperature sensing region 9. In Figs. 9A and 9B, the same components as those shown in Figs. 5A and 5B described above are given the same reference symbols, and descriptions thereof will be omitted.

[0095] 5A and 5B, the temperature sensing diode 20 is made of the polysilicon layer 21 on the semiconductor substrate 6, but the temperature sensing diode 42 (pn diode) in FIGS. 9A and 9B is made of an impurity region selectively formed on the surface of the semiconductor substrate 6. Specifically, the temperature sensing diode 42 is made of a p-type region 43 and an n-type +The p-type region 43 includes an n-type region 44. + If the n-type region 44 surrounds the p-type region 43, + Since the p-type regions 43 and n-type regions 44 do not overlap each other in a plan view, no separate wiring is required. + Contact can be easily made to either of the mold areas 44 .

[0096] The p-type region 43 is a part of the p-type region 19. + The n-type region 44 is formed in a floating state on the surface of the p-type region 19. + The n-type region 44 + The n-type source region 14 (see FIG. 4B) may be formed in the same process. + The n-type region 44 + 1×10 18 cm -3 ~5×10 21 cm -3 The n-type impurity concentration may be the same as that of the n-type impurity concentration of the first insulating layer 14, and the n-type impurity concentration of the second insulating layer 14 ... first insulating layer 14, and the n-type impurity concentration of the second insulating layer 14 may be the same as that of the first insulating

[0097] The temperature sensing diode 42 further includes p + The p-type contact region 45 and the p-type peripheral region 46 may be included. + The p-type contact region 45 is formed in the inner region of the p-type region 43 at a distance from the periphery of the p-type region 43, and the p-type peripheral region 46 is + The p-type peripheral region 46 may be formed to surround the p-type region 44. + The p-type region 44 is electrically connected to the p-type region 43 via the p-type region 19 below the p-type region 44. + The p-type contact region 45 is formed in a floating state on the surface of the p-type region 19. + The contact region 45 is a p + The p-type body contact region 15 (see FIG. 4B) may be formed in the same process. + The contact region 45 is a p + The same as the body contact region 15, 1×1018 cm -3 ~5×10 21 cm -3 The p-type impurity concentration may be the same as that of the p-type impurity concentration of the p-type impurity layer 11 and the p-type impurity layer 11 may be formed to the same depth.

[0098] The first electrode 10 is connected to the p + The second electrode 11 is connected to the n-type contact region 45 as a cathode electrode through a contact hole 28 in the interlayer insulating film 18. + It is connected to the mold area 44 .

[0099] As described above, the above-mentioned temperature sensing diode 42 can also fulfill the same function as the previously described temperature sensing diode 20. Furthermore, since the temperature sensing diode 42 is formed in the semiconductor substrate 6 itself, the pn junction can be brought closer to the current path on the front side, which is the heat generating portion of the semiconductor substrate 6, than in the case of the temperature sensing diode 20. This makes it possible to detect temperature changes in the semiconductor substrate 6 with high accuracy. Furthermore, a pn diode made of an impurity region operates well even in high temperature regions (for example, 200° C. or higher), and is therefore particularly effective for power devices such as SiC and GaN.

[0100] Next, variations in connection configurations when a plurality of temperature sensing diodes 20, 42 are provided will be described. Figures 10 to 14 are diagrams showing examples of connection configurations of the temperature sensing diodes 20, 42. Note that in Figures 10 to 14, reference symbols are given only to elements necessary for the description among the components shown in Figures 5A and 9A described above.

[0101] First, as shown in Fig. 10, the plurality of temperature sensing diodes 20, 42 may include a series-connected unit 47 configured by connecting a first electrode 10 (anode) on one side and a second electrode 11 (cathode) on the other side in series. The series-connected unit 47 may be configured of two temperature sensing diodes 20, 42 as shown in Fig. 10, or may be configured of three or more temperature sensing diodes 20, 42, although not shown.

[0102] According to the configuration of FIG. 10, the forward voltage V F Since the temperature change amount (shift amount) of increases in proportion to the number of connected temperature sense diodes 20, 42, the detection sensitivity of the temperature change can be improved. For example, the forward voltage V F When the amplitude of the temperature sensing diodes 20 and 42 is XmV / °C, five temperature sensing diodes 20 and 42 are connected in series to form a series-connected unit 47, so that the total amplitude of the series-connected unit 47 can be made 5XmV / °C.

[0103] 11, at least a pair of series-connected units 47 may be connected in parallel in the opposite directions to each other. That is, the terminal first electrode 10 of one series-connected unit 47 may be connected to the terminal second electrode 11 of the other series-connected unit 47 to form a terminal 48, and the terminal second electrode 11 of one series-connected unit 47 may be connected to the terminal first electrode 10 of the other series-connected unit 47 to form a terminal 49.

[0104] 11, there is no distinction between the anode and cathode polarities of the terminals 48, 49 of the assembly of temperature sense diodes 20, 42 which are made up of a plurality of series-connected units 47, so that it is possible to improve the degree of freedom of wiring such as bonding wires when assembling a semiconductor module 4 (see FIG. 2) etc. In other words, even if a reverse bias is applied to one series-connected unit 47, a forward bias is applied to the other series-connected unit 47 at that time, so that at least one of them can function as a temperature sense diode.

[0105] Next, as shown in Fig. 12, the plurality of temperature sensing diodes 20, 42 may include an anti-series connection unit 50 configured by connecting one and the other first electrodes 10 (anodes) in series with each other, or one and the other second electrodes 11 (cathodes) in series with each other. The anti-series connection unit 50 may be configured with two temperature sensing diodes 20, 42 as shown in Fig. 12, or may be configured with three or more temperature sensing diodes 20, 42, although not shown. Furthermore, a plurality of the anti-series connection units 50 may be connected in anti-series with each other as shown in Fig. 13.

[0106] 12 and 13, a reverse bias is applied to at least one of the temperature sensing diodes 20, 42 constituting the anti-series connection unit 50, increasing the total resistance of the anti-series connection unit 50. This makes it possible to reduce the current required for monitoring the temperature change of the temperature sensing diodes 20, 42, thereby achieving power saving.

[0107] 14, the temperature sensing diodes 20, 42 may include a configuration in which at least one pair is connected in parallel in the opposite directions. That is, the first electrode 10 of one temperature sensing diode 20, 42 may be connected to the second electrode 11 of the other temperature sensing diode 20, 42 to form a terminal 51, and the second electrode 11 of one temperature sensing diode 20, 42 may be connected to the first electrode 10 of the other temperature sensing diode 20, 42 to form a terminal 52.

[0108] 14, similarly to the configuration of Fig. 11, there is no distinction between the anode and cathode polarities of the terminals 51, 52 of the assembly of the temperature sense diodes 20, 42, so that the degree of freedom of wiring such as bonding wires can be improved when assembling the semiconductor module 4 (see Fig. 2) etc. In other words, even if a reverse bias is applied to one of the temperature sense diodes 20, 42, a forward bias is applied to the other temperature sense diode 20, 42 at that time, so that at least one of them can function as a temperature sense diode.

[0109] As described above, the connection form of the plurality of temperature sensing diodes 20, 42 is not limited to the configurations in Figures 10 to 14, and any suitable form can be adopted. Furthermore, the concept of the connection forms shown above (series, series+anti-parallel, anti-series, multiple anti-series, anti-parallel, etc.) can also be applied to the temperature sensing diode 66 in Figures 16A to 16C described later.

[0110] Fig. 15A is a schematic plan view showing the structure (trench gate structure) of the cell region 7 of the semiconductor device 1 of Fig. 3. Fig. 15B is a cross-sectional view (cross-sectional view taken along line BB) of Fig. 15A. Figs. 15A and 15B show another example of the structure of the cell region 7. In Figs. 15A and 15B, the same components as those shown in Figs. 4A and 4B described above are given the same reference symbols, and descriptions thereof will be omitted.

[0111] 15A and 15B, a gate trench 53 is formed in the semiconductor substrate 6 in the cell region 7. The gate trench 53 partitions each unit cell 54 of the switching element SW. The gate trench 53 may be formed in a lattice shape in a plan view as shown in FIG. 15A, or may be formed in a stripe shape or a honeycomb shape.

[0112] A p-type body region 55 is formed on the surface of each unit cell 54, and a n-type body region 55 is formed on the surface of the p-type body region 55. + The p-type source region 56 is formed in the p-type body region 55. The p-type impurity concentration of the p-type body region 55 is, for example, 1×10 15 cm -3 ~1×10 20 cm -3 Also, n + The n-type impurity concentration of the n-type source region 56 is higher than the impurity concentration of the n-type semiconductor substrate 6, and is, for example, 1×10 18 cm -3 ~5×10 21 cm -3 It may be.

[0113] n + The inner region of the source region 56 is +A body contact region 57 is formed. + The body contact region 57 is an n + The p-type source region 56 is formed in a depth direction. + The p-type impurity concentration of the p-type body contact region 57 is higher than that of the p-type body region 55, and is, for example, 1×10 18 cm -3 ~5×10 21 cm -3 It may be.

[0114] A gate insulating film 58 is formed on the inner surface of the gate trench 53 and the surface of the semiconductor substrate 6. The gate insulating film 58 may be made of, for example, silicon oxide (SiO2). The thickness of the gate insulating film 58 may be, for example, 300 Å to 600 Å.

[0115] A gate electrode 59 is buried in the gate trench 53. The gate electrode 59 faces the p-type body region 55 on the side surface of the gate trench 53 with a gate insulating film 58 interposed therebetween. The gate electrode 59 is made of, for example, n-type polysilicon (n-type doped polysilicon) but may be made of p-type polysilicon.

[0116] Next, the structure of the temperature sensing region 9 when the cell region 7 is as shown in FIGS. 15A and 15B will be described. FIG. 16A is a schematic plan view showing the structure of the temperature sensing region 9 of the semiconductor device 1 of FIG. 3. FIG. 16B is a cross-sectional view (cross-sectional view taken along line BB) of FIG. 16A. FIG. 16C is a cross-sectional view (cross-sectional view taken along line CC) of FIG. 16A. In FIGS. 16A to 16C, the same components as those shown in the above-mentioned FIGS. 5A and 5B are given the same reference symbols and will not be described.

[0117] 16A to 16C, the temperature sensing region 9 is defined by and surrounded by the gate trench 53. The temperature sensing region 9 may have, for example, a rectangular shape in plan view surrounded on all four sides by the gate trench 53, as shown in FIG.

[0118] In the temperature sensing region 9, the surface of the semiconductor substrate 6 is + A type region 60 is formed, + A p-type region 61 is formed below the n-type region 60. + It is in contact with the mold region 60. + The n-type region 60 has an n-type impurity concentration and a depth of n + 16B and 16C, the p-type region 61 may have a depth equal to that of the p-type source region 56. The p-type region 61 may have a p-type impurity concentration and a depth equal to that of the p-type body region 55, but may have a depth deeper than that of the p-type body region 55 and may have a protruding portion 62 that selectively protrudes downward.

[0119] A temperature sense trench 63, which is an example of the second trench of the present invention, is formed in an inner region of the temperature sense region 9. In other words, the temperature sense trench 63 is independent of the gate trench 53 that surrounds the temperature sense region 9. The temperature sense trench 63 may be formed to have the same width as the gate trench 53, for example.

[0120] The temperature sensing trench 63 may be formed so as to penetrate the p-type region 61, or, as shown in Figures 16B and 16C, it may be formed on the protrusion 62 so as not to penetrate the p-type region 61, and so that its bottom is located inside the p-type region 61 (protrusion 62).

[0121] The temperature sensing trench 63 is formed in a ring shape in a plan view, and a closed region 64 is defined inside the temperature sensing trench 63. + A contact region 65 is formed. + The mold contact region 65 may be formed over the entire surface of the closed region 64 as shown in FIG. 16A, or may be selectively formed only in a portion of the closed region 64, although this is not shown. + The p-type contact region 65 has a p-type impurity concentration and a depth of p + It may be the same as the mold body contact region 57 .

[0122] On the inner surface of the temperature sensing trench 63, the gate insulating film 58 of the cell region 7 is formed so as to extend to the temperature sensing region 9. Then, inside the gate insulating film 58, a temperature sensing diode 66 (pn diode) as an example of the temperature sensing element TS is formed.

[0123] The temperature sensing diode 66 is made of a buried polysilicon layer 67 buried in the temperature sensing trench 63. The temperature sensing diode 66 made of the buried polysilicon layer 67 may be formed in the same process as the gate electrode 59, or may be formed in a process separate from the gate electrode 59.

[0124] The temperature sensing diode 66 includes a p-type region 68 and a n-type + That is, the p-type region 68 is embedded to the bottom in a certain region of the annular temperature sensing trench 63, and an n-type region 69 is disposed adjacent to the p-type region 68. + The p-type region 69 may be embedded in other regions of the temperature sensing trench 63 to the bottom. + If the p-type region 68 and the n-type region 69 are adjacent to each other in the lateral direction, + Since the p-type regions 68 and n-type regions 69 do not overlap in a plan view, no separate wiring is required. + Contact can easily be made to either of the mold areas 69 .

[0125] The p-type impurity concentration of the p-type region 68 is, for example, 1×10 15 cm -3 ~1×10 20 cm -3 (same as p-type body region 55) + The n-type impurity concentration of the n-type region 69 is, for example, 1×10 18 cm -3 ~5×10 21 cm -3 (n + The source region 56 may be the same as the source region 56.

[0126] The temperature sensing diode 66 further includes a+ The semiconductor device may include a contact region 70. + The n-type contact region 70 is formed in contact with the p-type region 68. + The p-type region 68 is separated from the p-type region 69. + The p-type contact region 70 may be embedded to the bottom of the temperature sensing trench 63 and laterally adjacent to the p-type region 68 as shown in FIG. 16C, or may be disposed between the p-type region 68 and the n-type contact region 70 (not shown). + The p-type region 69 may be selectively formed on the surface of the p-type region 68 at a position away from the boundary with the p-type region 69. + The p-type impurity concentration of the contact region 70 is, for example, 1×10 18 cm -3 ~5×10 21 cm -3 (p + The contact region 57 may be the same as the body contact region 57.

[0127] The first electrode 10 in FIG. 3 is an anode electrode. + 3 is connected to the n-type contact region 70 as a cathode electrode. + It is connected to the mold region 69 .

[0128] As described above, the above temperature sensing diode 66 can also fulfill the same function as the previously described temperature sensing diode 20. Furthermore, since the temperature sensing diode 66 (pn diode) is embedded in the surface portion of the semiconductor substrate 6, the pn junction can be brought closer to the current path on the surface side, which is the heat generating portion of the semiconductor substrate 6, than in the case of the temperature sensing diode 20. This makes it possible to detect temperature changes in the semiconductor substrate 6 with high accuracy.

[0129] Although one embodiment of the present invention has been described above, the present invention can be embodied in other forms.

[0130] For example, a configuration may be adopted in which the conductivity type of each semiconductor portion of the semiconductor device 1 is inverted. That is, in the semiconductor device 1, a p-type portion may be n-type, and an n-type portion may be p-type.

[0131] As the temperature sensing element TS, in addition to the above-mentioned temperature sensing diodes 20, 42 (pn diodes), a Schottky barrier diode or the like can also be used.

[0132] In addition, various design modifications can be made within the scope of the claims. [Explanation of symbols]

[0133] 1 Semiconductor device 2. Source Pad 3 Gate Pad 4. Semiconductor Module 5 Short circuit protection circuit 6. Semiconductor Substrates 7 Cell Area 9 Temperature Sensing Area 10 1st electrode 11 Second electrode 12 p-type body region 13 Unit Cell 14 n + Type Source Area 16 Gate insulating film 17 Gate electrode 20 Temperature sensing diode 21 Polysilicon layer 22 p-type region 23n + type area 24 pages + Mold Contact Area 25 p-type outer region 26 p-type base layer 42 Temperature sensing diode 43 p-type region 44n + type area 45 p + Mold Contact Area 46 p-type outer region 47 Series Connection Units 48 terminals 49 Terminals 50 inverse series units 51 Terminal 52 Terminals 53 Gate Trench 54 Unit Cell 55 p-type body region 56 n + Type Source Area 58 Gate insulating film 59 Gate electrode 63 Temperature Sensing Trench 66 Temperature sensing diode 67 Buried Polysilicon Layer 68 p-type region 69 n + type area 70 p + Mold Contact Area SW Switching element TS Temperature sensing element G / D Gate driver

Claims

1. a semiconductor chip having a rectangular shape in a plan view and made of a semiconductor substrate having a front surface and a back surface opposite to the front surface; a switching element formed on the semiconductor substrate, the switching element performing a switching operation between a first electrode provided on the front surface side and a second electrode provided on the back surface side of the semiconductor substrate in response to a signal input to a control electrode formed on the front surface side of the semiconductor substrate; a gate finger extending from the control electrode along an outer periphery of the semiconductor chip and extending across a central portion of the semiconductor chip; a temperature sensing element provided on the front surface side and capable of outputting a signal dependent on temperature; a third electrode and a fourth electrode electrically connected to the temperature sensing element; the control electrode, the third electrode, and the fourth electrode have the same size and shape as each other, the control electrode is disposed at a center portion of one side of the semiconductor chip, and the third electrode and the fourth electrode are disposed side by side on one side of the control electrode along the side on which the control electrode is disposed, The temperature sensing element is disposed adjacent to the gate finger.

2. The semiconductor device as described in claim 1, including a diode element capable of outputting a temperature-dependent signal as the temperature sensing element.

3. 3. The semiconductor device according to claim 2, wherein an anode and a cathode of said diode element are connected to said third electrode and said fourth electrode, respectively.

4. the switching element is a MISFET in which the first electrode is a source electrode, the second electrode is a drain electrode, and the control electrode is a gate electrode; the source electrode has two regions separated by the gate finger that crosses a central portion of the semiconductor chip; 2 . The semiconductor device according to claim 1 , wherein said third electrode and said fourth electrode are disposed adjacent to a periphery of one of said two separated regions of said source electrode.

5. 4. The semiconductor device according to claim 1, wherein the switching element is a MISFET in which the first electrode is a source electrode, the second electrode is a drain electrode, and the control electrode is a gate electrode.

6. 6. The semiconductor device according to claim 1, wherein the third electrode and the fourth electrode are connected to terminals that are electrically independent from terminals to which the first electrode and the second electrode of the switching element are respectively connected.

7. 3. The semiconductor device according to claim 1, wherein said temperature sensing element includes at least a series-connected unit in which a pair of pn diodes are connected in series or in reverse series.

8. 3. The semiconductor device according to claim 1, wherein said temperature sensing element comprises at least a pair of pn diodes connected in anti-parallel.

9. 3. The semiconductor device according to claim 1, wherein said temperature sensing element is configured such that at least a pair of pn diodes connected in series are connected in parallel in opposite directions to each other.

10. The semiconductor device according to claim 1 , wherein the semiconductor substrate includes a SiC semiconductor layer.

11. The semiconductor device according to claim 10 , wherein the temperature sensing element is formed in a polysilicon layer on the SiC semiconductor layer.

12. 12. The semiconductor device according to claim 11, wherein the polysilicon layer forming the temperature sensing element has the same thickness as a gate electrode of the switching element.

13. 13. The semiconductor device according to claim 11, wherein said polysilicon layer forming said temperature sensing element includes a first conductivity type impurity region and a second conductivity type impurity region selectively introduced therein.

14. 13. The semiconductor device according to claim 11, wherein the polysilicon layer forming the temperature sensing element includes a base layer of a second conductivity type and an impurity region of a first conductivity type selectively introduced into a surface of the base layer.

15. The semiconductor device according to any one of claims 1 to 14, wherein the switching element includes a trench-gate type MISFET having a gate trench formed in the semiconductor chip and partitioning a unit cell, a gate electrode embedded in the gate trench, a body region of a first conductivity type formed in a surface portion of the unit cell, a source region of a second conductivity type formed in a surface portion of the body region, and a drain region of the second conductivity type formed on an opposite side of the source region with respect to the body region.

16. 16. The semiconductor device according to claim 1, wherein the temperature sensing element is disposed in a temperature sensing region between the third electrode and the fourth electrode.

17. 11. The semiconductor device according to claim 1, wherein the temperature sensing element comprises a first conductivity type region formed in the semiconductor substrate, and a second conductivity type region surrounding the first conductivity type region.

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