Display device

Abstract

To improve the reliability of a semiconductor device.SOLUTION: A semiconductor device has a drive circuit part and a display part (also referred to as a pixel part) on the same substrate. The drive circuit part and the display part have a thin-film transistor whose semiconductor layer is configured by an oxide semiconductor, and have first wiring and second wiring. The thin-film transistor has a source electrode layer or a drain electrode layer. The thin-film transistor of the drive circuit part is configured by sandwiching the semiconductor layer between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected with each other via an oxide conductive layer at an opening provided on a gate insulating film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to all electro-optical devices such as liquid crystal displays, semiconductor circuits, and electronic equipment. It is located. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used The technology of constructing thin film transistors (TFTs) using these elements is attracting attention. Electronic devices such as integrated circuits (ICs) and electro-optical devices It is widely used in child devices, and development is particularly urgent as a switching element for image display devices. There are many types of metal oxides and they are used for various purposes. Indium oxide is one of the most It is a well-known material and is used as a transparent electrode material required for liquid crystal displays, etc. It is being done.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin-film transistors that use metal oxides as channel formation regions and that exhibit excellent semiconductor properties are already known. (Patent Document 1 and Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] Thin film transistors using oxide semiconductor films have high operating speeds and are relatively easy to manufacture. Therefore, sufficient reliability is required.

[0007] To improve the operating characteristics and reliability of a thin film transistor using an oxide semiconductor film is one of the challenges.

[0008] In particular, it is preferable that the operating speed of thin film transistors used in the driver circuits is fast.

[0009] For example, the channel length (L) of a thin-film transistor can be shortened or the channel width (W) can be widened. However, shortening the channel length (L) reduces the switching In addition, the channel width (W) is increased, which reduces the switching characteristics, for example the on-off ratio. This increases the capacitance load of the thin film transistor itself.

[0010] In addition, a semiconductor device having a thin film transistor with stable electrical characteristics even if the channel length is short is also provided. It is also an object of the present invention to provide a body device.

[0011] In addition, when forming a plurality of different circuits on an insulating surface, for example, a pixel portion and a driver circuit may be formed on the same substrate. When formed on a substrate, the thin film transistor used in the pixel portion must have excellent switching characteristics. For example, a large on-off ratio is required, and the thin film transistors used in the drive circuits Fast operation speed is required. In particular, the higher the resolution of the display device, Since the time it takes to write a display image is shortened, the thin-film transistors used in the driver circuits operate faster. It is preferable to use speed.

[0012] In addition, it is also possible to reduce variations in electrical characteristics of thin film transistors using an oxide semiconductor film. This is one of the challenges. [Means for solving the problem]

[0013] One embodiment of the present invention includes a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driving circuit section and the display section are formed by a thin film transistor and a first wiring (also called a terminal or a connection electrode). The thin film transistor has a metal A gate electrode formed by the above-mentioned, a gate insulating film on the gate electrode, and the gate insulating film A source electrode ( a source electrode layer and a drain electrode (also referred to as a drain electrode layer), and an oxide semiconductor A protective insulating layer is provided on the source electrode and the drain electrode. The thin-film transistor of the display unit has a conductive layer at a position overlapping the oxide semiconductor layer on the protective insulating layer. The transistor is electrically connected to a pixel electrode (also called a pixel electrode layer), and the first wiring is a gate electrode. The first wiring is formed of the same material as the source electrode or the drain electrode. The first wiring and the second wiring of the driving circuit section are provided in the gate insulating film and the protective insulating layer. The semiconductor device is electrically connected through the opening (contact hole).

[0014] One embodiment of the present invention includes a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driving circuit section and the display section each have a thin film transistor, a first wiring, and a second wiring. A transistor has a gate electrode made of metal and a gate insulator on the gate electrode. a gate insulating film, an oxide semiconductor layer on the gate insulating film, and a metal on the oxide semiconductor layer. and a source electrode and a drain electrode formed on the oxide semiconductor layer. The thin film transistor of the driving circuit section is formed of an oxide semiconductor on the protective insulating layer. The thin film transistor in the display section is electrically connected to the pixel electrode. The first wiring is made of the same material as the gate electrode, and the second wiring is made of the source electrode or drain electrode. The first and second wirings of the driving circuit are formed of the same material as the gate electrode. The semiconductor device is electrically connected through an opening formed in an insulating film.

[0015] As a thin-film transistor for pixels and a thin-film transistor for driving circuits, Staggered thin-film transistors are used. Thin-film transistors for pixels and thin-film transistors for driver circuits The transistor is an oxide semiconductor layer exposed between the source electrode layer and the drain electrode layer. The transistor is a channel-etch type thin film transistor provided with an insulating film.

[0016] The thin film transistor for the driver circuit has a structure in which an oxide semiconductor layer is sandwiched between a gate electrode and a conductive layer. This reduces the variation in the threshold voltage of the thin film transistor, resulting in a stable It is possible to provide a semiconductor device including a thin film transistor having the desired electrical characteristics. The potential of the gate electrode layer may be the same as that of the gate electrode layer, may be a floating potential, or may be a fixed potential. The potential may be, for example, GND potential or 0V. In addition, by applying an arbitrary potential to the conductive layer, The threshold voltage of the transistor can be controlled.

[0017] One aspect of the present invention for realizing the above structure is a first substrate on which a driving circuit section is formed on the same substrate. A gate is formed in the first region and a second region in which a display portion is to be formed by a first photolithography process. A first electrode that functions as a contact electrode and a first wiring made of the same material as the first electrode are formed. A first insulating film that functions as a gate insulating film is formed on the first electrode and the first wiring. An oxide semiconductor layer is formed on the insulating film of the first insulating film by a second photolithography process. A heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer, and a third The second electrode functioning as a source electrode and the drain electrode are formed by the photolithography process. The third electrode functions as a second electrode and the source electrode or drain electrode is made of the same material. A line is formed, and a protective insulating layer is formed on the second electrode, the third electrode, and the oxide semiconductor layer. A second insulating film is formed, and a first insulating film overlapping the first wiring is formed by a fourth photolithography process. The insulating film and the second insulating film are selectively removed to form a first opening, and a second wiring is formed. The second insulating film is selectively removed to form a second opening, and a second electrode is formed in the second region. Alternatively, the second insulating film is selectively removed at a position overlapping with either one of the third electrodes. The third opening is formed by the fifth photolithography step, and the first and second openings are formed by the fifth photolithography step. A first conductive layer is formed to electrically connect the first wiring and the second wiring through the opening, and the first region is In the region, the same layer as the first conductive layer is provided at a position overlapping with the oxide semiconductor layer via the second insulating film. A fourth electrode made of a material is formed, and the thin-film transistor is formed through the third opening in the second region. A fifth conductive layer is made of the same material as the first conductive layer and electrically connects to the pixel electrode. The method for manufacturing a semiconductor device is characterized by forming an electrode.

[0018] The first opening, the second opening, and the third opening are simultaneously formed in the same photolithography process. The first conductive layer and the fourth electrode are simultaneously formed in the same photolithography process. The above configuration can be realized without increasing the number of photolithography steps.

[0019] A semiconductor in which the drive circuitry and display section are formed on the same substrate through five photolithography processes An apparatus can be provided.

[0020] One aspect of the present invention for realizing the above structure is a first substrate on which a driving circuit section is formed on the same substrate. A gate is formed in the first region and a second region in which a display portion is to be formed by a first photolithography process. A first electrode that functions as a contact electrode and a first wiring made of the same material as the first electrode are formed. A first insulating film that functions as a gate insulating film is formed on the first electrode and the first wiring. An oxide semiconductor layer is formed on the insulating film of the first insulating film by a second photolithography process. A heat treatment is performed to dehydrate or dehydrogenate the semiconductor layer, and a third photolithography is performed. The first insulating film on the first wiring is selectively removed to form a fourth opening, and an oxide A second electrode functioning as a source electrode is formed on the semiconductor layer by a fourth photolithography process. a second electrode acting as a drain electrode, and a third electrode acting as a drain electrode, and a second electrode acting as a drain electrode. A second wiring made of a material is formed, and a protective film is formed on the second electrode, the third electrode, and the oxide semiconductor layer. A second insulating film that functions as an insulating layer is formed, and a fifth photolithography process is performed to form a first insulating film. In the second region, a second electrode is disposed at a position overlapping with either the second electrode or the third electrode. The insulating film is selectively removed to form a third opening, and a sixth photolithography process is performed. In the first region, a fourth insulating film is formed at a position overlapping with the oxide semiconductor layer via the second insulating film. forming an electrode and electrically connecting the electrode to the thin film transistor through the third opening in the second region; forming a fifth electrode that is made of the same material as the fourth electrode and functions as a pixel electrode; The present invention relates to a method for manufacturing a semiconductor device.

[0021] The formation of the fourth opening by the third photolithography step can be performed after the formation of the first insulating film. The second photolithography step may be performed before the oxide semiconductor layer is formed by the second photolithography step.

[0022] In comparison with the above-described embodiment, after the oxide semiconductor layer is formed, a frame for providing an opening on the first wiring is provided. Since a photolithography process is added, a total of six photolithography processes are required to produce the same substrate. The driving circuit and display unit will be formed on the board, and the first wiring and the second wiring will be connected. Since the step of the opening for the first insulating film can be made only by the thickness of the first insulating film, the first insulating film can be formed with good coverage. The first wiring and the second wiring can be reliably connected, thereby improving the reliability of the semiconductor device. can be done.

[0023] In the above-mentioned photolithography process, the transmitted light has a plurality of intensities. The etching step may be performed using a mask layer formed by a multi-tone mask. stomach.

[0024] The mask layer formed using the multi-tone mask has a shape with multiple film thicknesses. The shape can be further modified by etching the metal into different patterns. It can be used for multiple etching processes. Thus, a mask layer corresponding to at least two different patterns can be formed. This reduces the number of exposure masks and the corresponding photolithography steps. This allows the process to be simplified.

[0025] The above configuration solves at least one of the above problems.

[0026] The oxide semiconductor used in this specification is InMO3(ZnO). m (m>0) A thin film is formed on the oxide semiconductor layer, and a thin film transistor is fabricated using the thin film as an oxide semiconductor layer. In addition, M is one or more metal elements selected from Ga, Fe, Ni, Mn, and Co. Indicates a metal element. For example, M can be Ga, Ga and Ni, or Ga and Ni. In some cases, the oxide semiconductor may contain the above-mentioned metal elements other than Ga, such as Fe. In addition to the metal elements contained as M, Fe, Ni and other transition metals are included as impurity elements. In the present specification, the term "In" refers to a transition metal oxide. MO3(ZnO) m In the oxide semiconductor layer with a structure represented by (m>0), M is Ga The oxide semiconductor with the structure containing In-Ga-Zn-O is called the In-Ga-Zn-O oxide semiconductor, and the thin film of the In-Ga-Zn-O oxide semiconductor is called the In-Ga-Zn-O oxide semiconductor. It is also called n-Ga-Zn-O type non-single crystal film.

[0027] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-Zn-O In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- Metal oxides of O, Sn-O, and Zn-O can be used. The oxide semiconductor layer made of such a material may contain silicon oxide.

[0028] Heat treatment is performed under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient and has low resistance, that is, becomes N-type ( N - Then, an oxide insulating film is formed in contact with the oxide semiconductor layer, and a heat treatment is performed after the formation. By performing heat treatment, the oxide semiconductor layer is made into an oxygen-excess state, and the resistance is increased, i.e., I In addition, solid-phase oxidation is performed to place the oxide semiconductor layer in an oxygen-excess state. This allows us to obtain thin film transistors with good electrical characteristics and high reliability. It is therefore possible to manufacture and provide a semiconductor device having the above-mentioned characteristics.

[0029] Dehydration or dehydrogenation is performed using inert gases such as nitrogen or noble gases (argon, helium, etc.). Heating in an atmosphere at 400°C or higher but lower than the strain point of the substrate, preferably 420°C or higher and 570°C or lower Heat treatment is performed to reduce impurities such as moisture contained in the oxide semiconductor layer. This prevents re-impregnation of the sintered body with water (H2O).

[0030] The heat treatment for dehydration or dehydrogenation is preferably carried out in a nitrogen atmosphere with H2O of 20 ppm or less. It is also preferable to carry out the treatment in ultra-dry air with an H2O concentration of 20 ppm or less.

[0031] The oxide semiconductor layer that has been dehydrated or dehydrogenated is Even when TDS was measured up to 450°C for the layer, two peaks of water and at least 300 The heat treatment conditions are set so that a peak that appears around 100 °C is not detected. The TDS test showed that the thin-film transistor using the oxide semiconductor layer that was dehydrogenated or dehydrogenated had a thermal conductivity of 45 Even when measurements are taken down to 0°C, the water peak that appears around 300°C is not detected.

[0032] The oxide semiconductor layer is dehydrated or dehydrogenated at a heating temperature T. When lowering the temperature, the same furnace used for dehydration or dehydrogenation is used, and the material is not exposed to the atmosphere. It is important not to reintroduce water or hydrogen. The semiconductor layer is made low-resistance, i.e., N-type (N - After that, the acid was made high-resistance and turned into type I. When a thin-film transistor is fabricated using a nitride semiconductor layer, the threshold voltage of the thin-film transistor (Vth) can be made positive, realizing what is called a normally-off switching element. The gate voltage of the thin film transistor is as close to 0V as possible to the positive threshold voltage. It is desirable for a semiconductor device (display device) to have a thin film transistor. If the threshold voltage is negative, even if the gate voltage is 0V, In active matrix display devices, the current flows through the active matrix. In this case, the electrical characteristics of the thin film transistors that make up the circuit are important, and The performance of the display device is affected. In particular, the threshold voltage of the thin film transistor is one of its electrical characteristics. It is important that even if the field effect mobility is high, the threshold voltage is high, or If it is negative, it is difficult to control the circuit. In the case of thin-film transistors with low drive voltage, the switching function of the TFT is not achieved. In the case of n-channel thin-film transistors, In this case, a channel is formed and drain current flows only when a positive voltage is applied to the gate. A transistor in which a channel does not form unless the driving voltage is high is desirable. A transistor that forms a channel and flows drain current even under negative voltage conditions is called a transistor. However, it is not suitable for use as a thin film transistor in a circuit.

[0033] In addition, the gas atmosphere used to lower the temperature from T is different from the gas atmosphere used to raise the temperature to T. A gas atmosphere may be switched to, for example, air in the same furnace where dehydration or dehydrogenation was performed. The inside of the furnace is filled with high-purity oxygen gas or N2O gas, ultra-dry air (dew point Cooling is performed by filling the container with water at a temperature of -40°C or less, preferably -60°C or less.

[0034] The moisture content in the film is reduced by a heat treatment for dehydration or dehydrogenation, and then the film is Cool slowly (or cool) in an atmosphere that is not prone to dew (dew point is -40°C or less, preferably -60°C or less). The oxide semiconductor film is used to improve the electrical characteristics of thin film transistors and to facilitate mass production. This will realize thin-film transistors that are both reliable and high performance.

[0035] In this specification, the method is carried out under an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.). This heat treatment is called a heat treatment for dehydration or dehydrogenation. Dehydrogenation does not only mean that hydrogen is released as H2 by the hydrogenation process, but also means that H For convenience, this process is referred to as dehydration or dehydrogenation, which also includes the elimination of OH and other groups.

[0036] Heat treatment is performed under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient and has low resistance, that is, becomes N-type ( N - To make something (e.g., convert it into something new).

[0037] In addition, the drain electrode layer overlaps with the oxygen-deficient high-resistance drain region (HRD). A resistance drain region is also formed. The oxygen-deficient high-resistance source region (HRS) overlaps the layer. e Source region) is formed.

[0038] Specifically, the carrier concentration in the high-resistance drain region is 1×10 18 / cm 3 Within the above range and the carrier concentration in the channel formation region is at least (1×10 18 / cm 3 Less than The carrier concentration in this specification is calculated from Hall effect measurements at room temperature. This refers to the carrier concentration value measured.

[0039] Then, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer is brought into an oxygen-excess state. By this, the resistance is further increased, that is, the I-type is formed, and a channel forming region is formed. The treatment for bringing the hydrated or dehydrogenated oxide semiconductor layer into an oxygen-excess state can be performed by dehydration or or forming an oxide insulating film in contact with a dehydrogenated oxide semiconductor layer by a sputtering method. or heat treatment after the formation of an oxide insulating film, or heat treatment in an atmosphere containing oxygen, or inactivation Heating in an oxygen atmosphere after heating in an oxygen atmosphere, ultra-dry air (dew point -40℃ After that, the mixture is cooled to a temperature of preferably -60°C or lower.

[0040] In addition, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer (which overlaps with the gate electrode layer) is In order to make the channel formation region in the region where the oxygen is present, a high resistance is achieved by selectively creating an oxygen-excess state. The oxide semiconductor layer may be in contact with the dehydrated or dehydrogenated oxide semiconductor layer. The source electrode layer and the drain electrode layer are formed of a metal electrode such as Ti. The exposed area that does not overlap with the drain electrode layer is selectively made into an oxygen-excessive state to form a channel formation area. When the oxygen-excess state is selectively created, the first layer overlapping the source electrode layer can be formed. A first high-resistance source region and a second high-resistance drain region overlapping the drain electrode layer are formed. The region between the first high-resistance source region and the second high-resistance drain region is a channel formation region. That is, the channel formation region is formed in a self-aligned manner between the source electrode layer and the drain electrode layer. is formed.

[0041] This allows the fabrication of a semiconductor device having thin film transistors with good electrical characteristics and high reliability. It will be possible to provide such information.

[0042] Note that a high-resistance drain region is formed in the oxide semiconductor layer overlapping with the drain electrode layer. This makes it possible to improve the reliability of the drive circuit. By forming a resistive drain region, the drain electrode layer, the high-resistance drain region, and the channel It is possible to form a structure in which the conductivity can be changed stepwise over the formation region. Therefore, when the drain electrode layer is connected to a wiring that supplies a high power supply potential VDD, Even if a high electric field is applied between the drain electrode layer and the drain electrode layer, the high resistance drain region acts as a buffer. This prevents a local high electric field from being applied, improving the breakdown voltage of the thin film transistor. It is possible.

[0043] In addition, in the oxide semiconductor layer overlapping with the drain electrode layer and the source electrode layer, By forming a high-resistance source region and a high-resistance in-region, the channel Specifically, the high resistance drain region can be formed by By forming the gate insulating film, the leakage current of the transistor flowing between the drain electrode layer and the source electrode layer is reduced. The drain electrode layer, the high-resistance drain region on the drain electrode layer side, and the channel-shaped The order is the channel region, the high resistance source region on the source electrode layer side, and the source electrode layer. In the drain formation region, current flows from the high-resistance drain region on the drain electrode layer side to the channel formation region. The leakage current is measured between the gate insulating layer and the channel formation region, which have high resistance when the transistor is off. It can be concentrated near the interface, and the back channel (channel away from the gate electrode layer) It is possible to reduce leakage current in the gate insulating film (part of the surface of the panel formation region).

[0044] In addition, a high resistance source region overlapping the source electrode layer and a high resistance drain region overlapping the drain electrode layer are The gate region overlaps a part of the gate electrode layer via the gate insulating layer, depending on the width of the gate electrode layer. As a result, the electric field strength in the vicinity of the end of the drain electrode layer can be more effectively reduced. do.

[0045] In addition, an oxide conductive layer may be formed between the oxide semiconductor layer and the source electrode and the drain electrode. The oxide conductive layer preferably contains zinc oxide as a component, and more preferably contains indium oxide. For example, zinc oxide, zinc aluminum oxide, zinc oxynitride, etc. Lead aluminum, zinc gallium oxide, or the like can be used. Drain region (LRN(Low Resistance N-type conduction ivity region, and LRD (Low Resistance Drain) region. Specifically, the carrier concentration in the low-resistance drain region is The HRD region is larger than the HRD region, e.g., 1×10 20 / cm 3 More than 1×10 21 / c m 3 The oxide conductive layer is preferably in the range of 100 to 2000 nm. By providing it between the transistor electrodes, the contact resistance between the electrodes and the oxide semiconductor layer can be reduced, This allows high-speed operation of the transistors, improving the frequency characteristics of the peripheral circuits (drive circuits). It can be raised.

[0046] The oxide conductive layer and the metal layer for forming the source and drain electrodes can be formed successively. It is.

[0047] The first and second wirings are formed by oxidizing the first and second wirings to function as LRN or LRD. Alternatively, the wiring may be a laminated wiring composed of the same material as the conductive layer and a metal material. By stacking conductive layers, the coverage of steps such as overcoming lower wiring and openings is improved. This reduces the wiring resistance. It is expected that this will have the effect of preventing high resistance and disconnection, making it possible to provide highly reliable semiconductor devices. can.

[0048] In addition, when the first wiring and the second wiring are connected as described above, the oxide conductive layer is sandwiched between them. By connecting the two parts together, an insulating oxide is formed on the metal surface of the connection part (contact part). It is expected that this will prevent the increase in contact resistance due to the contacts being damaged, resulting in highly reliable semiconductor equipment. Locations can be provided.

[0049] In addition, since thin-film transistors are easily damaged by static electricity, etc., For the line, a protection circuit for protecting the thin film transistor in the pixel area can be provided on the same substrate. The protection circuit is preferably formed using a nonlinear element using an oxide semiconductor layer. It is nice.

[0050] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. In addition, the specific names used in this specification are not intended to identify the invention. This does not indicate the Effect of the Invention

[0051] Semiconductor device including thin film transistors using oxide semiconductor layers and having excellent electrical characteristics and reliability This can be achieved. [Brief description of the drawings]

[0052] [Figure 1] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 2] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 3] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 5] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 6] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 8] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 9] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 10] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 11] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 12]FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 13] FIG. 2 illustrates a configuration of a signal line driver circuit. [Figure 14] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 15] 1A and 1B are a diagram illustrating a configuration of a shift register and a timing chart illustrating the operation of the shift register; [Figure 16] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 17] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 18] FIG. 1 is an external view showing an example of an electronic book. [Figure 19] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 20] FIG. 1 is an external view showing an example of a gaming machine. [Figure 21] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 22] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 23] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 24] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 25] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 26] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 27] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 28] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 29] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 30] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 31] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 32] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 33] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 34] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 35] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 36] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 37] 2A to 2C illustrate a manufacturing process of a semiconductor device. [Figure 38] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 39] A diagram explaining the calculation results of the water generation and desorption mechanism. [Diagram 40] FIG. 13 is a diagram for explaining the calculation results of an energy diagram. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0053] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. It is understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should be interpreted as being limited to the following description of the embodiment. In the configuration described below, parts having the same parts or similar functions are not included. The same reference numerals are used in common between different drawings for the corresponding parts, and the repeated explanations will be omitted.

[0054] (Embodiment 1) A manufacturing process of a semiconductor device including a thin film transistor will be described with reference to FIGS. .

[0055] FIG. 1 shows a liquid crystal display device as a semiconductor device according to one embodiment of the present invention. The pixel portion includes a thin film transistor 170 and a capacitor 147, and the thin film transistor 180 A driving circuit section including the pixel electrode layer 110 and an insulating layer 191 functioning as an alignment film are provided. A substrate 100, an insulating layer 193 functioning as an alignment film, a counter electrode layer 194, a color filter A liquid crystal layer 192 is sandwiched between an opposing substrate 190 having a colored layer 195 functioning as a liquid crystal layer. In addition, on the opposite side of the liquid crystal layer 192 of the substrate 100 and the counter substrate 190, Polarizing plates (layers having polarizers, also simply called polarizers) 196a and 196b are provided. The terminal portion of the port wiring is provided with a first terminal 121, a connection electrode 120, and a connection terminal electrode 128. A second terminal 122 and a connection terminal electrode 129 are provided at the terminal portion of the source line. do.

[0056] In the driving circuit section, the thin film transistor 180 is formed by forming a conductive layer above the gate electrode layer and the semiconductor layer. The drain electrode layer 165b is a conductive layer formed in the same process as the gate electrode layer. In the pixel portion, the dopant of the thin film transistor 170 is electrically connected to the dopant of the thin film transistor 170. The drain electrode layer is electrically connected to the pixel electrode layer 110 .

[0057] The manufacturing method will be described in detail below with reference to FIGS. 2 to 5 and 11. FIG. 5 shows a liquid crystal display device. 1 to 4 are plan views of the pixel portion of FIG. 5 along lines A1-A2 and B1-B2. This corresponds to a cross-sectional view of

[0058] After forming a conductive layer on the entire surface of the substrate 100, which is a substrate having an insulating surface, The photolithography process in step 1 is performed to form a resist mask, and unnecessary parts are removed by etching. The wiring and electrodes (gate electrode layer 101, gate electrode layer 161, conductive layer 162, A capacitance wiring 108 (also called a capacitance wiring layer) and a first terminal 121) are formed. ) When etching is performed so that the ends of the wiring and electrodes have a tapered shape, This is preferable because the coverage of the gate electrode layer 101 and the gate electrode layer 102 can be improved. 161 are included in the gate wiring.

[0059] There is no significant limitation on the substrate that can be used for the substrate 100 having an insulating surface. In any case, it is necessary for the insulating surface to have sufficient heat resistance to withstand subsequent heat treatment. The substrate 100 may be a glass substrate.

[0060] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. For the glass substrate, for example, aluminosilicate glass, alumina Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boric acid, it is more practical. Heat-resistant glass can be obtained. For this reason, it is recommended to use a glass substrate containing more BaO than B2O3. is preferred.

[0061] Instead of the above glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of an insulating material may be used. Alternatively, a substrate made of a crystallized glass may be used. Since the liquid crystal display device shown in the embodiment is a transmission type, the substrate 100 is a substrate having a light transmitting property. In the case of a reflective type, a non-transparent metal substrate or the like is used as the substrate 100. This is also fine.

[0062] The insulating film serving as the base film is a substrate 100, a gate electrode layer 101, a gate electrode layer 161, and a conductive layer 1 The base film may be provided between the first terminal 121 and the capacitor wiring 108. It has the function of preventing the diffusion of impurity elements from 00, and is used in silicon nitride films, silicon oxide films, and nitride oxide films. The insulating film is formed by a laminate structure of one or more films selected from a silicon film and a silicon oxynitride film. It is possible.

[0063] The gate electrode layer 101, the gate electrode layer 161, the conductive layer 162, the capacitor wiring 108, and the first The material of the terminal 121 is molybdenum, titanium, chromium, tantalum, tungsten, aluminum, etc. Uses metallic materials such as tungsten, copper, neodymium, scandium, etc., or alloy materials whose main components are these. The insulating film may be formed as a single layer or a laminate.

[0064] For example, the gate electrode layer 101, the gate electrode layer 161, the conductive layer 162, the capacitance wiring 108, and The two-layer laminated structure of the first terminal 121 is a molybdenum layer laminated on an aluminum layer. A two-layer structure with a molybdenum layer on a copper layer, or a two-layer structure with a molybdenum layer on a copper layer, or A two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on the titanium nitride layer and a molybdenum layer is laminated on the It is preferable to use a two-layer structure in which a tungsten layer is laminated. layer or tungsten nitride layer and an alloy layer of aluminum and silicon or aluminum and titanium It is preferable to use a laminate of an alloy layer of titanium and a titanium nitride layer or a titanium layer.

[0065] Next, the gate electrode layer 101, the gate electrode layer 161, the conductive layer 162, the capacitance wiring 108, and A gate insulating layer 102 is formed over the first terminal 121 (see FIG. 2(A)).

[0066] The gate insulating layer 102 is a silicon oxide layer formed by using a plasma CVD method, a sputtering method, or the like. , a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer, For example, the deposition gas is SiH4, oxygen, and nitrogen. A silicon oxynitride layer may be formed by plasma CVD. The thickness is 100 nm to 500 nm. In the case of a multilayer structure, the thickness is, for example, 50 nm to 2 A first gate insulating layer having a thickness of 000 nm or less, and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less on the first gate insulating layer. The second gate insulating layer has a thickness of 1 m or less.

[0067] In this embodiment, the gate insulating layer 102 is formed by a plasma CVD method to a thickness of 200 nm or more. A bottom silicon nitride layer is formed.

[0068] Next, an oxide semiconductor film 13 having a thickness of 2 nm to 200 nm is formed on the gate insulating layer 102. 0 (see Figure 2(B)).

[0069] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced. Reverse sputtering is performed to generate plasma, and the gate insulating layer 102 is adhered to the surface of the gate insulating layer 102. In reverse sputtering, the substrate is sputtered in an argon atmosphere. This is a method of modifying the surface by applying voltage using an RF power source to generate plasma near the substrate. Instead of the argon atmosphere, nitrogen, helium, etc. may be used. The atmosphere may be added with oxygen, NO, etc. Also, the atmosphere may be added with Cl 2. It may be performed in an atmosphere containing CF4 or the like.

[0070] Even if heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film 130, the oxide semiconductor film 130 is not oxidized. In order to make the semiconductor film amorphous, it is preferable to make the film thickness as thin as 50 nm or less. When the oxide semiconductor film is thinned, the oxide semiconductor layer is heated after the oxide semiconductor layer is formed. Crystallization can be suppressed.

[0071] The oxide semiconductor film 130 is an In-Ga-Zn-O based non-single crystal film, an In-Sn-Zn-O based , In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn- Al-Zn-O, In-Zn-O, In-Ga-O, Sn-Zn-O, Al-Z In this embodiment, an oxide semiconductor film based on nO, In-O, Sn-O, or Zn-O is used. In this embodiment, a sputtering method is used to deposit In-Ga-Zn-O oxide semiconductor targets. The oxide semiconductor film 130 is formed in a rare gas (typically, argon) atmosphere. Sputtering in an oxygen atmosphere or in an atmosphere of rare gas (typically argon) and oxygen In addition, when the sputtering method is used, SiO2 is The oxide semiconductor film 130 is formed by using a target containing 2% by weight or more and 10% by weight or less. The SiOx (x>0) that inhibits crystallization is added to the It is preferable to suppress crystallization during the heat treatment for the purpose.

[0072] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO=1:1:1[mol%], In:Ga:Zn=1:1:0.5[at%]) The distance between the substrate and the target was 100 mm, the pressure was 0.2 Pa, and the direct current (DC) was Power supply: 0.5 kW, argon and oxygen (argon:oxygen = 30 sccm:20 sccm, oxygen The film is formed in an atmosphere with a nitrogen flow rate of 40%). Note that if a pulsed direct current (DC) power supply is used, This is preferable because it reduces the damage and makes the film thickness distribution uniform. The thickness of the film is greater than or equal to 5 nm and less than or equal to 200 nm. Then, a film was formed by sputtering using an In-Ga-Zn-O oxide semiconductor target. A 20 nm thick In-Ga-Zn-O based non-single crystal film is deposited.

[0073] The sputtering method uses a high-frequency power source as the sputtering power source. There are two types of sputtering: DC sputtering and pulsed DC sputtering, which applies a bias in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC The sputtering method is mainly used when forming a metal film.

[0074] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The sputtering equipment can perform lamination deposition of different material films in the same chamber, or multiple deposition depositions in the same chamber. It is also possible to form films by discharging multiple types of materials simultaneously using the bar.

[0075] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. E using a plasma generating device using microwaves instead of glow discharge. There is a sputtering device that uses the CR sputtering method.

[0076] In addition, as a method for forming a film using a sputtering method, a target material and a sputtering method are used during film formation. Reactive sputtering is a method in which a compound thin film is formed by chemically reacting the components of the sputtering gas with the There are also sputtering methods in which a voltage is applied to the substrate during deposition, and bias sputtering methods in which a voltage is also applied to the substrate during deposition.

[0077] Next, a resist pattern is formed on the oxide semiconductor film 130 by performing a second photolithography process. A mask 137 is formed, and the oxide semiconductor film 130 and the gate insulating layer 1 are removed by etching. The unnecessary portion of the gate insulating layer 102 is removed to form a contact that reaches the first terminal 121. Then, a contact hole 119 and a contact hole 118 reaching the conductive layer 162 are formed (FIG. 2( See C). ).

[0078] In this manner, in a state where the oxide semiconductor film 130 is laminated on the entire surface of the gate insulating layer 102, When a step of forming a contact hole in the insulating layer 102 is performed, a laser is formed on the surface of the gate insulating layer 102. Since the resist mask does not come into direct contact with the gate insulating layer 102, contamination of the surface of the gate insulating layer 102 (such as adhesion of impurities) is prevented. ) can be prevented. This improves the condition of the device, leading to improved reliability.

[0079] A resist pattern may be formed directly on the gate insulating layer to open the contact holes. In that case, after removing the resist, a heat treatment is performed to dehydrate and decompose the surface of the gate insulating film. It is preferable to carry out hydrogenation and dehydroxylation treatment. For example, the treatment is carried out in an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) and oxygen atmosphere (400℃ or higher) The substrate is then heated to a temperature lower than the distortion point of the substrate, and impurities such as hydrogen and water contained in the gate insulating layer are removed. That's good.

[0080] Next, the resist mask 137 is removed, and the oxide semiconductor film 130 is subjected to a third photolithography. The islands are formed by etching using resist masks 135a and 135b formed by a lithography process. In addition, the oxide semiconductor layers 131 and 132 are formed in an island shape (see FIG. 3A). Resist masks 135a and 135b for forming the semiconductor layer are formed by the inkjet method. If the resist mask is formed by the inkjet method, a photomask is not required. This reduces manufacturing costs.

[0081] Next, the oxide semiconductor layers 131 and 132 are dehydrated or dehydrogenated. Hydrogenated oxide semiconductor layers 133 and 134 are formed (see FIG. 3B). The temperature of the first heat treatment for hydrogenation or dehydrogenation is 400° C. or higher and lower than the distortion point of the substrate, preferably The heat treatment time is 425°C or higher. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. If the temperature is less than 425°C, the heat treatment time is longer than one hour. The substrate is placed in an electric furnace, which is a type of heat treatment device, and the oxide semiconductor layer is heated under a nitrogen atmosphere. After the heat treatment, water and hydrogen are reabsorbed into the oxide semiconductor layer without exposure to the air. In this embodiment, the oxide semiconductor layer is dehydrated or The same furnace is used to heat the mixture from the dehydrogenation temperature T to a temperature that is high enough to prevent water from entering again. Specifically, the temperature is gradually cooled in a nitrogen atmosphere until the temperature drops by 100°C or more below the heating temperature T. Dehydration is not limited to nitrogen atmosphere, but can be performed under rare gas atmosphere such as helium, neon, argon, etc. Or dehydrogenation is carried out.

[0082] The oxide semiconductor layer is heat-treated at a temperature of 400 to 700°C to remove the oxide This allows hydration and dehydrogenation, preventing subsequent re-impregnation with water (H2O).

[0083] The following reaction pathway was analyzed as an example of the mechanism of water desorption from an oxide semiconductor film. (In the oxide semiconductor film, the reaction occurs not only as water but also as OH or H.) An In-Ga-Zn-O amorphous film was used as the conductor film.

[0084] In addition, the optimal molecular structure in the ground state of the computational model was calculated using density functional theory (DFT). The total energy of DFT is calculated by the potential energy, the electrostatic energy between electrons, and the electric field. It is expressed as the sum of the kinetic energy of the electrons and the exchange-correlation energy including all the complex interactions between electrons. In DFT, the exchange-correlation interaction is expressed as a generalized one-electron potential in terms of electron density. Since it is approximated by a function (meaning a function of a function), the calculation is fast and highly accurate. Weights of parameters related to exchange and correlation energies are calculated using the mixed functional B3LYP. In addition, La is used as the basis function for indium, gallium and zinc atoms. nL2DZ(Ne shell effective potential with split valence basis set) basis function), and 6-311 for other atoms (three contraction functions for each valence orbital) The triple split valence basis set used above was applied. For example, the orbitals 1s to 3s of a hydrogen atom are considered, and the basis functions of For elementary atoms, the orbitals 1s to 4s and 2p to 4p are taken into account. To improve accuracy, the p-function and the d-function are added to the polarization basis set for hydrogen atoms and oxygen atoms, respectively. Ta.

[0085] The quantum chemical calculation program used was Gaussian03. The experiment was carried out using a high-performance computer (SGI, Altix 4700).

[0086] By heat treatment for dehydration or dehydrogenation, -OH groups in the oxide semiconductor film are bonded to each other. It is thought that the reaction produces H2O. Therefore, the water production and desorption mechanism shown in Figure 39 is In Figure 39, since Zn is divalent, both M1 and M2 are If either M'-O or M'-O is Zn, one M'-O bond bound to Zn is deleted. do.

[0087] In Figure 39, M represents a metal atom, and there are three types of metal: In, Ga, and Zn. Initial state 1 In transition state 2, -OH forms a coordinate bond to bridge M1 and M2. The H in H is transferred to another -OH. In intermediate state 3, the resulting HO molecule is transferred to the metal atom. In the final state 4, the H2O molecule is detached and moves away to infinity.

[0088] The total combinations of (M1-M2) are: 1. In-In, 2. Ga-Ga, 3. Zn-Zn, There are six combinations: 4. In-Ga, 5. In-Zn, and 6. Ga-Zn. In this calculation, M' was replaced with H for the sake of simplicity. This was performed using a cluster calculation with a computational model.

[0089] In the calculation, the energy diagram corresponding to the reaction path in Figure 39 was obtained. As a representative combination of M1-M2, the calculation results for the case 1. In-In are shown in Figure 40. vinegar.

[0090] From Figure 40, it was found that the activation energy for water production was 1.16 eV. When a water molecule is removed, the energy becomes unstable by about 1.58 eV.

[0091] Conversely, when we look at the reaction in Figure 40 from right to left, we see that water enters the oxide semiconductor film. This can be seen as follows. Then, the water coordinated to the metal is hydrolyzed, creating two OH groups. The activation energy for this reaction is 0.47 eV.

[0092] Similarly, the reaction pathways for other combinations of (M1-M2) were analyzed. 1-6 Table 1 shows the activation energy (Ea [eV]) of the water production reaction for the case.

[0093] [Table 1]

[0094] From Table 1, it can be seen that the water generation reaction is likely to occur in 1.In-In and 4.In-Ga. On the other hand, the water-producing reaction is unlikely to occur in the Zn-Zn system. It is speculated that the water-producing reaction via the ion exchange membrane tends to be less likely to occur.

[0095] The heat treatment device is not limited to an electric furnace, and may be, for example, a GRTA (Gas Rapid Th thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Using RTA (Rapid Thermal Anneal) equipment such as LRTA devices can be used with halogen lamps, metal halide lamps, xenon Arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure mercury lamps, etc. This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp. TA devices use heat conduction or radiation from heating elements such as resistance heating elements as well as lamps. The GRTA is a gas processing system that uses high-temperature gas to heat the object to be processed. This is a method of performing heat treatment. The gas used is a rare gas such as argon, or a heating gas such as nitrogen. An inert gas that does not react with the material to be treated is used. Heat treatment may be performed at a temperature of from 0.degree. C. to 750.degree. C. for several minutes.

[0096] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. In particular, it is preferable that the oxide semiconductor layer does not contain water, hydrogen, or the like. The dehydration and dehydrogenation heat treatments are carried out at temperatures up to 700°C in a nitrogen atmosphere with H2O of 20 ppm or less. It is preferable to use nitrogen, helium, or neodymium for the heat treatment device. The purity of rare gas such as argon or nitrous oxide is 6N (99.9999%) or more, preferably 7N (9 9.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) It is preferable to use the following:

[0097] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized and microcrystalline. For example, the crystallinity may be 90% or more, or 80% or more. In some cases, the oxide semiconductor layer is a microcrystalline oxide semiconductor layer. Depending on the material of the semiconductor layer, it may become an amorphous oxide semiconductor that does not contain crystalline components. .

[0098] In addition, the first heat treatment of the oxide semiconductor layer is performed to process the oxide semiconductor layers into island-shaped oxide semiconductor layers 131 and 132. In that case, the first heat treatment may be performed on the oxide semiconductor film 130 before the first heat treatment. The substrate is then removed from the heating apparatus and a photolithography process is carried out.

[0099] The heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer is performed after the oxide semiconductor layer is formed. After the source electrode and the drain electrode are laminated on the conductor layer, After forming a passivation film, the above-mentioned step may be performed.

[0100] In addition, contact holes 118 and 119 are formed in the gate insulating layer 102 as shown in FIG. The step of forming the oxide semiconductor film 130 is performed after the oxide semiconductor film 130 is subjected to dehydration or dehydrogenation treatment. Good too.

[0101] Note that the etching of the oxide semiconductor film here is not limited to wet etching and may be dry etching. Etching may also be used.

[0102] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride ( CCl4) and the like) are preferred.

[0103] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4), sulfur hexafluoride (S F6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (H Br), oxygen (O2), and rare gases such as helium (He) and argon (Ar) A gas containing added sulfur, etc. can be used.

[0104] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0105] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0106] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium, etc. contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0107] In order to etch the desired shape, the etching conditions (etching Adjust the etching conditions (liquid, etching time, temperature, etc.) as appropriate.

[0108] Next, a metal conductive film made of a metal material is formed on the oxide semiconductor layers 133 and 134 by sputtering. It is formed by deposition or vacuum deposition.

[0109] The material of the metal conductive film is an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. Alternatively, an alloy film containing the above elements or an alloy film containing a combination of the above elements may be used. The metal conductive film may have a single layer structure or a laminated structure of two or more layers. For example, 2. A single layer structure of aluminum film containing silicon; 3. A titanium film laminated on an aluminum film Layer structure: Ti film, aluminum film layered on top of the Ti film, Ti on top of that In addition, titanium (Ti) and tantalum (T a), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), An alloy film made of a single or multiple combinations of elements selected from scandium (Sc), or A nitride film may also be used.

[0110] When a heat treatment is performed after the formation of the metal conductive film, the metal conductive film is required to have heat resistance sufficient to withstand the heat treatment. It is preferable to have the

[0111] Next, a fourth photolithography process is performed, and resist masks 136a, 136b, and 13 6c, 136d, 136e, and 136f are formed, and unnecessary portions are removed by etching the metal conductive film. The source electrode layer 105a, the drain electrode layer 105b, the source electrode layer 165a, The drain electrode layer 165b, the connection electrode 120, and the second terminal 122 are formed (FIG. 3(C) )reference.).

[0112] Note that the oxide semiconductor layers 133 and 134 are not removed when the metal conductive film is etched. The materials and etching conditions are appropriately adjusted as described above.

[0113] In this embodiment, a Ti film is used as the metal conductive film, and the oxide semiconductor layers 133 and 134 are In the present study, In-Ga-Zn-O oxide was used and ammonia water (Am) was used as the etchant. A mixture of monia, water, and hydrogen peroxide is used.

[0114] In this fourth photolithography step, the source electrode layers 105a, 165a, the drain The connection electrode 120 and the second terminal 122 are made of the same material as the first electrode layers 105b and 165b. The second terminal 122 is formed on the source wiring (the source electrode layer 105a , 165a)。 Also, the connection electrode 120 is electrically connected to the The contact hole 119 is formed in contact with the first terminal 121 and electrically connected thereto.

[0115] Note that resist masks 136a and 136b for forming the source electrode layer and the drain electrode layer are The holes 6b, 136c, 136d, 136e, and 136f may be formed by an inkjet method. When a resist mask is formed using the inkjet method, no photomask is used, so manufacturing costs are reduced. This can reduce costs.

[0116] Next, resist masks 136a, 136b, 136c, 136d, 136e, and 136f are The oxide insulating film 107 serving as a protective insulating film in contact with the oxide semiconductor layers 133 and 134 is removed. Form.

[0117] At this stage, the oxide semiconductor layers 133 and 134 are formed in regions in contact with the oxide insulating film. In this region, the gate electrode layer is overlapped with the gate insulating layer via the oxide insulating film 107 The region where they overlap is the channel formation region.

[0118] The oxide insulating film 107 has a thickness of at least 1 nm and is formed by an oxide deposition method such as a sputtering method. The insulating film 107 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed in. When hydrogen is contained in the oxide insulating film 107, the hydrogen can enter the oxide semiconductor layer or In the oxide semiconductor layer, oxygen is extracted by hydrogen, and the back channel of the oxide semiconductor layer is The resistance of the oxide insulating film becomes low (N-type), and a parasitic channel is formed. In order to obtain a film that contains as little hydrogen as possible, it is important not to use hydrogen in the film formation method. It is essential.

[0119] In this embodiment, a silicon oxide film having a thickness of 300 nm is formed by sputtering as the oxide insulating film 107. The substrate temperature during film formation should be between room temperature and 300°C. In the embodiment, the temperature is set to room temperature. The silicon oxide film is formed by sputtering using a rare gas (typically The reaction can be carried out under an atmosphere of, for example, argon or oxygen. A silicon oxide target or a silicon target can be used as the get. For example, Silicon oxide is formed by sputtering in an oxygen atmosphere using a silicon target. The oxide insulating film formed in contact with the oxide semiconductor layer whose resistance has been reduced by the first heat treatment can be formed. The membrane contains water, hydrogen ions, and OH - It does not contain impurities such as An inorganic insulating film that blocks the light from passing through the insulating film is used. Representative examples of the insulating film include a silicon oxide film, a silicon nitride oxide film, and an oxide film. A gallium film, an aluminum oxide film, an aluminum oxynitride film, or the like is used.

[0120] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or a nitrogen gas atmosphere. The heating is performed at a temperature of 00° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower (see FIG. 4(A)). For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. As a result, parts of the oxide semiconductor layers 133 and 134 overlapping with the oxide insulating film 107 are It is heated while in contact with the insulating film 107 .

[0121] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor layer is selectively treated with an oxygen-excess This is the state.

[0122] As a result, in the oxide semiconductor layer 133, a channel formation region overlapping with the gate electrode layer 161 is formed. The region 166 is an I-type region, and includes a high resistance source region 167a overlapping the source electrode layer 165a, A high-resistance drain region 167b overlapping the drain electrode layer 165b is formed in a self-aligned manner. Similarly, in the oxide semiconductor layer 134, the gate The channel forming region 116 overlapping with the electrode layer 101 is an I-type region. A high-resistance source region 117a overlapping the drain electrode layer 105b and a high-resistance drain region 117b overlapping the drain electrode layer 105b. The region 117b is formed in a self-aligned manner, and the oxide semiconductor layer 103 is formed.

[0123] In addition, the drain electrode layers 105b and 165b (and the source electrode layers 105a and 165a) overlap. In the folded oxide semiconductor layers 103 and 163, the high-resistance drain regions 117b and 167b ( or high resistance source regions 117a, 167a) are formed to form a circuit. The reliability can be improved. Specifically, the high-resistance drain regions 117b and 167b By forming the drain electrode layer 105b, 165b to the high resistance drain region 117b , 167b, the conductivity of the channel forming regions 116, 166 can be changed stepwise. Therefore, the drain electrode layers 105b and 165b can be provided with a high voltage power supply. When the gate electrode layers 101 and 161 are connected to a wiring that supplies a potential VDD, Even if a high electric field is applied between the drain electrode layers 105b and 165b, the high resistance drain region is prevented from being broken. This buffer prevents localized high electric fields from being applied, improving the breakdown voltage of the transistor. It is possible.

[0124] Also, the drain electrode layers 105b and 165b (and the source electrode layers 105a and 165a) are overlapped. In the folded oxide semiconductor layer, the high-resistance drain region 117b, 167b (or high-resistance source region By forming the semiconductor regions 117a and 167a, the channel formation region when the circuit is formed is This allows the leakage current in the regions 116 and 166 to be reduced.

[0125] In this embodiment, a silicon oxide film is formed as the oxide insulating film 107 by a sputtering method. After the formation of the oxide layer, a heat treatment is performed at 250°C to 350°C to remove the oxide layer between the source and drain regions. Oxygen is impregnated and diffused into the oxide semiconductor layer from the exposed portion (channel formation region) of the semiconductor layer. By forming a silicon oxide film by sputtering, the excess oxygen in the silicon oxide film is eliminated. The oxygen can be impregnated and diffused into the oxide semiconductor layer by heat treatment. The channel formation region can be made highly resistive by the impregnation and diffusion of oxygen into the oxide semiconductor layer. This allows the device to be a normally-off thin-film transistor. can be obtained.

[0126] Through the above steps, the thin film transistor 180 is formed in the driver circuit section and the pixel section is formed on the same substrate. The thin film transistor 170 can be fabricated in the above-mentioned manner. a high-resistance source region, a high-resistance drain region, and a channel formation region; Thus, the thin film transistors 170 and 18 are bottom gate type thin film transistors. 0 indicates that the high-resistance drain region or high-resistance source region acts as a buffer even when a high electric field is applied. This prevents a high electric field from being applied locally, improving the breakdown voltage of the transistor.

[0127] By forming the driver circuit section and the pixel section on the same substrate, the driver circuit and external signals can be connected The wiring can be shortened, making it possible to reduce the size and cost of the semiconductor device.

[0128] A protective insulating layer may be further formed over the oxide insulating film 107. For example, The RF sputtering method is suitable for mass production, so the protection film is This is a preferred method for forming an insulating layer. The protective insulating layer is formed by removing moisture, hydrogen ions, and OH - etc. It uses an inorganic insulating film that does not contain impurities and blocks them from entering from the outside, and nitrides A silicon film, an aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, or the like is used.

[0129] Next, a fifth photolithography step is performed to form a resist mask, and an oxide insulating film 1 By etching in step 07, a contact hole 125 reaching the drain electrode layer 105b is formed. Then, the resist mask is removed (see FIG. 4(B)). A contact hole 127 reaching the second terminal 122 and a contact electrode 120 reaching the connection electrode 120 are formed. A resist mask for forming the contact hole 126 is also formed. The resist mask may be formed by an inkjet method. Since no photomask is used, manufacturing costs can be reduced.

[0130] Next, a light-transmitting conductive film is formed. Indium (In2O3) and indium oxide tin oxide alloy (In2O3-SnO2, IT The transparent film is formed by sputtering or vacuum deposition. As another material for the conductive film, a nitrogen-containing Al-Zn-O-based non-single crystal film, i.e., Al- Zn-ON type non-single crystal film, Zn-O type non-single crystal film containing nitrogen, and A Sn-Zn-O based non-single crystal film may be used. The composition ratio (atomic %) of zinc is 47 atomic % or less, and the composition ratio of aluminum in the non-single crystal film is (atomic%), and the composition ratio (atomic%) of aluminum in the non-single crystal film is The composition ratio (atomic percent) of nitrogen in the material is larger than that in the material containing hydrochloric acid. However, etching of ITO is particularly prone to leaving residues, so Indium oxide-zinc oxide alloy (In2O3-ZnO) can be used to improve workability. good.

[0131] The composition ratio of the light-transmitting conductive film is expressed in atomic percent. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be used for the evaluation.

[0132] Next, a sixth photolithography process is performed to form a resist mask and to form a The pixel electrode layer 110, the conductive layer 111, and the terminal Electrodes 128 and 129 are formed, and the resist mask is removed. A cross-sectional view at this stage is shown in FIG. The plan view at this stage is shown in FIG.

[0133] In the sixth photolithography step, the gate insulating layer 102 in the capacitance section The oxide insulating film 107 serves as a dielectric, and the capacitance wiring 108 and the pixel electrode layer 110 form a storage capacitance. A quantity is formed.

[0134] The gate insulating layer 102 is a dielectric and is formed of a capacitance wiring and a capacitance electrode (also called a capacitance electrode layer). The capacitor 147, which is a storage capacitor to be used, can also be formed on the same substrate. The pixel electrodes are overlapped with the gate wiring of the adjacent pixels via the protective insulating film and the gate insulating layer. A storage capacitor may be formed by twisting the electrodes.

[0135] The terminal electrodes 128 and 129 formed on the terminal portion are electrodes or wiring used for connection with an FPC. The terminal electrode 128 formed on the first terminal 121 via the connection electrode 120 is This serves as a terminal electrode for connection that functions as an input terminal for the gate wiring. The formed terminal electrode 129 is a connection terminal electrode that functions as an input terminal of the source wiring. do.

[0136] 11(A1) and 11(A2) are top views of the gate line terminal portion at this stage. FIG. 11(A1) is a cross-sectional view taken along line C1-C2 in FIG. 11(A2). In FIG. 11A1, a conductive film is formed on the oxide insulating film 107. The conductive film 155 is a terminal electrode for connection that functions as an input terminal. In the terminal section, a first terminal 151 made of the same material as the gate line and a source The connection electrode 153, which is made of the same material as the wiring, overlaps directly with the gate insulating layer 102. The connection electrode 153 and the conductive film 155 are provided on the oxide insulating film 107. The contact holes are drilled through the substrate to provide direct contact and electrical continuity.

[0137] FIG. 11B1 and FIG. 11B2 are a top view and a cross-sectional view of a source wiring terminal portion. Also, FIG. 11(B1) is taken along the line D1-D2 in FIG. 11(B2). In FIG. 11B1, a conductive film formed over the oxide insulating film 107 The film 155 is a terminal electrode for connection that functions as an input terminal. In the terminal portion, an electrode 156 made of the same material as the gate wiring is connected to the source wiring. The electrode 1 overlaps the second terminal 150, which is electrically connected to the electrode 1 through the gate insulating layer 102. 56 is not electrically connected to the second terminal 150, and the electrode 156 is connected to the second terminal 150. By setting different potentials, such as floating, GND, or 0V, you can reduce noise. A capacitance for preventing electrostatic discharge or a capacitance for preventing static electricity can be formed. is electrically connected to the conductive film 155 through the oxide insulating film 107.

[0138] The gate wiring, source wiring, and capacitance wiring are arranged in multiple lines according to the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, The terminal 2 and the third terminal of the same potential as the capacitance wiring are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0139] In this way, six photolithography steps were performed using six photomasks to produce a thin film. A driving circuit section having a transistor 180, a pixel section having a thin film transistor 170, a storage capacitor A capacitor 147 having a large capacitance and an external output terminal portion can be completed. The pixel section is made up of an active area, and the active area consists of an active area for each pixel. The present invention can be used as one of the substrates for manufacturing a display device of an active matrix type. For the sake of convenience, this document refers to such a substrate as an active matrix substrate.

[0140] When manufacturing an active matrix type liquid crystal display device, an active matrix substrate A liquid crystal layer is provided between the active matrix substrate and a counter substrate having a counter electrode. The counter electrode is fixed to the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for

[0141] An insulating layer functioning as an alignment film is provided over the oxide insulating film 107, the conductive layer 111, and the pixel electrode layer 110. Form 191.

[0142] A colored layer 195, a counter electrode layer 194, and an insulating layer 19 functioning as an alignment film are formed on the counter substrate 190. The substrate 100 and the counter substrate 190 are connected to each other to adjust the cell gap of the liquid crystal display device. The liquid crystal layer 192 is sandwiched between the spacers and bonded together with a sealant (not shown). The lamination step may be carried out under reduced pressure.

[0143] The sealing material typically uses a visible light curing, ultraviolet light curing or heat curing resin. Typically, acrylic resin, epoxy resin, amine resin, etc. are used. In addition, photopolymerization initiators (typically ultraviolet rays), heat curing agents, fillers, coupling agents, etc. The composition may also include a coating agent.

[0144] The liquid crystal layer 192 is formed by filling the gap with a liquid crystal material. Alternatively, a dispenser method (dropping method) may be used in which the adhesive is dropped before bonding the facing substrate 190. After bonding the substrate 100 and the opposing substrate 190 together, liquid crystal is injected using capillary action. The liquid crystal material is not particularly limited, and various materials can be used. In addition, if a material exhibiting a blue phase is used as the liquid crystal material, the alignment film becomes unnecessary. This can be done.

[0145] A polarizing plate 196a is provided on the outer side of the substrate 100, and a polarizing plate 196b is provided on the outer side of the counter substrate 190. Thus, the transmissive liquid crystal display device of this embodiment mode can be manufactured (see FIG. 1).

[0146] Although not shown in the present embodiment, a black matrix (light-shielding layer), a polarizing member, a phase Optical members (optical substrates) such as a polarizing member and an anti-reflection member are provided as appropriate. A circularly polarized light source using a retardation substrate may be used. Alternatively, threads or the like may be used.

[0147] In an active matrix type liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the pixel electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0148] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, resulting in image retention. In order to improve the moving image characteristics of the LCD, There is a driving technique called black insertion, which displays black every other frame.

[0149] In addition, the vertical sync frequency should be increased to 1.5 times the normal frequency, preferably to 2 times or more, to improve the video characteristics. There is also a driving technology called double speed driving, which improves image quality.

[0150] In addition, in order to improve the video characteristics of liquid crystal display devices, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source to light intermittently within one frame period. In addition, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled, the LE can be switched according to the timing of the optical modulation of the liquid crystal layer. The timing of the LEDs can also be synchronized. This is particularly useful when displaying images with a large proportion of black areas occupying the entire screen. This has the effect of reducing power consumption.

[0151] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the conventional method.

[0152] By forming the thin film transistor using an oxide semiconductor, the manufacturing cost can be reduced. In particular, the above-described method can be used to form an oxide insulating film in contact with an oxide semiconductor layer. By this, it is possible to manufacture and provide a thin film transistor having stable electrical characteristics. Therefore, a semiconductor device having a thin film transistor with good electrical characteristics and high reliability can be provided. It can be provided.

[0153] Since the semiconductor layer in the channel formation region is a high resistance region, the electrical characteristics of the thin film transistor are This stabilizes the device and prevents an increase in the off-state current. This results in good electrical characteristics and reliability. It is possible to provide a semiconductor device having a thin film transistor with good performance.

[0154] In addition, thin film transistors are easily damaged by static electricity, etc. The protection circuit is preferably provided over the same substrate as the semiconductor device. It is preferable to use a nonlinear element. For example, the protection circuit is In this embodiment, a plurality of protection circuits are provided between the terminal and the signal line input terminal. A surge voltage is applied to the scanning lines, signal lines and capacitance bus lines due to static electricity or the like, and the pixel transistors are The protection circuit is designed to prevent the transistors from being destroyed. When a voltage is applied, the protection circuit is configured to release the electric charge to the common wiring. It is composed of a nonlinear element arranged in parallel between the scan line and the common line. The element is composed of a two-terminal element such as a diode or a three-terminal element such as a transistor. For example, it is possible to form the thin film transistor 170 in the pixel portion in the same process. For example, by connecting the gate and drain terminals of a transistor, It can have characteristics.

[0155] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0156] (Embodiment 2) In this embodiment, the oxide semiconductor layer and the source electrode layer or the drain electrode layer in Embodiment 1 are An example in which an oxide conductive layer is provided between an electrode layer and a source region and a drain region is shown in FIG. As shown in FIG. 7, the other steps can be performed in the same manner as in the first embodiment, and the same parts as in the first embodiment can be used. The description of the parts having the same functions and the repetition of the steps will be omitted. FIG. 7 is the same as FIG. 1 to FIG. 5 except for some steps, and therefore the same parts are designated by the same reference numerals. Reference numbers will be used and detailed explanations of the same parts will be omitted.

[0157] First, the steps up to the step of FIG. 3(B) in the first embodiment are carried out according to the first embodiment. A) is the same as FIG. 3(B).

[0158] An oxide conductive film 140 is formed on the dehydrated or dehydrogenated oxide semiconductor layers 133 and 134. A metal conductive film made of a metal conductive material is laminated on the oxide conductive film 140 .

[0159] The oxide conductive film 140 is formed by a method such as sputtering or vacuum deposition (electron beam deposition). The oxide conductive film 14 is formed by a method such as arc discharge ion plating or spraying. The material for 0 preferably contains zinc oxide as a component and does not contain indium oxide. As such an oxide conductive film 140, zinc oxide, zinc oxide, etc. Lead aluminum, zinc aluminum oxynitride, zinc gallium oxide, etc. can be applied. The film thickness is appropriately selected within the range of 50 nm to 300 nm. When using this method, deposition is performed using a target containing 2% to 10% by weight of SiO2. This process makes the oxide conductive film contain SiOx (X>0), which inhibits crystallization, and prevents the decrystallization process from being performed later. It is preferable to suppress crystallization during the heat treatment for hydration or dehydrogenation. stomach.

[0160] Next, a fourth photolithography process is performed, and resist masks 136a, 136b, and 13 6c, 136d, 136e, and 136f are formed, and unnecessary portions of the metal conductive film are removed by etching. The source electrode layer 105a, the drain electrode layer 105b, the source electrode layer 165a, The drain electrode layer 165b, the connection electrode 120, and the second terminal 122 are formed (FIG. 6(B) )reference.).

[0161] Note that when the metal conductive film is etched, the oxide conductive film 140, the oxide semiconductor layer 133, The materials and etching conditions are appropriately adjusted so that the layer 134 is not removed.

[0162] Next, resist masks 136a, 136b, 136c, 136d, 136e, and 136f are The source electrode layer 105a, the drain electrode layer 105b, the source electrode layer 165a, and the drain The oxide conductive film 140 is etched using the indium electrode layer 165b as a mask to form an oxide conductive layer 164a, 164b, and oxide conductive layers 104a, 104b are formed (see FIG. 6C). The oxide conductive film 140 containing zinc oxide is formed by removing an alkali such as a resist remover. This can be easily etched using an alkaline solution. In the same process, oxide is also formed on the terminals. Conductive layers 138, 139 are formed.

[0163] The difference in etching rate between the oxide semiconductor layer and the oxide conductive film is utilized to form a channel formation region. In order to form the conductive oxide film, an etching process is performed to divide the conductive oxide film. The oxide semiconductor layer is then heated to 1000° C., and the oxide semiconductor layer is heated to 1000° C. The conductive film is selectively etched.

[0164] Therefore, the resist masks 136a, 136b, 136c, 136d, 136e, and 136f The removal of the film is preferably performed by an ashing process. In this case, the oxide conductive film 140 and the oxide semiconductor layers 133 and 134 are excessively etched. In order to avoid this, the etching conditions (type of etchant, concentration, etching time) are adjusted appropriately. Adjust.

[0165] As in this embodiment, after the oxide semiconductor layer is etched into an island shape, the oxide conductive film and the gold A metal conductive film is laminated, and a wiring pattern including a source electrode layer and a drain electrode layer is formed using the same mask. By etching the GaN, an oxide conductive film remains under the wiring pattern of the metal conductive film. It can be done.

[0166] At the contact between the gate wiring (conductive layer 162) and the source wiring (drain electrode layer 165b), However, since the oxide conductive layer 164b is formed under the source wiring, the oxide The conductive layer 164b is preferable because it acts as a buffer and does not form an insulating oxide with the metal. is preferable.

[0167] The oxide insulating film 107 serving as a protective insulating film in contact with the oxide semiconductor layers 133 and 134 is formed. In this embodiment, a silicon oxide film having a thickness of 300 nm is used as the oxide insulating film 107. The film is formed by using a deposition method.

[0168] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or a nitrogen gas atmosphere. For example, the heating is performed in a nitrogen atmosphere. The second heat treatment is performed at 250°C for 1 hour under atmospheric pressure. Part of the oxide semiconductor layers 133 and 134 overlapping with the oxide insulating film 107 is in contact with the oxide insulating film 107. The material is heated in a

[0169] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor layer is selectively treated with an oxygen-excess This is the state.

[0170] As a result, in the oxide semiconductor layer 133, a channel formation region overlapping with the gate electrode layer 161 is formed. The region 166 is an I-type high-resistance region overlapping the source electrode layer 165a and the oxide conductive layer 164a. The anti-source region 167a and the high-temperature insulating layer 166a overlapping the drain electrode layer 165b and the oxide conductive layer 164b are The resistive drain region 167b is formed in a self-aligned manner, and the oxide semiconductor layer 163 is formed. Similarly, in the oxide semiconductor layer 134, the channel formation region 116 has an i-type conductivity. a high-resistance source region 117a overlapping the source electrode layer 105a and the oxide conductive layer 104a; A high-resistance drain region 117b overlapping the drain electrode layer 105b and the oxide conductive layer 104b The oxide semiconductor layer 103 is formed in a self-aligned manner.

[0171] The oxide semiconductor layers 163 and 103 and the drain electrode layer 105b made of a metal material, The oxide conductive layers 104b and 164b disposed between the pole layers 165b are low-resistance drain regions ( LRN (Low Resistance N-type conductivity) area It also functions as a low resistance drain (LRD) region. Similarly, the oxide semiconductor layers 163 and 103 and the source electrode layer 105a made of a metal material are The oxide conductive layers 104a and 164a disposed between the source electrode layers 165a are low-resistance sources. Low Resistance N-type conduction region (LRN) ty (also called LRS (Low Resistance Source) region) The drain electrode is made of an oxide semiconductor layer, a low-resistance drain region, and a metal material. By using a layered structure, the breakdown voltage of the transistor can be further improved. In general, the carrier concentration in the low-resistance drain region is higher than that in the high-resistance drain region (HRD region). is also large, for example 1×10 20 / cm 3 More than 1×10 21 / cm 3Within the following range preferable.

[0172] By the above steps, the thin film transistor 181 is formed in the driver circuit portion and the pixel portion is formed on the same substrate. The thin film transistor 171 can be fabricated in the above-mentioned manner. a high-resistance source region, a high-resistance drain region, and a channel formation region; Thus, the thin film transistors 171 and 18 are bottom-gate type thin film transistors. In the case of 1, the high-resistance drain region or the high-resistance source region acts as a buffer even when a high electric field is applied. This prevents a high electric field from being applied locally, improving the breakdown voltage of the transistor.

[0173] In the capacitance section, the capacitance wiring 108, the gate insulating layer 102, the oxide conductive layer 104b, The oxide conductive layer formed in the same process, the drain electrode layer 105b and the metal conductive layer formed in the same process A capacitor 146 is formed by laminating a conductive layer and an oxide insulating film 107.

[0174] Next, a planarization insulating layer 109 is formed over the oxide insulating film 107. In this case, the planarization insulating layer 109 is formed only in the pixel area. Heat-resistant polymers such as imide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can be used. ), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, a flat surface can be obtained. A chemical insulating layer 109 may be formed.

[0175] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0176] The method for forming the planarization insulating layer 109 is not particularly limited. Depending on the material, a sputtering method may be used. , SOG method, spin coating, dip, spray coating, droplet ejection method (inkjet method, Screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater In this embodiment, the planarization insulating layer 109 is formed by a machine such as a platenizer, a knife coater, or the like. It is formed using photosensitive acrylic.

[0177] Next, a fifth photolithography process is performed to form a resist mask and a planarizing insulating layer 1 09, and the oxide insulating film 107 is etched to form a contact that reaches the drain electrode layer 105b. A contact hole 125 is formed, and the resist mask is removed (see FIG. 6(D)). By etching here, a contact hole 127 reaching the second terminal 122, a connection electrode A contact hole 126 reaching 120 is also formed.

[0178] Next, a light-transmitting conductive film is formed, and a sixth photolithography process is performed. A mask is formed, and unnecessary portions are removed by etching to form the pixel electrode layer 110 and the conductive layer 11 1. Form terminal electrodes 128 and 129, and remove the resist mask (see FIG. 7(A)). .

[0179] As in the first embodiment, the liquid crystal layer 192 is sandwiched between the opposing substrates 190. A liquid crystal display device having the above structure is manufactured (see FIG. 7(B)).

[0180] The oxide conductive layer is formed as a source region and a drain region, and the oxide semiconductor layer is formed as a source electrode layer and a drain region. By providing the source region and the drain electrode layer, the resistance of the source region and the drain region can be reduced. This allows the transistor to operate at high speed. The use of an oxide conductive layer as a gate insulating layer improves the frequency characteristics of the peripheral circuits (drive circuits). This is effective for preventing the formation of oxide semiconductor layers. This is because the contact between the conductive layer and the oxide layer can reduce the contact resistance.

[0181] In addition, molybdenum (Mo), which is used as part of the wiring material in liquid crystal panels (e.g. , Mo / Al / Mo), the high contact resistance with the oxide semiconductor layer was an issue. Mo is less likely to oxidize than i, and therefore has a weaker effect of extracting oxygen from the oxide semiconductor layer. This is because the contact interface of the oxide semiconductor layer does not become n-type. The connection is achieved by interposing an oxide conductive layer between the semiconductor layer and the source and drain electrode layers. This reduces the contact resistance and improves the frequency characteristics of the peripheral circuits (drive circuits).

[0182] Since the channel length of the thin film transistor is determined during etching of the oxide conductive layer, For example, the channel length L can be shortened to 0.1 μm or more and 2 μm or less. The operating speed can be increased.

[0183] (Embodiment 3) In this embodiment, the oxide semiconductor layer and the source electrode in Embodiment 1 or 2 are A conductive oxide layer is provided between the source and drain electrode layers. Other examples are shown in Figs. 8 and 9. Therefore, the rest is the same as in the first or second embodiment. and a part having the same function as in embodiment 1 or embodiment 2. 8 and 9 are the same as those in FIG. 1 to FIG. 7. Since the two models are the same except for some differences, the same reference numerals are used for the same parts and detailed explanations of the same parts are provided. The details are omitted.

[0184] First, according to the first embodiment, a metal conductive film is formed on the substrate 100, and the metal conductive film is The first end is etched using a resist mask formed by a photolithography process. The gate electrode layer 161, the conductive layer 162, the gate electrode layer 101, and the capacitance wiring 108 are Form.

[0185] Next, the first terminal 121, the gate electrode layer 161, the conductive layer 162, the gate electrode layer 101, A gate insulating layer 102 is formed on the gate wiring 108, and an oxide semiconductor film and an oxide conductive film are laminated on the gate insulating layer 102. The gate insulating layer, the oxide semiconductor film, and the oxide conductive film are successively formed without exposure to air. It is possible.

[0186] A resist mask is formed over the oxide conductive film by a second photolithography process. the gate insulating layer, the oxide semiconductor film, and the oxide conductive film are etched using a mask; A contact hole 119 reaching the first terminal 121 and a contact hole 162 reaching the conductive layer 162 are provided. Form a hole 118.

[0187] The resist mask by the second photolithography process is removed, and then a second photoresist is formed on the oxide conductive film. A resist mask is formed by the third photolithography process. An island-shaped oxide semiconductor layer and an island-shaped oxide conductive layer are formed using a resist mask by a deposition process.

[0188] In this manner, in a state where the oxide semiconductor film and the oxide conductive film are laminated on the entire surface of the gate insulating layer, When a step of forming a contact hole in the gate insulating layer is performed, a resist mask is formed on the surface of the gate insulating layer. Since the mask does not come into direct contact with the gate insulating layer, contamination of the gate insulating layer surface (such as adhesion of impurities) can be prevented. Therefore, the state of the interfaces between the gate insulating layer and the oxide semiconductor film and between the gate insulating layer and the oxide conductive film can be improved. This leads to improved reliability.

[0189] Next, the oxide semiconductor layer and the oxide conductive layer are stacked, and then heat-treated for dehydration and dehydrogenation. Heat treatment at a temperature of 400°C to 700°C dehydrates and dehydrates the oxide semiconductor layer. This hydrogenates the material and prevents it from being re-impregnated with water (H2O) thereafter.

[0190] This heat treatment can be used to remove the crystallization inhibitors such as silicon oxide from the oxide conductive layer. The oxide conductive layer is then crystallized. The crystals of the oxide conductive layer grow in a columnar shape relative to the underlying surface. As a result, in order to form the source electrode layer and the drain electrode layer, the gold layer on the oxide conductive layer is When etching a metal conductive film, the formation of undercuts can be prevented.

[0191] In addition, the conductivity of the oxide conductive layer is improved by heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer. Note that only the oxide conductive layer can be heat-treated at a lower temperature than the oxide semiconductor layer. It is okay to understand that.

[0192] In addition, the first heat treatment of the oxide semiconductor layer and the oxide conductive layer is performed to form an island-shaped oxide semiconductor layer and This can also be performed on an oxide semiconductor film and an oxide conductive film before they are processed into an oxide conductive layer. In this case, after the first heat treatment, the substrate is removed from the heating apparatus and a photolithography process is performed. Do the following.

[0193] Through the above steps, the oxide semiconductor layers 133 and 134 and the oxide conductive layers 142 and 143 are obtained. (See FIG. 8A.) The oxide semiconductor layer 133, the oxide conductive layer 142, and the oxide semiconductor layer The oxide conductive layer 134 and the oxide conductive layer 143 are island-shaped stacked layers formed using the same mask. do.

[0194] Next, a fourth photolithography process is performed, and resist masks 136a, 136b, and 13 6c, 136d, 136e, and 136f are formed, and unnecessary portions of the metal conductive film are removed by etching. The source electrode layer 105a, the drain electrode layer 105b, the source electrode layer 165a, The drain electrode layer 165b, the connection electrode 120, and the second terminal 122 are formed (FIG. 8(B) )reference.).

[0195] Note that when the metal conductive film is etched, the oxide conductive layers 142 and 143 and the oxide semiconductor layer The materials and etching conditions are appropriately adjusted so that the layers 133 and 134 are not removed. .

[0196] Next, resist masks 136a, 136b, 136c, 136d, 136e, and 136f are The source electrode layer 105a, the drain electrode layer 105b, the source electrode layer 165a, and the drain The oxide conductive layers 142 and 143 are etched using the oxide electrode layer 165b as a mask. The metal conductive layers 164a and 164b and the oxide conductive layers 104a and 104b are formed (FIG. 8(C) The oxide conductive layers 142 and 143, which are made of zinc oxide, are formed by, for example, removing the resist. It can be easily etched using an alkaline solution such as ethyl acetate.

[0197] Therefore, the resist masks 136a, 136b, 136c, 136d, 136e, and 136f The removal of the film is preferably performed by an ashing process. In this case, the oxide conductive layers 142 and 143 and the oxide semiconductor layers 133 and 134 are excessively etched. In order to prevent chipping, the etching conditions (type of etchant, concentration, etching time) should be carefully considered. Adjust as appropriate.

[0198] The oxide insulating film 107 serving as a protective insulating film in contact with the oxide semiconductor layers 133 and 134 is formed. In this embodiment, a silicon oxide film having a thickness of 300 nm is used as the oxide insulating film 107. The film is formed by using a deposition method.

[0199] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or a nitrogen gas atmosphere. For example, the heating is performed in a nitrogen atmosphere. The second heat treatment is performed at 250°C for 1 hour under atmospheric pressure. Part of the oxide semiconductor layers 133 and 134 overlapping with the oxide insulating film 107 is in contact with the oxide insulating film 107. The material is heated in a

[0200] Through the above steps, the oxide semiconductor layer after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor layer is selectively treated with an oxygen-excess This is the state.

[0201] As a result, in the oxide semiconductor layer 133, a channel formation region overlapping with the gate electrode layer 161 is formed. The region 166 is an I-type high-resistance region overlapping the source electrode layer 165a and the oxide conductive layer 164a. The anti-source region 167a and the high-temperature insulating layer 166a overlapping the drain electrode layer 165b and the oxide conductive layer 164b are The resistive drain region 167b is formed in a self-aligned manner, and the oxide semiconductor layer 163 is formed. Similarly, in the oxide semiconductor layer 134, a channel is formed overlapping with the gate electrode layer 101. The region 116 is an I-type region, and has a high conductivity type overlapping the source electrode layer 105a and the oxide conductive layer 104a. The resistive source region 117a overlaps the drain electrode layer 105b and the oxide conductive layer 104b. The high-resistance drain region 117b is formed in a self-aligned manner, and the oxide semiconductor layer 103 is formed. can be.

[0202] The oxide semiconductor layers 163 and 103 and the drain electrode layer 105b made of a metal material, The oxide conductive layers 104b and 164b disposed between the pole layers 165b are low-resistance drain regions ( Similarly, the oxide semiconductor layer 163 also functions as a region between the oxide semiconductor layer 162 and the oxide semiconductor layer 163. 103 and a source electrode layer 105a made of a metal material, and a source electrode layer 165a are disposed between the The oxide conductive layers 104a and 164a are low-resistance source regions (also called LRN regions or LRS regions). The drain region is made of an oxide semiconductor layer, a low-resistance drain region, and a metal material. By using this structure for the gate electrode layer, the breakdown voltage of the transistor can be further improved. Specifically, the carrier concentration in the low-resistance drain region is higher than that in the high-resistance drain region (HRD region). ), e.g., 1×10 20 / cm 3 More than 1×10 21 / cm 3 Within the following range It is preferable to have one.

[0203] Through the above steps, a thin film transistor 182 is formed in the driver circuit section and a thin film transistor 183 is formed in the pixel section on the same substrate. The thin film transistor 172 can be fabricated on the same substrate. a high-resistance source region, a high-resistance drain region, and a channel formation region; Thus, the thin film transistors 172 and 18 are bottom gate type thin film transistors. 2. The high-resistance drain region or high-resistance source region acts as a buffer even when a high electric field is applied. This prevents a high electric field from being applied locally, improving the breakdown voltage of the transistor.

[0204] Next, a fifth photolithography step is performed to form a resist mask, and an oxide insulating film 1 A contact hole 125 reaching the drain electrode layer 105b is formed by etching in step 07. Then, the resist mask is removed (see FIG. 8(D)). A contact hole 127 reaching the second terminal 122, a contact hole 127 reaching the connection electrode 120 A hole 126 is also formed.

[0205] Next, a light-transmitting conductive film is formed, and a sixth photolithography process is performed. A mask is formed, and unnecessary portions are removed by etching to form the pixel electrode layer 110 and the conductive layer 11 1. Form terminal electrodes 128 and 129, and remove the resist mask (see FIG. 9(A)). .

[0206] As in the first embodiment, the liquid crystal layer 192 is sandwiched between the opposing substrates 190. A liquid crystal display device having the above structure is manufactured (see FIG. 9(B)).

[0207] The oxide conductive layer is formed as a source region and a drain region, and the oxide semiconductor layer is formed as a source electrode layer and a drain region. By disposing it between the drain electrode layer, the resistance of the source region and the drain region is reduced. The source region and the drain region are electrically connected to each other. The use of an oxide conductive layer as a gate insulating layer improves the frequency characteristics of the peripheral circuits (drive circuits). This is effective for preventing the formation of oxide semiconductor layers. This is because contact between the conductive layer and the oxide conductive layer can reduce the contact resistance.

[0208] An oxide conductive layer is interposed between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. This reduces the contact resistance and improves the frequency characteristics of the peripheral circuits (drive circuits). .

[0209] Since the channel length of the thin film transistor is determined during etching of the oxide conductive layer, For example, the channel length L is 0.1 μm or more and 2 μm or less. , and the operation speed can be increased.

[0210] (Embodiment 4) Here, in a liquid crystal display device in which a liquid crystal layer is sealed between a first substrate and a second substrate, A common connection portion is formed on the first substrate for electrically connecting to the counter electrode provided on the second substrate. In addition, a thin film transistor is formed as a switching element on the first substrate. The manufacturing process of the common connection portion is made common to the manufacturing process of the switching element of the pixel portion. This allows the formation of the film without complicating the process.

[0211] The common connection portion is disposed at a position overlapping a sealant for bonding the first substrate and the second substrate. The sealing material is electrically connected to the counter electrode via conductive particles contained therein. The common connection part is provided in a place where it does not overlap with the sealing material (excluding the pixel part), and the common connection part A paste containing conductive particles is provided separately from the sealing material so as to overlap the opposing electrode. A connection is made.

[0212] FIG. 36(A) is a cross-sectional view of a semiconductor device in which a thin film transistor and a common connection portion are fabricated on the same substrate. FIG.

[0213] In FIG. 36A, the thin film transistor 220 electrically connected to the pixel electrode layer 227 is , a channel-etched thin film transistor arranged in a pixel portion. In this embodiment, The same structure as that of the thin film transistor 170 of the first embodiment is used.

[0214] FIG. 36B is a diagram showing an example of a top view of the common connection portion, and the dashed line C3-C4 in the diagram The cross-sectional view of the common connection part taken along the line corresponds to FIG. 36(A). The same parts as in 36(A) will be explained using the same reference numerals.

[0215] The common potential line 210 is provided on the gate insulating layer 202 and is connected to the source of the thin film transistor 220. The gate electrode layer is made of the same material and in the same process as the source electrode layer and the drain electrode layer.

[0216] The common potential line 210 is covered with a protective insulating layer 203. The thin film transistor 2 has a plurality of openings at positions overlapping the line 210. The contact hole connecting the drain electrode layer 20 and the pixel electrode layer 227 is formed in the same process. It is manufactured.

[0217] In addition, since the area size is significantly different here, the contact hole in the pixel area and the common In FIG. 36(A), the opening of the pixel section is called the opening of the connection section. The connections are not shown to the same scale. For example, the length of the dashed line C3-C4 of the common connection is 50 0 μm, whereas the width of a thin-film transistor is less than 50 μm, and in fact is 36(A) shows the pixel area and the common connection area for ease of understanding. The continuations are shown at different scales.

[0218] The common electrode layer 206 is provided on the protective insulating layer 203, and the pixel electrode layer 227 of the pixel portion It is made of the same materials and in the same process.

[0219] In this way, the manufacturing process of the common connection portion is common to the manufacturing process of the switching element of the pixel portion. It is preferable that the common potential line is a metal wiring so as to reduce the wiring resistance.

[0220] A first substrate on which a pixel section and a common connection section are provided and a second substrate having a counter electrode are then Secure it in place using a sealant.

[0221] When the sealing material contains conductive particles, the sealing material and the common connection part are overlapped with each other. For example, in a small LCD panel, the diagonal corners of the pixel area are aligned. Two common connection parts are arranged overlapping the sealant. In addition, in large liquid crystal panels, Four or more common connections are disposed in overlapping relation with the sealant.

[0222] The common electrode layer 206 is an electrode that comes into contact with the conductive particles contained in the sealing material. The substrate is electrically connected to the counter electrode of the substrate.

[0223] When using the liquid crystal injection method, a pair of substrates are fixed with a sealant, and then liquid crystal is injected between the pair of substrates. In addition, when the liquid crystal dropping method is used, a sealant is applied to the second substrate or the first substrate. After drawing and dropping liquid crystal, the pair of substrates are bonded together under reduced pressure.

[0224] In this embodiment, an example of a common connection portion electrically connected to the counter electrode has been shown. Not limited to this, it is used for connecting parts to other wiring, connecting parts to external connection terminals, etc. It is possible.

[0225] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0226] (Embodiment 5) In this embodiment mode, a manufacturing process of a thin film transistor is partially different from that in Embodiment Mode 1. 10 is the same as FIG. 1 to FIG. 5 except for some differences in the steps. The same reference numerals are used in the following description, and detailed explanations of the same parts will be omitted.

[0227] First, according to the first embodiment, a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer are formed on a substrate. The oxide semiconductor film 130 is then divided into islands by a second photolithography process. The oxide semiconductor layers 131 and 132 are then processed into a rectangular shape.

[0228] Next, the oxide semiconductor layers 131 and 132 are dehydrated or dehydrogenated. The temperature of the first heat treatment for hydrogenation is 400° C. or higher and lower than the distortion point of the substrate, preferably 42° C. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. If the temperature is less than 100° C., the heat treatment time is longer than 1 hour. The substrate is placed in an electric furnace, which is one of the processing equipment, and the oxide semiconductor layer is heated in a nitrogen atmosphere. After the heat treatment, the oxide semiconductor layer is prevented from being exposed to the air and from being recontaminated with water or hydrogen. After that, high-purity oxygen gas and high-purity NO gas are added to the same furnace. Or, cool the tank by introducing ultra-dry air (dew point below -40°C, preferably below -60°C). It is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. The purity of oxygen gas or NO gas introduced into the heat treatment device is 6N (99.9999%). or more, preferably 7N (99.99999%) or more (i.e., in oxygen gas or N2O gas) It is preferable to keep the impurity concentration in the above range to 1 ppm or less, and preferably 0.1 ppm or less.

[0229] The heat treatment device is not limited to an electric furnace, and may be, for example, a GRTA (Gas Rapid Th thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Using RTA (Rapid Thermal Anneal) equipment such as LRTA devices can be used with halogen lamps, metal halide lamps, xenon Arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure mercury lamps, etc. This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp. TA devices use heat conduction or radiation from heating elements such as resistance heating elements as well as lamps. The GRTA is a gas processing system that uses high-temperature gas to heat the object to be processed. This is a method of performing heat treatment. The gas used is a rare gas such as argon, or a heating gas such as nitrogen. An inert gas that does not react with the material to be treated is used. Heat treatment may be performed at a temperature of from 0.degree. C. to 750.degree. C. for several minutes.

[0230] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or heat treatment at a temperature between 200℃ and 300℃ in an oxygen gas or N2O gas atmosphere. The theory may also be carried out.

[0231] In addition, the first heat treatment of the oxide semiconductor layers 131 and 132 is performed to process the oxide semiconductor layers into island-shaped oxide semiconductor layers. In that case, the first heat treatment may be performed on the oxide semiconductor film 130 before the first heat treatment. The substrate is then removed from the heating apparatus and a photolithography process is carried out.

[0232] By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, and thus a high resistance As a result, the oxide semiconductor layers 168 and 118 are entirely i-type. do.

[0233] Next, a resist pattern is formed on the oxide semiconductor layers 168 and 118 by a third photolithography process. A mask is formed and selectively etched to form a source electrode layer and a drain electrode layer. Then, the oxide insulating film 107 is formed by a sputtering method.

[0234] Next, in order to reduce the variation in the electrical characteristics of the thin-film transistors, Alternatively, heat treatment (preferably at 150°C or higher and lower than 350°C) is performed under a nitrogen gas atmosphere. For example, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0235] A resist mask is formed by a fourth photolithography process, and selective etching is performed. The first terminal 121, the conductive layer 162, and the drain electrode layer are formed on the gate insulating layer and the oxide insulating layer. 105b, a contact hole reaching the second terminal 122 is formed. After forming the film, a resist mask is formed by a fifth photolithography process, and selective The pixel electrode layer 110, the conductive layer 111, the terminal electrode 128, and the terminal electrode 12 9. Form the wiring layer 145.

[0236] In this embodiment, the first terminal 121 and the terminal electrode 128 are connected via the connection electrode 120. In this example, the drain electrode layer 165b and the conductive layer 162 are directly connected to each other without using a wiring. This is done via the line layer 145.

[0237] In the capacitance section, the capacitance wiring 108, the gate insulating layer 102, the source electrode layer and the drain The metal conductive layer, the oxide insulating film 107, and the pixel electrode layer 110 are formed in the same process as the pixel electrode layer. A capacitor 148 is formed from a laminated layer.

[0238] By the above steps, the thin film transistor 183 is formed in the driver circuit portion and the pixel portion is formed on the same substrate. A thin film transistor 173 can be fabricated on the substrate 172 .

[0239] As in the first embodiment, the liquid crystal layer 192 is sandwiched between the opposing substrates 190. A liquid crystal display device having the above structure is manufactured (see FIG. 10).

[0240] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0241] (Embodiment 6) In this embodiment, at least a part of the driver circuit and a thin film transistor to be disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0242] The thin film transistor disposed in the pixel portion is formed according to any one of the first to fifth embodiments. Since the thin film transistors shown in the first to fifth embodiments are n-channel TFTs, the driver circuit Of these, a part of the driver circuit that can be configured with n-channel TFTs is a thin-film transistor in the pixel area. It is formed on the same substrate as the resistor.

[0243] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 includes a signal line driver circuit 5303 and a signal line driver circuit 5304. is arranged extending from a signal line driver circuit 5304, and a plurality of scanning lines are arranged in a first scanning line driver circuit The scanning lines and the signal line driver circuit 5303 are arranged. At the intersections of the lines, pixels each having a display element are arranged in a matrix. The display device substrate 5300 is a flexible printed circuit board (FPC). It is connected to a timing control circuit 5305 (also called a controller or control IC) via a connection part such as The NI 8110 is connected to the

[0244] In FIG. 12A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of external components such as drive circuits, and therefore reduces costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, and the reliability and yield can be improved.

[0245] The timing control circuit 5305 is, for example, A first scanning line driving circuit start signal (GSP1), a scanning line driving circuit clock signal The timing control circuit 5305 also supplies the second scanning line driving circuit (GCLK1). For example, a start signal for the second scanning line driving circuit (GSP2) (S It supplies the clock signal (GCLK2) for the scanning line driver circuit. The timing control circuit 5305 supplies a start signal for the signal line driver circuit 5304 to the signal line driver circuit. (SSP), clock signal for signal line driver circuit (SCLK), data for video signal (DAT A) (also called video signal), and latch signal (LAT). The clock signal may be a plurality of clock signals with different periods, or may be an inverted clock signal. The first scanning line driving circuit may be supplied with the signal (CKB). It is possible to omit either the second scanning line driver circuit 5302 or the second scanning line driver circuit 5303.

[0246] In FIG. 12B, a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302, The second scanning line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to its structure, the field effect mobility is smaller than that of a transistor using a single crystal semiconductor. The driving circuit formed on the substrate 5300 can be configured by the thin film transistor. Therefore, it is possible to increase the size of the display device, reduce the cost, and improve the yield. do.

[0247] The thin film transistors described in Embodiments 1 to 5 are n-channel TFTs. 3(A) and 13(B) show the configuration and operation of a signal line driver circuit configured with n-channel TFTs. An example will be given below.

[0248] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 includes switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a A plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) are provided. The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example will be explained.

[0249] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are respectively connected to the wiring 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0250] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , or high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in sequence.

[0251] The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have a function of controlling whether or not potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k The thin film transistor 56 has a function of supplying the potential to the signal lines S1 to Sk. Each of 03_1 to 5603_k has a function as a switch.

[0252] In addition, the wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal that

[0253] Next, the operation of the signal line driver circuit of FIG. 13(A) will be described with reference to the timing chart of FIG. 13(B). FIG. 13B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. These are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is a period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0254] In the drawings of the present embodiment, the signal waveforms of the components are not rounded for clarity. Therefore, the scale may not necessarily be limited to the actual scale. It should be noted that

[0255] During the period T1 to the period TN, the shift register 5601 outputs an H-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. Since 5603_1 to 5603_k are turned on, wiring 5604_1 to 5604_k and signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to a selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, Then, the video signal data (DATA) is sent to the pixels in the selected row in order of k columns. It will be written.

[0256] As described above, video signal data (DATA) is written to the pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written more quickly. This can prevent under-crowding.

[0257] The shift register 5601 and the switching circuit 5602 may be the same as those in the first embodiment. It is possible to use a circuit composed of thin film transistors shown in the above to 5. In this case, All the transistors in the soft resistor 5601 are of N-channel type. It is possible.

[0258] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be described with reference to FIG. 14 and FIG. 15.

[0259] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal ( A selection signal is generated by inputting a clock (CLK) and a start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scan line. The gate electrodes of the transistors of the pixels for one line are connected to the scanning line. Since the transistors of the pixels in one line must be turned on at the same time, a buffer The resistor used is capable of passing a large current.

[0260] The shift register includes a first pulse output circuit 10_1 to an N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 14(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is output from a third wiring 13, and a fourth clock signal CK4 is output from a fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the path (called the previous signal OUT(n-1)) (n is a natural number between 2 and N) is input. In addition, in the first pulse output circuit 10_1, the third pulse output circuit 1 Similarly, the signal from the n-th pulse output circuit 10_n in the second stage or later is input. is a signal from the (n+2)th pulse output circuit 10_(n+2) two stages later (later stage signal O Therefore, the pulse output circuit of each stage outputs the following / or a first output signal OUT(1) (SR ) to OUT(N)(SR), a second output signal (OUT( 1) to OUT(N) are output. As shown in FIG. 14(A), the shift register Since the last two stages of the A second start pulse SP2 and a third start pulse SP3 are separately input. It is sufficient to complete it.

[0261] The clock signal (CK) goes between H and L levels (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are The fourth clock signal (CK4) is delayed by 1 / 4 cycle in sequence. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is sent to the GCL It is sometimes called K or SCLK, but here we will use CK as the explanation.

[0262] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to The fourth wiring 14 is electrically connected to the fourth wiring 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third wiring 13. The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The third input terminal 23 is electrically connected to the fourth wiring 14. There are.

[0263] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 14(B)). In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 22, a second clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the second input terminal 24. A third clock signal CK3 is input to the input terminal 23 of the second clock CLK1, and a start signal CK4 is input to the fourth input terminal 24 of the third clock CLK2. A pulse is input, the next stage signal OUT(3) is input to the fifth input terminal 25, and the first output A first output signal OUT(1)(SR) is output from a terminal 26, and a second output signal OUT(1)(SR) is output from a second output terminal 27. The second output signal OUT(1) is output.

[0264] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are each a three-terminal thin-film transistor. In addition to TFTs (also called Thin Film Transistors), The four-terminal thin film transistor described in the above embodiment can be used. An equivalent circuit of the four-terminal thin film transistor 28 described in the above embodiment is shown in FIG. In this specification, a thin film transistor has two gate electrodes via a semiconductor layer. In this case, the gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is called the upper gate electrode. The upper electrode is also called the upper gate electrode.

[0265] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor in which an oxide semiconductor is used for a semiconductor layer including a channel formation region, A configuration capable of controlling the threshold voltage is preferable. The threshold voltage of 8 is set by controlling the potential of the upper and / or lower gate electrodes. It is possible to control the value to a desired value.

[0266] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. 14(B) will be described with reference to FIG. This is explained in (D).

[0267] The pulse output circuit shown in FIG. 14(D) includes a first transistor 31 to a thirteenth transistor. The first input terminal 21 to the fifth input terminal 25, In addition to the first output terminal 26 and the second output terminal 27, a power supply to which a first high power supply potential VDD is supplied is provided. A power supply line 51, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied. A signal is supplied to the first transistor 31 to the thirteenth transistor 43 from a power supply line 53 connected to the The power supply potential is supplied to each of the power supply lines. The first power supply potential VDD is a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VC C is a potential higher than the third power supply potential VSS. The fourth clock signal (CK4) is a signal that alternates between H and L levels at regular intervals. When it is at H level, it is VDD, and when it is at L level, it is VSS. By making the potential VDD higher than the potential VCC of the power supply line 52, the operation is not affected. The potential applied to the gate electrode of the transistor can be kept low without This reduces the shift in the threshold voltage of the first transistor and suppresses deterioration. Among the transistors 31 to 43, the first transistor 31 and the sixth transistor The transistors 36 to 9 are preferably four-terminal thin film transistors. The first transistor 31 and the sixth to ninth transistors 36 to 39 are preferably The operation of the transistor is to set the potential of the node to which either the source or drain electrode is connected to the gate A transistor that requires switching by a control signal from an electrode, and has a gate electrode Fast response to input control signals (sharp rise in on-current) This is a transistor that can reduce malfunctions in the output circuit. By using a thin-film transistor, the threshold voltage can be controlled, making malfunctions less likely. It is possible to provide a pulse output circuit that can reduce the

[0268] In FIG. 14D, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; (the lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal a gate electrode electrically connected to the first terminal of the ninth transistor 39 and a gate electrode electrically connected to the first terminal of the fourth transistor The third transistor 33 is electrically connected to the gate electrode of the first terminal The first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53, The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate of the second transistor 32. The electrode of the fourth transistor 34 is electrically connected to the gate electrode of the fourth transistor 34. The sixth transistor 36 has a first terminal electrically connected to the power supply line 52, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 33. The gate electrode of the transistor 34 is electrically connected to the gate electrode of the transistor 34. The seventh transistor (the gate electrode of the seventh transistor) is electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode (a lower gate electrode and an upper gate electrode) electrically connected to the second terminal of the is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrodes (the lower gate electrode and the upper gate electrode) are connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the second transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to The gate electrodes (the lower gate electrode and the upper gate electrode) are electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 2. 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. 41 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27. The gate electrodes of the second transistor 32 and the fourth transistor The twelfth transistor 42 is electrically connected to the gate electrode of the first terminal of the transistor 34. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 5 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode The seventh transistor 37 has a gate electrode (lower gate electrode and upper gate electrode) are electrically connected.

[0269] In FIG. 14D, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor The connection point of the gate electrode of the ninth transistor 40 and the second terminal of the ninth transistor 39 is defined as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, The second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is a node Let's call it B.

[0270] FIG. 15(A) shows the pulse output circuit described in FIG. 14(D) as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and a signal input to or output from a second output terminal 27.

[0271] Specifically, a first clock signal CK1 is input to the first input terminal 21, and A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse is input to the fourth input terminal 24, and a clock signal CK3 is input to the fifth input terminal The next stage signal OUT(3) is input to the first output terminal 25, and the first output signal OUT (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. will be done.

[0272] A thin film transistor is defined as a transistor having at least three elements including a gate, a drain, and a source. An element having a terminal. A channel forming region is formed in the region overlapping with the gate. By controlling the potential of the gate, the drain is The current flowing between the drain and the source can be controlled. Since it depends on the structure and operating conditions of the thin film transistor, it is difficult to know which is the source or drain. Therefore, it is difficult to determine whether the region that functions as the source and drain is a In some cases, the regions are not called the source or drain. These may be referred to as the first terminal and the second terminal.

[0273] In FIG. 14(D) and FIG. 15(A), node A is put into a floating state, and the boot A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0274] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 15(B) corresponds to a vertical blanking period, and the period 62 corresponds to a gate selection period. do.

[0275] As shown in FIG. 15A, the ninth transistor has a gate to which the second power supply potential VCC is applied. By providing the transistor 39, the following can be achieved before and after the bootstrap operation: There are such advantages.

[0276] In the absence of the ninth transistor 39, the gate electrode of which is applied with the second power supply potential VCC, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes higher than the first power supply potential VDD. Then, the source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, between the gate and the source, between the gate and the drain In both cases, a large bias voltage is applied, which places a large stress on the transistor. Therefore, the ninth power supply potential VCC is applied to the gate electrode. By providing the transistor 39, the voltage of the node A is increased by the bootstrap operation. The potential of the second terminal of the first transistor 31 is increased, but the potential of the second terminal of the first transistor 31 is not increased. That is, by providing the ninth transistor 39, It is possible to reduce the value of the negative bias voltage applied between the gate and source of the transistor 31. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the stress-induced Deterioration of the first transistor 31 can be suppressed.

[0277] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The transistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0278] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and Because it is possible to increase the field effect mobility and reduce the degree of degradation. In addition, a transistor using an oxide semiconductor can be used as an Compared to transistors using amorphous silicon, a higher potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line, and the wiring between the circuits is Since the number of power supply lines can be reduced, the circuit can be made more compact.

[0279] The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 a clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38; The input electrodes (lower gate electrode and upper gate electrode) are supplied with a second input terminal 22. The clock signal is applied to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode). A clock signal is supplied to the gate electrode of the eighth transistor by the second input terminal 22. The gate electrodes of the gate electrodes of the first input terminal 23 are connected to the gate electrodes of the second input terminal 23. Therefore, the same effect can be obtained by switching the wiring so that the clock signal is supplied. In the shift register shown in FIG. The seventh transistor 37 is turned off, and the eighth transistor 38 is turned on. The seventh transistor 37 is turned off, and the eighth transistor 38 is turned on. When the power supply 38 is turned off, the second input terminal 22 and the third input terminal 23 are turned on. The voltage drop at node B is applied to the gate of the seventh transistor 37. 2 due to a drop in the potential of the gate electrode of the eighth transistor 38 and a drop in the potential of the gate electrode of the eighth transistor 39. On the other hand, in the shift register shown in FIG. The seventh transistor 37 and the eighth transistor 38 are both in an on state. is on, the eighth transistor 38 is off, and then the seventh transistor 37 is off. By turning off the eighth transistor 38, the second input terminal 22 and The voltage drop at the node B caused by the voltage drop at the input terminal 23 of the third transistor is The potential of the gate electrode of the transistor 38 can be reduced to one time. The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 are connected to the third A clock signal is supplied from the input terminal 23, and the gate electrode (lower A clock signal is supplied to the lower gate electrode and the upper gate electrode from a second input terminal 22. This is because the number of times the potential of node B changes is reduced. This is because noise can be reduced.

[0280] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are held at the L level. By configuring the node B to periodically receive a high-level signal during this period, It is possible to suppress malfunction of the output circuit.

[0281] (Embodiment 7) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. It is possible to manufacture a semiconductor device (also called a display device) having a display function. The transistors and part or the entire driver circuit are integrated on the same substrate as the pixel section, An on-panel can be formed.

[0282] The display device includes a display element. A liquid crystal element (also called a liquid crystal display element) is used as the display element. In addition, displays that change contrast electrically, such as electronic ink, can be used. A medium can also be applied.

[0283] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above is mounted. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is The element substrate is provided with a means for supplying a current to the display element in each of the plurality of pixels. The display element may be in a state where only the pixel electrodes of the display element are formed, or a conductive film that becomes the pixel electrodes may be formed. may be in a state after the formation of a film and before etching to form a pixel electrode, All forms apply.

[0284] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0285] The appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device, will be described with reference to FIG. 16(A1) and 16(A2) show thin film transistors 4010 and 4011 and a liquid crystal display. The element 4013 is disposed between the first substrate 4001 and the second substrate 4006 by a sealant 4005. FIG. 16(B) is a plan view of the panel sealed by the above method. Equivalent to the cross-sectional view at -N.

[0286] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0287] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 16A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0288] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 16B, the thin film transistor included in the pixel portion 4002 A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The protective insulating layer 4020 and the protective insulating layer 4021 are formed on the thin film transistors 4010 and 4011. 021 is provided.

[0289] The thin film transistors 4010 and 4011 each include the oxide semiconductor layer described in any of Embodiments 1 to 5. Thin film transistors with high reliability, including thin film transistors for driving circuits, can be used. The transistor 4011 may be the thin film transistor 180 or 181 shown in any one of the first to fifth embodiments. 182, 183, the thin film transistor 4010 for the pixel is the thin film transistor 170 , 171, 172, and 173 can be used. The transistors 4010 and 4011 are n-channel thin film transistors.

[0290] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the gate insulating film at a position overlapping the channel formation region of the nitride semiconductor layer, In addition, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0291] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0292] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Room can be used.

[0293] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line arranged on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the counter electrode layer 40 to the conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0294] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. Since the liquid crystal display is optically isotropic, no alignment treatment is required, and the viewing angle dependency is small.

[0295] In addition to the transmission type liquid crystal display device, the present invention can also be applied to a semi-transmission type liquid crystal display device.

[0296] In addition, in liquid crystal display devices, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and a colored layer (color In this example, the polarizing plate is placed on the substrate in the order of the filter and the electrode layer used for the display element. The laminated structure of the polarizing plate and the colored layer is not limited to the embodiment, and may be provided on the polarizing side. The setting may be appropriately determined depending on the materials of the plate and the colored layer and the manufacturing process conditions. A light-shielding film that functions as a black matrix may be provided.

[0297] In addition, an insulating layer 4020 is formed on the thin film transistors 4010 and 4011 . The insulating layer 4020 is formed using a material and a method similar to those of the oxide insulating film 107 described in Embodiment 1. However, in this embodiment, the insulating layer 4020 is formed of silicon oxide by a sputtering method. A bare film is formed.

[0298] A protective insulating layer may be formed over the insulating layer 4020. Then, a silicon nitride film is formed by RF sputtering (not shown).

[0299] In addition, an insulating layer 4021 is formed as a planarization insulating film. The planarization insulating layer 109 may be formed of the same material and by the same method as in the embodiment 2. Heat-resistant organic materials such as polyimide, benzocyclobutene, polyamide, and epoxy In addition to the above organic materials, low-k materials, silicon materials, etc. can be used. Use oxysilane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by laminating a plurality of insulating films made of these materials, the insulating layer 40 can be formed. 21 may be formed.

[0300] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a S OG method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen lean printing, offset printing, etc.), doctor knife, roll coater, curtain coater A knife coater or the like can be used. By using the same as the mold, a semiconductor device can be manufactured efficiently.

[0301] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Light-transmitting conductive materials such as indium zinc oxide and indium tin oxide doped with silicon oxide Conductive materials can be used.

[0302] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0303] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0304] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0305] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layer and the drain electrode layer of the thin film transistor 4011. The gate electrode layer is formed of the same conductive film.

[0306] In FIG. 16, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. The embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0307] FIG. 17 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed in this specification. 1 shows an example in which a liquid crystal display module is configured as a semiconductor device.

[0308] FIG. 17 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604 and a colored layer 2605 are arranged to form a display area. is necessary for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. The colored layers are arranged corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. A wiring board 2609 is connected to the wiring circuit section 2608 of the TFT board 2600, and the controller The LCD has external circuits such as a filter circuit and a power supply circuit. The layers may be laminated with a retardation plate interposed therebetween.

[0309] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0310] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0311] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is. (Embodiment 8)

[0312] The semiconductor device disclosed in the present specification is flexible and can be used for electronic books (electronic Children's books, posters, advertisements inside trains and other vehicles, various cards such as credit cards The present invention can be applied to the display unit in an electronic device, etc. An example of the electronic device is shown in FIG.

[0313] FIG. 18 shows an example of an electronic book. For example, an electronic book 2700 includes a housing 2701 and The housing 2701 and the housing 2703 are The device is integrated with an axis portion 2711, and can be opened and closed with the axis portion 2711 as an axis. This configuration makes it possible to operate like a paper book.

[0314] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 18) and An image can be displayed on the display unit 2707 in FIG.

[0315] FIG. 18 shows an example in which the housing 2701 is provided with an operation unit and the like. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a touch panel, a touch screen, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. This is also fine.

[0316] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0317] (Embodiment 9) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames; mobile phones (also called mobile phones or mobile phone devices); Examples include game machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. do.

[0318] FIG. 19A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this embodiment, the housing 9601 is supported by a stand 9605. The figure shows a configuration in which

[0319] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0320] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0321] FIG. 19B shows an example of a digital photo frame. In the frame 9700, a display unit 9703 is incorporated in a housing 9701. 3 is capable of displaying various images, for example images taken with a digital camera. By displaying data, it can function just like a normal photo frame.

[0322] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The captured image data can be displayed on the display portion 9703 .

[0323] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0324] FIG. 20(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 20(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and may be at least as described in the present specification. The present invention is not limited to the above, and may be applied to any configuration having the semiconductor device disclosed in the above and other auxiliary equipment. The portable game machine shown in FIG. 20(A) can be used to play a game recorded on a recording medium. The function of reading out the program or data and displaying it on the display unit, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 20(A) has the following functions: The functions are not limited to these, and various functions can be provided.

[0325] FIG. 20B shows an example of a slot machine, which is a large-scale gaming machine. Slot Machine 9 The slot machine 900 includes a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to the above, and may be configured to include at least the semiconductor device disclosed in the present specification. The configuration may include appropriate auxiliary equipment.

[0326] FIG. 21A is a perspective view showing an example of a portable computer.

[0327] The portable computer of FIG. 21(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display unit 9303 and a keyboard. The lower housing 9302 having the base 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to type on the keyboard, the hinge unit needs to be opened. The user can perform input operations by looking at the display portion 9303.

[0328] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the touch panel. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the USB communication standard is inserted. There are.

[0329] The upper housing 9301 further includes a display unit 93 that can be slid and stored inside the upper housing 9301. 07, it is possible to realize a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display unit.

[0330] The display portion 9303 or the foldable display portion 9307 is a video display device such as a liquid crystal display panel. is used.

[0331] The portable computer shown in FIG. 21A is configured with a receiver and the like, and is also a television. It is possible to receive a broadcast and display the video on the display portion 9303 or the display portion 9307. In addition, the hinge unit connecting the upper housing 9301 and the lower housing 9302 is kept in the closed state. Also, the display unit 9307 can be slid to expose the entire screen, and the user can adjust the screen angle. You can also watch TV broadcasts. In this case, the hinge unit is opened and the display unit 9 303 is not displayed, and only the circuit for displaying the TV broadcast is started. Portable computers with minimal power consumption and limited battery capacity It is useful in.

[0332] FIG. 21(B) shows a portable electronic device that can be worn on the user's arm like a wristwatch. FIG. 13 is a perspective view showing an example of a story.

[0333] This mobile phone is a main body having at least a communication device having a telephone function and a battery. A band part 9204 for attaching the body to the arm, and an adjustment part for adjusting the fastening state of the band part to the arm It is composed of a joint part 9205, a display part 9201, a speaker 9207, and a microphone 9208. There are.

[0334] The main body also has an operation switch 9203, which serves as a power input switch and a display switching switch. In addition to the camera switch and the camera start switch, there are also other buttons, such as a button that starts an Internet program. Each function can be associated with a specific function, such as being started.

[0335] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the mobile phone. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. In FIG. 21(B), a display button 9202 is shown on a display unit 9201. Input can be made by touching the screen with a finger or other object.

[0336] The main body also includes an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. The camera unit 9206 has a step. Note that the camera unit does not necessarily have to be provided.

[0337] The mobile phone shown in FIG. 21(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in a memory or the like. As a configuration equipped with a storage device, television broadcasts can be recorded in the memory. The mobile phone shown in FIG. 2 may have a function for collecting location information such as GPS.

[0338] The display unit 9201 is an image display device such as a liquid crystal display panel. Since a mobile phone is small and lightweight, the battery capacity is limited. The display device used in 1 preferably uses a panel that can be driven with low power consumption.

[0339] Although FIG. 21B illustrates an electronic device that is worn on the arm, the electronic device is not limited to this. It is sufficient that the device has a shape that can be carried around.

[0340] (Embodiment 10) In this embodiment mode, the thin film transistor shown in any one of Embodiments 1 to 5 is used as one mode of a semiconductor device. An example of a display device having a star will be described with reference to FIGS. An example of a liquid crystal display device using a liquid crystal element as an element will be described with reference to FIGS. The TFTs 628 and 629 used in the liquid crystal display devices of FIGS. The thin film transistor shown in FIG. 5 can be applied to the thin film transistor shown in FIG. This thin film transistor has excellent electrical characteristics and high reliability and can be easily fabricated.

[0341] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. VA type is a type of method for controlling the arrangement of liquid crystal molecules in an LCD panel, and when voltage is applied When no light is applied, the liquid crystal molecules are oriented vertically to the panel surface. In particular, pixels are divided into several regions (subpixels), each of which has a different This is called multi-domain or multi-domain. In the following description, a liquid crystal display device in which a multi-domain design is taken into consideration will be described. explain.

[0342] 23 and 24 show a pixel electrode and a counter electrode, respectively. FIG. 2 is a plan view of the substrate side on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. FIG. 22 shows the structure. FIG. 24 shows a plan view of the substrate on which the counter electrode is formed. The following description will be given with reference to these figures.

[0343] FIG. 22 shows a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode layer 640 and the like are formed is laminated on the counter substrate 601. 4 shows the state in which liquid crystal has been injected.

[0344] Although not shown, a first colored film, a second colored film, and a third colored film are formed on the opposing substrate 601 at positions where spacers are to be formed. The second colored film, the third colored film, and the counter electrode layer 640 are formed. The height of the protrusion 644 for controlling the crystal orientation and the spacer are made different. An alignment film 648 is formed on the substrate 24, and an alignment film 646 is formed on the counter electrode layer 640. A liquid crystal layer 650 is formed between them.

[0345] The spacers may be columnar or bead spacers. In the case of a photo-sensitive element, it may be formed on the pixel electrode layer 624 formed on the substrate 600 .

[0346] On the substrate 600, a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 6 The pixel electrode layer 624 includes a TFT 628, a wiring 616, and a storage capacitor 630. The contacts are formed through an insulating film 620 that covers the insulating film 30 and a third insulating film 622 that covers the insulating film 620. A contact hole 623 is connected to the wiring 618. The TFT 628 is the same as that shown in the first to fifth embodiments. A thin film transistor can be appropriately used.

[0347] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been made.

[0348] FIG. 23 shows a structure on a substrate 600. The pixel electrode layer 624 is made of the material shown in the embodiment mode 1. The pixel electrode layer 624 is provided with a slit 625. The slit 625 is formed by This is for controlling the orientation.

[0349] The TFT 629 and the pixel electrode layer 626 and the storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode layer 624, and the storage capacitor portion 630 can be formed in the same manner. Both the TFT 628 and the TFT 629 are connected to the wiring 616. The pixel of the panel is composed of pixel electrode layer 624 and pixel electrode layer 626. The pixel electrode layer 624 and the pixel electrode layer 626 are sub-pixels.

[0350] The structure on the opposing substrate side is shown in FIG. 24. The opposing electrode layer 640 is made of the same material as the pixel electrode layer 624. On the counter electrode layer 640, protrusions 6 for controlling the alignment of liquid crystal are preferably formed. 44 has been formed.

[0351] The equivalent circuit of this pixel structure is shown in Figure 25. TFT628 and TFT629 both have gate The line 602 is connected to the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected to each other. By making the positions different, the operations of the liquid crystal elements 651 and 652 can be made different. That is, the potentials of the capacitance wiring 604 and the capacitance wiring 605 are individually controlled. The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0352] When a voltage is applied to the pixel electrode layer 624 having the slit 625, The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (diagonal electric field). By arranging the 644 in an alternating pattern, a diagonal electric field is effectively generated, and the liquid crystal By controlling the orientation, the direction in which the liquid crystal is oriented can be made to differ depending on the location. The viewing angle of the LCD panel is expanded by creating a multi-domain structure.

[0353] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 26 to 29. do.

[0354] 26 and 27 show the pixel structure of a VA type liquid crystal display panel. FIG. 26 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure.

[0355] In this pixel structure, one pixel has multiple pixel electrodes, each of which is connected to a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independent. The device has a configuration for controlling the above.

[0356] The pixel electrode layer 624 is connected to the TFT 628 through the contact hole 623 by the wiring 618. In addition, the pixel electrode layer 626 is connected to the wiring 619 through the contact hole 627. The gate wiring 602 of the TFT 628 and the gate The wiring 603 is separated so that different gate signals can be applied. The wiring 616 functioning as a data line is used in common for the TFT 628 and the TFT 629. The TFT 628 and the TFT 629 are the thin film transistors shown in the first, second, fifth and sixth embodiments. can be used appropriately.

[0357] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes and are separated by a slit 625. The pixel electrode layer 626 is arranged so as to surround the outside of the pixel electrode layer 624 that spreads in a V shape. A voltage is applied to the pixel electrode layer 624 and the pixel electrode layer 626 through the TFT 628. The alignment of the liquid crystal is controlled by changing the polarity of the TFT 629. The equivalent circuit is shown in FIG. 29. The TFT 628 is connected to the gate wiring 602. The TFT 628 and the TFT 629 are both connected to the wiring 616. To give different gate signals to the gate wiring 602 and the gate wiring 603, Therefore, the operation of the liquid crystal element 651 and the liquid crystal element 652 can be made different. By controlling the operation of T628 and TFT629 individually, the liquid crystal element 651 and the liquid crystal element The orientation of the liquid crystals in 652 can be precisely controlled to widen the viewing angle.

[0358] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 28 shows the structure of the opposing substrate side. The opposing electrode layer 640 is shared between different pixels. The electrode is connected to the pixel electrode, but a slit 641 is formed therein. The polar layer 624 and the slits 625 on the pixel electrode layer 626 side are arranged so as to interdigitate with each other. This makes it possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. In this case, the orientation direction of the liquid crystal can be varied depending on the location, thereby widening the viewing angle. In FIG. 28, a pixel electrode layer 624 and a pixel electrode 625 are formed on the substrate 600 shown in FIG. The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are shown by dashed lines. are arranged overlapping each other.

[0359] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626. An alignment film 646 is also formed on the layer 640. The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are formed. The pixel electrode layer 626 and the liquid crystal layer 627 are overlapped to form a first liquid crystal element. The layer 650 and the counter electrode layer 640 overlap each other to form a second liquid crystal element. The pixel structure of the display panel described in FIG. 26 to FIG. 29 has a first liquid crystal element and a second liquid crystal element in one pixel. The display has a multi-domain structure in which crystal elements are provided.

[0360] Next, we will explain the in-plane switching type liquid crystal display device. In the in-plane switching type, This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be expanded to approximately 180 degrees. A liquid crystal display device to be used will be described.

[0361] FIG. 30 shows a structure in which an electrode layer 607, a TFT 628, and a pixel electrode layer 624 connected to the TFT 628 are formed. The substrate 600 and the opposing substrate 601 are overlapped and liquid crystal is injected. A colored film 636, a flattening film 637, etc. are formed on the opposing substrate 601. No counter electrode is disposed on the substrate 601 side. A liquid crystal layer 650 is formed via an alignment film 646 and an alignment film 648 .

[0362] On the substrate 600, an electrode layer 607, a capacitance wiring 604 connected to the electrode layer 607, and a T The capacitance wiring 604 is formed at the same time as the gate wiring 602 of the TFT 628. The TFT 628 can be formed using the thin film transistor shown in any one of the first to fifth embodiments. The electrode layer 607 may be the pixel electrode layer described in any of the embodiments 1 to 5. The electrode layer 607 may be formed of a similar material. A gate insulating film 606 is formed on the electrode layer 607 and the capacitance wiring 604. can be.

[0363] The wiring 616 and the wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in a liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source region or drain region of the TFT 628 is connected to the source and drain regions. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0364] An insulating film 620 is formed on the wiring 616 and the wiring 618. A pixel electrode connected to the wiring 618 is formed through a contact hole 623 formed in the insulating film 620. The pixel electrode layer 624 is the same as the pixel electrode layer shown in any of the embodiments 1 to 5. It is formed using the same material.

[0365] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed by inserting a gate insulating film 606 between the electrode layer 607 and the pixel electrode layer 624. The method is thus formed.

[0366] 31 is a plan view showing the configuration of a pixel electrode. The surface structure is shown in Figure 30. A slit 625 is arranged in the pixel electrode layer 624. The liquid crystal alignment layer 625 is for controlling the alignment of the liquid crystal. In this case, the electric field is applied to the electrode layer 607 and The gate insulating layer 607 is located between the pixel electrode layer 624 and the pixel electrode layer 624. A film 606 is disposed, and the thickness of the gate insulating film 606 is 50 nm or more and 200 nm or less, Since the thickness of the liquid crystal layer is sufficiently thin compared with the thickness of the liquid crystal layer, which is 2 μm or more and 10 μm or less, the thickness of the substrate 60 is substantially An electric field is generated in a direction parallel to 0 (horizontal direction). This electric field controls the alignment of the liquid crystal. The liquid crystal molecules are rotated horizontally by using an electric field in a direction approximately parallel to the substrate. Since the crystal molecules are horizontal in any state, the effect of contrast due to the viewing angle is small. In addition, the electrode layer 607 and the pixel electrode layer 624 are both light-transmitting electrodes. Since the polarity is high, the aperture ratio can be improved.

[0367] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0368] Figures 32 and 33 show the pixel structure of an IPS type liquid crystal display device. Figure 33 is a plan view. FIG. 32 shows a cross-sectional structure corresponding to the cutting line VW shown in the figure.

[0369] FIG. 32 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, The opposing substrate 601 is overlapped and liquid crystal is injected. A coloring film 636, a planarizing film 637, etc. are formed. The pixel electrodes are disposed on the substrate 600 side. Therefore, no counter electrode is provided on the counter substrate 601 side. A liquid crystal layer 650 is formed between the first and second alignment films 646 and 648 .

[0370] A common potential line 609 and a TFT 628 are formed on the substrate 600. 9 can be formed simultaneously with the gate wiring 602 of the TFT 628. For this, the thin film transistors described in any of Embodiments 1 to 5 can be applied.

[0371] The wiring 616 and the wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in a liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source region or drain region of the TFT 628 is connected to the source and drain regions. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0372] An insulating film 620 is formed on the wiring 616 and the wiring 618. A pixel electrode connected to a wiring 618 through a contact hole 623 formed in the film 620 The pixel electrode layer 624 is formed in the same manner as the pixel electrode layer described in any of the embodiments 1 to 5. As shown in FIG. 33, the pixel electrode layer 624 is formed using the same material. The comb-shaped electrodes formed at the same time as the potential line 609 are formed so as to generate a horizontal electric field. The comb-tooth portion of the electrode layer 624 is alternately interdigitated with the comb-shaped electrode formed at the same time as the common potential line 609. It is formed to fit together.

[0373] When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by this electric field. Rotate the molecules horizontally. In this case, the liquid crystal molecules are horizontal in any state, so the viewing angle This has little effect on contrast, etc., and results in a wider viewing angle.

[0374] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is provided with a gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. The capacitance electrode 615 and the pixel electrode layer 624 are formed through a contact hole 63. It is connected via 3.

[0375] Next, a configuration of a TN type liquid crystal display device will be described.

[0376] Figures 34 and 35 show the pixel structure of a TN type liquid crystal display device. Figure 35 is a plan view. The cross-sectional structure corresponding to the cutting line KL shown in the figure is shown in FIG. The following description will be given with reference to these two figures.

[0377] The pixel electrode layer 624 is formed through a contact hole 623 and a wiring 618 formed in the insulating film 620. The wiring 616 that functions as a data line is connected to the TFT 628 through the The TFT 628 is connected to any one of the TFTs shown in the first to fifth embodiments. It is possible.

[0378] The pixel electrode layer 624 is formed using any of the pixel electrode layers described in Embodiments 1 to 5. The gate wiring 604 can be formed simultaneously with the gate wiring 602 of the TFT 628. A gate insulating film 606 is formed on the wiring 602 and the capacitance wiring 604. A gate insulating film 606 is formed between the capacitance wiring 604 and the capacitance electrode 615. The electrode 615 and the pixel electrode layer 624 are connected via a contact hole 623 .

[0379] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. The liquid crystal layer 650 is provided between the pixel electrode layer 624 and the counter electrode layer 640 with an alignment film 648 and an alignment layer 649. It is formed through a membrane 646 .

[0380] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been made.

[0381] The colored film 636 may be formed on the substrate 600 side. A polarizing plate is attached to the surface opposite to the surface on which the transistors are formed, and a counter substrate 601 A polarizing plate is attached to the surface opposite to the surface on which the counter electrode layer 640 is formed.

[0382] Through the above steps, a liquid crystal display device can be manufactured as a display device.

[0383] (Embodiment 11) In this embodiment mode, another example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. I will explain this in more detail.

[0384] A gate electrode layer is formed on a substrate having an insulating surface (S101 in FIG. 37). The materials are molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, A single layer is made of metallic materials such as neodymium and scandium, or alloy materials mainly composed of these. The film may be formed by laminating or stacking.

[0385] A gate insulating layer is formed on the gate electrode layer (S102 in FIG. 37). A silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, etc. are formed by using a CVD method or a sputtering method. A silicon nitride oxide layer, a silicon oxide layer, or an aluminum oxide layer can be formed as a single layer or a stacked layer. In this embodiment, the gate insulating layer is formed by a plasma CVD method to a thickness of 200 nm or less. A silicon nitride layer is formed.

[0386] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the gate insulating layer. (S103 in FIG. 37). In this embodiment, an In-Ga-Zn-O based oxide semiconductor target Using a 3000-millimeter-wavelength heater, an In-Ga-Zn-O-based oxide semiconductor film is formed by sputtering. .

[0387] Next, the oxide semiconductor film is Then, etching is performed to form island-shaped oxide semiconductor layers (S104 in FIG. 37).

[0388] Next, heat treatment is performed for dehydration or dehydrogenation of the oxide semiconductor layer. The temperature of the heat treatment for the curing is set to 400° C. or higher and lower than 700° C. of the substrate (S105 in FIG. 37). In this embodiment, the heat treatment is performed at 450° C. in a nitrogen atmosphere. The substrate is placed in an electric furnace, which is one of the equipments, and the oxide semiconductor layer is heated in a nitrogen atmosphere. After the heat treatment, the oxide semiconductor layer is not exposed to the air and water or hydrogen is prevented from re-mixing. In this embodiment, the oxide semiconductor layer is dehydrated or dehydrogenated. From the heating temperature T to a temperature that is high enough to prevent water from entering again, use the same furnace. The specimen is cooled slowly in a nitrogen atmosphere until the temperature drops by 100°C below the heating temperature T. Dehydration or dehydration under a rare gas atmosphere such as, but not limited to, helium, neon, or argon Perform elementalization.

[0389] The oxide semiconductor layer is heat-treated at a temperature of 400 to 700°C to remove the oxide This allows hydration and dehydrogenation, preventing subsequent re-impregnation with water (H2O).

[0390] The heat treatment device is not limited to an electric furnace, and may be, for example, a GRTA (Gas Rapid Th thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Using RTA (Rapid Thermal Anneal) equipment such as LRTA devices can be used with halogen lamps, metal halide lamps, xenon Arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure mercury lamps, etc. This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp. TA devices use heat conduction or radiation from heating elements such as resistance heating elements as well as lamps. The GRTA is a gas processing system that uses high-temperature gas to heat the object to be processed. This is a method of performing heat treatment. The gas used is a rare gas such as argon, or a heating gas such as nitrogen. An inert gas that does not react with the material to be treated is used. Heat treatment may be performed at a temperature of from 0.degree. C. to 750.degree. C. for several minutes.

[0391] In the heat treatment for dehydration or dehydrogenation, nitrogen, helium, neon, or argon is used. It is preferable that the rare gas such as argon does not contain water, hydrogen, or the like. In contrast, the dehydration and dehydrogenation heat treatments carried out at 400℃ to 700℃ have a H2O concentration of 20ppm. It is preferable to carry out the process in a nitrogen atmosphere of 0.1 to 1.0 m or less. Alternatively, the nitrogen introduced into the heat treatment device, The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. Preferably, 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, It is preferable that the concentration of the ion exchange resin is 0.1 ppm or less.

[0392] Next, a resist mask formed by a photolithography process is used to mask the gate insulating layer. Removing the necessary portion, an opening (contact hole) is formed in the gate insulating layer (S in FIG. 37). 106).

[0393] Next, a metal conductive film made of a metal material is formed on the oxide semiconductor layer by sputtering or vacuum deposition. is formed.

[0394] The material of the metal conductive film is an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. Alternatively, an alloy film containing the above elements or an alloy film containing a combination of the above elements may be used. The metal conductive film may have a single layer structure or a laminated structure of two or more layers. For example, 2. A single layer structure of aluminum film containing silicon; 3. A titanium film laminated on an aluminum film Layer structure: Ti film, aluminum film layered on top of the Ti film, Ti on top of that In addition, titanium (Ti) and tantalum (T a), Tungsten (W), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), A film, alloy film, or other film made of a single or multiple combinations of elements selected from scandium (Sc) Alternatively, a nitride film may be used.

[0395] When a heat treatment is performed after the metal conductive film is formed, the metal conductive film must have heat resistance to withstand the heat treatment. It is preferable to make the above-mentioned

[0396] Next, a photolithography process is performed to form a resist mask and etch the metal conductive film. The unnecessary portions are removed by etching to form the source electrode layer and the drain electrode layer (S in FIG. 37). 107).

[0397] In order to prevent the oxide semiconductor layer from being removed during etching of the metal conductive film, The materials and etching conditions are adjusted appropriately.

[0398] In this embodiment, a laminate of a Ti film, an Al film, and a Ti film is used as the metal conductive film, and an oxide The semiconductor layer is made of In-Ga-Zn-O oxide and ammonium peroxide is used as the etchant. A mixture of ammonia, water, and hydrogen peroxide is used.

[0399] Next, the target and the substrate are heat-treated in a chamber in which an oxide insulating film is formed (Figure 3 After the heat treatment, the target and the substrate are cooled (S109 in FIG. 37) and then cooled to room temperature. The oxide insulating film is formed (S110 in FIG. 37). The heating temperature is 100° C. or more and 250° C. or less. This can be done as follows.

[0400] The oxide insulating film has a thickness of at least 1 nm (preferably 100 nm to 500 nm). nm or less) sputtering method, etc., which does not mix impurities such as water and hydrogen into the oxide insulating film In this embodiment, the oxide insulating film is formed to a thickness of 30 A silicon oxide film with a thickness of 0 nm is formed by sputtering. The substrate temperature during film formation is set at room temperature or higher. The temperature is set to room temperature in this embodiment. The deposition by the argon method is carried out under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. The reaction can be carried out under an atmosphere of nitrogen (typically argon) and oxygen. A silicon oxide target or a silicon target can be used as the target. Silicon oxide can be formed by sputtering in an oxygen atmosphere using a target. The oxide insulating film formed in contact with the low-resistance oxide semiconductor layer is resistant to moisture and hydrogen. On and OH - It does not contain impurities such as chlorine and has an antibacterial effect that blocks them from entering from the outside. An organic insulating film is used, typically a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or An aluminum oxynitride film or the like is used.

[0401] A protective insulating layer may be further formed on the oxide insulating film. The RF sputtering method is suitable for mass production, so the protection film is This is a preferred method for forming an insulating layer. The protective insulating layer is formed by removing moisture, hydrogen ions, and OH - etc. It uses an inorganic insulating film that does not contain impurities and blocks them from entering from the outside, and nitrides A silicon film, an aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, or the like is used. In this embodiment mode, a silicon nitride film is used as the protective insulating layer.

[0402] The oxide insulating film is formed by sputtering (in an oxygen atmosphere, at room temperature) to a thickness of 100 nm. The base film is used, and the protective insulating layer is deposited by sputtering (under nitrogen and argon atmosphere, at room temperature). The thickness may be 100 nm.

[0403] After the oxide insulating film is formed, the insulating film is heated in an inert gas atmosphere or a nitrogen gas atmosphere. (preferably at 200°C or higher and 400°C or lower, for example at 250°C or higher and 350°C or lower) For example, heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0404] Next, the oxide insulating film and the protective insulating layer are selectively etched to form an opening (S1 in FIG. 37). 11) A planarizing insulating layer may be formed on the protective insulating layer. In some cases, a heat treatment of about 250°C is required during formation of the oxide. After forming the insulating film, the heat treatment can be omitted in an inert gas atmosphere or a nitrogen gas atmosphere. good.

[0405] Next, a light-transmitting conductive film is formed. Indium (In2O3) and indium oxide tin oxide alloy (In2O3-SnO2, IT The transparent film is formed by sputtering or vacuum deposition. As another material for the conductive film, a nitrogen-containing Al-Zn-O-based non-single crystal film, i.e., Al- Zn-ON type non-single crystal film, Zn-O type non-single crystal film containing nitrogen, and A Sn-Zn-O based non-single crystal film may be used. The composition ratio (atomic %) of zinc is 47 atomic % or less, and the composition ratio of aluminum in the non-single crystal film is (atomic%), and the composition ratio (atomic%) of aluminum in the non-single crystal film is The composition ratio (atomic percent) of nitrogen in the material is larger than that in the material containing hydrochloric acid. However, etching of ITO is particularly prone to leaving residues, so Indium oxide-zinc oxide alloy (In2O3-ZnO) can be used to improve workability. good.

[0406] Next, a photolithography process is performed to form a resist mask, and a transparent layer is formed by etching. The unnecessary portion of the conductive film having the resist mask is removed to form a pixel electrode layer and a conductive layer. (S112 in FIG. 37).

[0407] Next, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours ( In this embodiment, the heat treatment is performed at 150° C. for 10 hours. The treatment may be performed by maintaining a constant heating temperature or by heating from room temperature to 100°C to 200°C. The heating to the heating temperature and the cooling from the heating temperature to room temperature may be repeated several times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By performing the heat treatment, the heating time can be shortened. Hydrogen is then taken into the oxide insulating layer, resulting in a normally-off thin film transistor. This makes it possible to improve the reliability of the semiconductor device.

[0408] Through the above steps, thin film transistors are formed in the driver circuit portion and the pixel portion on the same substrate. It can be manufactured.

[0409] As in the first embodiment, the liquid crystal layer is sandwiched between the opposing substrates, and the liquid crystal display of this embodiment is formed. It is possible to create a display device.

[0410] (Embodiment 12) In this embodiment, an example in which an oxide semiconductor layer is surrounded by a nitride insulating film as viewed from a cross section is shown in FIG. FIG. 38 shows a top view of the oxide insulating layer and the edge position thereof, which are different from those shown in FIG. 1. Since the present embodiment is the same except for the difference in configuration, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are provided. The explanation will be omitted.

[0411] The thin film transistor 180 arranged in the driving circuit is a channel etch type thin film transistor. A gate electrode layer 161 and a first insulating film made of a nitride insulating film are formed on a substrate 100 having an insulating surface. The first gate insulating layer 188, the second gate insulating layer 187a made of an oxide insulating film, and the oxide semiconductor The thin film includes a conductor layer 163, a source electrode layer 165a, and a drain electrode layer 165b. The oxide insulating film that covers the transistor 180 and is in contact with the channel formation region of the oxide semiconductor layer 163 is A protective insulating layer 178 is further provided on the oxide insulating layer 177a. The gate electrode layer 161 and the oxide semiconductor layer 177a are formed on the oxide insulating layer 177a. A conductive layer 111 is provided in a position overlapping with the layer 163 .

[0412] The thin film transistor 170 disposed in the pixel portion is a channel etch type thin film transistor. A gate electrode layer 101 and a first layer made of a nitride insulating film are formed on a substrate 100 having an insulating surface. The first gate insulating layer 188, the second gate insulating layer 187b made of an oxide insulating film, and the oxide semiconductor The thin film transistor includes a thin film transistor layer 103, a source electrode layer 105a, and a drain electrode layer 105b. The oxide insulating layer 103 covers the transistor 170 and is in contact with a channel formation region of the oxide semiconductor layer 103. A protective insulating layer 178 is further formed on the oxide insulating layer 177b. A pixel electrode layer 105b is formed on the protective insulating layer 178 and contacts the drain electrode layer 105b. 110 is provided.

[0413] In this embodiment, the gate insulating layer is formed as a gate electrode in the thin film transistors 170 and 180. The nitride insulating film and the oxide insulating film are stacked from the oxide insulating layer side. During the formation, the oxide insulating film of the second gate insulating layer is also selectively removed to expose the nitride insulating film. Process it so that it comes out.

[0414] At least the oxide insulating layers 177a, 177b, the second gate insulating layers 187a, 187b The top surface shape is wider than the top surface shapes of the oxide semiconductor layers 163 and 103. It is preferable that the upper surface shape covers 80 and 170.

[0415] Further, the upper and side surfaces of the oxide insulating layers 177a and 177b are covered, and the first gate insulating layer A protective insulating layer 178 made of a nitride insulating film is formed in contact with the nitride insulating film.

[0416] The protective insulating layer 178 and the first gate insulating layer 188 made of a nitride insulating film are formed by sputtering. Silicon nitride films, silicon oxynitride films, aluminum nitride films obtained by the etching method and plasma CVD method, Moisture, hydrogen ions, and OH - It does not contain impurities such as An inorganic insulating film is used to block these substances from entering from the outside.

[0417] In this embodiment, the oxide semiconductor layer 16 is used as the protective insulating layer 178 made of a nitride insulating film. 3, 103, the upper surface and the side surface are surrounded by the RF sputtering method, and a film having a thickness of 100 nm is formed. A silicon nitride film is provided. A protective insulating layer 178 is formed on the first gate insulating film made of a nitride insulating film. It is configured to be in contact with edge layer 188.

[0418] By forming the structure shown in FIG. 38, the manufacturing process after forming the protective insulating layer 178 made of a nitride insulating film In the process, it is possible to prevent moisture from entering from the outside. For example, even after the device is completed as a liquid crystal display device, it will continue to prevent moisture from entering from the outside for a long period of time. This makes it possible to improve the long-term reliability of the device.

[0419] In the present embodiment, a configuration in which one thin film transistor is surrounded by a nitride insulating film has been shown. However, the present invention is not limited to this, and a configuration in which a plurality of thin film transistors are surrounded by a nitride insulating film may be used. A plurality of thin film transistors in the region may be surrounded by a nitride insulating film. A protective insulating layer 178 and a first gate insulating film 179 are formed so as to surround the periphery of the pixel portion of the active matrix substrate. A region in contact with the insulating layer 188 may be provided.

[0420] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is. [Explanation of symbols]

[0421] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminals 25 Input terminal 26 Output terminal 27 Output terminal 28 Thin-film transistor 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 42 Transistor 43 Transistor 51 Power line 52 Power line 53 Power line 100 Substrates 101 Electrode 102 Gate insulating layer 103 Oxide semiconductor layer 107 Oxide insulating film 108 Capacitance wiring 109 Planarizing insulating layer 110 Pixel electrode layer 111 Conductive layer 116 Channel formation region 118 Contact Hole 119 Contact Hole 120 Connection electrode 121 Terminal 122 Terminal 125 Contact Hole 126 Contact Hole 127 Contact Hole 128 Terminal electrode 129 Terminal electrode 130 Oxide Semiconductor Film 131 Oxide semiconductor layer 133 Oxide Semiconductor Layer 134 Oxide semiconductor layer 137 Resist Mask 138 Oxide Conductive Layer 140 Oxide Conductive Film 142 Oxide conductive layer 143 Oxide Conductive Layer 145 Wiring layer 146 capacity 147 capacity 148 capacity 150 Terminals 151 Terminal 153 Connection electrode 155 Conductive Film 156 Electrode 161 Gate electrode layer 162 Conductive Layer 163 Oxide semiconductor layer 166 Channel Formation Region 168 Oxide semiconductor layer 170 Thin-film transistor 171 Thin-film transistor 172 Thin-film transistor 173 Thin-film transistor 178 Protective Insulation Layer 180 Thin Film Transistor 181 Thin-film transistor 182 Thin-film transistor 183 Thin-film transistor 188 Gate Insulation Layer 190 Opposing substrate 191 Insulating Layer 192 Liquid crystal layer 193 Insulating Layer 194 Counter electrode layer 195 Colored layer 202 Gate insulating layer 203 Protective insulation layer 206 Common electrode layer 210 Common potential line 220 Thin-film transistor 227 Pixel electrode layer 402 Gate insulating layer 600 Substrates 601 Opposing substrate 602 Gate wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606 Gate insulating film 607 Electrode layer 609 Common potential line 615 Capacitive electrode 616 Wiring 618 Wiring 619 Wiring 620 Insulating film 622 Insulating film 623 Contact Hole 624 Pixel electrode layer 625 Slit 626 Pixel electrode layer 627 Contact Hole 628 TFT 629 TFT 630 Holding capacity section 631 Holding capacity section 633 Contact Hole 636 Colored film 637 Planarization film 640 Counter electrode layer 641 Slit 644 Protrusion 646 Orientation Film 648 Orientation Film 650 Liquid crystal layer 651 Liquid crystal element 652 Liquid crystal element 104a Oxide conductive layer 104b Oxide conductive layer 105a Source electrode layer 105b Drain electrode layer 117a High resistance source region 117b High-resistance drain region 135a Resist mask 136a Resist mask 164a Oxide conductive layer 164b Oxide conductive layer 165a Source electrode layer 165b Drain electrode layer 167a High resistance source region 167b High-resistance drain region 177a Oxide insulating layer 177b Oxide insulating layer 187a Gate insulating layer 187b Gate insulating layer 196a Polarizing plate 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4020 Protective insulation layer 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4035 Spacer 4040 Conductive layer 5300 Board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing Control Circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin Film Transistor 5604 Wiring 5605 Wiring 9201 Display section 9202 Display button 9203 Operation switch 9205 Adjustment part 9206 Camera Department 9207 Speaker 9208 Mike 9301 Upper housing 9302 Lower housing 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing Device 9307 Display section 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 Slot Machine 9901 Case 9903 Display section

Claims

1. A first transistor, a second transistor, and a capacitor, the first transistor includes a first gate electrode layer, a first oxide semiconductor layer, a first source electrode layer, a first drain electrode layer, and a second gate electrode layer; the second transistor includes a third gate electrode layer, a second oxide semiconductor layer, a second source electrode layer, and a second drain electrode layer; the first transistor has a dual-gate structure having a region where the first gate electrode layer and the second gate electrode layer overlap with each other through the first oxide semiconductor layer; the second transistor has a single-gate structure having a region where the third gate electrode layer and the second oxide semiconductor layer overlap with each other, the first oxide semiconductor layer contains indium, gallium, and zinc; the second oxide semiconductor layer contains indium, gallium, and zinc; the capacitor includes a first conductive layer, a first insulating layer, a second insulating layer, and a second conductive layer; the first conductive layer has a region overlapping with the second conductive layer via the first insulating layer and the second insulating layer; the first conductive layer is provided on the same layer as the first gate electrode layer and has the same material; the second conductive layer has a region that functions as a pixel electrode electrically connected to the second transistor, the first insulating layer has a region in contact with a lower surface of the first oxide semiconductor layer, a region in contact with an upper surface of the first gate electrode layer, a region in contact with a lower surface of the second oxide semiconductor layer, and a region in contact with an upper surface of the third gate electrode layer; the second insulating layer has a region in contact with an upper surface of the first oxide semiconductor layer, a region in contact with a lower surface of the pixel electrode, and a region in contact with an upper surface of the second oxide semiconductor layer; one of the first source electrode layer or the first drain electrode layer is electrically connected to a third conductive layer; the third conductive layer is provided on the same layer as the first gate electrode layer and has the same material; in a cross-sectional view of the first transistor in a channel length direction, the first oxide semiconductor layer has a region in contact with the other of the first source electrode layer and the first drain electrode layer at an end portion of the first oxide semiconductor layer, an end portion of the first oxide semiconductor layer having a region in contact with the other of the first source electrode layer and the first drain electrode layer does not have a region overlapping with the first gate electrode layer and does not have a region overlapping with the second gate electrode layer in a cross-sectional view of the first transistor in a channel length direction.

2. In claim 1, an organic resin layer on the second transistor; The organic resin layer has a region located between the second insulating layer and the second conductive layer.

Images