High-performance epitaxial seed substrate, method for manufacturing high-performance epitaxial seed substrate, semiconductor substrate, and method for manufacturing semiconductor substrate

Abstract

To obtain the epitaxial and solid epitaxial growth seed substrate of III group nitride, such as AlN, AlxGa1-xN (0<X<1) and GaN having less crystal defects, high quality and low cost.SOLUTION: An epitaxial growth seed substrate includes: a support substrate; a planarization layer provided on the upper surface of the support substrate and having a thickness of 0.5-3 μm; and a seed crystal layer provided on the upper surface of the planarization layer. The support substrate includes a III group nitride polycrystalline ceramics; a composite ceramic core formed of at least one or more kinds of nitrides or oxides of III or IV groups and consisting of a fiber-like single crystal; and a sealing layer sealing the core and having a thickness of 0.05-1.5 μm. The seed crystal layer is a Si<111>single crystal layer having a thickness of 0.04-1.5 μm.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a high-quality seed substrate for epitaxy of group III nitrides having characteristics such as high thermal conductivity, high strength, high dimensional accuracy, low warpage, and few defects, such as aluminum nitride (AlN), aluminum gallium nitride (Al x Ga 1-x N (where 0 < x < 1), gallium nitride (GaN), and a method for manufacturing the same. That is, it relates to a high-quality and inexpensive AlN, Al x Ga 1-x N (0 < X < 1), a seed substrate for epitaxial growth of group III nitrides such as GaN-based, a method for manufacturing the same, a semiconductor substrate using the same, and a method for manufacturing the same.

Background Art

[0002] Crystal substrates of group III nitrides such as AlN-based and GaN-based have a wide bandgap and excellent high-frequency characteristics with short-wavelength luminescence and high breakdown voltage. For this reason, substrates of group III nitrides are expected to be applied to devices such as light-emitting diodes (LEDs), lasers, Schottky diodes, power devices, and high-frequency devices. For example, instead of mercury lamps, AlN-based crystal substrates are used for sterilizing the ballast water of tanks and, these days, for the purpose of removing corona viruses, etc. The demand for single-crystal substrates of AlN and / or Al x Ga 1-x N (0.5 < X < 1) is increasing more and more.

[0003] However, currently, these AlN and / or Al x Ga 1-xFor a single crystal substrate of N(0.5 < X < 1), for example, regarding an AlN single crystal substrate, as described in Non-Patent Document 1 and Non-Patent Document 2, since AlN has no melting point, it is difficult to manufacture by the general melt method using a silicon (Si) single crystal or the like. It is manufactured by the sublimation method (modified Lely method) at 1700 - 2250 °C under a N2 atmosphere using silicon carbide (SiC) or AlN as a seed crystal, or as disclosed in Patent Document 1 and Non-Patent Document 3, it is made by the hydride vapor phase epitaxy (HVPE) method on a sapphire substrate or an AlN substrate obtained by the sublimation method. Since the AlN single crystal by the sublimation method requires a high temperature for crystal growth, currently, due to device constraints, it is at most a small-diameter substrate with a diameter of φ2 - φ4 inches and is extremely expensive. The dislocation density of the AlN single crystal obtained by the sublimation method is < 10 5 cm -2 which is relatively small. On the other hand, it has the drawbacks that the crystal is colored due to contamination by carbon and metal impurities derived from carbon materials such as crucibles and heat insulators, the resistivity is low, and the ultraviolet transmittance is also low. On the other hand, the AlN single crystal made by the hydride vapor phase epitaxy (HVPE) method on a sapphire substrate is relatively inexpensive and has less coloring, but due to the difference in lattice constants between AlN and sapphire, many defects occur in the AlN crystal and it has a low resistivity. Also, the AlN crystal obtained by depositing an HVPE film on an AlN substrate by the sublimation method has a relatively small dislocation density and small defects, but due to the coloring contamination from the underlying AlN substrate, the transmittance for deep ultraviolet light emission is low and the resistivity is low. Moreover, since the expensive sublimation method AlN crystal is used as it is as a substrate that also serves as a seed crystal, there is a drawback that the cost is extremely high.

[0004] As described above, AlN is of low quality and high price, and the expected characteristics cannot be obtained even when devices for various applications are fabricated. Also, in response to the recent demands for higher output and miniaturization, it is difficult to cope with heat generation, dimensional accuracy, and warping, which hinders the wide spread and expansion of applications of these substrates.

[0005] As for GaN-based substrates, bulk GaN substrates grown by growing GaN crystals in liquids such as liquid ammonia or Na flux are relatively high quality with few defects, but are extremely expensive because they require high-temperature and high-pressure equipment. Also, like the AlN substrates produced by the sublimation method, they are used as seed crystals and base substrates, so they are extremely expensive. On the other hand, if GaN crystals are grown heteroepitaxially on sapphire substrates using MOCVD or hydride vapor phase epitaxy (HVPE, THVPE), which grow crystals in the vapor phase, it is theoretically possible to grow high-quality and large crystals. However, in reality, the lattice constants and thermal expansion coefficients of the GaN crystals grown and the sapphire base substrate are significantly different, so many crystal defects and cracks occur during production, and high-quality crystals cannot be obtained.

[0006] On the other hand, with the recent start of 5G communication and the progress of electric vehicles, GaN-based crystal substrates are required to have higher high frequency characteristics and higher voltage resistance, and like AlN-based crystal substrates, they are also required to have higher thermal conductivity, higher mechanical strength, higher dimensional accuracy, and less warpage due to increased output, miniaturization, and electric vehicles, and there is a strong demand for them to meet these requirements as the substrate diameter increases. Therefore, in recent years, in addition to the conventional demands for fewer defects and lower prices, there is an urgent need to improve the above-mentioned high thermal conductivity, high strength, high dimensional accuracy, and low warpage of III-nitride crystal substrates such as AlN-based and GaN-based. However, the reality is that, like AlN-based substrates, GaN-based crystal substrates have not made much progress in improving these new requirements.

[0007] As one of the solutions to these problems, Patent Document 2 describes a support substrate having an AlN ceramic core and a sealing layer that seals the AlN ceramic core with a multilayer film of SiO2 / P-Si / SiO2 / Si3N4, a planarization layer such as SiO2 on the upper surface of the support substrate, and further, a Si crystal as a seed crystal on the upper surface of the planarization layer. <111> There is disclosed a bonded substrate, so-called QST (product name) substrate, having a seed crystal layer formed by thin film transfer of a thin film of a GaN-based semiconductor substrate.

[0008] However, in the above patent, if the thickness of each multilayer film that seals the core, or between the sealing layer, the flattening layer, and the seed crystal layer is not well balanced, the thermal stress caused by the difference in thermal expansion coefficient will be large, and cracks or chips will easily occur between the layers, or the support substrate will be easily warped or distorted. As a result, the contamination and various distortions caused by the diffusion of impurities in the AlN ceramic core will be removed by the seed crystal Si <111> As a result, the epitaxial growth film becomes poor in characteristics due to many crystal defects, the thermal conductivity and dimensional stability are reduced, and further, the Si <111> In addition, the Si seed crystals, which are different from the above, often cause a decrease in yield when transferring the thin film to the support substrate. <111> Epi-film defects, thought to be due to the nature of the film itself, also frequently occur, and improvements to these issues were desired.

[0009] Therefore, the inventors started by reducing the thermal stress between the layers and by <111> As a result of a thorough investigation of the relationship between the origin of the epitaxial film and the characteristics of the epitaxial film, it was found that the thermal stress between each layer was reduced and the seed crystal Si <111> It was found that the number of oxidation-induced stacking faults (OSFs) contained in the CrN alloy is extremely important. 2 We discovered that the epitaxial film has very few crystal defects and is in good condition when performed as described below, and have previously filed related patent applications (Patent Application No. 2021-038731 (filing date: March 10, 2021) and Patent Application No. 2021-098993 (filing date: June 14, 2021), both of which were unpublished at the time of filing this application).

[0010] However, even with this improvement, improvements in high thermal conductivity, high dimensional accuracy, high strength, low warpage, and other areas that are essential for the above-mentioned recent, increasingly sophisticated new applications were insufficient, and further improvements and measures were necessary.

[0011] Although some types of polycrystalline ceramics of III-nitrides have relatively high thermal conductivity, the thermal resistance increases at grain boundaries, such as between the polycrystalline grains of the ceramic raw material or at the fusion bonding surface with the sintering aid, and it cannot be expected to exceed a certain value. For example, even AlN polycrystalline ceramics, which are said to have high thermal conductivity, usually have an upper limit of about 170 W / mK. In addition, AlN ceramics have relatively low mechanical strength (fracture toughness), with a fracture toughness of up to 3 MPa·m 1 / 2 This is about half that of Si3N4 ceramics. Therefore, this is insufficient for the thermal conductivity and mechanical strength required for the recent high-power and EVs, and furthermore, the low dimensional accuracy and low warpage caused by this low mechanical strength are also major problems.

[0012] Non-Patent Document 5 discloses the addition of fiber- or whisker-shaped single crystals to polycrystalline ceramics as a method for increasing thermal conductivity and strength. However, there are no examples of using fiber- or whisker-shaped single crystals in bonded substrates, for which nano-level smoothness is essential. This is because the fiber- or whisker-shaped single crystals added to the polycrystalline ceramics rise to the surface, making it impossible to form a nano-level smooth surface. Even if an attempt is made to forcibly smooth the surface by polishing, the fiber or whisker steps occur frequently, and the surface smoothness of Ra 0.2 nm or less required for bonding cannot be obtained. Therefore, it has been common knowledge until now that it is completely inappropriate to introduce fiber- or whisker-shaped single crystals into bonded substrates. [Prior art documents] [Patent documents]

[0013] [Patent Document 1] Patent No. 6042545 [Patent Document 2] Patent No. 6626607 [Patent Document 3] Patent No. 2936916 [Non-patent literature]

[0014] [Non-Patent Document 1] Japanese Journal of Applied Physics; Vol.46,No.17,2007,pp.L389-L391 [Non-Patent Document 2] SEI Technical Review; No.177, p88 - p91 [Non-Patent Document 3] Fujikura Technical Report; No.119, Vol.2 in 2010, p33 - p38 [Non-Patent Document 4] LEDs Magazine Japan; December 2016, p30 - p31 [Non-Patent Document 5] Iron and Steel; Vol.80(1994)No.3, p N91 - p N99 [Summary of the Invention] [Problems to be Solved by the Invention]

[0015] The present invention has been made in view of the above circumstances, and aims to obtain a high-quality seed substrate for epitaxial growth of group III nitrides such as AlN, Al x Ga 1-x N(0 < X < 1), GaN, etc., which have few crystal defects, high characteristics, high thermal conductivity, high strength, low warpage even for large-diameter substrates, and are inexpensive, as well as a method for manufacturing the same, and a semiconductor substrate and a method for manufacturing the same. [Means for Solving the Problems]

[0016] To achieve the above object, a seed substrate for epitaxial growth according to an embodiment of the present invention includes a support substrate, a planarization layer provided on the upper surface of the support substrate and having a thickness of 0.5 to 3 μm, and a seed crystal layer provided on the upper surface of the planarization layer. The support substrate includes a core of a composite ceramic composed of a polycrystalline ceramic of a group III nitride and a fibrous single crystal of at least one nitride or oxide of group III or IV, and a sealing layer having a thickness of 0.05 to 1.5 μm for sealing the core. The seed crystal layer is a layer of Si<111> single crystal having a thickness of 0.04 to 1.5 μm.

[0017] This configuration makes it possible to achieve flatness that allows bonding. In other words, the fiber-like (or whisker-like) single crystal added to the core is covered with both a sealing layer and a flat layer that are well-suited to each other, so no layer separation occurs. Subsequent polishing also does not cause separation, cracks, or steps, making it possible to achieve the surface smoothness required for bonding, with an Ra of 0.2 nm or less. As a result, for example, in one example where AlN single crystal fiber is introduced into AlN ceramics, the thermal conductivity is ~200 W / mK and the fracture toughness is ~10 Mpa m 1 / 2 This will enable the manufacture of epitaxial substrates and devices that are ideal for the recent trend toward higher output and vehicle-mounted applications that are subject to greater shocks. In addition, the warping of the support substrate during bonding of the seed substrate during the epitaxial substrate manufacturing process significantly affects the process yield, but this warping has been greatly improved, significantly improving the yield. As a result, the cost of epitaxial substrates can also be reduced.

[0018] In the present invention, in the composite ceramic forming the core, the III nitride polycrystalline ceramic may be an AlN ceramic, and the fibrous single crystal may be AlN, Si3N4 or Al2O3.

[0019] In the present invention, the sealing layer may include at least a layer of Si3N4.

[0020] In the present invention, the planarization layer is made of SiO2, silicon oxynitride (Si x O y N z The layer may be a single layer of either AlAs or AlAs, or a multilayer of any combination of these.

[0021] In the present invention, the seed crystal layer is made of Si <111> The oxidation induced stacking fault (OSF) of a single crystal is 10 / cm 2 It is preferable that the following is satisfied: Si <111> The OSF in the seed crystal is 10 particles / cm 2By keeping the number of oxidation-induced stacking faults (OSFs) (number / cm2) below, defects during epitaxial growth can be reduced and the subsequent device characteristics can be improved. 2 ) can be measured by the evaluation method described in Patent Document 3.

[0022] In the present invention, the seed crystal layer is made of Si <111> It is preferable that the electrical resistivity (room temperature) is 1 kΩ cm or more.

[0023] In the present invention, a stress adjustment layer may be further provided on the bottom surface of the support substrate as required.

[0024] In the present invention, the stress adjustment layer has a thermal expansion coefficient that allows it to correct any warpage that may be caused after the flattening layer is provided. The stress adjustment layer may be made of SiO2, Si3N4, amorphous Si, polycrystalline Si, or a combination of these. When compatibility with electrostatic chucks is also taken into consideration, the stress adjustment layer is preferably made of polycrystalline Si, at least at the bottom layer of the support substrate, created by a method selected from the group consisting of sputtering, plasma CVD, and LPCVD. In this case, in order to improve affinity with the sealing layer, SiO2 and / or silicon oxynitride (Si x O y N z ) may be interposed between the sealing layer and the polycrystalline Si layer. When a polycrystalline Si film is used, the polycrystalline Si itself or the amorphous Si may be polycrystallized by heating or a laser, or the polycrystalline Si may have a surface layer partially nitrided to improve oxidation resistance. Providing a polycrystalline Si film as the bottom layer is preferable in terms of increasing the chucking force of the electrostatic chuck. This is because the electrostatic chucking force becomes stronger as the resistivity of the film becomes lower and the distance from the film to the electrostatic chuck electrode becomes shorter.

[0025] In the present invention, the sealing layer is preferably formed by the LPCVD method.

[0026] In the present invention, the planarizing layer may be formed on one side or the entire upper surface of the support substrate, or an AlAs film may be formed by any one of plasma CVD, LPCVD, and low pressure MOCVD.

[0027] In the present invention, the seed crystal layer has an OSF of 10 / cm 2 and electrical resistivity (room temperature) of 1 kΩ cm or more. <111> After hydrogen and / or He ion implantation into the single crystal, the Si <111> The single crystal is bonded to the top surface of the planarization layer and then thermally bonded to the Si <111> It is preferable that the thin film be formed by peeling off the surface layer of the single crystal and transferring the thin film.

[0028] A semiconductor substrate according to an embodiment of the present invention is characterized in that a III-V group semiconductor thin film is formed on the upper surface of any one of the above seed substrates for epitaxial growth. The III-V group semiconductor thin film is preferably a nitride semiconductor thin film containing Ga and / or Al.

[0029] A method for producing a seed substrate for epitaxial growth according to an embodiment of the present invention includes the steps of: preparing a composite ceramic core made of a polycrystalline ceramic of a group III nitride and a fibrous single crystal of at least one type of group III or IV nitride or oxide; forming a sealing layer having a thickness of 0.05 μm to 1.5 μm so as to enclose the core to form a support substrate; forming a planarizing layer having a thickness of 0.5 μm to 3.0 μm on the upper surface of the support substrate; and depositing a Si <111> and providing a seed crystal layer having a thickness of 0.04 to 1.5 μm by thin-film transfer of a single crystal.

[0030] In the present invention, the sealing layer is preferably formed by the LPCVD method.

[0031] In the present invention, the planarization layer is formed on one side or the entire surface of the upper surface of the support substrate by forming SiO2 and / or silicon oxynitride (Si x O y N z ) or AlAs may be formed by plasma CVD, LPCVD, or low pressure MOCVD.

[0032] In the present invention, in the step of providing a seed crystal layer, the OSF is 10 / cm 2and electrical resistivity (room temperature) of 1 kΩ cm or more. <111> After hydrogen and / or He ion implantation into the single crystal, the Si <111> A single crystal is bonded to the top surface of the planarization layer, and then peeled off by physical means at 450°C or less to form a Si <111> The seed crystal layer may be provided by thin-film transfer of the surface layer of a single crystal.

[0033] In the present invention, in the step of providing a seed crystal layer, the oxidation induced stacking fault density is 10 / cm 2 Si <111> After implanting hydrogen and / or He ions into the single crystal, the Si <111> A seed crystal layer may be provided by thin-film transferring a surface layer of 0.20 to 1.7 μm of the single crystal and adjusting the thickness to 0.04 to 1.5 μm.

[0034] Alternatively, in the step of providing a seed crystal layer, the oxidation induced stacking fault density is 10 / cm 2 and electrical resistivity (room temperature) of 1 kΩ cm or more. <111> After implanting hydrogen and / or He ions into the single crystal, the Si <111> A seed crystal layer may be provided by thin-film transferring a surface layer of 0.20 to 1.7 μm of the single crystal and adjusting the thickness to 0.04 to 1.5 μm.

[0035] In the present invention, in the step of providing the seed crystal layer, a thin film transferred Si <111> The thickness of the seed crystal layer may be adjusted to 0.04 to 1.5 μm by subjecting the single crystal to CMP polishing and / or etching with a chemical solution.

[0036] The present invention may further include a step of providing a stress adjustment layer on the bottom surface of the support substrate, the stress adjustment layer having a thermal expansion coefficient capable of further correcting the warpage of the planarizing layer after the planarizing layer is provided, and may be made of polycrystalline silicon prepared by a method selected from at least a sputtering method, a plasma CVD method, and an LPCVD method, and / or a polycrystalline silicon whose surface layer is partially nitrided in a nitrogen atmosphere.

[0037] Furthermore, a method for manufacturing a semiconductor substrate according to an embodiment of the present invention includes the steps of manufacturing a seed substrate for epitaxial growth by any one of the methods for manufacturing a seed substrate for epitaxial growth described above, and forming a III-V semiconductor thin film on an upper surface of the seed substrate for epitaxial growth. Effect of the Invention

[0038] According to the present invention, it is possible to provide an epitaxial seed substrate which is excellent in terms of crystal defects, high thermal conductivity, high strength, low warpage, and low cost, and a semiconductor substrate using the same. [Brief description of the drawings]

[0039] [Figure 1] FIG. 2 is a diagram showing a cross-sectional structure of a seed substrate 1. [Diagram 2] 1A to 1C are diagrams showing a procedure for manufacturing a seed substrate 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0040] Hereinafter, the embodiments of the present invention will be described in detail, but the present invention is not limited to these.

[0041] A cross-sectional structure of a seed substrate for epitaxial growth of a III-nitride according to this embodiment (hereinafter, sometimes simply referred to as a "seed substrate") 1 is shown in Fig. 1. The seed substrate 1 shown in Fig. 1 has a planarization layer 4 and a Si <111> The support substrate 3 has a structure in which the seed crystal layer 2 is laminated. If necessary, a stress adjustment layer 5 is provided on the surface (lower surface) of the support substrate 3 opposite to the surface on which the flattening layer 4 is laminated.

[0042] The support substrate 3 includes a core 31 that serves as a core material of the support substrate 3 , and a sealing layer 32 that covers the core 31 .

[0043] The core 31 is a composite ceramic made of polycrystalline ceramic powder of group III nitride, sintering aids, etc., and fibrous single crystals of at least one type of group III or group IV nitride or oxide. The composite ceramic is preferably made by sintering a powder raw material of polycrystalline ceramic (e.g., AlN, Si3N4, GaN, or a mixture of these), a fibrous single crystal of a group III or group IV nitride or oxide (e.g., a simple substance or a mixture of AlN, Si3N4, or Al2O3), and a sintering aid (e.g., Y2O3, Al2O3, CaO, etc.).

[0044] The most suitable support substrate for epitaxial growth of III-nitride crystals, which is the object of the present invention, is AlN composite ceramics, which has a lattice constant and thermal expansion coefficient close to those of epitaxial films, has the best thermal conductivity, and can use relatively inexpensive raw materials. Composite ceramics can be made by mixing polycrystalline AlN powder, fibrous AlN single crystals, Y2O3, etc., and then directly sintering the mixture in a hot press at 1750 to 2000°C in a N2 atmosphere. Alternatively, the above raw materials, polycrystalline AlN powder, fibrous AlN single crystals, and Y2O3, can be directly sintered in a hot press at 1750 to 2000°C. 3、 A slurry may be prepared using polymers such as poval or methyl cellulose, plasticizers such as polyethylene glycol, and a solvent such as water, then molded into a sheet using a doctor blade or the like, degreased in a degreasing furnace, and then sintered in a firing furnace. In general, a hot press is used when characteristics are important, while in general, sheet molding / normal pressure sintering is used when cost is important.

[0045] More specifically, in order to further improve the thermal conductivity, mechanical strength and warpage of AlN ceramics made of polycrystalline AlN powder and sintering aids, a fibrous single crystal of a group III or IV nitride or oxide may be added to the polycrystalline AlN powder to form a composite ceramic. The fibrous single crystal to be added may be selected from fibrous single crystals of AlN, Si3N4 or Al2O3 that have high thermal conductivity, a high aspect ratio, the same or relatively close thermal expansion coefficient as the matrix of the AlN powder, affinity with the AlN powder and electrical insulation.

[0046] The thermal conductivities of fibrous single crystals of AlN, Si3N4, or Al2O3 are approximately 270 - 300 W / mK, 100 - 140 W / mK, and 20 - 45 W / mK respectively, which are relatively high in thermal conductivity, but there are significant differences in their numerical values. Also, because these fibrous single crystals have a large aspect ratio, adding them improves mechanical strength and, at the same time, suppresses the thermal expansion coefficient and warping of the substrate. The order of their mechanical strength is usually Si3N4 < Al2O3 < AlN, and the price order is Al2O3 < Si3N4 < AlN. Therefore, for their introduction, it is only necessary to consider the properties suitable for the application and economy, and select from the above three types alone or in combination. Examples of single introduction are shown below.

[0047] When extremely high thermal conductivity is required and mechanical strength is not so necessary, it is advisable to select AlN fibrous single crystals. On the contrary, when thermal conductivity is sufficient but impact resistance is required, such as in automotive applications, it is advisable to select Si3N4 fibrous single crystals. Also, when cost is emphasized and both thermal conductivity and mechanical strength are moderately high, it is only necessary to select Al2O3 fibrous single crystals.

[0048] Note that the mixing ratio of fibrous single crystals in composite ceramics is selected considering the effect - to - cost ratio, and it is preferably in the range of 5 - 50 wt%. If the mixing ratio is less than 5%, the effect of improving properties is small, and if it exceeds 50%, the effect tends to saturate and the effect - to - cost ratio is low. The substrate for epitaxy of the present invention needs to be placed on a semiconductor line in subsequent device processing. Therefore, after sintering, after processing into a wafer shape, the sintered body is ground and polished to a substrate thickness of 200 - 1000 μm, and CMP polishing is further performed to improve smoothness and achieve a mirror finish.

[0049] In the present invention, the above composite ceramic core is encapsulated with a 0.05-1.5 μm sealing layer of the present invention, particularly a layer containing at least a layer of Si3N4, to form a support substrate, and then covered with a 0.5-3 μm flattening layer provided on the upper surface of the support substrate. The fiber-like or whisker-like single crystal is blended with the AlN powder matrix, and completely integrated by the lamination effect of the two layers, and then polished to obtain a flatness of Ra=0.2 nm or less that allows bonding. That is, by optimizing the composition and thickness of the above two layers, which are essential components of the present invention, a synergistic effect between the two layers is exerted, and only then can the flatness that allows bonding be obtained. The flattening layer may be a single layer film of SiO2, silicon oxynitride, or AlAs, or a multilayer film of any combination of these (for example, a laminate of SiO2 and silicon oxynitride, or a laminate of SiO2 and AlAs).

[0050] If the composite ceramic prepared above is used as the core 31 alone, it will have adverse effects such as the generation of numerous crystal defects and coloring in the target epitaxial single crystal due to metal impurities in raw materials such as AlN powder and fibrous single crystals, sintering binders such as Y2O3 powder, and carbon, oxygen, and other impurities from the insulation materials, furnace materials, containers, etc. during sintering.

[0051] For this reason, a sealing layer 32 is provided to encase and seal the composite ceramic core 31. Specifically, when sealing the core 31 with the sealing layer 32, it is necessary to consider the composition and thickness of each layer constituting the sealing layer 32 so that the thermal stress is as small as possible and the thermal conduction is as large as possible. In the present invention, it is preferable to optimize the total thickness of the sealing layer 32 within the range of 0.05 to 1.5 μm in terms of characteristics and manufacturing costs.

[0052] The composition of the sealing layer 32 can be appropriately selected taking into consideration the thermal expansion coefficient and thermal conductivity, but in order to further enhance its ability to prevent impurity diffusion, it is preferable to cover and seal the entire layer with a film made of at least silicon nitride (Si3N4).

[0053] If necessary, for example, if an electrostatic chuck is to be used, p-Si may be provided as a layer for the electrostatic chuck in this sealing layer 32. This p-Si layer may be formed between the composite ceramic core and the Si3N4 layer, or may be provided together with or below the stress adjustment layer 5 described below. In this case, if the adhesiveness between p-Si and Si3N4 is insufficient, a layer having high adhesive performance such as SiO2 or silicon oxynitride (Si x O y N z Furthermore, in order to prevent oxidation of p-Si, it is also possible to use polycrystalline Si, partly nitrided.

[0054] In the case of a seed substrate for epitaxial growth of III-nitrides such as GaN for high frequencies, particularly for ultra-high frequencies such as millimeter waves in the gigahertz band, in order to avoid high frequency loss in a device fabricated using an epitaxial layer grown using the seed substrate, the above-mentioned Si <111> The electrical resistivity (at room temperature) of the seed crystal layer 2 is preferably 1 kΩ cm or more. <111> This is because in the seed crystal layer 2, high frequency loss due to millimeter waves in the gigahertz band becomes large, causing the device to generate heat and consume large amounts of power, making it difficult to obtain the required characteristics.

[0055] When providing a p-Si film for electrostatic chuck, the resistance of the p-Si film is preferably higher within a range where the necessary chucking force can be obtained, and the position of the p-Si film should be formed as a lower layer of the core 31 as far away as possible from the seed crystal layer 2 on which the epitaxial film is laminated, or below the stress adjustment layer 5. Alternatively, it is preferable to form a multilayer film simultaneously with the stress adjustment layer 5. High-resistance p-Si has less high-frequency loss. Also, when it is disposed below the support substrate 3, it is close to the electrostatic chuck, so that a sufficient electrostatic force is generated even with high resistance. Therefore, the substrate can be sufficiently attracted without doping. To further reduce high-frequency loss, it is more preferable to remove the p-Si layer by back-grinding the substrate at the end of device fabrication. When providing the stress adjustment layer 5, it is preferable to maintain the resistance of the p-Si as high as possible, but there is no restriction on the minimum doping of boron (B), phosphorus (P), etc. required to generate the necessary electrostatic force.

[0056] If the sealing layer 32 is too thick, the stress between the layers due to the difference in thermal expansion coefficient increases, causing peeling between the layers. Therefore, even if films of various compositions are selected and combined, it is not preferable for the thickness of the sealing layer 32 to exceed 1.5 μm. On the other hand, from the viewpoint of the function of sealing impurities, a thickness of less than 0.05 μm is insufficient to prevent the diffusion of impurities. For the above reasons, it is preferable that the thickness of the sealing layer 32 is in the range of 0.05 to 1.5 μm. The method for forming the sealing layer can be selected from film formation methods such as MOCVD, atmospheric pressure CVD, LPCVD, and sputtering, but it is particularly preferable to use the LPCVD method in terms of film quality, film coverage, and impurity diffusion prevention ability.

[0057] A planarization layer 4 having a thickness of 0.5 to 3 μm is laminated on at least the sealing layer 32 on the upper surface of the support substrate 3. The planarization layer 4 is made of SiO2, Al2O3, Si3N4, SiC or silicon oxynitride (Si x O y N z ), and ceramic film materials such as Si, GaAs, and AlAs, which are often used as sacrificial layers in etching, etc., are selected. However, SiO2 and / or silicon oxynitride (Six O y N z It is preferably selected from AlAs or the like.

[0058] Note that the planarization layer 4 is usually laminated only on one side of the sealing layer 32 from the cost aspect. However, when the warpage is large, it can also be formed so as to cover the entire sealing layer 32. The thickness of the planarization layer 4 should be sufficient to fill the voids, unevenness, or steps caused by the fibrous single crystal described above in the composite ceramic core 31 with the sealing layer 32, and at the same time, it is necessary to obtain a smoothness sufficient for the transfer of the seed crystal. However, if the planarization layer 4 is too thick, even in the case of a composite ceramic core containing a fibrous single crystal, the thermal stress of the thick planarization layer cannot be sufficiently suppressed, which may cause warpage or cracks in the seed substrate 1, which is not preferable. Therefore, it is preferably provided with a thickness of at least 0.5 to 3 μm on the upper surface. If the thickness is less than 0.5 μm, it is difficult to fill the voids, unevenness, or steps caused by the fibrous single crystal in the composite ceramic core 31 with the sealing layer 32 and the planarization layer 4. On the other hand, if the thickness is 3 μm or more, warpage and cracks are likely to occur due to the planarization layer 4.

[0059] From the viewpoints of the required film quality and film formation efficiency, the plasma CVD method, the LPCVD method, or the low-pressure MOCVD method is suitable for forming the planarization layer 4. The laminated planarization layer 4 is subjected to a heat treatment for sintering or CMP polishing for smoothing according to the film situation, in preparation for the thin film transfer of the seed crystal layer 2 described later.

[0060] The seed crystal layer 2 is provided by thin film transferring a seed crystal onto the surface of the planarization layer 4. The seed crystal used for the thin film transfer is a substrate having a crystal structure similar to that of group III nitrides such as AlN, Al x Ga 1-x N (0 <X <1), GaN, etc. are selected. Therefore, AlN, Si<111>, SiC, SCAM, AlN, AlGaN, sapphire, etc. are considered. However, Si<111> is preferable in terms of ease of increasing the diameter, availability of mass-produced commercial products, and low cost. Among the Si<111> crystals, the number of oxidation-induced stacking faults (OSF) is 10 per cm2 Si <111> Single crystals are particularly preferred.

[0061] Si, which will be the seed for epitaxial growth in the next process <111> Single crystal OSF is 10 / cm 2 If the OSF density is less than 10 / cm, the epitaxially grown crystal will have fewer defects, which will result in high performance devices using the seed crystal, and the yield will be good, resulting in low cost. 2 If the temperature exceeds this limit, the number of defects in the epitaxially grown crystals will increase rapidly, deteriorating device characteristics, and inevitably reducing yields and increasing costs.

[0062] S <111> If the electrical resistivity (room temperature) of the single crystal is less than 1 kΩ cm, the resistance will cause high frequency loss, increase power consumption, and generate heat, degrading the device characteristics. For this reason, when using the epitaxial and bare substrates obtained by epitaxial growth on the seed substrate 1 for high frequency devices, especially for 5G and beyond, it is necessary to use Si <111> It is preferable to select a single crystal with an electrical resistivity (room temperature) of 1 kΩ·cm or more.

[0063] S <111> The single crystal is implanted with ions limited to hydrogen and / or helium (He) ions, which have little effect on the electrical resistance of the single crystal substrate, and then the Si <111> The ion-implanted surface of the single crystal is bonded to the top surface of the flattening layer 4, and is peeled off using a physical means such as a fingernail at a temperature of 450° C. or less. <111> The surface layer of the single crystal is separated at the ion implantation depth, and a thin film of is transferred to the planarization layer 4. That is, a seed crystal layer 2 is provided on the upper surface of the planarization layer 4. Unlike heavy elements such as boron (B), light elements such as hydrogen and He are suitable for ion implantation into seed crystals in that they cause little damage to the seed crystal due to ion implantation and do not reduce electrical resistance. In addition, by performing peeling and transfer at a low temperature of 450°C or less, the Si <111> This can prevent thermal damage to the single crystal.

[0064] The final thickness of the seed crystal layer 2 is preferably 0.04 to 1.5 μm. In ion implantation, the layer damaged by ions alone has a thickness of approximately 0.1 μm, and if it is less than 0.04 μm, good seed crystals cannot be obtained. Furthermore, if the transfer thickness is 1.5 μm or more, the ion implanter requires high-output ion energy, and the ion implanter becomes huge in size, requiring a huge investment and being uneconomical. In order to provide a seed crystal layer 2 of an appropriate thickness, Si <111> The surface layer of the single crystal may be thin-film-transferred to a thickness of 0.20 to 1.7 μm, and then the thickness may be adjusted to 0.04 to 1.5 μm. <111> The thickness of the single crystal thin film is limited by the margin required for removing the damaged layer during ion implantation, and limited by the limitations of the ion implantation device (larger device size and higher cost due to high acceleration voltage). The thickness can be in the range of 0.1 to 2.0 μm, but is more preferably 0.20 to 1.7 μm. The thickness can be adjusted by CMP polishing and / or etching with a chemical solution.

[0065] More specifically, hydrogen and / or He ions are implanted into the seed crystal to a depth of 0.2 to 1.7 μm, and then the upper surface of the planarizing layer 4 is bonded to the ion-implanted surface of the seed crystal. The seed crystal may then be peeled off at a temperature of 450° C. or less by a physical method such as gas pressure or a fingernail. By setting the treatment temperature at 450° C. or less, it is possible to suppress stress and thermal damage due to impurity diffusion and thermal stress that are likely to occur in the seed crystal of the thin film transferred by treatment at a high temperature exceeding 450° C.

[0066] After that, the top surface of the transferred thin film is polished by CMP and / or lightly etched with a chemical solution to remove the damaged layer caused by the ion implantation, and a seed single crystal thin film (seed crystal layer) having a thickness of 0.04 to 1.5 μm is obtained. If higher uniformity is required for the ion implantation, it is recommended to form a film of SiO2 or the like on the ion implantation surface of the seed substrate as necessary before the ion implantation.

[0067] In the present invention, a stress adjustment layer 5 may be added to the bottom surface of the support substrate 3 depending on the circumstances. The stress adjustment layer 5 corrects the warpage of the seed substrate 1 caused by the formation of the planarization layer 4. For the stress adjustment layer 5, a film material and thickness having a thermal expansion coefficient capable of correcting the warpage of the seed substrate 1 are selected. As the stress adjustment layer 5, it is preferable to form a film of at least polycrystalline Si (p-Si) in order to also accommodate an electrostatic chuck. From the viewpoint of warpage correction and affinity with the sealing layer 32, SiO2 and / or silicon oxynitride (Si x O y N z ) may be interposed. Also, a part of the polycrystalline silicon may be nitrided to impart oxidation resistance.

[0068] Next, the steps of the method for producing the III-nitride-based epitaxial growth seed substrate 1 according to this embodiment will be described with reference to Fig. 2. Note that in cases where a suitable method for forming each layer has already been described together with the configuration of each part of the seed substrate 1, a duplicated description here will be omitted.

[0069] First, a composite ceramic core 31 is prepared, which is made of a polycrystalline ceramic of a group III nitride and a fibrous single crystal of at least one type of group III or group IV nitride or oxide (S01 in FIG. 2). Then, a sealing layer 32 is formed to a thickness of 0.05 μm to 1.5 μm so as to encase the core 31, to form a support substrate 3 (S02 in FIG. 2). At this time, the sealing layer 32 is preferably formed by the LPCVD method. Then, a flattening layer 4 is formed on the upper surface of the support substrate 3 to a thickness of 0.5 μm to 3.0 μm (S03 in FIG. 2). In addition, if necessary, a stress adjustment layer 5 is formed on the lower surface of the support substrate 3 (S04 in FIG. 2). After the flattening layer 4 is provided, the stress adjustment layer 5 is preferably formed of SiO2, Si3N4, amorphous Si, polycrystalline Si, or a combination of these materials to correct the warpage. However, when considering compatibility with electrostatic chucks, polycrystalline Si is directly formed on the bottom layer of the support substrate 3 by at least one of the sputtering method, plasma CVD, and LPCVD method, or when it is difficult to bond the bottom layer of the support substrate 3 to the polycrystalline Si, a lump of SiO2 and / or silicon oxynitride (Si x O y N z ) is formed, and then a polycrystalline Si layer is preferably formed thereunder. The polycrystalline Si may be polycrystalline Si itself, or the amorphous Si may be polycrystallized by heating or laser or the like. The surface layer may be partially nitrided to improve oxidation resistance, or a Si3N4 film may be formed after partially nitriding the surface layer to further improve oxidation resistance. The planarization layer 4 and the stress adjustment layer 5 may be formed simultaneously.

[0070] In addition to S01 to S04, a seed crystal for peeling and transferring the seed crystal layer 2, Si <111> A single crystal substrate 20 is prepared (S11 in FIG. 2). Next, ions are implanted into one surface (ion implanted surface) of the single crystal substrate 20 to form a separation position (embrittled layer) 21 in the single crystal substrate 20 (S12 in FIG. 2).

[0071] Next, the ion-implanted surface of the single crystal substrate 20 is bonded to the planarization layer 4 formed on the support substrate 3 to form a bonded substrate (S21 in FIG. 2). If necessary, the bond may be heated to 450° C. or less to increase the bond strength. Thereafter, the single crystal substrate 20 is separated at the peeling position 21 of the single crystal substrate 20 in the bonded substrate (S22 in FIG. 2). In this manner, a Si <111> The single crystal film of is transferred as a thin film as a seed crystal layer 2. The thickness of the transferred seed crystal layer 2 is adjusted by CMP polishing and / or etching with a chemical solution as necessary. <111> The surface of the remaining portion of single crystal substrate 20 is polished again to provide an ion-implanted surface, so that the remaining portion can be reused for thin-film transfer of a seed crystal layer when producing yet another Group III nitride-based composite substrate.

[0072] As described above, the configuration and manufacturing method of the epitaxial growth seed substrate 1, the epitaxial growth seed substrate 1 according to the present invention is a seed substrate for epitaxial growth comprising a support substrate, a 0.5-3 μm planarization layer provided on the upper surface of the support substrate, and a seed crystal layer provided on the upper surface of the planarization layer. The support substrate comprises a composite ceramic core made of a Group III nitride polycrystalline ceramic and fibrous single crystals of at least one or more Group III or Group IV nitrides or oxides, and a sealing layer of 0.05-1.5 μm that seals the core. The number of oxidation-induced stacking faults is 10 / cm. 2 Si <111> A seed crystal layer of 0.04 to 1.5 μm is provided by thin-film transfer of the surface layer of the single crystal. According to the present invention, particularly due to the following features 1) to 3), high thermal conductivity, high strength, high dimensional accuracy, and low warpage are achieved by the addition of the fibrous single crystal, and as an additional effect, a high-performance, low-cost epitaxial film crystal substrate can be obtained. 1) A composite ceramic core is used, which is made of a polycrystalline ceramic of a group III nitride and a fibrous single crystal of at least one or more group III or IV nitrides or oxides; 2) Thermal stress is minimized by optimizing the composition and film thickness of each layer, such as the support substrate, the planarizing layer, and the seed crystal layer; 3) The seed crystal layer has an oxidation-induced stacking fault density of 10 / cm.2 Si <111> The surface layer of a single crystal is transferred into a thin film. These results of the present invention are the result of not only individual factors, but also the successful expression of the "synergistic effect" in which each factor complements the other. Other secondary factors that contribute to the realization of the effects of the present invention include 4) further stress reduction using a stress adjustment layer as necessary, and 5) thin film transfer by ion implantation limited to light elements such as hydrogen and / or He, followed by peeling off at 450°C or less using a physical means such as a fingernail.

[0073] The substrate of the present invention significantly improves the characteristics of devices, such as light-emitting diodes used in the deep ultraviolet region (UVC; 200 to 280 nm), which are becoming increasingly higher in output, frequency, and voltage resistance as their applications expand to 5G communications and electric vehicles, and also significantly improves the manufacturing yield of devices, enabling cost reduction. EXAMPLES

[0074] The present invention will be described in more detail below with reference to examples and comparative examples, but the present invention is not limited to these examples.

[0075] [Example 1] (Preparation of the support substrate) The following support substrate 3 was prepared, which has a structure in which a composite ceramic core 31 made of a group III nitride polycrystalline ceramic and a group III nitride fiber-shaped single crystal is covered with a sealing layer 32. That is, for the composite ceramic core 31, 80 parts by weight of commercially available AlN powder, 20 parts by weight of commercially available AlN fiber-shaped single crystal, and 5 parts by weight of commercially available Y2O3 as a sintering aid were mixed with an organic binder, a solvent, and the like to prepare a green sheet, which was degreased and sintered at 1900°C in a N2 atmosphere. The sintered body was hollowed out into a wafer of φ8 inches, which was then polished on both sides to prepare a composite ceramic core of φ8 inches x t725μm substrate. When the Ra of the surface of this AlN composite ceramic core substrate was measured after polishing, some steps like fiber-shaped single crystals were observed. The Ra indicating the flatness was measured, and the 10-point average Ra was 520nm (0.52μm). The entire AlN composite ceramic core 31 was covered with a 0.1 μm thick silicon oxynitride layer by LPCVD, and then another LPCVD device was used to seal the entire core with a 0.4 μm thick Si3N4 layer to form a sealing layer 32. The total thickness of the sealing layer 32 was 0.5 μm. For the purpose of further flattening the Si3N4 layer, a 6 μm thick SiO2 layer was laminated on only one side of the upper layer by plasma CVD (ICP-CVD device). After that, the layer was baked at 1000°C, and the SiO2 was polished to a thickness of 2 μm by CMP polishing. The Ra, which indicates the flatness, was measured and found to be 0.18 nm on average at 10 points. It was confirmed that the flatness was sufficient for bonding, and the layer was prepared for the next step of thin film transfer of the seed crystal.

[0076] (Seed crystal preparation) The evaluation in Patent Document 3 showed that the number of oxidation-induced stacking faults (OSF) was 9 / cm 2 A silicon wafer with a diameter of 8 inches and a thickness of 725 μm has an electrical resistivity (room temperature) of 1.2 kΩ cm. <111> A single crystal substrate was prepared as a seed crystal substrate. Hydrogen was ionized into the Si substrate at 100 keV with a depth of 0.6 μm and a dose of 8 × 10 17 cm -2 The ion implantation was carried out under the following conditions.

[0077] The ion-implanted Si was applied to the planarization layer 4 (thickness: 2 μm) of the support substrate 3 that had been prepared in advance. <111> We attempted to transfer a thin film of the surface layer (0.6 μm) of a single crystal. The composite ceramic core contained an AlN fiber-like single crystal, but the seed crystal Si <111> The Si during ion implantation and transfer was <111> The damaged area of ​​the single crystal was lightly polished by CMP, and the Si <111> The single crystal layer was used as a 0.3 μm-thick seed crystal layer 2. The obtained seed substrate 1 was free from cracks, film peeling, and warping as a result of the film thicknesses between the layers of the sealing layer 32, the sealing layer 32, the planarizing layer 4, and the seed crystal layer 2 being balanced with respect to the thermal stresses.

[0078] The remaining Si after thin film transfer <111> A single crystal substrate can be repeatedly used as a large number of seed crystals by repeatedly performing ion implantation on the single crystal substrate, which is extremely economical.

[0079] The characteristics of this seed substrate 1 as a seed substrate for epitaxial growth of GaN were simply evaluated according to the following recipe and method.

[0080] The seed substrate 1 was subjected to epitaxial growth in an MOCVD apparatus. At this time, AlN and AlGaN were formed in the epitaxial layer in the growth direction from the seed substrate 1 side, and then GaN was epitaxially grown. In this epitaxial growth, an AlN layer of 110 nm and an AlGaN layer of 140 nm were formed, and then the GaN epitaxial layer thickness was set to 5 um. During the epitaxial growth, TMAl (trimethylaluminum) was used as the Al source, TMGa (trimethylgallium) was used as the Ga source, and NH3 was used as the N source. The carrier gases were N2 and H2, and the process temperature was in the range of 900 (pre-stage) to 1200°C (GaN film growth).

[0081] The thermal conductivity, mechanical strength (fracture toughness), and warp (warp evaluation) of the above epitaxial substrate were measured, and were found to be 230W / mK and 9Mpa m, respectively. 1 / 2The average grain size was 22μm. To evaluate the dislocation density, etch pits were generated by molten alkali (KOH) etching and the etch pit density (EPD) was measured. X-ray rocking curve (XRC) measurements were also performed to evaluate the crystallinity.

[0082] As a result, the EPD is 0.1 × 10 4 cm -2 and showed an extremely low dislocation density. Furthermore, the full width at half maximum FWHM in the XRC measurement of the (0002) plane of the substrate (hereinafter simply referred to as "FWHM of 0002 XRC") was 128 arcsec, and a high-quality GaN single crystal was obtained. These results show that the seed substrate 1 of this example has excellent properties as a seed substrate for epitaxial growth. When an epitaxial substrate having an epitaxial layer provided on this seed substrate 1 was used for a 30 GHz / 20 Gbps high-frequency device, the surface temperature of the device was 45°C, and no temperature rise due to high-frequency loss that would be particularly problematic was observed.

[0083] [Comparative Example 1] The support substrate in Example 1 was made of 100 parts by weight of commercially available AlN powder and 5 parts by weight of commercially available Y2O3 as a sintering aid, and the Si <111> Single crystal substrate with oxidation-induced stacking faults (OSFs) of 15 / cm 2 The electrical resistivity (at room temperature) is 0.7 kΩ cm. <111> The conditions were the same as in Example 1, including the evaluation method, except that a single crystal substrate was used as the seed crystal layer 2 having a thickness of 1.7 μm and a thin film was transferred onto the single crystal substrate.

[0084] As in Example 1, the thermal conductivity of the epitaxial substrate, the fracture toughness as a measure of mechanical strength, and the WARP as an evaluation of warping were measured, and the results were 150 W / mK and 3 MPa m 1 / 2 The dislocation density was 55 μm. Etch pits were generated by molten alkali (KOH) etching to evaluate the dislocation density, and EPD measurements were performed. XRC measurements were also performed to evaluate the crystallinity. As a result, the EPD was 10 × 10 4 cm -2The result showed an extremely large dislocation density. In addition, the FWHM of 0002XRC was 920 arcsec, resulting in a GaN single crystal with poor crystallinity compared to Example 1. When this epitaxial substrate was used for a 30 GHz / 20 Gbps high-frequency device, the surface temperature of the device rose to 132°C due to high-frequency loss, and water cooling was required for long-term use.

[0085] [Example 2] The conditions, including the evaluation method, were the same as in Example 1, except that the support substrate in Example 1 was made of 80 parts by weight of commercially available AlN powder, 30 parts by weight of commercially available Si3N4 fibrous single crystal, and 5 parts by weight of commercially available Y2O3 and 2 parts by weight of Al2O3 as sintering aids.

[0086] As in Example 1, the thermal conductivity of the epitaxial substrate, the fracture toughness as a measure of mechanical strength, and the WARP as an evaluation of warping were measured, and the results were 175 W / mk and 15 Mpa m 1 / 2 The WARP was extremely small, with a WARP of 7 μm. To evaluate the dislocation density, etch pits were generated by molten alkali (KOH) etching and EPD measurements were performed. XRC measurements were also performed to evaluate the crystallinity. The EPD was 0.6×10 4 cm -2 The dislocation density was relatively small. The FWHM of 0002XRC was 320 arcsec, and the crystallinity was slightly worse than that of Example 1. When this epitaxial substrate was used for a 30 GHz / 20 Gbps high-frequency device, the surface temperature of the device was 78°C due to high-frequency loss, and it was possible to use it for a long time with only air cooling. [Explanation of symbols]

[0087] Type 1 board 2 Seed crystal layer 3 Supporting substrate 4 Planarization layer 5 Stress adjustment layer 20 Single crystal substrates for seed crystals 21 Peeling position

Claims

1. A support substrate; a planarization layer of 0.5 to 3 μm provided on the upper surface of the support substrate; a seed crystal layer provided on an upper surface of the planarization layer; A seed substrate for epitaxial growth comprising: The support substrate is A composite ceramic core made of a polycrystalline ceramic of a group III nitride and a fibrous single crystal of at least one group III or IV nitride or oxide; a sealing layer having a thickness of 0.05 to 1.5 μm that seals the core; The seed layer is a 0.04 to 1.5 μm layer of Si<111> single crystal. A seed substrate for epitaxial growth comprising:

2. The polycrystalline ceramic of III-nitride forming the core is AlN ceramic, and the fibrous single crystal is AlN, Si ３ N ４ Or Al ２ O ３ 2. The seed substrate for epitaxial growth according to claim 1,

3. The sealing layer comprises at least Si ３ N ４ 3. The seed substrate for epitaxial growth according to claim 1, further comprising a layer of:

4. The planarization layer is made of SiO ２ , silicon oxynitride (Si ｘ O ｙ N ｚ 4. The seed substrate for epitaxial growth according to claim 1, which is a single layer film of either AlAs or AlAs, or a multilayer film of any combination of these.

5. The number of oxidation-induced stacking faults in the Si<111> single crystal forming the seed crystal layer is 10 / cm ２ 5. The seed substrate for epitaxial growth according to claim 1, wherein:

6. 6. The seed substrate for epitaxial growth according to claim 1, wherein the electrical resistivity (at room temperature) of the Si<111> single crystal constituting the seed crystal layer is 1 kΩ·cm or more.

7. 7. The seed substrate for epitaxial growth according to claim 1, further comprising a stress adjustment layer on a bottom surface of the support substrate.

8. 8. The epitaxial growth seed substrate according to claim 7, wherein the stress adjustment layer has a thermal expansion coefficient that enables further straightening of the warp after the planarization layer is provided, and is made of polycrystalline Si prepared by a method selected from at least a sputtering method, a plasma CVD method, and a LPCVD method.

9. The stress adjustment layer is formed of SiO. ２ and / or silicon oxynitride (Si ｘ O ｙ N ｚ 9. The seed substrate for epitaxial growth according to claim 7, characterized in that the seed substrate for epitaxial growth comprises polycrystalline silicon provided with a layer (10) interposed therebetween and / or a surface layer of polycrystalline silicon which is partially nitrided.

10. 10. The seed substrate for epitaxial growth according to claim 1, wherein the sealing layer is formed by a low pressure chemical vapor deposition (LPCVD) method.

11. The planarization layer is formed on one or the entire upper surface of the support substrate. ２ and / or silicon oxynitride (Si ｘ O ｙ N ｚ 11. The seed substrate for epitaxial growth according to claim 1, wherein a film of AlAs or AlAs is formed by any one of plasma CVD, LPCVD and low pressure MOCVD.

12. The seed crystal layer has an oxidation-induced stacking fault density of 10 / cm ２ 12. The epitaxial growth seed substrate according to claim 1, wherein the epitaxial growth seed substrate is provided by ion-implanting hydrogen and / or He into a Si<111> single crystal having an electrical resistivity (room temperature) of 1 kΩ cm or more at 450° C. or less, and then peeling off a surface layer of the Si<111> single crystal by physical means at 450° C. or less to perform thin-film transfer.

13. 13. A semiconductor substrate comprising the seed substrate for epitaxial growth according to claim 1 and a III-V semiconductor thin film formed on the upper surface of the seed substrate.

14. 14. The semiconductor substrate according to claim 13, wherein the III-V group semiconductor thin film is a nitride semiconductor thin film containing Ga and / or Al.

15. Providing a core made of a polycrystalline ceramic of a group III nitride and a fibrous single crystal of at least one group III or IV nitride or oxide; forming a sealing layer having a thickness of 0.05 μm to 1.5 μm inclusive so as to enclose the core, thereby forming a supporting substrate; forming a planarization layer having a thickness of 0.5 μm to 3.0 μm on an upper surface of the support substrate; providing a seed crystal layer having a thickness of 0.04 to 1.5 μm on the upper surface of the planarization layer by thin-film transfer of a Si<111> single crystal; A method for manufacturing a seed substrate for epitaxial growth comprising the steps of:

16. 16. The method for producing a seed substrate for epitaxial growth according to claim 15, wherein the sealing layer is formed by a low pressure chemical vapor deposition (LPCVD) method.

17. The planarization layer is formed on one or the entire upper surface of the support substrate. ２ and / or silicon oxynitride (Si ｘ O ｙ N ｚ 17. The method for producing a seed substrate for epitaxial growth according to claim 15, wherein a film of AlAs is formed on the substrate by any one of plasma CVD, LPCVD and low pressure MOCVD.

18. In the step of providing the seed crystal layer, the oxidation induced stacking fault density is 10 / cm ２ 18. The method for producing a seed substrate for epitaxial growth according to claim 15, further comprising the steps of: implanting hydrogen and / or He ions into a Si<111> single crystal having an electrical resistivity (room temperature) of 1 kΩ cm or more at 450° C. or less; bonding the Si<111> single crystal to an upper surface of the planarizing layer; and peeling the Si<111> single crystal by physical means at 450° C. or less to form a thin film of a surface layer of the Si<111> single crystal, thereby providing the seed crystal layer.

19. In the step of providing the seed crystal layer, the oxidation induced stacking fault density is 10 / cm ２ 19. The method for producing a seed substrate for epitaxial growth according to claim 15, wherein hydrogen and / or He are ion-implanted into a Si<111> single crystal having a temperature of 0.15 to 1.5° C. or less, and then a surface layer of 0.20 to 1.7 μm of the Si<111> single crystal is thin-film-transferred by a physical means at 450° C. or less, and the thickness is adjusted to 0.04 to 1.5 μm, thereby providing the seed crystal layer.

20. In the step of providing the seed crystal layer, the oxidation induced stacking fault density is 10 / cm ２ 19. The method for producing a seed substrate for epitaxial growth according to any one of claims 15 to 18, characterized in that the seed crystal layer is provided by ion-implanting hydrogen and / or He into a Si<111> single crystal having an electrical resistivity (room temperature) of 1 kΩ cm or more at 450° C. or less, and then thin-film-transferring 0.20 to 1.7 μm of the surface layer of the Si<111> single crystal by physical means at 450° C. or less, and adjusting the thickness to 0.04 to 1.5 μm.

21. 21. The method for producing a seed substrate for epitaxial growth according to claim 19, wherein in the step of providing the seed crystal layer, the thin-film-transferred Si<111> single crystal is subjected to CMP polishing and / or etching with a chemical solution to adjust the thickness of the seed crystal layer to 0.04 to 1.5 μm.

22. 22. The method for producing a seed substrate for epitaxial growth according to claim 15, further comprising the step of providing a stress adjustment layer on a bottom surface of the support substrate.

23. 23. The method for producing a seed substrate for epitaxial growth according to claim 22, characterized in that the stress adjustment layer has a thermal expansion coefficient that enables further correction of warpage after the planarization layer is provided, and is made of polycrystalline Si produced by a method selected from at least a sputtering method, a plasma CVD method, and a LPCVD method, and / or a surface layer of polycrystalline Si partially nitrided in a nitriding atmosphere.

24. A step of producing a seed substrate for epitaxial growth by the method for producing a seed substrate for epitaxial growth according to any one of claims 15 to 23; forming a III-V semiconductor thin film on the upper surface of the epitaxial growth seed substrate; A method for manufacturing a semiconductor substrate comprising the steps of:

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