Method for manufacturing bit line structures, method for manufacturing semiconductor structures and semiconductor structures

Abstract

The present disclosure provides a method for manufacturing a bit line structure, a semiconductor structure, and a semiconductor structure, the method for manufacturing a bit line structure including the steps of: forming a bit line conductive layer on a surface of a semiconductor substrate, the bit line conductive layer being partially positioned in a groove on the surface of the semiconductor substrate; forming a first protective layer on the bit line conductive layer and the surface of the semiconductor substrate; forming a first barrier layer on the surface of the first protective layer; passivating the surface of the first barrier layer; forming a sacrificial layer on the surface of the first barrier layer, the sacrificial layer having a filling portion to be filled in the groove; and cleaning and removing the portion of the sacrificial layer other than the filling portion with an etchant. The present disclosure provides a method for manufacturing a bit line structure, the method for manufacturing a semiconductor structure, and a semiconductor structure, the method including the steps of: forming a bit line conductive layer on a surface of a semiconductor substrate, the bit line conductive layer being partially positioned in a groove on the surface of the semiconductor substrate; forming a first protective layer on the surface of the first barrier layer; forming a first barrier layer on the surface of the first protective layer; passivating the surface of the first barrier layer; forming a sacrificial layer on the surface of the first barrier layer, the sacrificial layer having a filling portion to be filled in the groove; and cleaning and removing the portion of the sacrificial layer other than the filling portion with an etchant. The present disclosure provides a method for passivating the first barrier layer, the method for increasing the etching selectivity of the etchant to the sacrificial layer and the first barrier layer, so that the conductive layer in the first barrier layer is not damaged when the sacrificial layer is cleaned and removed with the etchant.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This disclosure claims priority to Chinese application "Method for manufacturing bit line structure, method for manufacturing semiconductor structure and semiconductor structure," filed on August 13, 2020, bearing application number 202010811435.X, the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD The present disclosure relates to the field of semiconductor technology, and more particularly to a method for fabricating a bit line structure, a method for fabricating a semiconductor structure, and a semiconductor structure. [Background technology]

[0003] In recent years, with the rapid development of nanodevices in the semiconductor industry, the minimum feature size in chip production is constantly decreasing, and the technology as a whole is continuing to develop in the direction of further miniaturization of the critical dimension. For example, in the manufacturing process of advanced dynamic random access memory (DRAM), the level of the manufacturing process of the bit line has a serious impact on the electrical characteristics, yield, and reliability of the subsequent chip. In particular, with the ever-shrinking critical dimension, there is a tendency for the sacrificial layer to be highly fine and stable. Here, the method of removing the sacrificial layer of the bit line tends to become important.

[0004] As shown in FIGS. 1 and 2, in the conventional manufacturing process, the etching selectivity (i.e., the ratio of the etching rate of the etching solution for the sacrificial layer 150 to the etching rate of the etching solution for the barrier layer 140) of the etchant (e.g., phosphoric acid solution, H3PO4) to the sacrificial layer 150 (e.g., silicon nitride, Si3N4) and the barrier layer 140 (e.g., silicon oxide, SiO2) is small, so that when the sacrificial layer 150 is stripped by the etchant, the barrier layer 140 is easily etched away, and thus the protective layer 130 is partially removed, causing etching damage 121 (W Missing; W is tungsten) to the conductive layer 120 in the barrier layer 140.

[0005] To address the above issues, it is necessary to optimize the manufacturing method of the bit line structure. Summary of the Invention

[0006] One primary objective of the present disclosure is to overcome at least one of the deficiencies of the prior art, and provide a method for fabricating a bit line structure, which can avoid the conductive layer being damaged by the etchant.

[0007] Another primary objective of the present disclosure is to overcome at least one of the deficiencies of the prior art described above and provide a method for fabricating a semiconductor structure that employs the method for fabricating a bit line structure described above.

[0008] Yet another primary object of the present disclosure is to overcome at least one of the deficiencies of the above-mentioned prior art and provide a semiconductor structure manufactured by the above-mentioned method for manufacturing a semiconductor structure.

[0009] To achieve the above objectives, the present disclosure adopts the following technical solutions:

[0010] According to one aspect of the present disclosure, there is provided a method for fabricating a bit line structure, the method comprising: forming a bit line conductive layer on a surface of a semiconductor substrate, the bit line conductive layer being partially located within a trench in the surface of the semiconductor substrate; forming a first protective layer on the bit line conductive layer and a surface of the semiconductor substrate; forming a first barrier layer on a surface of the first protective layer; performing a passivation treatment on the surface of the first barrier layer; forming a sacrificial layer on a surface of the first barrier layer, the sacrificial layer having a filling portion to be filled in the groove; and washing and removing the portion of the sacrificial layer other than the filled portion using an etching solution.

[0011] According to one embodiment of the present disclosure, the passivation treatment includes a plasma treatment, an ion implantation or a thermal oxidation treatment.

[0012] According to one embodiment of the present disclosure, the first barrier layer after passivation treatment includes a two-layer thin film structure including a first thin film layer adjacent to the first protective layer and a second thin film layer away from the first protective layer, and an etching selectivity between the sacrificial layer and the second thin film layer is greater than an etching selectivity between the sacrificial layer and the first thin film layer.

[0013] According to one embodiment of the present disclosure, the material of the first barrier layer includes silicon oxide, the passivation treatment includes nitrogen plasma treatment, and the material of the second thin film layer includes silicon oxynitride.

[0014] According to one embodiment of the present disclosure, the first protective layer has a thickness of 1 nm to 3 nm and / or the first barrier layer has a thickness of 2 nm to 8 nm.

[0015] According to one embodiment of the present disclosure, a material of the first protective layer includes silicon nitride, and / or a material of the first barrier layer includes silicon oxide, and / or a material of the sacrificial layer includes silicon nitride.

[0016] According to one embodiment of the present disclosure, the etching solution contains a phosphoric acid solution, the temperature of the etching solution is 100° C. to 120° C., and / or the concentration of the etching solution is 40% to 60%.

[0017] According to an embodiment of the present disclosure, after cleaning and removing the portion of the sacrificial layer other than the filling portion using the etching solution, removing the exposed first barrier layer; forming a second barrier layer on the bit line conductive layer and on a surface of the semiconductor substrate; and forming a second protective layer on a surface of the second barrier layer.

[0018] According to an embodiment of the present disclosure, when the sacrificial layer is cleaned and removed using the etching solution, pre-cleaning the surface of the sacrificial layer with a diluted hydrofluoric acid solution to remove an oxide layer on the surface of the sacrificial layer; and cleaning the sacrificial layer with a phosphoric acid solution to remove portions of the sacrificial layer other than the filled portion.

[0019] According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor structure, the method comprising: providing a semiconductor substrate having a groove on a surface thereof; forming a bit line structure in the semiconductor substrate using a method for fabricating a bit line structure according to any of the above embodiments of the present disclosure.

[0020] According to one embodiment of the present disclosure, the passivation treatment includes a plasma treatment, and when the passivation treatment is performed on the first barrier layer, preheating a processing chamber of the processing apparatus; placing the semiconductor structure on which the first barrier layer is to be formed into a process chamber; adding a reactive medium and subjecting the surface of the first barrier layer to a plasma treatment; cooling the processing chamber; and removing the semiconductor structure.

[0021] According to yet another aspect of the present disclosure, there is provided a semiconductor structure, the semiconductor structure including a semiconductor substrate, a bit line conductive layer, and a bit line plug spacer layer, the semiconductor substrate having a groove on a surface thereof, the bit line conductive layer being partially located within the groove on the surface of the semiconductor substrate, the bit line plug spacer layer being filled within the groove, the bit line plug spacer layer including a first protective layer, a first barrier layer after a passivation process, and a filling portion.

[0022] According to one embodiment of the present disclosure, the first protective layer has a thickness of 1 nm to 3 nm and / or the first barrier layer has a thickness of 2 nm to 8 nm.

[0023] According to one embodiment of the present disclosure, a material of the first protective layer includes silicon nitride, and / or a material of the first barrier layer includes silicon oxide, and / or a material of the filling portion includes silicon nitride.

[0024] According to one embodiment of the present disclosure, the first barrier layer after passivation treatment includes a two-layer thin film structure including a first thin film layer adjacent to the first protective layer and a second thin film layer away from the first protective layer, and an etching selectivity between the filling portion and the second thin film layer is greater than an etching selectivity between the filling portion and the first thin film layer.

[0025] According to one embodiment of the present disclosure, the material of the first thin film layer includes silicon oxide, and the material of the second thin film layer includes silicon oxynitride.

[0026] As can be seen from the above technical solutions, the advantages and positive effects of the method for manufacturing a bit line structure according to the present disclosure are as follows:

[0027] The present disclosure increases the etching selectivity of the etchant to the sacrificial layer and the first barrier layer by performing a passivation treatment on the first barrier layer, and thus does not damage the conductive layer in the first barrier layer when the sacrificial layer is washed away using the etchant. In addition to realizing the above-mentioned functional effects, the present disclosure does not require the addition of an activator to the etchant compared to the conventional process, so the cleaning process of the present disclosure is simple and does not affect the product yield. In addition, the present disclosure does not require the thickness of the first barrier layer to be increased, and the filling quality of the grooves can be ensured, and the design requirements for miniaturization and thinning of the critical dimensions of semiconductor products can be met. [Brief description of the drawings]

[0028] [Figure 1] 1A-1C are schematic diagrams of a semiconductor structure at different steps in a conventional method for fabricating a bit line structure. [Diagram 2] 2A and 2B are enlarged contrast views of the structure of a portion of the bit line structure shown in FIG. 1 before and after removal of the sacrificial layer by etching. [Diagram 3]1A-1D are schematic diagrams of a semiconductor structure at different steps in a method for fabricating a bit line structure according to an exemplary embodiment. [Figure 4] 2A-2C are enlarged schematic diagrams of one bit line structure of a semiconductor structure at different steps during a method of fabricating the bit line structure according to one example embodiment. [Diagram 5] 2A-2C are enlarged schematic diagrams of one bit line structure of a semiconductor structure at different steps during a method of fabricating the bit line structure according to one example embodiment. [Figure 6] 2A-2C are enlarged schematic diagrams of one bit line structure of a semiconductor structure at different steps during a method of fabricating the bit line structure according to one example embodiment. [Figure 7] 2A-2C are enlarged schematic diagrams of one bit line structure of a semiconductor structure at different steps during a method of fabricating the bit line structure according to one example embodiment. [Figure 8] 2A-2C are enlarged schematic diagrams of one bit line structure of a semiconductor structure at different steps during a method of fabricating the bit line structure according to one example embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029] In the following, exemplary embodiments will be described more fully with reference to the drawings. However, the exemplary embodiments can be implemented in various forms and should not be understood to be limited to the embodiments described herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. Since the same reference numerals in the drawings indicate the same or similar structures, detailed descriptions thereof will be omitted.

[0030] 3 to 8, each of which is a representative schematic diagram of a semiconductor structure at each step in the method for manufacturing a bit line structure according to the present disclosure. In the exemplary embodiment, the method for manufacturing a bit line structure according to the present disclosure is described by taking the manufacturing of a bit line applied to a dynamic random access memory as an example. It is easily understood by those skilled in the art that various modifications, additions, substitutions, deletions or other changes may be made to the specific embodiments below in order to apply the related design of the present disclosure to the manufacturing method of other types of semiconductor structures, and these modifications are still within the scope of the principle of the method for manufacturing a bit line structure according to the present disclosure.

[0031] As shown in FIGS. 3 to 8, in this embodiment, a method for fabricating a bit line structure according to the present disclosure includes: forming a bit line conductive layer 220 on a surface of a semiconductor substrate 210, the bit line conductive layer 220 being partially located within a groove on the surface of the semiconductor substrate 210; forming a first protective layer 230 on the surface of the bit line conductive layer 220 and the semiconductor substrate 210; forming a first barrier layer 240 on a surface of the first protective layer 230; performing a passivation treatment on the surface of the first barrier layer 240; forming a sacrificial layer 250 on a surface of the first barrier layer 240, the sacrificial layer 250 having a filling portion 251 to be filled in the groove 211; and washing and removing the portion of the sacrificial layer 250 other than the filling portion 251 using an etching solution.

[0032] Up to this point, the fabrication of the semiconductor bit line is essentially complete.

[0033] According to the above design, the present disclosure performs a passivation process on the first barrier layer 240, thereby increasing the etching selectivity of the etchant to the sacrificial layer 250 and the first barrier layer 240, so that the bit line conductive layer 220 in the first barrier layer 240 will not be damaged when the sacrificial layer 250 is washed away using the etchant. Also, compared with the conventional process, the present disclosure does not need to add an activator to the etchant, and does not need to increase the thickness of the first barrier layer 240.

[0034] Specifically, as shown in FIG. 3, a semiconductor layered structure is specifically shown, which may be a representative example of a semiconductor structure in the step of "forming a bit line conductive layer 220" in this embodiment. Here, the semiconductor substrate 210 has a groove 211 on the surface. The bit line conductive layer 220 is formed in the groove 211 on the surface of the semiconductor substrate 210, and includes a metal layer 221 and a bit line plug 222, and may further include titanium nitride 223 (TiN) and a silicon nitride cover layer. The bit line plug 222 is formed in the groove 211 on the surface of the semiconductor substrate 210, a layer of titanium nitride 223 is formed on the bit line plug 222, a metal layer 221 is formed on the layer of titanium nitride 223, and a layer of silicon nitride is further formed on the metal layer 221.

[0035] Specifically, as shown in Fig. 4, an expanded layered structure of a semiconductor bit line is specifically shown, which may be a representative example of a bit line in the step of "forming a first protective layer 230" in this embodiment. Here, the first protective layer 230 is formed on the surface of the bit line conductive layer 220 and the surface of the semiconductor substrate 210 (parts where the bit line conductive layer 220 is not provided), that is, the first protective layer 230 is formed on the groove wall of the groove 211 and on a part of the groove bottom where the bit line conductive layer 220 (bit line plug 222) is not provided.

[0036] Preferably, in this embodiment, for the step of "forming the first protective layer 230", the thickness of the first protective layer 230 is preferably 1 nm to 3 nm, such as 1 nm, 1.5 nm, 2 nm, 3 nm, etc. In other embodiments, the thickness of the first protective layer 230 may be less than 1 nm or greater than 3 nm, such as 0.8 nm, 4 nm, 5 nm, etc., and is not limited to this embodiment.

[0037] Preferably, in this embodiment, for the step of "forming the first protective layer 230", the material of the first protective layer 230 may preferably include silicon nitride. Here, in the step of "forming the sacrificial layer 250", the material of the sacrificial layer 250 may also preferably include silicon nitride, so for easy distinction, when the silicon nitride layer is the first protective layer 230, it may be called Inner SiN, and when silicon nitride is the sacrificial layer 250, it may be called Outer SiN.

[0038] Specifically, as shown in FIG. 5, an expanded layered structure of a semiconductor bit line is specifically shown, which may be a representative example of a bit line in the step of "forming a first barrier layer 240" in this embodiment. Here, the first barrier layer 240 is formed on the surface of the first protective layer 230, that is, the groove wall of the groove 211 and the part of the groove bottom where the bit line conductive layer 220 (bit line plug 222) is not installed are both sequentially formed with the first protective layer 230 and the first barrier layer 240. Here, in this embodiment, the material of the first barrier layer 240 may include, but is not limited to, silicon oxide.

[0039] 6, an expanded layered structure of a semiconductor bit line is specifically shown, which may be a representative example of a bit line structure in the "passivation" step of this embodiment, in which a first barrier layer 240 is formed on the surface of a first protective layer 230, and then a passivation process is performed on the surface of the first barrier layer 240.

[0040] Preferably, in this embodiment, for the "passivation treatment" step, the passivation treatment for the first barrier layer 240 may preferably include plasma treatment. Moreover, the plasma treatment may preferably be nitrogen (N2) plasma treatment. In other embodiments, the passivation treatment for the first barrier layer 240 may adopt other passivation processes or combinations, such as ion implantation, thermal oxidation treatment, etc., and is not limited to this embodiment.

[0041] Preferably, as shown in FIG. 6, in this embodiment, for the "passivation" step, the first barrier layer 240 includes approximately two layers of thin film structure after the surface is passivated. For the convenience of understanding and explanation, these two layers of thin film structure are defined as a first thin film layer 241 and a second thin film layer 242, respectively, in this specification. Here, the first thin film layer 241 is adjacent to the first protective layer 230, and the second thin film layer 242 is away from the first protective layer 230 (i.e., adjacent to the sacrificial layer 250 formed in a later process). Based on this, the first thin film layer 241 may be understood to have a layer structure that is approximately the same as the property state of the first barrier layer 240 when it is not passivated, and thus the second thin film layer 242 is a layer that is changed from the property state of the first barrier layer 240 when it is not passivated. Here, the change of the second thin film layer 242 includes that the etching selectivity between the sacrificial layer 250 and the second thin film layer 242 is greater than the etching selectivity between the sacrificial layer 250 and the first thin film layer 241, i.e., after the first barrier layer 240 is passivated, the etching selectivity between the sacrificial layer 250 and the first barrier layer 240 is greater. In other embodiments, the first barrier layer 240 may form a two-layer or more-layer thin film structure by different types of passivation treatment, and the etching selectivity between at least one of the thin film structures between the sacrificial layer 250 and the first barrier layer 240 is greater than the etching selectivity between the sacrificial layer 250 and another thin film structure. Or, the first barrier layer 240 after the passivation treatment may still retain a single-layer thin film structure, and the etching selectivity between the sacrificial layer 250 and the first barrier layer 240 after the treatment is greater than the etching selectivity between the sacrificial layer 250 and the first barrier layer 240 before the treatment. That is, after passivation, the first barrier layer 240 may form various possible layered thin film structures, and the etching selectivity between the sacrificial layer 250 and the first barrier layer 240 is increased after the first barrier layer 240 is passivated.

[0042] For example, according to a design in which the material of the first barrier layer 240 includes silicon oxide and the passivation treatment includes nitrogen plasma treatment, in this embodiment, after the silicon oxide is treated with nitrogen plasma, the material of the second thin film layer 242 includes silicon oxynitride (SiON). Based on this, if the material of the sacrificial layer 250 includes silicon nitride, the etching selectivity between silicon nitride and silicon oxynitride is greater than the etching selectivity between silicon nitride and silicon oxide, that is, after the first barrier layer 240 is treated with nitrogen plasma, the etching selectivity between the sacrificial layer 250 and the first barrier layer 240 is increased.

[0043] Preferably, in this embodiment, for the step of "forming the first barrier layer 240", the thickness of the first barrier layer 240 is preferably 2 nm to 8 nm, such as 2 nm, 3 nm, 4 nm, 5 nm, etc. In other embodiments, the thickness of the first barrier layer 240 may be less than 2 nm, such as 1 nm, 1.5 nm, etc., and is not limited to this embodiment. It should be noted that the present disclosure employs a process step of passivating the first barrier layer 240, thereby increasing the etching selectivity between the sacrificial layer 250 formed in the subsequent manufacturing process and the first barrier layer 240, so that under the same etching conditions (e.g., the temperature, concentration, and cleaning time of the etching solution are all the same), in order to achieve the same etching removal effect, the thickness required for forming the first barrier layer 240 in this disclosure is smaller than the thickness required for forming the barrier layer in the conventional process. That is, the preferred range of the thickness of the first barrier layer 240 in this embodiment is actually something that cannot be realized by the conventional process, and cannot be achieved by simply selecting a data range.

[0044] Preferably, according to the design, the passivation treatment includes a plasma treatment. In this embodiment, for the "passivation treatment" step, the step of passivating the first barrier layer 240 preferably includes, specifically, preheating a processing chamber of the processing apparatus; placing the semiconductor structure on which the first barrier layer 240 is to be formed into a processing chamber; adding a reactive medium and subjecting the surface of the first barrier layer 240 to a plasma treatment; cooling the processing chamber; and removing the semiconductor structure.

[0045] Continuing from the above, the plasma treatment for the first barrier layer 240 may preferably adopt a treatment device such as a plasma surface treatment device. On this basis, the semiconductor structure is placed in the treatment chamber of the plasma surface treatment device, and the treatment chamber is preheated before the semiconductor structure is placed in it. After the semiconductor structure is placed in the preheated treatment chamber, a reactive medium (e.g., nitrogen, etc.) is added into the treatment chamber, and the reactive medium is used to perform plasma treatment on the surface of the first barrier layer 240 of the semiconductor structure. After the treatment is completed, the treatment chamber in which the semiconductor structure is placed is cooled, and finally the cooled semiconductor structure is removed from the treatment chamber. In other embodiments, when other types of plasma treatment processes or other types of passivation processes are adopted for the "passivation treatment" step, the specific steps and flow of the passivation treatment may be flexibly selected, and are not limited to this embodiment.

[0046] Specifically, as shown in FIG. 7, an expanded layered structure of a semiconductor bit line is specifically shown, which may be a representative example of a bit line structure in the step of "forming a sacrificial layer 250" in this embodiment. Here, the sacrificial layer 250 is formed on the surface of the first barrier layer 240 after the passivation process. In addition, the filling portion 251 of the sacrificial layer 250 is filled in the groove 211 (the portion where the first protective layer 230 and the first barrier layer 240 are not formed). That is, in the portion of the cavity of the groove 211 where the bit line conductive layer 220 (bit line plug 222) is not installed, the groove wall and a part of the groove bottom are both sequentially formed with the first protective layer 230 and the first barrier layer 240, and the remaining cavity of the portion is completely filled with the sacrificial layer 250 (filling portion 251). Based on this, a bit line plug spacer layer 260 is formed in the groove 211 on both sides of the bit line plug 222 of the semiconductor structure. The bit line plug spacer layer 260 includes a first protective layer 230, a first barrier layer 240, and an unremoved sacrificial layer 250 (filling portion 251). In this embodiment, the material of the sacrificial layer 250 may include, but is not limited to, silicon nitride (when the material of the first protective layer 230 also includes silicon nitride, the silicon nitride of the sacrificial layer 250 becomes Outer SiN).

[0047] Continuing from the above, the present disclosure performs a passivation treatment on the first barrier layer 240 before forming the sacrificial layer 250, thereby increasing the etching selectivity between the sacrificial layer 250 and the first barrier layer 240. Specifically, the specific definition of the etching selectivity includes the ratio of the etching rate of the etching solution for the former to the etching rate of the etching solution for the latter under the same etching conditions. Based on this, the "etching selectivity between the sacrificial layer 250 and the first barrier layer 240" is the ratio of the etching rate of the etching solution for the sacrificial layer 250 to the etching rate of the etching solution for the first barrier layer 240, and an increase in the ratio indicates that the etching rate of the etching solution for the sacrificial layer 250 is faster under the same etching conditions. Therefore, in the subsequent etching cleaning step of "cleaning away the sacrificial layer 250", the present disclosure can achieve cleaning away of the sacrificial layer 250 and reduce or avoid etching of the first barrier layer 240, thereby protecting the first protective layer 230 (which typically comprises the same material as the sacrificial layer 250, e.g., silicon nitride) inside the first barrier layer 240 from being etched away, and further protecting the bit line conductive layer 220 inside the first protective layer 230 from etching damage.

[0048] Specifically, as shown in FIG. 8, an expanded layered structure of the semiconductor bit line is specifically shown, which may be a representative example of the bit line structure in the step of "cleaning and removing the sacrificial layer 250" in this embodiment. Here, in this step, the semiconductor structure after the sacrificial layer 250 is formed is wet cleaned using an etching solution, and the remaining parts other than the filling part 251 of the sacrificial layer 250 are etched and removed with the etching solution. Based on this, the semiconductor structure after the sacrificial layer 250 is cleaned and removed has the first protective layer 230, the first barrier layer 240, and the filling part 251 of the sacrificial layer 250 sufficiently filled in the groove 211, and maximizes the functional effect of preventing the occurrence of defects such as short circuits. Up to this point, the manufacture of the semiconductor bit line is basically completed.

[0049] Preferably, in this embodiment, for the step of "cleaning away the sacrificial layer 250", the etching solution may preferably include a phosphoric acid solution. In other embodiments, the etching solution may select other types of etching liquid or solution, and is not limited to this embodiment.

[0050] Preferably, in this embodiment, for the step of "cleaning and removing the sacrificial layer 250", for example, the etching solution includes a phosphoric acid solution, and the temperature of the etching solution is preferably 100°C to 120°C, such as 100°C, 105°C, 110°C, 120°C, etc. In other embodiments, the temperature of the etching solution may be lower than 100°C or higher than 120°C, such as 95°C, 125°C, 150°C, 160°C, etc., and is not limited to this embodiment. It should be noted that the present disclosure employs a process step of passivating the first barrier layer 240, thereby increasing the etching selectivity between the sacrificial layer 250 formed in the subsequent manufacturing process and the first barrier layer 240, and the temperature of the etching solution employed in this disclosure is lower than the temperature of the etching solution in the conventional process, thereby achieving a larger etching selectivity. Of course, in other embodiments, the present disclosure may employ a temperature of the etching solution similar to that of the conventional process. That is, the preferred range of the etching solution temperature in this embodiment is not actually realizable by conventional processes and cannot be achieved by simply selecting a data range.

[0051] Preferably, in this embodiment, for the step of "cleaning and removing the sacrificial layer 250", for example, the etching solution includes a phosphoric acid solution, and the concentration of the etching solution is preferably 40% to 60%°C, such as 40%, 45%, 50%, 60%, etc. In other embodiments, the concentration of the etching solution may be less than 40% or greater than 60%, such as 38%, 65%, 70%, 85%, etc., and is not limited to this embodiment. It should be noted that the present disclosure employs a process step of passivating the first barrier layer 240, thereby increasing the etching selectivity between the sacrificial layer 250 formed in the subsequent manufacturing process and the first barrier layer 240, and the concentration of the etching solution employed in the present disclosure may be less than the concentration of the etching solution in the conventional process, thus achieving a larger etching selectivity. Of course, in other embodiments, the present disclosure may employ a concentration of the etching solution similar to that in the conventional process. That is, the preferred range of etching solution concentration in this embodiment is not actually achievable by conventional processes and cannot be achieved by simply selecting a data range.

[0052] Preferably, in this embodiment, for the step of "cleaning and removing the sacrificial layer 250", the sacrificial layer 250 is preferably etched and cleaned, specifically, Pre-cleaning the surface of the sacrificial layer 250 with a diluted hydrofluoric acid solution to remove the oxide layer on the surface of the sacrificial layer 250; The method may further include a step of cleaning the sacrificial layer 250 with a phosphoric acid solution to remove the portions of the sacrificial layer 250 other than the filling portion 251.

[0053] Continuing from the above, in a specific manufacturing process, after the sacrificial layer 250 is formed on the surface of the first barrier layer 240, the sacrificial layer 250 is exposed and in contact with air, so that a native oxide layer may be formed on the surface of the sacrificial layer 250. In contrast, the present disclosure adds a pre-cleaning step before cleaning the sacrificial layer 250 with an etching solution, thereby effectively removing the native oxide layer formed on the surface of the sacrificial layer 250, and thus the cleaning and removal of the sacrificial layer 250 by the etching solution is more effective, and the stability and controllability of the manufacturing process are desirable.

[0054] In addition, the specific step of etching and cleaning the sacrificial layer 250 may be preferably performed using a trench-type wet cleaning apparatus. Specifically, the surface of the sacrificial layer 250 may be pre-cleaned for 5s to 15s using a hydrofluoric acid solution diluted at 200:1. Next, the pre-cleaned semiconductor structure is placed in the trench-type wet cleaning apparatus and trench-type wet cleaning is performed using a phosphoric acid solution at a low temperature and low concentration (for example, at a temperature of 100°C to 120°C and a concentration of 40% to 60%), followed by washing with water and drying with isopropanol, and then the dried semiconductor structure is taken out of the trench-type wet cleaning apparatus.

[0055] Following the above, in order to discuss and prove the functional effects of the method for fabricating a bit line structure according to the present disclosure, the applicant has conducted a large amount of experiments and simulation calculations. The experimental and calculation results prove beyond any doubt the existence of the relevant functional effects of the present disclosure. In the following, the relevant functional effects of the present disclosure will be explained by comparing two specific embodiments of the present disclosure with the conventional process.

[0056] Referring to Table 1 below, the comparison between the present disclosure and the conventional process was made using process conditions such as "whether or not to perform pre-cleaning", "concentration of the etching solution, for example phosphoric acid", "temperature of the etching solution, for example phosphoric acid", and "passivation treatment, for example nitrogen plasma treatment", and the "etching selectivity" of the sacrificial layer and barrier layer (first barrier layer of the present disclosure) of the semiconductor bit line structure obtained in each process was compared. Based on this, in the conventional process, the step of performing nitrogen plasma treatment on the barrier layer was not adopted, the phosphoric acid concentration was high at 75% to 88%, the phosphoric acid temperature was high at 150°C to 165°C, and the step of performing pre-cleaning on the sacrificial layer was not adopted, and the etching selectivity ratio of the sacrificial layer and barrier layer obtained as a result was about 5:1. In Example 1 of the present disclosure, the step of performing nitrogen plasma treatment on the first barrier layer was adopted, the phosphoric acid concentration and phosphoric acid temperature were the same as those of the conventional process, and similarly the step of performing pre-cleaning on the sacrificial layer was not adopted, and the etching selectivity ratio of the sacrificial layer and barrier layer obtained as a result was about 16:1. In Example 2 of the present disclosure, a step of performing nitrogen plasma treatment on the first barrier layer was adopted, the phosphoric acid concentration was low at 40% to 60%, the phosphoric acid temperature was low at 100°C to 120°C, and the sacrificial layer was pre-cleaned by ultrapure water cleaning with, for example, H2O:HF (49%) = 200:1 for 10 s, thereby obtaining an etching selectivity ratio of the sacrificial layer to the barrier layer of about 32:1. Therefore, it was revealed that the semiconductor bit line structure manufactured by the manufacturing method of the bit line structure according to the present disclosure can certainly increase the etching selectivity ratio of the sacrificial layer to the first barrier layer, and therefore it can certainly be ensured that the conductive layer in the first barrier layer is not damaged by cleaning and removing the sacrificial layer with an etching solution when the thickness of the first barrier layer is small.

[0057] [Table 1]

[0058] It should be noted here that the methods of fabricating bit line structures shown in the drawings and described herein are merely examples of a few of the many methods that may employ the principles of the present disclosure, and it should be expressly understood that the principles of the present disclosure are in no way limited to any of the details or any of the steps of the methods of fabricating bit line structures shown in the drawings or described herein.

[0059] Based on the detailed description of an exemplary embodiment of a method for fabricating a bit line structure according to the present disclosure above, an exemplary embodiment of a method for fabricating a semiconductor structure according to the present disclosure will now be described.

[0060] In this embodiment, a method for manufacturing a semiconductor structure according to the present disclosure includes: providing a semiconductor substrate having a groove on a surface thereof; forming a bit line structure in the semiconductor substrate using the method for fabricating the bit line structure described in the above embodiment according to the present disclosure.

[0061] It should be noted that in the method for manufacturing a bit line structure according to the present disclosure, in each embodiment consistent with the inventive concept, various possible process steps may be employed before and after the formation of the bit line structure to further form functional or technical structures required for various semiconductor structures, and are not limited to the present embodiment.

[0062] For example, after forming the bit line structure in the above steps of the method for manufacturing a semiconductor structure according to the present disclosure, the first barrier layer may be removed and then functional structures such as a second barrier layer and a second protective layer may be formed in sequence. In addition, the steps of forming each of the functional structures may still be realized by processes such as deposition (Dep) and etching (Etch), and in the process of carrying out the above processes, techniques such as patterning may still be realized with technological layered structures such as silicon oxide and silicon nitride, and are not limited to this embodiment. By removing the first barrier layer and then forming the second barrier layer and the second protective layer again, it is possible to avoid the adverse effect on the semiconductor structure caused by surface damage formed in the first barrier layer when removing the sacrificial layer.

[0063] It should be noted here that the methods for manufacturing semiconductor structures shown in the drawings and described herein are merely examples of many types of manufacturing methods that may employ the principles of the present disclosure, and it should be expressly understood that the principles of the present disclosure are in no way limited to any of the details or any of the steps of the methods for manufacturing semiconductor structures shown in the drawings or described herein.

[0064] Based on the detailed description of an exemplary embodiment of a method for fabricating a bit line structure and a semiconductor structure according to the present disclosure above, an exemplary embodiment of a semiconductor structure according to the present disclosure will now be described with reference to FIG.

[0065] In this embodiment, the semiconductor structure according to the present disclosure is manufactured by the method for manufacturing a semiconductor structure according to the present disclosure described in the above embodiment.

[0066] 8, the semiconductor structure according to the present disclosure includes a semiconductor substrate 210, a bit line conductive layer 220, and a bit line plug spacer layer 260. Here, a groove 211 is formed on the surface of the semiconductor substrate 210. The bit line conductive layer 220 is partially located in the groove 211 on the surface of the semiconductor substrate. The bit line plug spacer layer 260 is filled in the groove, and the bit line plug spacer layer includes a first protective layer 230, a first barrier layer 240 after passivation processing, and a filling portion 251.

[0067] Preferably, in this embodiment, the first protective layer 230 may have a thickness of preferably 1 nm to 3 nm.

[0068] Preferably, in this embodiment, the first barrier layer 240 may have a thickness of preferably 2 nm to 8 nm.

[0069] Preferably, in this embodiment, the material of the first protective layer 230 preferably includes silicon nitride.

[0070] Preferably, in this embodiment, the first barrier layer 240 may be made of a material preferably comprising silicon oxide.

[0071] Preferably, in this embodiment, the filler 251 may preferably comprise a material such as silicon nitride.

[0072] Preferably, in this embodiment, the first barrier layer 240 after passivation treatment includes a two-layer thin film structure including a first thin film layer 241 adjacent to the first protective layer 230 and a second thin film layer 242 away from the first protective layer 230, in which the etching selectivity of the filling portion 251 and the second thin film layer 242 is greater than the etching selectivity of the filling portion 251 and the first thin film layer 241.

[0073] Preferably, in this embodiment, the first thin film layer 241 is made of a material including silicon oxide, and the second thin film layer 242 is made of a material including silicon oxynitride.

[0074] It should be noted here that the semiconductor structures shown in the drawings and described herein are merely examples of many types of semiconductor structures in which the principles of the present disclosure can be employed, and it should be expressly understood that the principles of the present disclosure are in no way limited to any of the details or components of the semiconductor structures shown in the drawings or described herein.

[0075] In summary, the present disclosure increases the etching selectivity of the etchant to the sacrificial layer and the first barrier layer by performing a passivation treatment on the first barrier layer, and thus does not damage the conductive layer in the first barrier layer when the sacrificial layer is washed away using the etchant. In addition to realizing the above-mentioned functional effects, the present disclosure does not require the addition of an activator to the etchant compared to the conventional process, so the cleaning process of the present disclosure is simple and does not affect the product yield. In addition, the present disclosure does not require the thickness of the first barrier layer to be increased, and further meets the design requirements for miniaturization and thinning of the critical dimensions of semiconductor products.

[0076] Although the present disclosure has been described with reference to some exemplary embodiments, it should be understood that the technical terms used are for the purpose of explanation and illustration, and not for the purpose of limitation. Since the present disclosure can be specifically implemented in various forms without departing from the spirit or substance of the disclosure, it should be understood that the above-mentioned embodiments are not limited to any of the details described above, but should be broadly interpreted in the spirit and scope defined by the appended claims, and all changes and modifications within the scope of the claims or their equivalents should be included in the appended claims. [Explanation of symbols]

[0077] 111 Groove 120 Conductive layer 121 Etching damage 130 Protective layer 140 Barrier Layer 150 Sacrificial Layer 210 Semiconductor substrate 211 Groove 220 bit line conductive layer 221 Metal layer 222 bit line plug 223 Titanium nitride 230 1st protective layer 240 First Barrier Layer 241 1st thin film layer 242 Second thin film layer 250 Sacrificial Layer 251 Filling Section 260 Bit Line Plug Spacer Layer

Claims

1. 1. A method of manufacturing a bit line structure comprising the steps of: forming a bit line conductive layer on a surface of a semiconductor substrate, the bit line conductive layer being partially located within a trench in the surface of the semiconductor substrate; forming a first protective layer on the bit line conductive layer and on a surface of the semiconductor substrate; forming a first barrier layer on a surface of the first protective layer; performing a passivation treatment on a surface of the first barrier layer to increase an etching selectivity of an etching solution to the sacrificial layer and the first barrier layer, the passivation treatment including a plasma treatment or an ion implantation; forming the sacrificial layer on a surface of the first barrier layer, the sacrificial layer having a filling portion to be filled in the groove; and cleaning and removing a portion of the sacrificial layer other than the filling portion using an etching solution; When the sacrificial layer is washed away using the etching solution, pre-cleaning the surface of the sacrificial layer with a diluted hydrofluoric acid solution to remove an oxide layer on the surface of the sacrificial layer; and cleaning the sacrificial layer with a phosphoric acid solution to remove portions of the sacrificial layer other than the filled portion.

2. The first barrier layer after passivation treatment includes a two-layer thin film structure including a first thin film layer adjacent to the first protective layer and a second thin film layer away from the first protective layer, and an etching selectivity between the sacrificial layer and the second thin film layer is greater than an etching selectivity between the sacrificial layer and the first thin film layer. A method for fabricating the bit line structure of claim 1.

3. The material of the first barrier layer includes silicon oxide, the passivation treatment includes a nitrogen plasma treatment, and the material of the second thin film layer includes silicon oxynitride.

3. A method for fabricating a bit line structure as claimed in claim 2.

4. the first protective layer has a thickness of 1 nm to 3 nm and the first barrier layer has a thickness of 2 nm to 8 nm; and / or The material of the first protective layer includes silicon nitride, the material of the first barrier layer includes silicon oxide, and the material of the sacrificial layer includes silicon nitride. A method for fabricating the bit line structure of claim 1.

5. The etching solution includes a phosphoric acid solution, and the temperature of the etching solution is 100° C. to 120° C.; and / or The concentration of the etching solution is 40% to 60%. A method for fabricating the bit line structure of claim 1.

6. After cleaning and removing the portion of the sacrificial layer other than the filling portion using the etching solution, removing the exposed first barrier layer; forming a second barrier layer on the bit line conductive layer and on a surface of the semiconductor substrate; and forming a second protective layer on a surface of the second barrier layer. A method for fabricating the bit line structure of claim 1.

7. 1. A method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate having a groove on a surface thereof; and forming a bit line structure in the semiconductor substrate using a method for manufacturing a bit line structure according to any one of claims 1 to 6.

8. The passivation treatment includes a plasma treatment, and when the passivation treatment is performed on the first barrier layer, preheating a processing chamber of the processing apparatus; placing the semiconductor structure on which the first barrier layer is to be formed into a processing chamber; adding a reactive medium and subjecting the surface of the first barrier layer to a plasma treatment; cooling the processing chamber; and removing the semiconductor structure. A method for manufacturing a semiconductor structure according to claim 7.

9. 1. A semiconductor structure comprising: A semiconductor substrate having a groove on a surface thereof; a bit line conductive layer located partially within a trench in a surface of the semiconductor substrate; a bit line plug spacer layer filled in the groove, the bit line plug spacer layer including a first protective layer, a first barrier layer after passivation processing, and a filling portion; the first barrier layer after passivation treatment includes a two-layer thin film structure including a first thin film layer adjacent to the first protective layer and a second thin film layer away from the first protective layer, and an etching selectivity between the filling portion and the second thin film layer is greater than an etching selectivity between the filling portion and the first thin film layer; A semiconductor structure, wherein the material of the first thin film layer comprises silicon oxide and the material of the second thin film layer comprises silicon oxynitride.

10. the first protective layer has a thickness of 1 nm to 3 nm; or The first barrier layer has a thickness of 2 nm to 8 nm.

10. The semiconductor structure of claim 9.

11. The material of the first protective layer includes silicon nitride, or The material of the first barrier layer includes silicon oxide, or The material of the filling portion contains silicon nitride.

10. The semiconductor structure of claim 9.

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