Method and system for manufacturing integrated circuits - Patents.com

Abstract

A method for manufacturing an integrated circuit includes calculating a loss value according to first measurement data and first compensation data associated with a first group of marks on the wafer and second measurement data and second compensation data associated with a second group of marks on the wafer, and adjusting a first set of parameters associated with the first compensation data and the second compensation data so that a difference between the loss value and a target loss value is less than a loss threshold.

Description

[Technical field]

[0001] The present invention relates generally to the field of semiconductor technology, and more particularly to methods and systems for manufacturing integrated circuits. [Background technology]

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to Chinese Patent Application No. 202011612527.1, filed on December 30, 2020, the disclosure of which is incorporated herein by reference.

[0003] Photolithography is an important process in the field of integrated circuit manufacturing. The process quality of photolithography directly affects the indicators such as yield, reliability, chip performance, and useful life of integrated circuits. The improvement of the process quality of photolithography is closely correlated with the stability of these indicators.

[0004] One type of photolithography is called photolithography. In this method, a photomask is irradiated with light such as ultraviolet light, and the pattern on the photomask is transferred to the photoresist on the wafer by exposure. The photoresist contains one or more components that undergo chemical changes during exposure to ultraviolet light. The property changes caused in the photoresist therefore allow selective removal of exposed or unexposed portions of the photoresist. In this way, photolithography allows the pattern from the photomask to be transferred to the photoresist, and then the photoresist is selectively removed to reveal the pattern. Furthermore, photolithography can be performed by repeating the above-mentioned operations to superimpose multiple pattern layers.

[0005] With the continuous innovation of semiconductor process technology, how to control the overlay offset between multiple pattern layers has already become a critical factor for the yield of integrated circuits. How to reduce the overlay offset has already become one of the major challenges in the semiconductor industry. Meanwhile, stitching technology is widely adopted in the manufacture of charge-coupled device (CCD) and complementary metal-oxide semiconductor (CMOS) image sensors (CIS) due to the size constraint of the photomask. How to control the stitching offset is another challenge.

[0006] Anamorphic lenses have been introduced into high numerical aperture extreme ultraviolet (EUV) photolithography technology to provide a pattern layer with higher resolution. In this technology, the pattern on the photomask needs to be stretched and deformed in a single direction (e.g., X-direction), and the deformed pattern on the photomask needs to be repeatedly exposed, and then the stitching technique is used to form a pattern layer on the wafer. In high numerical aperture EUV photolithography technology, the control of stitching offset is also essential. Calibration of overlay offset and stitching offset plays an important role in photolithography. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] US Patent Application Publication No. 2003 / 0059691 Summary of the Invention [Problem to be solved by the invention]

[0008] One of the objectives of an embodiment of the present invention is to provide a method for manufacturing an integrated circuit such that stitching offsets and overlay offsets are taken into account during offset calibration, thereby effectively reducing the stitching offsets and overlay offsets in the process of manufacturing the integrated circuit. [Means for solving the problem]

[0009] An embodiment of the present invention provides a method for manufacturing an integrated circuit, including: calculating a loss value according to first measurement data and first compensation data associated with a first group of marks on the wafer and second measurement data and second compensation data associated with a second group of marks on the wafer; and adjusting a first set of parameters associated with the first compensation data and the second compensation data such that a difference between the loss value and a target loss value is smaller than a loss threshold. Another embodiment of the present invention is a compound of the formula:

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[0010] [Figure 1] 1 is a schematic diagram of a wafer according to one embodiment of the present invention. [Figure 2(a)] 2 is a schematic diagram of an area on a wafer according to one embodiment of the present invention. [Figure 2(b)] 4 is a schematic diagram of an area on a wafer according to another embodiment of the present invention. [Figure 3(a)] FIG. 2 is a schematic diagram of measurement data according to an embodiment of the present invention. [Figure 3(b)] FIG. 2 is a schematic diagram of compensation data according to an embodiment of the present invention. [Figure 4] 2 is a flow diagram of a method for manufacturing an integrated circuit according to one embodiment of the present invention. [Figure 5(a)] FIG. 5 is a vector diagram of the overlay offset after performing the method shown in FIG. 4. [Figure 5(b)] FIG. 5 is a vector diagram of stitching offsets obtained after performing the method shown in FIG. 4. [Figure 6] 4 is a flow diagram of a method for manufacturing an integrated circuit according to a comparative embodiment of the present invention. [Figure 7] 4 is a flow diagram of a method for manufacturing an integrated circuit according to a comparative embodiment of the present invention. [Figure 8(a)] FIG. 7 is a vector diagram of the overlay offset after performing the method shown in FIG. 6. [Figure 8(b)] FIG. 7 is a vector diagram of stitching offsets obtained after performing the method shown in FIG. 6. [Figure 9]1 is an exemplary system according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In order to better understand the spirit of the present invention, the present invention is further described below with reference to some preferred embodiments thereof.

[0012] Various embodiments of the present invention will be described in detail below. Although specific embodiments are discussed, it should be understood that these embodiments are used for illustration purposes. It is obvious to those skilled in the art that other materials and configurations can be used without departing from the spirit and scope of the present invention.

[0013] FIG. 1 is a schematic diagram of a wafer according to one embodiment of the present invention.

[0014] FIG. 1 is a schematic diagram of a wafer W1. The wafer W1 can include multiple regions 10. Each region 10 can include one complete semiconductor device, e.g., a chip. The devices in each region 10 on the wafer W1 can be fabricated by a semiconductor device that performs multiple work steps (including, but not limited to, deposition, etching, exposure, and development) on the substrate of the wafer. Each work step performed by the semiconductor device can form multiple layers of microstructures on the substrate to form the device that ultimately needs to be fabricated.

[0015] Due to the varying areas of the semiconductor devices being fabricated, region 10 may exceed the size limits of each operation performed by the semiconductor device. Therefore, in some embodiments, the semiconductor device may define multiple sub-regions within region 10. Operational steps may be performed individually in the sub-regions within region 10 to ultimately complete the device that needs to be fabricated in region 10.

[0016] In some embodiments, the region 10 can include sub-regions 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, and 10i. In some other embodiments of the present invention, the number of sub-regions can be determined according to practical requirements. For example, the number of sub-regions can be greater than 9 or less than 9.

[0017] 2(a) is a schematic diagram of an area on a wafer according to an embodiment of the present invention. As shown in FIG. 2(a), area 100 is divided into a central area 102 and a peripheral area 104 located outside of the central area 102.

[0018] The region 100 includes a first sub-region 106a and a second sub-region 106b. The first sub-region 106a and the second sub-region 106b are disposed in the central region 102. The second sub-region 106b is adjacent to the first sub-region 106a. In FIG. 2(a), the first sub-region 106a and the second sub-region 106b are different in size. However, in some other embodiments of the present invention, the first sub-region 106a and the second sub-region 106b may be the same in size.

[0019] A number of overlay marks 108 may be located in the perimeter region 104 of the area 100. The overlay marks 108 may be used to calibrate the position of a particular area on a current layer of the wafer relative to a particular area on one or two previous layers. In FIG. 2(a), the number of the overlay marks 108 is six. However, in some other embodiments of the present invention, the number of the overlay marks 108 can be determined according to actual requirements. For example, the number of the overlay marks 108 can be more than six or less than six. Furthermore, in some other embodiments of the present invention, the overlay marks 108 can be disposed at other positions in the outer circumferential region 104. The overlay marks 108 are not limited to being disposed at the outer circumferential region 104. In some other embodiments of the present invention, the overlay marks 108 can be disposed at any position within the region 100.

[0020] The size of the first sub-region 106a may be equal to or smaller than the exposure size of the semiconductor device (e.g., aligner). The size of the second sub-region 106b may be equal to or smaller than the exposure size of the semiconductor device (e.g., aligner). The size of the region 100 is larger than the exposure size of the semiconductor device (e.g., aligner). When the size of the electronic component that needs to be manufactured is larger than the exposure size of the semiconductor device (e.g., aligner), the electronic component may be produced in a stitching manner. That is, different regions of the electronic component can be manufactured separately by using independent exposure procedures to finally form a complete electronic component.

[0021] When different regions of an electronic component are fabricated by using independent exposure procedures, stitching marks may be placed on the wafer for calibration between the different regions.

[0022] For example, a plurality of stitching marks 110 may be disposed in the perimeter region 104 between the first sub-region 106a and the second sub-region 106b. A plurality of stitching marks 110 may be disposed near the intersection 100e of the first sub-region 106a and the second sub-region 106b. A plurality of stitching marks 110 may be disposed adjacent to the intersection 100e of the first sub-region 106a and the second sub-region 106b. The stitching marks may be used to calibrate the position of the current sub-region with respect to the adjacent sub-region. For example, the stitching marks 110 may be used to calibrate the position of the first sub-region 106a with respect to the second sub-region 106b. In FIG. 2(a), the number of stitching marks 110 is two. However, in some other embodiments of the present invention, the number of stitching marks 110 can be determined according to actual requirements. For example, the number of stitching marks 110 can be more than two or less than two. Furthermore, in FIG. 2(a), the stitching marks 110 are disposed in the outer peripheral region 104 between the first sub-region 106a and the second sub-region 106b. However, in some other embodiments of the present invention, the stitching marks 110 can be disposed in the central region 102 between the first sub-region 106a and the second sub-region 106b. In some embodiments, the stitching marks 110 can also be disposed in the central region 102 along the intersection 100e.

[0023] 2(b) is a schematic diagram of an area on a wafer according to another embodiment of the present invention. As shown in FIG. 2(b), area 200 is divided into a central area 202 and a peripheral area 204 located outside of central area 202.

[0024] The region 200 includes a first sub-region 206a, a second sub-region 206b, a third sub-region 206c, and a fourth sub-region 206d. The first sub-region 206a, the second sub-region 206b, the third sub-region 206c, and the fourth sub-region 206d are located in the central region 202. The second sub-region 206b is located between the first sub-region 206a and the third sub-region 206c, and the third sub-region 206c is located between the second sub-region 206b and the fourth sub-region 206d.

[0025] A number of overlay marks 208 are disposed in the outer periphery region 204 of the region 200. The overlay marks 208 can be used to calibrate the position of a particular region on a current layer of the wafer relative to a particular region on one or two previous layers. In FIG. 2(b), the number of the overlay marks 208 is eight. However, in some other embodiments of the present invention, the number of the overlay marks 208 can be determined according to practical requirements. For example, the number of the overlay marks 208 can be more than eight or less than eight. Furthermore, in some other embodiments of the present invention, the overlay marks 208 can be disposed at other positions in the outer periphery region 204. The overlay marks 208 are not limited to being disposed in the outer periphery region 204. In some other embodiments of the present invention, the overlay marks 208 can be disposed at any position in the region 200.

[0026] A plurality of stitching marks 210 may be separately disposed in the circumferential region 204 between the first sub-region 206a and the second sub-region 206b. A plurality of stitching marks 210 may be separately disposed in the circumferential region 204 between the second sub-region 206b and the third sub-region 206c. A plurality of stitching marks 210 may be separately disposed in the circumferential region 204 between the third sub-region 206c and the fourth sub-region 206d.

[0027] The stitching mark 210 may be disposed near an intersection 200e1 between the first sub-region 206a and the second sub-region 206b. The stitching mark 210 may be disposed adjacent to the intersection 200e1 between the first sub-region 206a and the second sub-region 206b. The stitching mark 210 may be disposed near an intersection 200e2 between the second sub-region 206b and the third sub-region 206c. The stitching mark 210 may be disposed adjacent to the intersection 200e2 between the second sub-region 206b and the third sub-region 206c. The stitching mark 210 may be disposed near an intersection 200e3 between the third sub-region 206c and the fourth sub-region 206d. The stitching mark 210 may be located adjacent the intersection 200e3 of the third sub-region 206c and the fourth sub-region 206d.

[0028] The stitching marks can be used to calibrate the position of a current sub-region relative to adjacent sub-regions. For example, the stitching marks 210 can be used to calibrate the position of the first sub-region 206a relative to the second sub-region 206b. The stitching marks 210 can be used to calibrate the position of the second sub-region 206b relative to the third sub-region 206c. The stitching marks 210 can be used to calibrate the position of the third sub-region 206c relative to the fourth sub-region 206d.

[0029] In FIG. 2(b), the number of stitching marks 210 is six. However, in some other embodiments of the present invention, the number of stitching marks 210 can be determined according to actual requirements. For example, the number of stitching marks 210 can be more than six or less than six. In addition, the stitching marks 210 can be disposed at other positions between the first sub-region 206a and the second sub-region 206b. The stitching marks 210 can be disposed at other positions between the second sub-region 206b and the third sub-region 206c. The stitching marks 210 can be disposed at other positions between the third sub-region 206c and the fourth sub-region 206d. In some embodiments, the stitching marks 210 can also be disposed in the central region 202 along the intersections 200e1, 200e2, or 200e3.

[0030] It should be understood that in some embodiments of the present invention, region 100 or region 200 may include another number of sub-regions, for example, four or more, or six or more sub-regions. In certain embodiments of the present invention, region 100 or region 200 may be region 10 shown in FIG. 1. Multiple overlay marks may be disposed in the perimeter region of region 100 or region 200. Multiple stitching marks may be disposed in the perimeter region between the sub-regions.

[0031] In existing methods for manufacturing integrated circuits, stitching offset and overlay offset are considered as two different types of offset. Therefore, during calibration, only stitching offset is calibrated independently or only overlay offset is calibrated independently. For example, a semiconductor device (e.g., an aligner) can calculate an offset relative to a stitching mark to obtain a parameter set for calibrating stitching offset. The obtained parameter set can only be used to calibrate stitching offset. If the obtained parameter set is used to calibrate overlay offset, acceptable results cannot be expected. In fact, in existing manufacturing methods, if the overlay offset is calibrated according to the parameter set to calibrate stitching offset, it is very difficult to meet the manufacturing specification of the wafer. Similarly, in existing manufacturing methods, if the stitching offset is calibrated according to the parameter set used to calibrate overlay offset, it is also very difficult to meet the manufacturing specification of the wafer.

[0032] The present invention proposes a calibration method that takes into account both the overlay offset and the stitching offset, and the obtained parameter set can be executed by a semiconductor device (e.g., an aligner) to calibrate both the overlay offset and the stitching offset during the manufacturing of the wafer. The calibration method proposed in the present invention can be performed based on the following formula:

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[0033] Compensation data for each stitching mark j can be obtained based on the following formula: *Stitch j =Stitch_loc j ×t (Formula 3)

[0034] In Equation 3, Stitch_loc j is the coordinate vector of each stitching mark. The coordinate vectors of all stitching marks on the wafer can form one coordinate matrix. t in Equation 2 and t in Equation 3 are the same group of parameters, which can be called a parameter set. Stitch_loc j After calculating t, the compensation data associated with each stitching mark can be obtained. The compensation data may be a vector including a magnitude and a direction.

[0035] Based on Equation 1, Equation 2, and Equation 3, the loss value L 2 A parameter set t can be calculated and found that satisfies a preset condition. The parameter set t can be read by a semiconductor device (e.g., an aligner) to calibrate the overlay offset and stitching offset during the manufacturing of the wafer.

[0036] In some embodiments, to calculate the parameter set t, a target loss value L target and loss threshold L threshold For example, the obtained parameter set t may satisfy the following condition:

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[0037] In some embodiments, the weight values ​​α and β may be further adjusted depending on the number of overlay marks and the number of stitching marks. In some embodiments, Equation 5 can be rewritten as the following equation depending on the number of overlay marks and the number of stitching marks:

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[0038] FIG. 3(a) is a schematic diagram of measurement data according to one embodiment of the present invention. FIG. 3(a) is a schematic diagram of measurement data associated with an area 100 on a wafer. The measurement data represents the magnitude and direction that needs to be calibrated / compensated for in the wafer manufacturing process. As shown in FIG. 3(a), overlay marks 108_1, 108_2, 108_3, 108_4, 108_5, 108_6 are located in the perimeter area 104 of the area 100. Stitching marks 110_1, 110_2 are located at the intersections of the first sub-area 106a and the second sub-area 106b.

[0039] The measurement data associated with overlay mark 108_1 is the vector

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[0040] Figure 3(b) is a schematic diagram of compensation data associated with an area 100 on a wafer according to one embodiment of the present invention.

[0041] The compensation data associated with overlay mark 108_1 is represented by vector OVL1. The compensation data associated with overlay mark 108_2 is represented by vector OVL2. The compensation data associated with overlay mark 108_3 is represented by vector OVL3. The compensation data associated with overlay mark 108_4 is represented by vector OVL4. The compensation data associated with overlay mark 108_5 is represented by vector OVL5. The compensation data associated with overlay mark 108_6 is represented by vector OVL6.

[0042] The compensation data associated with stitching mark 110_1 is represented by vector Stitch1, and the compensation data associated with stitching mark 110_2 is represented by vector Stitch2.

[0043] The vectors OVL1, OVL2, OVL3, OVL4, OVL5, and OVL6 shown in FIG. 3(b) are vectors shown in FIG. 3(a).

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[0044] The magnitudes and directions of the vectors shown in FIG. 3(b) are merely examples and may vary depending on actual conditions in different wafer fabrication processes.

[0045] Figure 4 is a flow diagram of a method for manufacturing an integrated circuit according to an embodiment of the present invention. The flow diagram of Figure 4 can be used to manufacture wafer W1 shown in Figure 1. The flow diagram of Figure 4 can be used to manufacture an integrated circuit in region 100 shown in Figure 2(a). The flow diagram of Figure 3 can be used to manufacture an integrated circuit in region 200 shown in Figure 2(b). In some embodiments, the steps of the method of Figure 4 may be operated by a semiconductor manufacturing tool. In some embodiments, the steps of the method of Figure 4 may be operated by an aligner.

[0046] As shown in FIG. 4, in operation S10, a loss value is calculated according to first measurement data and first compensation data associated with a first group of marks on the wafer, and second measurement data and second compensation data associated with a second group of marks on the wafer.

[0047] In some embodiments, in operation S10, the loss value L 2 are vectors correlating with overlay marks 108_1, 108_2, 108_3, 108_4, 108_5, and 108_6, respectively.

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[0048] In operation S20, a target loss value and a loss threshold are set. In some embodiments, the target loss value L target and loss threshold L threshold may be set. In operation S30, a first set of parameters associated with the first compensation data and the second compensation data is adjusted such that the difference between the loss value and the target loss value is less than a loss threshold. 2 and the target loss value L 2 target The difference between this and the loss threshold L thresholdParameter set t is adjusted so that the compensation data OVL of the overlay mark is smaller than OVL (see Equation 4). i According to Equation 3, the parameter set t is the compensation data Stitch j It is correlated with.

[0049] In operation S40, the overlay offset on the wafer is calibrated according to the first parameter set. In some embodiments, the overlay offset on the wafer is calibrated according to the parameter set t obtained in operation S30.

[0050] In operation S50, the stitching offset on the wafer is calibrated according to the first parameter set. In some embodiments, the stitching offset on the wafer is calibrated according to the parameter set t obtained in operation S30. It should be noted that although the order of operations S40 and S50 is shown in FIG. 4, in some embodiments, operations S40 and S50 may be performed simultaneously, and in some embodiments, operation S50 may be performed before operation S40.

[0051] FIG. 5(a) is a vector diagram of the overlay offset after performing the method shown in FIG. 4. Specifically, FIG. 5(a) is a diagram of the remaining offset vector that needs to be compensated after performing calibration using the method shown in FIG. 4. As can be seen from FIG. 5(a), the offset vector value of the overlay mark is already very small. That is, after compensation, the offset value between the overlay mark on the current layer of the wafer and the overlay mark on the one or two previous layers is already greatly reduced, thereby greatly reducing the overlay offset on the wafer.

[0052] FIG. 5(b) is a vector diagram of the stitching offset obtained after performing the method shown in FIG. 4. As can be seen from FIG. 5(b), after compensation, the value of the stitching offset between regions on the wafer is very small and can be almost ignored. That is, after compensation, the stitching offset between regions is also greatly reduced.

[0053] FIG. 6 is a flow diagram of a method for manufacturing an integrated circuit according to a comparative embodiment of the present invention. In operation S60, a first model is applied to measurement data associated with the overlay marks on the wafer to obtain a first parameter set, e.g., a conventional overlay model (e.g., a wafer-level model or an area-level model) is applied to measurement data associated with all overlay marks on the wafer to obtain a parameter set Ds1.

[0054] In operation S62, the overlay offset on the wafer is calibrated according to the first parameter set. For example, the overlay offset on the wafer is compensated according to the parameter set Ds1. Specifically, the semiconductor device (e.g., aligner) can compensate the overlay offset between the current layer of the wafer and one or two previous layers according to the parameter set Ds1.

[0055] In operation S64, the stitching offset on the wafer is calibrated according to the first parameter set. For example, the stitching offset on the wafer is compensated according to the parameter set Ds1. It should be noted that the parameter set Ds1 is obtained according to the conventional overlay model, so that the operation S64 of compensating the stitching offset according to the parameter set Ds1 cannot achieve a sufficient calibration effect.

[0056] FIG. 7 is a flow diagram of a method for manufacturing an integrated circuit according to a comparative embodiment of the present invention.

[0057] In act S70, a second model is applied to measurement data associated with the stitching marks on the wafer to obtain a second set of parameters.

[0058] For example, a conventional stitching model (eg, a wafer-level model or an area-level model) is applied to measurement data associated with all stitching marks on the wafer to obtain a parameter set Ds2. In operation S72, the stitching offset on the wafer is calibrated according to the second parameter set. For example, the stitching offset on the wafer is compensated according to the parameter set Ds2. Specifically, the semiconductor device (e.g., an aligner) can compensate for the stitching offset between regions on the wafer according to the parameter set Ds2.

[0059] In operation S74, the overlay offset on the wafer is calibrated according to the second parameter set. For example, the overlay offset on the wafer is compensated according to the parameter set Ds2. It should be noted that the parameter set Ds2 is obtained according to the conventional stitching model, so that the operation S74 of compensating the overlay offset according to the parameter set Ds2 cannot achieve a sufficient calibration effect.

[0060] Figure 8(a) is a vector diagram of an overlay offset after performing the method shown in Figure 6. Specifically, Figure 8(a) is a schematic diagram of the remaining offset vectors that need to be compensated after compensating for the overlay offset on a wafer (i.e., operation S62) using the method shown in Figure 6. Compared with the offset vector diagram in Figure 5(a), the offset vector values ​​shown in Figure 8(a) are still relatively large.

[0061] Fig. 8(b) is a vector diagram of the stitching offset obtained after performing the method shown in Fig. 6. Specifically, Fig. 8(b) is a schematic diagram of the remaining offset vectors that need to be compensated after performing the method shown in Fig. 6 to compensate for the stitching offset on the wafer (i.e., operation S64). Compared with the offset vector diagram shown in Fig. 5(b), the offset vector values ​​shown in Fig. 8(b) are still relatively large.

[0062] Similarly, after performing the method shown in Figure 7, the remaining offset vectors that need to be compensated in the vector diagram of the overlay offset are greater than the offset vector values ​​shown in Figure 5(a). Similarly, after performing the method shown in Figure 7, the remaining offset vectors that need to be compensated in the vector diagram of the stitching offset are greater than the offset vector values ​​shown in Figure 5(b).

[0063] [Table 1] As can be seen from Table 1, compared to FIG. 8(a), the values ​​of the remaining overlay offset obtained after compensation in FIG. 5(a) are reduced by 50% and 57% (50% horizontally and 57% vertically). That is, compared to the method shown in FIG. 6, the method shown in FIG. 4 significantly reduces the overlay offset on the wafer.

[0064] Furthermore, compared to FIG. 8(b), the remaining stitching offset values ​​obtained after compensation in FIG. 5(b) are both reduced by 95% (95% horizontally and 95% vertically). That is, compared to the method shown in FIG. 6, the method shown in FIG. 4 significantly reduces the stitching offset on the wafer.

[0065] Therefore, the efficiency of compensating for overlay offsets and stitching offsets of the method shown in Figure 4 is much higher than that of the method shown in Figure 6. Similarly, the efficiency of compensating for overlay offsets and stitching offsets of the method shown in Figure 4 is also much higher than that of the method shown in Figure 7.

[0066] Moreover, some other embodiments of the present invention further provide a system for manufacturing an integrated circuit as shown in FIG. 9. The system includes a processor, a non-volatile computer readable medium storing computer executable instructions, and a handler. The non-volatile computer readable medium storing computer executable instructions may be coupled to the processor. The handler may be configured to support a wafer. The processor can execute the computer executable instructions to perform the method for manufacturing an integrated circuit on a wafer as shown in FIG. 4, FIG. 6, and FIG. 7. The present invention proposes a method for obtaining a calibration by considering both stitch compensation and overlay compensation. Both overlay offset and stitching offset can be significantly reduced by using the method for manufacturing an integrated circuit proposed in the present invention.

[0067] The processor may be any suitable processor known in the art, such as a parallel processor, and may be part of a personal computer system, an image computer, a mainframe computer system, a workstation, a network appliance, an Internet appliance, or other device. In some embodiments, the various steps, functions, and / or operations of the systems and subsystems therein and methods disclosed herein are performed by one or more of electronic circuits, logic gates, multiplexers, programmable logic devices, ASICs, analog or digital controls / switches, microcontrollers, or computing systems. For example, the various steps described throughout this disclosure may be performed by a single processor (or computer system), or alternatively, by multiple processes (or multiple computer systems). As such, the above description should not be construed as a limitation on the disclosure, but merely as an example.

[0068] The system may include a detector that can image or otherwise measure features on the wafer using a light beam or an electron beam.

[0069] It should be noted that throughout this specification, the phrase "one embodiment of the present invention" or similar terminology is intended for its purposes to indicate that a particular feature, structure, or characteristic described in conjunction with another embodiment is included in at least one embodiment, and is not necessarily present in all embodiments. Thus, corresponding appearances of the phrase "one embodiment of the present invention" or similar terminology throughout this specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics in any particular embodiment can be combined in any suitable manner with one or more other embodiments.

[0070] The technical contents and technical features of the present invention have been disclosed above. However, those skilled in the art can still make substitutions and modifications based on the teachings and disclosures of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the contents disclosed in the embodiments, but should include various substitutions and modifications without departing from the present invention, and be encompassed by the claims of this patent.

Claims

1. 1. A method for manufacturing an integrated circuit, comprising: calculating, using a processor, a loss value according to first measurement data and first compensation data associated with a first group of marks on the wafer and second measurement data and second compensation data associated with a second group of marks on the wafer; using the processor to adjust a first set of parameters associated with the first compensation data and the second compensation data such that a difference between the loss value and a target loss value is less than a loss threshold; Including, calibrating an overlay offset on the wafer according to the first parameter set; calibrating a stitching offset on the wafer according to the first parameter set; The method of claim 1, further comprising:

2. 2. A method for manufacturing an integrated circuit as recited in claim 1, wherein the first group of marks is located on the periphery of a first area and a second area on the wafer, and the second group of marks is located adjacent an intersection of the first area and the second area.

3. 2. The method for manufacturing an integrated circuit according to claim 1, characterized in that the loss value is further calculated according to a first weight value associated with the first group of marks and a second weight value associated with the second group of marks.

4. 4. A method for manufacturing an integrated circuit as recited in claim 3, wherein the first weight value is associated with a number of marks in the first group and the second weight value is associated with a number of marks in the second group.

5. 4. A method for manufacturing an integrated circuit as recited in claim 3, wherein said first weight value is inversely proportional to the number of marks in said first group and said second weight value is inversely proportional to the number of marks in said second group.

6. 2. A method for manufacturing an integrated circuit as recited in claim 1, wherein the first compensation data is obtained according to the first parameter set and a first coordinate matrix associated with the first group of marks.

7. 2. The method for manufacturing an integrated circuit according to claim 1, wherein the second compensation data is obtained according to the first parameter set and a second coordinate matrix associated with the second group of marks.

8. 10. A method for manufacturing an integrated circuit according to claim 1, comprising the steps of: the first compensation data includes a first group of components associated with the first group of marks in a first direction and a second group of components associated with the first group of marks in a second direction; A method comprising:

9. 10. A method for manufacturing an integrated circuit according to claim 1, comprising the steps of: the second compensation data includes a first group of components associated with the second group of marks in a first direction and a second group of components associated with the second group of marks in a second direction; A method comprising:

10. 10. A method for manufacturing an integrated circuit according to claim 1, comprising the steps of: the first measurement data includes a first group of components associated with the first group of marks in a first direction and a second group of components associated with the first group of marks in a second direction; A method comprising:

11. 10. A method for manufacturing an integrated circuit according to claim 1, comprising the steps of: the second measurement data includes a first group of components associated with the second group of marks in a first direction and a second group of components associated with the second group of marks in a second direction; A method comprising:

12. 1. A method for manufacturing an integrated circuit, comprising: The following formula: [0010] calculating a loss value for the wafer using a processor according to During the ceremony, L ２ is the loss value, O.V.L. ｉ is a first compensation data associated with a first group of marks on the wafer, [0025] is a first measurement data associated with the first group of marks, Stitch ｊ is second compensation data associated with a second group of marks on the wafer; [0030] is second measurement data associated with the second group of marks, α is a first weight value, β is the second weight value, Including steps, adjusting a first set of parameters associated with the first compensation data and the second compensation data such that a difference between the loss value and a target loss value is less than a loss threshold; calibrating an overlay offset on the wafer according to the first parameter set; calibrating a stitching offset on the wafer according to the first parameter set; The method of claim 1, further comprising:

13. 13. A method for manufacturing an integrated circuit as recited in claim 12, characterized in that the first compensation data is obtained according to the first parameter set and a first coordinate matrix associated with the first group of marks, and the second compensation data is obtained according to the first parameter set and a second coordinate matrix associated with the second group of marks.

14. 13. A method for manufacturing an integrated circuit according to claim 12, comprising the steps of: The first weight value is [0045] and The second weight value is [0050] and S ｖｏｌ is a specification parameter associated with the overlay offset on the wafer, S ｓｔｉｔｃｈ is a specification parameter associated with a stitching offset on the wafer; A method comprising:

15. 13. A method for manufacturing an integrated circuit according to claim 12, comprising the steps of: The first weight value is [006] and The second weight value is [0070] and S ｖｏｌ is a specification parameter associated with the overlay offset on the wafer, S ｓｔｉｔｃｈ is a specification parameter associated with a stitching offset on the wafer, n is the number of marks in the first group; m is the number of marks in the second group; A method comprising:

16. 15. A method for manufacturing an integrated circuit according to claim 14, comprising the steps of: [0080] calculating a loss value using the processor according to During the ceremony, OVLX ｉ is compensation data associated with the first group of marks in a first direction, [0097] is measurement data associated with the first group of marks in the first direction, OVLY ｉ is compensation data associated with the first group of marks in a second direction, [0089] is measurement data associated with the first group of marks in the second direction, Stitch X ｊ is compensation data associated with the second group of marks in the first direction, ##EQU00011## is measurement data associated with the second group of marks in the first direction, Stitch Y ｊ is compensation data associated with the second group of marks in the second direction, ##EQU00012## is measurement data associated with the second group of marks in the second direction, S ｖｏｌＸ is a specification parameter associated with an overlay offset in the first direction on the wafer, S ｖｏｌＹ is a specification parameter associated with the overlay offset in the second direction on the wafer, S ｓｔｉｔｃｈＸ is a specification parameter associated with a stitching offset in the first direction on the wafer, S ｓｔｉｔｃｈＹ is a specification parameter associated with the stitching offset in the second direction on the wafer; The method further comprising the steps of:

17. 1. A system for manufacturing integrated circuits, comprising: A processor; a non-transitory computer readable medium storing computer executable instructions and coupled to the processor; a handler configured to support a wafer; Equipped with The processor executes the computer-executable instructions to calculating a loss value according to first measurement data and first compensation data associated with a first group of marks on the wafer and second measurement data and second compensation data associated with a second group of marks on the wafer; adjusting a first set of parameters associated with the first compensation data and the second compensation data such that a difference between the loss value and a target loss value is less than a loss threshold; calibrating an overlay offset on the wafer according to the first set of parameters; calibrating a stitching offset on the wafer according to the first parameter set; A system characterized in that

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