Charge detection device and charge detection method in semiconductor manufacturing

Abstract

Provided is a charge detection apparatus and a charge detection method that can appropriately evaluate damage to a semiconductor device, including whether the charge generated during a semiconductor process is positive or negative. [Solution] The device comprises an antenna structure 12, a diode, and a MOSFET 10, the diode including a first diode 14 connected between the antenna structure 12 and the gate of the MOSFET 10, a positive charge detection device 100 connected in the forward direction with respect to positive antenna charge generated in the antenna structure 12, and a negative charge detection device 100 connected in the forward direction with respect to negative antenna charge.

Description

[Technical field]

[0001] The present invention relates to an electric charge detection device and an electric charge detection method in the manufacture of semiconductor devices, and more particularly to a manufacturing evaluation device and a manufacturing evaluation method for evaluating plasma damage to semiconductor devices that occurs during a manufacturing process using plasma. [Background technology]

[0002] In the manufacturing of semiconductor devices, there are many processes that use plasma, such as plasma etching processes and plasma CVD processes. Plasma is a state in which positively charged ions and negatively charged electrons exist, and it is known that the charges in the plasma enter the conductors on the surface of semiconductor elements exposed to the plasma, and flow into the semiconductor substrate via the gate electrode and gate insulating film. This causes serious problems such as damage and destruction of the gate insulating film, deterioration of the reliability of LSIs, and a decrease in the yield rate.

[0003] A manufacturing evaluation apparatus for semiconductor devices is disclosed that has a plurality of first MOS devices on the same semiconductor substrate, each of which has an antenna exposed to plasma connected to its gate electrode and in which the voltage applied between the gate electrode and the substrate is limited to different values ​​by protective diodes connected in parallel to the gate electrode (Patent Document 1). It is also disclosed that the forward voltage Vf can be changed by the number of diodes connected in series by changing the forward voltage (Vf=V1 / V2 / V3) of the protective diodes. This makes it possible to evaluate the degree of damage to the MOSFET as the magnitude of Vf from the value of the forward voltage Vf.

[0004] Also disclosed is a field effect MOS transistor having a p-type semiconductor substrate, an n-type high concentration source / drain region formed on the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode made of a first polycrystalline silicon formed on the gate insulating film, a protection diode made of a second polycrystalline silicon formed on the semiconductor substrate, an intermediate insulating film formed on the gate electrode made of the first polycrystalline silicon and the protection diode made of the second polycrystalline silicon, a first metal electrode wiring connecting the gate electrode made of the first polycrystalline silicon and the protection diode made of the second polycrystalline silicon, and a second metal electrode wiring connecting the protection diode made of the second polycrystalline silicon and the semiconductor substrate (Patent Document 2). The protection diode made of the second polycrystalline silicon is insulated from the semiconductor substrate by the intermediate insulating film, and a parasitic pn junction is not formed. This makes it possible to connect the protection diode even in a depletion type NMOS transistor with a negative threshold. It is also said that the connection of the protection diode is not affected by the body / well voltage, and the forward voltage of the protection diode can be adjusted by the number of polysilicon diodes connected in series.

[0005] Also, a plasma-induced damage test structure has been disclosed that includes a MOS transistor under test, an antenna, a first pad, and a switch MOS transistor, the antenna being connected to the gate electrode of the MOS transistor under test, and the first pad being connected to the gate electrode of the MOS transistor under test via the switch MOS transistor (Patent Document 3). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2000-332076 [Patent Document 2] Patent Publication No. 2006-24601 [Patent Document 3] China Patent Application Publication No. 116417437 Summary of the Invention [Problem to be solved by the invention]

[0007] When plasma is used in the manufacturing process of semiconductor devices, the degree of damage caused to the device by electric charge varies depending on the process conditions and also on whether the electric charge is positive or negative. The technology in Patent Document 1 can only evaluate positive electric charge induced by the process. If a p-type MOSFET is used to evaluate negative electric charge, the degree of damage detected differs between n-type MOSFET and p-type MOSFET depending on the amount of electric charge, so the effects of positive and negative electric charge cannot be compared.

[0008] The technical purpose of Patent Document 2 is to prevent forward current from flowing through a protection diode connected to the gate of a depletion-type n-type MOSFET that requires a negative gate voltage to be applied for cutoff. If the protection diode is formed on the substrate and a PN junction is formed between the protection diode and the substrate, the forward voltage Vf can only be -0.7V. In Patent Document 2, two protection diodes are connected in series to set the forward voltage Vf to -1.4V. However, as in Patent Document 1, no consideration is given to distinguishing between positive and negative charges.

[0009] Patent Document 3 discloses only a configuration in which the gate of a MOS transistor and an antenna are directly connected, and does not disclose a configuration in which other components are connected between the gate of the MOS transistor and the antenna. [Means for solving the problem]

[0010] One aspect of the present invention is a charge detection device for evaluating damage due to charges generated during a semiconductor process, comprising: an antenna structure formed on a semiconductor substrate; a diode; and a MOSFET, wherein the diode includes a first diode, the first diode is connected between the antenna structure and a gate of the MOSFET, and is connected to be in a forward direction with respect to a positive antenna charge generated in the antenna structure for detecting a positive charge, or the first diode is connected between the antenna structure and a gate of the MOSFET, and is connected to be in a forward direction with respect to a negative antenna charge generated in the antenna structure for detecting a negative charge.

[0011] It is preferable that the diode further includes a second diode, which is connected between the antenna structure and a well or a body of the MOSFET and is connected in a reverse direction to a positive antenna charge generated in the antenna structure for positive charge detection, or the second diode is connected between the antenna structure and a body or a well of the MOSFET and is connected in a reverse direction to a negative antenna charge generated in the antenna structure for negative charge detection.

[0012] It is also preferable that a plurality of the first diodes are provided, and the plurality of the first diodes are connected in series.

[0013] It is also preferable that the diode is formed in a polysilicon layer insulated from the semiconductor substrate.

[0014] It is also preferable that the diode is formed on an SOI substrate, the diode is formed in an active region of the SOI substrate, and is insulated from the surroundings by an insulator and an element isolation region of the SOI substrate.

[0015] Another aspect of the present invention is a charge detection method using the charge detection device described above to evaluate damage caused by charges occurring during a process.

[0016] Here, it is preferable to determine the positive or negative polarity of the charge that caused the damage based on the connection direction of the diode connected to the damaged MOSFET.

[0017] It is also preferable to evaluate the extent of the damage based on the number of the first diodes connected in series to the damaged MOSFET.

[0018] The degree of damage is preferably evaluated by comparing the damage between n-type MOSFETs or between p-type MOSFETs.

[0019] Another aspect of the present invention is a charge detection device for evaluating damage caused by charges generated during a semiconductor process, comprising: a first antenna structure formed on a semiconductor substrate; an n-type MOSFET; a diode connected between the first antenna structure and a gate of the n-type MOSFET, the diode being connected in a forward direction with respect to a positive antenna charge generated in the first antenna structure for detecting a positive charge, or connected in a forward direction with respect to a negative antenna charge generated in the first antenna structure for detecting a negative charge; a second antenna structure formed on the semiconductor substrate; a p-type MOSFET; and another diode connected between the second antenna structure and a gate of the p-type MOSFET, the diode being connected in a forward direction with respect to a positive antenna charge generated in the second antenna structure for detecting a positive charge, or connected in a forward direction with respect to a negative antenna charge generated in the second antenna structure for detecting a negative charge. Effect of the Invention

[0020] According to the present invention, it is possible to provide a charge detection apparatus and a charge detection method that can appropriately evaluate damage to a semiconductor device during processing, regardless of whether the charge is positive or negative. [Brief description of the drawings]

[0021] [Figure 1]FIG. 1 is a diagram illustrating a configuration of a charge detection device according to a first embodiment. [Diagram 2] FIG. 1 is a diagram illustrating a configuration of a charge detection device according to a first embodiment. [Diagram 3] FIG. 1 is a diagram illustrating a configuration of a charge detection device according to a first embodiment. [Figure 4] FIG. 1 is a diagram illustrating a configuration of a charge detection device according to a first embodiment. [Diagram 5] 1 is a cross-sectional view illustrating a structure of a charge detection device according to a first embodiment. [Figure 6] FIG. 13 is a diagram illustrating a configuration of a charge detection device according to a second embodiment. [Figure 7] FIG. 13 is a diagram illustrating a configuration of a charge detection device according to a second embodiment. [Figure 8] FIG. 13 is a diagram illustrating a configuration of a charge detection device according to a second embodiment. [Figure 9] FIG. 13 is a diagram illustrating a configuration of a charge detection device according to a second embodiment. [Figure 10] FIG. 11 is a schematic cross-sectional view showing the structure of a charge detection device according to a second embodiment. [Figure 11] 5 is a schematic cross-sectional view showing another example of the structure of the charge detection device in the first embodiment. FIG. [Figure 12] 5A to 5C are diagrams illustrating a method for manufacturing the charge detection device according to the embodiment of the present invention. [Figure 13] 5 is a flowchart showing a charge detection process using the charge detection device according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] [First embodiment] 1 to 4 show the configuration of a charge detection device 100 according to a first embodiment. The charge detection device 100 includes a MOSFET 10, an antenna structure 12, and a first diode .

[0023] The charge detection device 100 can be used to detect positive charges and / or negative charges that may damage a semiconductor device in a process for forming the device. That is, the charge detection device 100 is used as a TEG (Test Element Group) used to evaluate the effect of charges (antenna charges) generated from the antenna structure 12 in a process for manufacturing a semiconductor element.

[0024] 1 shows a configuration in which an n-type MOSFET is used as a MOSFET 10 to detect positive charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and an antenna structure 12. The first diode 14 is connected in a forward direction from the antenna structure 12 to the gate electrode of the MOSFET 10. The source electrode of the MOSFET 10 is connected to the body or well.

[0025] In this structure, when a positive charge is induced in the antenna structure 12, the first diode 14 is forward biased by the positive charge, and a positive charge voltage is applied to the gate of the MOSFET 10. In contrast, when a negative charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the negative charge, and the application of a negative charge voltage to the gate of the MOSFET 10 is prevented.

[0026] 2 shows a configuration in which an n-type MOSFET is used as the MOSFET 10 to detect negative charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in a reverse direction from the antenna structure 12 to the gate electrode of the MOSFET 10. The source electrode of the MOSFET 10 is connected to the body or well.

[0027] In this structure, when a negative charge is induced in the antenna structure 12, the first diode 14 is forward biased by the negative charge, and a negative charge voltage is applied to the gate of the MOSFET 10. In contrast, when a positive charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the positive charge, and the application of a positive charge voltage to the gate of the MOSFET 10 is prevented.

[0028] 3 shows a configuration in which a p-type MOSFET is used as the MOSFET 10 to detect positive charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in a forward direction from the antenna structure 12 to the gate electrode of the MOSFET 10. The source electrode of the MOSFET 10 is connected to the body or well.

[0029] In this structure, when a positive charge is induced in the antenna structure 12, the first diode 14 is forward biased by the positive charge, and a positive charge voltage is applied to the gate of the MOSFET 10. In contrast, when a negative charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the negative charge, and the application of a negative charge voltage to the gate of the MOSFET 10 is prevented.

[0030] 4 shows a configuration in which a p-type MOSFET is used as the MOSFET 10 to detect negative charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in a reverse direction from the antenna structure 12 to the gate electrode of the MOSFET 10. The source electrode of the MOSFET 10 is connected to the body or well.

[0031] In this structure, when a negative charge is induced in the antenna structure 12, the first diode 14 is forward biased by the negative charge, and a negative charge voltage is applied to the gate of the MOSFET 10. In contrast, when a positive charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the positive charge, and the application of a positive charge voltage to the gate of the MOSFET 10 is prevented.

[0032] 1 to 4, by changing the number of first diodes 14 connected in series, it is possible to adjust the forward voltage Vf of all the first diodes 14 connected from the antenna structure 12 to the MOSFET 10. By providing MOSFETs with different numbers of first diodes 14 connected in series, it is possible to investigate the degree of influence of plasma from the degree of damage to each MOSFET.

[0033] 1 to 4 may be formed as a TEG on the same semiconductor substrate. Also, each charge detection device 100 may be formed as a TEG on the same semiconductor substrate by changing the number of first diodes 14 connected in series.

[0034] The positive and negative polarities of the charge can be detected in both the n-type MOSFET and the p-type MOSFET. The degree of damage inflicted varies depending on whether the MOSFET 10 is an n-type MOSFET or a p-type MOSFET. For example, the n-type MOSFET may not be damaged, and only the p-type MOSFET may be damaged. Conversely, only the n-type MOSFET may be damaged, and no damage may occur in the p-type MOSFET. Therefore, it is important to measure both the n-type MOSFET and the p-type MOSFET to confirm the degree of damage.

[0035] It is preferable that the first diode 14 is formed in a region insulated from the substrate, rather than inside the semiconductor substrate, so that a parasitic junction in the first diode 14 is eliminated, and it is possible to prevent the formation of a leakage current path other than the antenna for the charge during the process.

[0036] 5 shows a cross-sectional structure of the charge detection device 100 according to the first embodiment. The arrangement, size, and other aspects of each part in FIG. 5 have been modified to make the structure of the charge detection device 100 easier to understand.

[0037] The charge detection device 100 can be manufactured by a normal CMOS process. A p-type well 22p and an n-type well 22n are formed in a p-type substrate 20. The elements are insulated from each other by a buried insulating layer (STI: shallow trench isolation) 24. An n-type MOSFET 10n is formed in the p-type well 22p. A p-type MOSFET 10p is formed in the n-type well 22n. A gate insulating film is formed on the surface of the substrate 20. In FIG. 5, the gaps between the surface of the substrate 20 and the gate electrode, the first diode 14, and the second diode 16 indicate insulating films.

[0038] 5, two first diodes 14a and 14b are connected in series between the antenna structure 12a and the gate electrode G of the n-type MOSFET 10n. The first diodes 14a and 14b are connected in the forward direction from the antenna structure 12a to the gate electrode G of the n-type MOSFET 10n.

[0039] In addition, two first diodes 14c and 14d are connected in series between the antenna structure 12b and the gate electrode G of the p-type MOSFET 10p. The first diodes 14c and 14d are connected in the opposite direction from the antenna structure 12b toward the gate electrode G of the p-type MOSFET 10p.

[0040] The first diodes 14a to 14d are made of polysilicon. The polysilicon can be formed simultaneously with the polysilicon constituting the gate electrodes of the n-type MOSFET 10n and the p-type MOSFET 10p, for example. The first diodes 14a to 14d can be formed by adding n-type dopants and p-type dopants only to necessary regions of the polysilicon using a plurality of masks. For example, a doping process of the n+ gate electrodes and a doping process of the p+ gate electrodes of the n-type MOSFET 10n and the p-type MOSFET 10p can be utilized.

[0041] However, other special polysilicon layers may be used, and other special doping processes may be applied. Also, by changing the regions to which the n-type dopants and p-type dopants are added, it is possible to form the first diode 14 connected in the opposite direction to that shown in FIG. 5.

[0042] By providing two polysilicon first diodes 14a and 14b in series with a forward voltage Vf, the charging voltage for the n-type MOSFET 10n is reduced by 2Vf. By connecting one, two, ...n first diodes 14 in series, the damage level in the manufacturing process using plasma can be examined from the damage inflicted on the n-type MOSFET 10n. Similarly, by providing two polysilicon first diodes 14c and 14d in series with a forward voltage Vf, the charging voltage for the p-type MOSFET 10p is reduced by 2Vf. By connecting one, two, ...n first diodes 14 in series, the damage level in the manufacturing process using plasma can be examined from the damage inflicted on the p-type MOSFET 10p.

[0043] [Second embodiment] 6 to 9 show the configuration of a charge detection device 200 in the second embodiment. The charge detection device 200 includes a MOSFET 10, an antenna structure 12, a first diode 14, and a second diode 16.

[0044] The charge detection apparatus 200 can be used to detect positive and / or negative charges that may be damaging to a semiconductor device during the process of forming the device.

[0045] 6 shows a configuration in which an n-type MOSFET is used as the MOSFET 10 to detect positive charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in a forward direction from the antenna structure 12 to the gate electrode of the MOSFET 10. Furthermore, a second diode 16 is connected between the connection point of the antenna structure 12 and the first diode 14 and the body or well. The second diode 16 is connected in a forward direction from the body or well to the antenna structure 12. The source electrode of the MOSFET 10 is connected to the body or well.

[0046] In this structure, when a positive charge is induced in the antenna structure 12, the first diode 14 is forward biased by the positive charge, and a positive charge voltage is applied to the gate of the MOSFET 10. At this time, the second diode 16 is in a reverse bias state. On the other hand, when a negative charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the negative charge, and the application of a negative charge voltage to the gate of the MOSFET 10 is prevented. At this time, the second diode 16 is in a forward bias state, and the negative charge induced in the antenna structure 12 is alleviated.

[0047] 7 shows a configuration in which an n-type MOSFET is used as the MOSFET 10 to detect negative charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in a reverse direction from the antenna structure 12 to the gate electrode of the MOSFET 10. Furthermore, a second diode 16 is connected between the connection point of the antenna structure 12 and the first diode 14 and the body or well. The second diode 16 is connected in a reverse direction from the body or well to the antenna structure 12. The source electrode of the MOSFET 10 is connected to the body or well.

[0048] In this structure, when a negative charge is induced in the antenna structure 12, the first diode 14 is forward biased by the negative charge, and a negative charge voltage is applied to the gate of the MOSFET 10. At this time, the second diode 16 is in a reverse bias state. On the other hand, when a positive charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the positive charge, and the application of a positive charge voltage to the gate of the MOSFET 10 is prevented. At this time, the second diode 16 is in a forward bias state, and the positive charge induced in the antenna structure 12 is alleviated.

[0049] 8 shows a configuration in which a p-type MOSFET is used as the MOSFET 10 to detect positive charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in a forward direction from the antenna structure 12 to the gate electrode of the MOSFET 10. Furthermore, a second diode 16 is connected between the connection point of the antenna structure 12 and the first diode 14 and the body or well. The second diode 16 is connected in a forward direction from the body or well to the antenna structure 12. The source electrode of the MOSFET 10 is connected to the body or well.

[0050] In this structure, when a positive charge is induced in the antenna structure 12, the first diode 14 is forward biased by the positive charge, and a positive charge voltage is applied to the gate of the MOSFET 10. At this time, the second diode 16 is in a reverse bias state. On the other hand, when a negative charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the negative charge, and the application of a negative charge voltage to the gate of the MOSFET 10 is prevented. At this time, the second diode 16 is in a forward bias state, and the negative charge induced in the antenna structure 12 is alleviated.

[0051] 9 shows a configuration in which a p-type MOSFET is used as the MOSFET 10 to detect negative charges. A first diode 14 is connected between the gate electrode of the MOSFET 10 and the antenna structure 12. The first diode 14 is connected in a reverse direction from the antenna structure 12 to the gate electrode of the MOSFET 10. Furthermore, a second diode 16 is connected between the connection point of the antenna structure 12 and the first diode 14 and the body or well. The second diode 16 is connected in a reverse direction from the body or well to the antenna structure 12. The source electrode of the MOSFET 10 is connected to the body or well.

[0052] In this structure, when a negative charge is induced in the antenna structure 12, the first diode 14 is forward biased by the negative charge, and a negative charge voltage is applied to the gate of the MOSFET 10. At this time, the second diode 16 is in a reverse bias state. On the other hand, when a positive charge is induced in the antenna structure 12, the first diode 14 is reverse biased by the positive charge, and the application of a positive charge voltage to the gate of the MOSFET 10 is prevented. At this time, the second diode 16 is in a forward bias state, and the positive charge induced in the antenna structure 12 is alleviated.

[0053] According to the charge detection device 200 of the second embodiment, compared to the charge detection device 100 of the first embodiment, the effect of charges other than those of the desired polarity can be suppressed by the action of the second diode 16.

[0054] 6 to 9, by changing the number of first diodes 14 connected in series, it is possible to adjust the forward voltage Vf of all the first diodes 14 connected from the antenna structure 12 to the MOSFET 10. By providing MOSFETs with different numbers of first diodes 14 connected in series, it is possible to investigate the degree of influence of plasma from the degree of damage to each MOSFET.

[0055] However, since the second diode 16 serves as a bypass path for reverse charge, it is more suitable to use it alone rather than in series.

[0056] 6 to 9 may be formed as a TEG on the same semiconductor substrate. Also, each charge detection device 200 may be formed as a TEG on the same semiconductor substrate by changing the number of first diodes 14 and second diodes 16 connected in series.

[0057] The polarity of the charge can be detected in both the n-type MOSFET and the p-type MOSFET. The degree of damage inflicted varies depending on whether the MOSFET 10 is an n-type MOSFET or a p-type MOSFET. For example, the n-type MOSFET may not be damaged, and only the p-type MOSFET may be damaged. Conversely, only the n-type MOSFET may be damaged, and no damage may occur in the p-type MOSFET.

[0058] It is preferable that the first diode 14 and the second diode 16 are formed in an area insulated from the semiconductor substrate, which suppresses parasitic junctions in the first diode 14 and the second diode 16 and prevents the formation of a leakage current path for charges during the process.

[0059] Fig. 10 shows a cross-sectional structure of a charge detection device 200 according to the second embodiment. The arrangement, size, and other aspects of each part in Fig. 10 have been modified to make the structure of the charge detection device 200 easier to understand.

[0060] The charge detection device 200 can be manufactured by a normal CMOS process. A p-type well 22p and an n-type well 22n are formed in a p-type substrate 20. The elements are insulated from each other by a buried insulating layer (STI: shallow trench isolation) 24. An n-type MOSFET 10n is formed in the p-type well 22p. A p-type MOSFET 10p is formed in the n-type well 22n. A gate insulating film is formed on the surface of the substrate 20. In FIG. 10, the gaps between the surface of the substrate 20 and the gate electrode, the first diode 14, and the second diode 16 indicate insulating films.

[0061] 10, one first diode 14a is connected between the antenna structure 12a and the gate electrode G of the n-type MOSFET 10n. The first diode 14a is connected in a forward direction from the antenna structure 12a toward the gate electrode G of the n-type MOSFET 10n. In addition, one second diode 16a is connected between the antenna structure 12a and the body or well electrode B. The second diode 16a is connected in a reverse direction from the antenna structure 12a toward the body or well electrode B.

[0062] Furthermore, one first diode 14b is connected between the antenna structure 12b and the gate electrode G of the p-type MOSFET 10p. The first diode 14b is connected in a reverse direction from the antenna structure 12b toward the gate electrode G of the p-type MOSFET 10p. Furthermore, one second diode 16b is connected between the antenna structure 12b and the body or well electrode B. The second diode 16b is connected in a forward direction from the antenna structure 12b toward the body or well electrode B.

[0063] The first diodes 14a and 14b and the second diodes 16a and 16b are made of polysilicon. The polysilicon can be formed, for example, at the same time as the polysilicon constituting the gate electrodes of the n-type MOSFET 10n and the p-type MOSFET 10p. The first diodes 14a and 14b and the second diodes 16a and 16b can be formed by adding n-type dopants and p-type dopants to the polysilicon using multiple masks. For example, a doping process of the n+ gate electrodes and a doping process of the p+ gate electrodes of the n-type MOSFET 10n and the p-type MOSFET 10p can be used. However, other special polysilicon layers may be used. Also, other doping processes may be applied. Also, by changing the regions to which the n-type dopants and the p-type dopants are added, the first diode 14 and the second diode 16 connected in the opposite direction to that in FIG. 10 can be formed.

[0064] Note that a plurality of first diodes 14a may be connected in series. By connecting a plurality of first diodes 14a in series, the damage level in the manufacturing process using plasma can be examined from the damage given to the n-type MOSFET 10n. However, since the second diode 16a serves as a bypass path for the reverse charge, it is more suitable to use only one diode rather than connecting them in series.

[0065] Alternatively, multiple first diodes 14b may be connected in series. By connecting multiple first diodes 14b in series, the damage level in the manufacturing process using plasma can be examined from the damage inflicted on the p-type MOSFET 10p. However, since the second diode 16a serves as a bypass path for the reverse charge, it is more suitable to use only one diode rather than connecting them in series.

[0066] [Configuration using SOI substrate] FIG. 11 shows a cross-sectional structure of a charge detection device 100 in the case where the present invention is applied to an SOI-CMOS.

[0067] A buried oxide layer (BOX: Buried Oxide) 26 is provided on the p-type substrate 20. A p-type well 22p and an n-type well 22n are formed on the buried oxide layer 26. An n-type MOSFET 10n is formed in the p-type well 22p. A p-type MOSFET 10p is formed in the n-type well 22n. The elements are insulated from each other by a buried insulating layer (STI: Shallow Trench Isolation). A gate insulating film is formed on the surface of the substrate 20. In FIG. 11, the gap between the substrate 20 and the gate electrode indicates an insulating film. Note that several layout ideas are known for taking out the body or well electrode in SOI-CMOS, but the details are not shown in FIG. 11.

[0068] 11, two first diodes 14a and 14b are connected between the antenna structure 12a and the gate electrode G of the n-type MOSFET 10n. The first diodes 14a and 14b are connected in a forward direction from the antenna structure 12a toward the gate electrode G of the n-type MOSFET 10n. The first diodes 14a and 14b are formed in a region of the n-type well 22n that is electrically insulated from other elements by the BOX and STI.

[0069] Two first diodes 14c and 14d are connected between the antenna structure 12b and the gate electrode G of the p-type MOSFET 10p. The first diodes 14c and 14d are connected in a forward direction from the antenna structure 12b toward the gate electrode G of the p-type MOSFET 10p. The first diodes 14c and 14d are formed in a region of a p-type well 22p that is electrically insulated from other elements in the SOI.

[0070] The charge detection device 200 can also be applied to SOI CMOS. That is, similar to the configuration shown in Fig. 11, a buried oxide layer 26 is provided in the substrate 20 to form an SOI structure, and the first diode 14 and the second diode 16 are formed in the SOI structure to form the charge detection device 200.

[0071] In this way, when SOI is used, by forming the first diode 14 and the second diode 16 in the bulk of the semiconductor substrate, parasitic junctions in the first diode 14 and the second diode 16 are suppressed, and leakage current can be suppressed.

[0072] [Manufacturing method] 12 shows a method for manufacturing the charge detection device 100. Hereinafter, the method for manufacturing the charge detection device 100 will be described with reference to FIG.

[0073] First, as shown in FIG. 12(a), a buried insulating layer 24, which is an element isolation region, is formed in a p-type semiconductor substrate 20. The buried insulating layer 24 can be STI (Shallow Trench Isolation). The buried insulating layer 24 is formed to a depth of, for example, 300 nm. Next, after forming a mask by photolithography or the like, a p-type dopant is ion-implanted into the substrate 20 to form a p-type well 22p (PW). For example, boron (B) is implanted at 270 keV with a concentration of 2.0×10 13 / cm2, 8.0×10 at 120 keV 12 / cm 2 and 2 × 10 at 40 keV 12 / cm2 is implanted in multiple steps to form a p-type well 22p. Next, after forming a mask by photolithography or the like, an n-type dopant is ion-implanted into the substrate 20 to form an n-type well 22n (NW). For example, phosphorus (P) is implanted at 2.0×10 13 / cm 2 , 8.0 × 10 at 240 keV 12 / cm 2 and 2 × 10 at 60 keV 12 / cm 2 The n-type well 22n is formed by implanting ions in multiple steps. However, the dopant concentrations and dopant profiles of the p-type well 22p and the n-type well 22n are not limited to these, and may be any that function as the p-type well 22p and the n-type well 22n.

[0074] Next, a gate insulating film for the n-type MOSFET 10n and the p-type MOSFET 10p is formed on the surface of the substrate 20. The gate insulating film can be formed by, for example, an oxynitridation method. The thickness of the gate insulating film is preferably, for example, 3 nm. However, the method of forming the gate insulating film and its thickness are not limited to this, and may be appropriately set depending on the characteristics of the semiconductor element formed on the substrate 20. The gate insulating film may be formed of a silicon oxide film (SiO2), a silicon nitride film (SiN), a silicon oxynitride film (SiO x N y 12, the gap between the surface of the substrate 20 and the gate electrode, the first diode 14, and the second diode 16 is shown as the gap.

[0075] Subsequently, as shown in FIG. 12(b), polysilicon that will become the gate electrode G and the first diode 14 (14a to 14d) is formed. The polysilicon can be formed by chemical vapor deposition (CVD) or the like using a silicon-containing source gas such as silane (SiH4). The film thickness of the polysilicon can be, for example, 200 nm. The polysilicon is formed into a desired shape as the gate electrode G and the first diode 14 (14a to 14d) by applying photolithography and etching. However, the manufacturing method and film thickness of the polysilicon are not limited to this and may be appropriately set according to the characteristics of the semiconductor element to be formed.

[0076] Thereafter, the source region and drain region of the n-type MOSFET 10n, the n-type polysilicon gate, and the n-type region of the first polysilicon diode 14 (14a to 14b) are formed. For example, photolithography is used to implant arsenic (As) into desired regions at 3×10 ions with an ion implantation energy of 23 keV. 15 / cm 2 Next, the source and drain regions of the p-type MOSFET 10p, the p-type polysilicon gate, and the p-type region of the first polysilicon diode 14 (14a to 14d) are formed. For example, boron fluoride (BF2) is implanted at a concentration of 2×10 with an ion implantation energy of 13 keV. 15 / cm 2 However, the energy and dopant concentration of the ion implantation may be appropriately set according to the required characteristics of the device.

[0077] At this time, in order to have different concentrations in the polysilicon regions of the first diode 14 (14a to 14d) during n-type and p-type ion implantation, an additional process may be provided to perform the ion implantation separately.

[0078] Generally, cobalt silicide is formed as the gate electrode and the source and drain regions, but it is necessary to prevent silicidation in the region of the first diode 14 (14a to 14d). Therefore, for example, a silicon nitride layer (SiN layer) is deposited as a silicide protection layer, and the regions corresponding to the gate electrode G and the source and drain regions are etched to form openings, and then a silicidation process is performed, thereby preventing silicidation of the polysilicon constituting the first diode 14 (14a to 14d).

[0079] The process of forming the first diode 14 can also be applied to the process of forming the second diode 16 in the charge detection device 200 in the same manner.

[0080] 12(c), the steps of depositing an interlayer insulating film, drilling contact holes, filling plugs, CMP, a metal wiring step including a desired antenna pattern for forming the antenna structure 12, a contact electrode forming step, and an upper layer wiring step are performed. Furthermore, the charge detection device 100 is manufactured through a BEOL (Back End of Line) step. These steps can be performed in the same manner as the manufacturing steps of general semiconductor devices.

[0081] [Charge detection method] Hereinafter, a method for detecting electric charge from plasma in a manufacturing process of a semiconductor device using the charge detection device 100 will be described with reference to a flowchart of the electric charge detection method shown in FIG.

[0082] Charge detection processing is performed using a total of four types of charge detection devices 100, namely, two types of charge detection devices 100 using n-type MOSFETs 10 and two types of charge detection devices 100 using p-type MOSFETs 10, as shown in FIGS. 1 to 4.

[0083] In the first step S10, the amount of shift in the threshold voltage Vth of each of the n-type MOSFET 10 and the p-type MOSFET 10, the amount of reduction in the drain-source current, and the leakage current in the gate insulating film are measured.

[0084] In the second step S12, based on the measurement results, for example, in comparison between the charge detection device 100 of the n-type MOSFET 10 shown in Fig. 1 and the charge detection device 100 of the n-type MOSFET 10 shown in Fig. 2, if the damage to the charge detection device 100 of the n-type MOSFET 10 shown in Fig. 1 is large, it is found that charging due to positive charges has occurred. Conversely, if the damage to the charge detection device 100 of the n-type MOSFET 10 shown in Fig. 2 is large, it is found that charging due to negative charges has occurred.

[0085] Similarly, in comparing the charge detection device 100 of the p-type MOSFET 10 shown in Fig. 3 with the charge detection device 100 of the p-type MOSFET 10 shown in Fig. 4, it is found that charging due to positive charges has occurred if the damage of the charge detection device 100 of the p-type MOSFET 10 shown in Fig. 3 is greater. Conversely, it is found that charging due to negative charges has occurred if the damage of the charge detection device 100 of the p-type MOSFET 10 shown in Fig. 4 is greater.

[0086] At this time, a phenomenon may occur in which none of the n-type MOSFETs 10 are damaged, and only one of the p-type MOSFETs 10 is damaged. Conversely, a phenomenon may occur in which none of the p-type MOSFETs 10 are damaged, and only one of the n-type MOSFETs 10 is damaged. Therefore, in preparation for such a phenomenon, it is preferable to check for damage in the four types of charge detection devices 100 shown in FIGS. 1 to 4.

[0087] In the third step S14, when the positive or negative charge is determined, the charge level (degree) is evaluated based on the number of first diodes 14 connected in series. For example, if damage is found in the n-type MOSFET 10 shown in FIG. 1, the level of positive charge is determined according to the number of first diodes 14 connected in series to the MOSFET 10. As a specific example, if damage is found in the n-type MOSFET 10 in which three first diodes 14 are connected in series, and no damage is found in the n-type MOSFET 10 in which four first diodes 14 are connected in series, the intensity of the positive charge is determined to be level 3. The charge levels of the other types of charge detection devices 100 shown in FIGS. 2 to 4 can be evaluated in a similar manner.

[0088] When damage is observed in both the charge detection device 100 including the n-type MOSFET 10 and the charge detection device 100 including the p-type MOSFET 10, it is preferable to evaluate the charge level of both. However, since the degree of damage differs between the n-type and the p-type, when comparing the degree of the effect of the charge in different processes, it is preferable to perform the evaluation based on the degree of damage between the n-type charge detection devices 100 or the degree of damage between the p-type charge detection devices 100.

[0089] Moreover, when the four types of charge detection devices 200 shown in FIGS. 6 to 9 are used, the charge detection process can be performed in the same manner as above.

[0090] [Configuration of the invention] [Configuration 1] A charge detection device for evaluating damage caused by charges generated during a semiconductor process, comprising: The antenna structure is formed on a semiconductor substrate, and the antenna structure includes a diode and a MOSFET. the diode includes a first diode; the first diode is connected between the antenna structure and the gate of the MOSFET and is connected in a forward direction with respect to a positive antenna charge generated in the antenna structure for positive charge detection; or the first diode is connected between the antenna structure and a gate of the MOSFET, and is connected in a forward direction with respect to negative antenna charge generated in the antenna structure for negative charge detection. [Configuration 2] 2. The charge detection device according to claim 1, the diode further includes a second diode; the second diode is connected between the antenna structure and a body or well of the MOSFET and is connected in a direction opposite to a positive antenna charge generated in the antenna structure for positive charge detection; or the second diode is connected between the antenna structure and a body or well of the MOSFET, and is connected in a reverse direction with respect to a negative antenna charge generated in the antenna structure for detecting negative charges. [Configuration 3] The charge detection device according to any one of configurations 1 and 2, A plurality of the first diodes are provided, A charge detection device comprising a plurality of the first diodes connected in series. [Configuration 4] 4. The charge detection device according to any one of configurations 1 to 3, wherein the diode is formed in a polysilicon layer insulated from the semiconductor substrate. [Configuration 5] The charge detection device according to any one of configurations 1 to 3, It is formed on an SOI substrate, The charge detection device, wherein the diode is formed in an active region of the SOI substrate and is insulated from the surroundings by an insulator and an element isolation region of the SOI substrate. [Configuration 6] 6. A charge detection method, comprising: evaluating damage caused by charges occurring during a process, using the charge detection device according to any one of configurations 1 to 5. [Configuration 7] The charge detection method according to configuration 6, A charge detection method comprising: determining the positive or negative polarity of the charge that caused the damage based on the connection direction of the diode connected to the damaged MOSFET. [Configuration 8] The charge detection method according to any one of configurations 6 and 7, a charge detection method for evaluating a degree of damage based on the number of the first diodes connected in series with the damaged MOSFET; [Configuration 9] The charge detection method according to configuration 7, The charge detection method is characterized in that the degree of damage is evaluated by comparing damage between n-type MOSFETs or between p-type MOSFETs. [Configuration 10] A charge detection device for evaluating damage caused by charges generated during a semiconductor process, comprising: a first antenna structure formed on a semiconductor substrate; An n-type MOSFET and a diode connected between the first antenna structure and a gate of the n-type MOSFET, the diode being forward-connected to a positive antenna charge generated in the first antenna structure for positive charge detection, or forward-connected to a negative antenna charge generated in the first antenna structure for negative charge detection; a second antenna structure formed on the semiconductor substrate; A p-type MOSFET and another diode connected between the second antenna structure and the gate of the p-type MOSFET, the diode being forward-connected to a positive antenna charge generated in the second antenna structure for positive charge detection, or to a negative antenna charge generated in the second antenna structure for negative charge detection; A charge detection device comprising: [Explanation of symbols]

[0091] 10 MOSFET, 12 (12a, 12b) antenna structure, 14 (14a-14d) first diode, 16 (16a-16d) second diode, 20 substrate, 22n n-type well, 22p p-type well, 24 buried insulating layer, 26 buried oxide layer, 100, 200 charge detection device.

Claims

1. A charge detection device for evaluating damage caused by charges generated during a semiconductor process, comprising: The antenna structure is formed on a semiconductor substrate, and the antenna structure includes a diode and a MOSFET. the diode includes a first diode; The first diode is connected between the antenna structure and the gate of the MOSFET and is connected in a forward direction with respect to a positive antenna charge generated in the antenna structure for positive charge detection; or The charge detection device is characterized in that the first diode is connected between the antenna structure and the gate of the MOSFET, and is connected so as to be in a forward direction with respect to negative antenna charges generated in the antenna structure in order to detect negative charges.

2. 2. The charge detection device according to claim 1, The diode further includes a second diode, the second diode is connected between the antenna structure and a body or well of the MOSFET and is connected in a direction opposite to a positive antenna charge generated in the antenna structure for positive charge detection; or The charge detection device is characterized in that the second diode is connected between the antenna structure and the body or well of the MOSFET, and is connected in a reverse direction with respect to negative antenna charges generated in the antenna structure to detect negative charges.

3. 3. The charge detection device according to claim 1, A plurality of the first diodes are provided, A charge detection device comprising a plurality of the first diodes connected in series.

4. 2. The charge detection device according to claim 1, wherein the diode is formed in a polysilicon layer insulated from the semiconductor substrate.

5. 2. The charge detection device according to claim 1, formed on an SOI substrate, The charge detection device, wherein the diode is formed in an active region of the SOI substrate and is insulated from the surroundings by an insulator and an element isolation region of the SOI substrate.

6. 13. A charge detection method, comprising: evaluating damage caused by charges occurring during a process, using the charge detection device according to claim 1.

7. 7. The charge detection method according to claim 6, A charge detection method, comprising: determining the positive or negative polarity of the charge that caused the damage based on the connection direction of the diode connected to the damaged MOSFET.

8. The charge detection method according to claim 6 or 7, and evaluating the degree of damage based on the number of said first diodes connected in series with said damaged MOSFET.

9. 8. The charge detection method according to claim 7, The charge detection method is characterized in that the degree of damage is evaluated by comparing damage between n-type MOSFETs or between p-type MOSFETs.

10. A charge detection device for evaluating damage caused by charges generated during a semiconductor process, comprising: a first antenna structure formed on a semiconductor substrate; an n-type MOSFET; a diode connected between the first antenna structure and the gate of the n-type MOSFET, the diode being connected in a forward direction with respect to a positive antenna charge generated in the first antenna structure for detecting a positive charge, or being connected in a forward direction with respect to a negative antenna charge generated in the first antenna structure for detecting a negative charge; a second antenna structure formed on the semiconductor substrate; A p-type MOSFET; another diode connected between the second antenna structure and the gate of the p-type MOSFET, the diode being forward-connected to a positive antenna charge generated in the second antenna structure for positive charge detection, or forward-connected to a negative antenna charge generated in the second antenna structure for negative charge detection; A charge detection device comprising:

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