Method for verifying logic circuit, program for verifying logic circuit, and system for verifying logic circuit

Abstract

Provided is a technology with which it is possible for a user to stop an unnecessary function block and quickly execute a simulation of a logic circuit. This method for verifying whether or not there is an abnormality in a logic circuit includes: a step (S825) for extracting a clock signal and a resetting signal that are inputted to each of a plurality of function blocks included in a logic circuit; a step (S810) for referring to a test bench; s step for referring to a stoppability assessment table in which is stored information indicating whether each of the plurality of function blocks can be stopped within a test in which the test bench is used; and a step (S840, S845, S855) for stopping the clock signal and the resetting signal inputted to one or more function blocks that do not affect the activity of a function block being verified, in accordance with information acquired from the stoppability assessment table, and executing a test of the function block being verified based on the test bench.

Description

[Technical field]

[0001] The present disclosure relates to a technique for verifying a logic circuit, and more particularly to speeding up the verification of a logic circuit. [Background technology]

[0002] In the development of semiconductor products such as LSIs (Large Scale Integration) that have large-scale logic circuits, ASICs (Application Specific Integrated Circuits), FPGAs (Field Programmable Gate Arrays), etc., are often used. In either case, logic circuit simulators are used to verify the consistency of the logic circuits in the semiconductors.

[0003] However, in recent years, as the scale of semiconductor devices has increased, the increase in simulation time has become a problem, and therefore there is a demand for technology to shorten the simulation time for semiconductor logic circuits.

[0004] Regarding a technique for shortening the simulation time of a logic circuit, for example, Japanese Patent Laid-Open Publication No. 2006-185202 (Patent Document 1) discloses a circuit simulation device and method, which "describes in advance in test bench information a description of non-verification block information indicating the conditions for a block to be excluded from verification, or prepares in advance simulation results and activation conditions for each module, automatically detects blocks that are not subject to verification in the target circuit by a non-verification block information search means, generates circuit information for resource-saving simulation in which the non-verification block is described as a module as a dummy block describing the minimum information including at least input / output terminal information, and performs verification using this circuit information for resource-saving simulation, thereby performing highly valid verification and highly efficient verification work" (see [Abstract]). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-185202 A Summary of the Invention [Problem to be solved by the invention]

[0006] According to the technology disclosed in Patent Document 1, the user needs to manually set the conditions of blocks that are not subject to verification in the logic circuit simulation, and the user needs to understand the operation of the logic circuit in detail. This causes problems such as a limited number of engineers who can perform logic circuit simulation, or high learning costs for logic circuit simulation. Therefore, there is a need for a technology that enables even a user who is not familiar with the operation of logic circuits to stop unnecessary functional blocks and perform logic circuit simulation at high speed.

[0007] The present disclosure has been made in consideration of the above-described background, and an object of one aspect is to provide a technique that enables even a user who is not familiar with the operation of logic circuits to stop unnecessary functional blocks and quickly execute a simulation of a logic circuit. [Means for solving the problem]

[0008] According to an embodiment, there is provided a method for verifying a logic circuit, comprising the steps of: extracting a clock signal and a reset signal input to each of a plurality of functional blocks included in the logic circuit, referring to a test bench, referring to a stoppability determination table storing information indicating whether each of the plurality of functional blocks can be stopped in a test using the test bench, and stopping the clock signal and the reset signal to one or more functional blocks that do not affect the operation of the functional block to be verified according to the information acquired from the stoppability determination table, and executing a test of the functional block to be verified based on the test bench. Effect of the Invention

[0009] According to an embodiment, even a user who is not familiar with the operation of logic circuits can stop unnecessary functional blocks and quickly execute a simulation of the logic circuit.

[0010] The above and other objects, features, aspects and advantages of the present disclosure will become apparent from the following detailed description of the disclosure taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0011] [Figure 1] 1 shows an example of a configuration of a semiconductor 100 that can be verified by a verification system 200 according to the present embodiment. [Diagram 2] FIG. 2 shows an example of a hardware configuration of a verification system 200 according to the present embodiment. [Diagram 3] FIG. 2 illustrates an example of a function block table 300. [Figure 4] FIG. 4 illustrates an example of a test bench 400. [Diagram 5] FIG. 13 is a diagram illustrating an example of a stop target table 500. [Figure 6] FIG. 6 is a diagram showing an example of a first stop possibility determination table 600. [Figure 7] FIG. 7 is a diagram showing an example of a second stop possibility determination table 700. [Figure 8] FIG. 1 is a diagram showing an example of a procedure of a verification process for a logic circuit (semiconductor) by a verification system 200. [Figure 9] 11 is a diagram showing an example of a procedure for extracting a clock and a reset signal of each functional block 110. FIG. [Figure 10] FIG. 11 is a diagram illustrating an example of a procedure of a trial process. [Figure 11] FIG. 11 is a diagram illustrating an example of a result of a trial process. [Figure 12] 13 is a diagram showing an example of a criterion for determining whether an input signal has an effect on a functional block 110. FIG. [Figure 13] It is a diagram showing an example of a list 1300 indicating the presence or absence of changes in input signals of all functional blocks 110 included in the semiconductor to be verified. [Figure 14] It is a diagram showing an example of a trial result file 1400.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the technical idea according to the present disclosure will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed descriptions thereof will not be repeated.

[0013] Embodiment 1. <A. Outline of Verification of Logic Circuit> FIG. 1 is a diagram showing an example of the configuration of a semiconductor 100 that can be verified by a verification system 200 (see FIG. 2) according to the present embodiment. Referring to FIG. 1, the structure of the semiconductor 100, the simulation of the logic circuit included in the semiconductor 100, and the problems in the case of performing the simulation of the logic circuit will be described. Note that the verification system 200 can perform operation verification of a CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Processing Unit), or any other semiconductor.

[0014] (a. Configuration of Semiconductor) The semiconductor 100 includes one or more functional blocks 110 and one or more wirings 120. The one or more functional blocks 110 can be connected to each other via the wiring 120.

[0015] The functional block 110 is a group of circuits for realizing a certain function. In this specification, the term "logic circuit" includes the entire configuration of a semiconductor (e.g., the semiconductor 100), each functional block included in the semiconductor (e.g., functional blocks 110 (funcA to funcG)), a minimum unit of logic circuit such as an AND circuit, an OR circuit, or a NAND circuit, or a combination of these. Therefore, it can also be said that the functional block 110 is included in the logic circuit (semiconductor 100). It can also be said that the functional block 110 is composed of one or more logic circuits (an AND circuit, an OR circuit, a NAND circuit, etc.).

[0016] A logic circuit (semiconductor) simulation is performed on a functional block basis. A logic circuit simulation is usually performed to verify whether each logic circuit constituting a semiconductor operates normally. Therefore, hereinafter, "logic circuit simulation" may also be referred to as "logic circuit (semiconductor) verification or testing, or functional block verification or testing." "Semiconductor verification or functional block verification" also includes simulating the operation of one or more logic circuits included in a semiconductor. Furthermore, hereinafter, when referring to individual functional blocks shown in FIG. 1 etc., they will be described as funcA to funcG, and when referring to these functional blocks collectively, they will be referred to as functional block 110.

[0017] The wiring 120 propagates signals generated within the semiconductor 100. The wiring 120 outputs signals within the semiconductor 120 to the outside, inputs signals from the outside to the inside of the semiconductor 120, or inputs an output signal of one functional block 110 to another functional block 110. The arrows on the wiring 120 indicate the direction of the signals.

[0018] As shown in FIG. 1, each functional block 110 is connected to other functional blocks 110 via wiring 120. In addition, each functional block 110 may cooperate with each other to execute one process. Therefore, for example, when verifying the operation of funcA, it is necessary to verify the operation of other functional blocks 110 that may affect the operation of funcA. In the example of FIG. 1, funcB, funcD, funcF, and funcG directly output signals to funcA, and may affect the processing and operation of funcA. funcB outputs a signal to funcA via funcG, and may affect the processing and operation of funcA. In addition, funcE outputs a signal to funcD, and may affect the processing and operation of funcD. As a result, funcE may affect the processing and operation of funcA.

[0019] However, there is a possibility that the output signals of funcB to funcG do not affect the processing and operation of funcA. Therefore, as described below, the verification system 200 can determine whether or not the functional block 110 to be verified is affected by other functional blocks 110 by analyzing the design specification or the verification specification or by executing a test in advance in an auto mode.

[0020] In addition, the impact of a certain functional block 110 on the functional block 110 being verified includes a change in the internal processing of the functional block 110 being verified caused by a change in the output signal of a certain functional block 110 causing a change in the output signal of the functional block 110 being verified.

[0021] (b. Functional Block Testing) A test bench 400 (see FIG. 4) is used for verification within the semiconductor 100. A "test bench" is a setting file for verifying whether a logic circuit operates according to specifications. For example, it includes settings for input signals used in simulation.

[0022] Verification system 200 according to this embodiment verifies the operation of each functional block 110 with reference to test bench 400. Based on the description of test bench 400, verification system 200 generates input signals to input pins of semiconductor 100 or input signals to each functional block 110, and simulates the operation of each functional block 110. If the operation (output signal) of each functional block 110 in the simulation is as specified, verification system 200 determines that semiconductor 100 is normal.

[0023] Note that the test bench 400 may be created for each function or specification to be verified, and there may be one or more test benches 400. Therefore, when a design change occurs in the semiconductor under development, the verification system 200 needs to perform verification again using the multiple test benches 400.

[0024] (c. Issues when verifying function blocks) As described above, the verification system 200 can perform operation verification of each functional block 110 included in the semiconductor 100 by using one or more test benches 400. However, in recent years, the number of functions mounted on semiconductors has been increasing and becoming more complex. As a result, the execution time of a simulation for verifying each function (functional block) of a semiconductor has also been increasing.

[0025] For example, suppose that a design change occurs in the semiconductor 100. In this case, the verification system 200 needs to re-verify the function blocks 110 using multiple test benches 400. However, if all the function blocks 110 are operated and tested every time a design change occurs in the semiconductor, an enormous amount of time will be spent on verifying the operation of the semiconductor, which may cause delays in the development schedule.

[0026] Therefore, the verification system 200 according to the present embodiment speeds up the simulation (verification of the operation of the functional block 110) by stopping the operation of functional blocks that do not affect the operation of the functional block to be verified.

[0027] More specifically, the verification system 200 according to this embodiment stops the operation of one or more functional blocks 110 that do not affect the operation of the functional block 110 being verified by stopping clock signals and reset signals to one or more functional blocks 110 that do not affect the operation of the functional block 110 being verified (i.e., do not affect the test).

[0028] In this specification, "stopping the clock signal and reset signal to a certain functional block 110" includes changing the clock signal and reset signal so as to put the certain functional block 110 in a stopped state. For example, a certain functional block 110 operates with a reset signal (LOW) and stops with a reset signal (HIGH). In this case, "stopping the reset signal to a certain functional block 110" means making the reset signal HIGH (i.e., stopping the supply of the reset signal (LOW) that operates the certain functional block 110).

[0029] To this end, the verification system 200 extracts a clock signal and a reset signal input to each of the multiple functional blocks 110 included in the logic circuit. The verification system 200 also refers to the test bench 400, and further refers to a stoppability determination table that stores information indicating whether each of the multiple functional blocks 110 can be stopped in a test using the test bench 400. The verification system 200 stops the clock signal and the reset signal to one or more functional blocks 110 that do not affect the operation of the functional block 110 to be verified according to the information acquired from the stoppability determination table, and executes a test of the functional block 110 to be verified based on the test bench 400.

[0030] In this specification, the "stoppable / non-stoppable table" includes the "first stoppable / non-stoppable table (see FIG. 6)", the "second stoppable / non-stoppable table (see FIG. 7)", or both. The first stoppable / non-stoppable table, the second stoppable / non-stoppable table, and the trial result file (see FIG. 14) may be collectively referred to as the stoppable / non-stoppable table.

[0031] <B. Configuration of Verification System> FIG. 2 is a diagram showing an example of the hardware configuration of a verification system 200 according to the present embodiment. With reference to FIG. 2, the hardware configuration of the verification system 200 will be described. Also, the configuration of the software executed by the verification system 200 will be described.

[0032] As used herein, the term "system" encompasses a configuration consisting of one or more devices, a server, a virtual machine or container constructed in a cloud environment, or a configuration consisting of at least a part of these. In one aspect, the verification system 200 may be connected to input / output devices such as a display and a keyboard and used by a user. In another aspect, the verification system 200 may provide various functions to a user as a cloud service or a web application via a network. In this case, the user can use the functions of the verification system 200 via a browser or client software installed on their own terminal.

[0033] The verification system 200 mainly includes a processor 201, a memory 202, a storage 203, an external device IF (Interface) 204, an input IF 205, an output IF 206, and a communication IF 207 as its hardware configuration. These components are interconnected by an internal bus 208.

[0034] The processor 201 can execute programs for realizing various functions of the verification system 200. The processor 201 is constituted by, for example, at least one integrated circuit. The integrated circuit may be constituted by, for example, at least one CPU, at least one GPU, at least one FPGA, at least one ASIC, or a combination thereof.

[0035] The memory 202 stores programs executed by the processor 201 and data referenced by the processor 201. In one aspect, the memory 202 may be realized by a dynamic random access memory (DRAM), a static random access memory (SRAM), or the like.

[0036] Storage 203 is a non-volatile memory, and may store programs executed by processor 201 and data referenced by processor 201. In this case, processor 201 executes programs read from storage 203 to memory 202, and references data read from storage 203 to memory 202. In one aspect, storage 203 may be realized by a hard disk drive (HDD), a solid state drive (SSD), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a flash memory, or the like.

[0037] The external device IF 204 can be connected to any external device such as a printer, a scanner, an external HDD, etc. In one aspect, the external device IF 204 may be realized by a USB (Universal Serial Bus) terminal or the like.

[0038] The input IF 205 may be connected to any input device such as a keyboard, a mouse, a touch pad, a game pad, etc. In one aspect, the input IF 205 may be realized by a USB terminal, a PS / 2 terminal, a Bluetooth (registered trademark) module, etc.

[0039] The output IF 206 can be connected to any output device such as a cathode ray tube display, a liquid crystal display, an organic EL (Electro-Luminescence) display, etc. In one aspect, the output IF 206 may be realized by a USB terminal, a D-sub terminal, a DVI (Digital Visual Interface) terminal, an HDMI (High-Definition Multimedia Interface) terminal, etc.

[0040] The communication IF 207 is connected to other devices via a wired network or a wireless network. In one aspect, the communication IF 207 may be realized by a wired LAN (Local Area Network) port, a Wi-Fi (Wireless Fidelity) (registered trademark) module, or the like. In another aspect, the communication IF 207 may transmit and receive data using a communication protocol such as TCP / IP (Transmission Control Protocol / Internet Protocol) or UDP (User Datagram Protocol).

[0041] The simulator 210 is software for verifying the semiconductor 100 (logic circuit), and is stored in the storage 203. The processor 201 can implement various functions described with reference to FIGS. 3 to 14 by reading the simulator 210 from the storage 203 to the memory 202 and executing the simulator 210. In a certain aspect, the simulator 210 may be implemented as hardware. The simulator 210 includes, as main functional components, a signal extracting unit 211, a test bench acquiring unit 212, a stop possibility determining unit 213, and a test executing unit 214.

[0042] The signal extraction unit 211 extracts the clock signal and reset signal (or the signal generation source and path) provided to each functional block 110. The extraction of the clock signal and reset signal may include identifying the wiring 120 that supplies a clock signal to each functional block 110 and the wiring 120 that supplies a reset signal to each functional block 110. The extraction of the clock signal and reset signal may also include identifying the location of interruption of various signals to each functional block 110 in the semiconductor 100 (logic circuit). The signal extraction unit 211 stores information on the extracted clock signal and reset signal in a functional block table 300 (see FIG. 3 ). The functional block table 300 is stored in the storage 203.

[0043] In a certain aspect, the signal extraction unit 211 may extract a clock signal and a reset signal (or a source or a path of the signal) provided to each functional block 110 by analyzing a code written in a hardware description language. The code 220 is an example of a code written in a hardware description language. An example of an analysis procedure of the signal extraction unit 211 will be described with reference to the code 220. The signal extraction unit 211 may analyze the code 220 and determine that "CLK" that appears only in an always construct is a clock signal. Furthermore, the signal extraction unit 211 may determine that (rstl) that appears in both an always construct and a begin end construct is a reset signal.

[0044] Note that the user may store the source code of the semiconductor 100 for performing operation verification in advance in the storage 203 via the external device IF 204, the input IF 205, the communication IF 207, or the like. The signal extraction unit 211 reads out the source code stored in the storage 203 to extract the clock signal and the reset signal to be provided to each functional block 110.

[0045] The test bench acquisition unit 212 reads out the test bench 400 from the storage 203. In addition, the test bench acquisition unit 212 outputs the test information and a test execution request read out from the test bench 400 to the test execution unit 214. Note that a user may store one or more test benches 400 in advance in the storage 203 via the external device IF 204, the input IF 205, the communication IF 207, or the like.

[0046] The haltability determination unit 213 analyzes a test execution log when the test bench 400 is executed. The haltability determination unit 213 determines whether an input signal to a certain functional block 110 from one or more other functional blocks 110 affects an output signal of the certain functional block 110 based on the analysis result of the execution log. The haltability determination unit 213 stores information for determining whether or not a certain functional block 110 can be stopped when verifying the operation of the other functional blocks 110 in the first haltability determination table 600 or the second haltability determination table 700 based on the determination result.

[0047] More specifically, it is assumed that there are test benches 400A, 400B, 400C, 400D, 400E, and 400F. It is assumed that the test execution unit 214 executes the operation verification of a certain function block 110 using the test bench 400A. In this case, the stoppability determination unit 213 may determine other function blocks 110 that can be stopped (do not affect the test) when the operation verification of the certain function block 110 is performed using the test bench 400A. Alternatively, the stoppability determination unit 213 may determine other function blocks 110 that cannot be stopped (affect the test) when the operation verification of the certain function block 110 is performed using the test bench 400A. The stoppability determination unit 213 stores the determination result in either the first stoppability determination table 600 or the second stoppability determination table 700 based on the contents of the test bench 400 used. The first stoppage availability determination table 600 and the second stoppage availability determination table 700 are stored in the storage 203. When executing a trial process described later, the stoppage availability determination unit 213 stores a determination result in a trial result file 1400 (see FIG. 14).

[0048] The test execution unit 214 executes a test (operation verification) of the functional block 110 based on test information, a test execution request, the functional block table 300, the first stoppability determination table 600, the second stoppability determination table 700, or the trial result file 1400.

[0049] The test execution unit 214 can execute a test based on the test bench 400 by referring to the test information. Also, the test execution unit 214 can determine one or more functional blocks 110 that can be stopped during test execution by referring to the first stoppability determination table 600, the second stoppability determination table 700, or the trial result file 1400. Furthermore, the test execution unit 214 discriminates clock signals and reset signals to one or more functional blocks 110 that can be stopped during test execution by referring to the functional block table 300, and can stop one or more functional blocks 110 that can be stopped during test execution by stopping these signals.

[0050] Note that when there is no information in the first stoppability determination table 600, the second stoppability determination table 700, or the trial result file 1400 corresponding to the test bench 400 used, the test execution unit 214 may execute a test (operation verification) of the functional block 110 based on the test information and the test execution request. That is, the test execution unit 214 may execute the test without stopping one or more functional blocks 110 that can be stopped during test execution.

[0051] <C. Setting Information Used in Verification Processing> Next, with reference to FIGS. 3 to 7, the setting information used by the verification system 200 for verifying a logic circuit will be described. The verification system 200 can execute the processes shown in the flowcharts of FIGS. 8 to 10 by referring to each setting information shown in FIGS. 3 to 7.

[0052] In one aspect, each piece of setting information shown in FIGS. 3 to 7 may be represented as a table of a relational database, or may be represented in any other data format, such as CSV (Comma Separated Value) or JSON (JavaScript (registered trademark) Object Notation).

[0053] (a. Setting information) Fig. 3 is a diagram showing an example of the function block table 300. An example of the configuration of the function block table 300 will be described with reference to Fig. 3.

[0054] The functional block table 300 stores information on the clock pin and reset pin of each functional block 110. The functional block table 300 includes a functional block name item 301, a module name item 302, a clock pin item 303, and a reset pin item 304 as main items.

[0055] The function block name item 301 is a name or identifier for uniquely identifying the function block 110. Taking the semiconductor 100 as an example, funcA to funcG correspond to the function block name item 301.

[0056] The module name item 302 indicates a function (module) to be realized by each functional block 110. In one aspect, a plurality of functional blocks 110 may cooperate with each other to realize one module. In another aspect, a single functional block 110 may realize one module.

[0057] The clock pin item 303 indicates an input port of a clock signal in each functional block 110, or a wiring 120 connected to the input port. When each functional block 110 is considered as an individual semiconductor chip, each functional block 110 has a plurality of ports (pins), and receives a clock signal from one of the plurality of ports (clock pin).

[0058] The reset pin item 304 indicates an input port of a reset signal in each functional block 110, or a wiring 120 connected to the input port. When each functional block 110 is considered as an individual semiconductor chip, each functional block 110 has a plurality of ports (pins) and receives a reset signal from one of the plurality of ports (reset pin). In one aspect, each functional block 110 may be reset when the signal of the reset pin changes from 1 (HIGH) to 0 (LOW). In another aspect, each functional block 110 may be reset when the signal of the reset pin changes from 0 (LOW) to 1 (HIGH).

[0059] The verification system 200 can determine the clock pin and the reset pin of the functional block 110 to be stopped by referring to the functional block table 300. Furthermore, when stopping the functional block 110 on a module basis, the verification system 200 can determine the clock pin and the reset pin corresponding to the module name item 302 of the module to be stopped.

[0060] Fig. 4 is a diagram showing an example of a test bench 400. An example of the configuration of the test bench 400 will be described with reference to Fig. 4.

[0061] The test bench 400 is a setting file for verifying whether or not a logic circuit operates according to specifications. The test bench 400 is prepared by a user before the operation verification (simulation) of the functional block 110 is executed. The user inputs the created test bench 400 to the verification system 200. In one aspect, the user may create the test bench 400 by using any means such as a test bench editor provided by the verification system 200. In another aspect, the verification system 200 may automatically generate some settings of the test bench 400.

[0062] The test bench 400 mainly includes a verification target item 401, a control mode item 402, a manual mode setting item 403, a spec mode setting item 404, and a verification mode item 405. Note that the test bench 400 may include any information such as signals input to each functional block 110 in addition to the items shown in FIG.

[0063] A verification target item 401 indicates a functional block 110 to be verified. In the example of Fig. 4, funcA is specified as the functional block 110 to be verified.

[0064] The control mode item 402 indicates the control mode of the verification (test) executed by the verification system 200. The control modes include a manual mode, an auto mode, and a high-speed control OFF mode.

[0065] The manual mode (MANUAL) is a mode in which a test (verification) of the functional block 110 to be verified is performed according to a description in a specification created in advance by a user. The specification includes a design specification created from a design perspective and a verification specification created from a verification perspective. When the manual mode is selected, the verification system 200 stops other functional blocks 110 that do not affect the functional block 110 to be verified during the test according to a description in the analyzed specification. When manual is selected in the control mode item 402, the verification system 200 selects the type of manual mode based on the manual mode setting item 403.

[0066] The auto mode (AUTO) is a mode in which the operation verification of the functional block 110 to be verified is automatically performed. The verification system 200 can determine the functional block 110 that does not affect the operation of the functional block 110 to be verified from the execution log of the trial process, the execution log of the high-speed control OFF mode, or the execution log of the manual mode, which will be described later with reference to FIG. 10. In the auto mode, a test of the functional block 110 to be verified is performed based on information obtained from the execution log of the verification process executed in advance (list information of the functional blocks 110 that do not affect the operation of the functional block 110 to be verified). That is, the auto mode can be said to be a mode in which the execution log of a test executed once is used to stop the functional block 110 that does not affect the operation of the functional block 110 to be verified in the second or subsequent tests. By using the auto mode, a user can appropriately test each functional block 110 even if the user does not have sufficient knowledge about the semiconductor 100.

[0067] The high-speed control OFF mode (OFF) is a mode in which a test is performed without stopping any of the functional blocks 110. In one aspect, when the high-speed or control OFF mode is selected, the verification system 200 may obtain a test execution log and determine, from the log, functional blocks 110 that do not affect the operation of the functional block 110 to be verified. Furthermore, the verification system 200 may register the determination result in the first stoppability determination table 600 or the second stoppability determination table 700.

[0068] The manual mode setting item 403 is an item for selecting the type of manual mode. There are a spec mode (SPEC) and a verification mode (VERIFICATION). The spec mode is a test based on a design specification. When the spec mode is selected, the verification system 200 refers to the first stop possibility determination table 600 and stops the function block 110 that does not affect the operation of the function block 110 to be verified during the test. Also, when the verification mode is selected, the verification system 200 refers to the second stop possibility determination table 700 and stops the function block 110 that does not affect the operation of the function block 110 to be verified during the test.

[0069] The spec mode setting item 404 is a setting that is used when the spec mode is selected in the manual mode setting item 403. The spec mode setting item 404 is set to one of a plurality of operation modes created based on the design specifications.

[0070] The verification mode item 405 is a setting that is used when the verification mode is selected in the manual mode setting item 403. The verification mode item 405 is set to one of a plurality of operation modes created based on the verification specifications.

[0071] FIG. 5 is a diagram showing an example of the stop target table 500. An example of the configuration of the stop target table 500 will be described with reference to FIG. 5. The stop target table 500 includes information on whether each function block 110 can be stopped for each verification mode. The verification system 200 can refer to the stop target table 500 and determine the function blocks 110 that can be stopped (are permitted to be stopped during a test). The verification system 200 stops the function blocks 110 that are permitted to be stopped during a test, for example, based on the stop permission determination table.

[0072] The stop target table 500 includes, as main items, a function block name item 501, a manual mode setting item 502, and an auto mode setting item 503.

[0073] The function block name item 501 is a name or identifier for uniquely identifying the function block 110. Taking the semiconductor 100 as an example, funcA to funcG correspond to the function block name items 301.

[0074] The manual mode setting item 502 indicates whether each functional block 110 can be stopped in the manual mode. In the example of Fig. 5, funcA cannot be stopped (non-target) in the manual mode. Conversely, funcB to funcG can be stopped (target) in the manual mode.

[0075] The auto mode setting item 503 indicates whether or not each functional block 110 can be stopped in the manual mode. In the example of Fig. 5, funcA to funcG are stoppable (target) in the auto mode.

[0076] In one aspect, verification system 200 may receive setting input for stop target table 500 from a user before executing a test. For example, a user may set a function block 110 that the user wants to operate in manual mode as unstoppable. In another aspect, verification system 200 may automatically input a setting to setting item 503 for auto mode or automatically update setting item 503 for auto mode.

[0077] Fig. 6 is a diagram showing an example of a first stoppage possibility determination table 600. An example of the configuration of the first stoppage possibility determination table 600 will be described with reference to Fig. 6. The first stoppage possibility determination table 600 mainly includes a function block name item 601 and a design specification mode item 610. In the example of Fig. 6, the design specification mode item 610 includes six design specification modes (specA to specF).

[0078] The first stop possibility determination table 600 is a table created from the viewpoint of design specifications. The verification system 200 analyzes the design specifications inputted to the verification system 200 by a user to generate or update the first stop possibility determination table 600. More specifically, the verification system 200 can determine whether an output signal of a certain functional block 110 affects another functional block 110 based on information such as the wiring connection relationship of each functional block 110 described in the design specifications and the input / output directions of signals.

[0079] In one aspect, verification system 200 may analyze a plurality of design specifications to determine whether each functional block 110 can be stopped. For example, assume that a design specification is created for each function (corresponding to each of specA to specF) to be implemented in semiconductor 100. In this case, verification system 200 may analyze each design specification and extract information on whether each functional block 110 can be stopped for each specification (corresponding to each of columns of specA to specF).

[0080] In another aspect, the verification system 200 may analyze a single design specification describing specifications for a plurality of functions to determine whether each functional block 110 can be stopped. For example, assume that a single design specification describing specifications for all functions (corresponding to each of specA to specF) implemented in the semiconductor 100 has been created. In this case, the verification system 200 may analyze the single design specification and extract information on whether each functional block 110 can be stopped for each specification (corresponding to each of the columns of specA to specF).

[0081] The design specification may be text data, HyperText Markup Language (HTML) data, Extensible Markup Language (XML) data, or data expressed in any other format.

[0082] In another aspect, verification system 200 may execute a test in auto mode and generate information to be stored in first stoppability determination table 600 from an execution log of the test. For example, assume that a test in spec mode (specA) is specified in test bench 400. Also assume that there is no column for specA in first stoppability determination table 600 or that the column for specA is empty. In this case, verification system 200 operates all function blocks 110 in accordance with test bench 400 to execute a test. Then, verification system 200 may generate stoppability information of each function block 110 during execution of the test of specA from the execution log and store the stoppability information in the column for specA.

[0083] The function block name item 601 is a name for uniquely identifying the function block 110. Taking the semiconductor 100 as an example, funcA to funcG correspond to the function block name item 601.

[0084] The design specification mode item 610 indicates whether each function block 110 can be stopped in a test based on each design specification mode. In the example of Fig. 6, when a test based on specA, which is one of the design specification modes, is executed, funcA, funcC, funcF, and funcG must operate (cannot be stopped), and funcB, funcD, and funcE do not have to operate (can be stopped). Similarly, when a test based on specB, which is one of the design specification modes, is executed, funcA and funcB must operate (cannot be stopped), and funcC, funcD, funcE, funcF, and funcG do not have to operate (can be stopped).

[0085] When a test in spec mode and a design specification mode (specA to specG) to be used for the test are specified in the test bench 400, the verification system 200 can determine the functional blocks 110 that can be stopped in the specified design specification mode by referring to the first stoppability determination table 600.

[0086] Fig. 7 is a diagram showing an example of a second stoppage possibility determination table 700. An example of the configuration of the second stoppage possibility determination table 700 will be described with reference to Fig. 7. The second stoppage possibility determination table 700 mainly includes a function block name item 701 and a verification specification mode item 710. In the example of Fig. 7, the verification specification mode item 710 includes six verification specification modes (verificationA to verificationF).

[0087] The second stop possibility determination table 700 is a table created from the viewpoint of the verification specification. The verification system 200 analyzes the verification specification inputted to the verification system 200 by the user, and generates or updates the second stop possibility determination table 700. More specifically, the verification system 200 can determine whether an output signal of a certain functional block 110 affects other functional blocks 110 from operation information (input / output signals, etc.) of each functional block 110 described in the verification specification. The design specification is a specification created by a designer based on design data, whereas the verification specification is a specification created by a verifier from the viewpoint of verification (test). Note that the person who creates the design specification or the verification specification may be different from the person who uses the verification system 200. If each specification is registered in advance in the verification system 200, the person who uses the verification system 200 can use the function of the verification system 200 to speed up the execution of the test of the semiconductor 100 even if he or she is not familiar with the specifications of the semiconductor 100 (logic circuit).

[0088] In one aspect, verification system 200 may analyze a plurality of verification specifications to determine whether each functional block 110 can be stopped. For example, it is assumed that a verification specification is created for each function (corresponding to each of verificationA to verificationF) implemented in semiconductor 100. In this case, verification system 200 may analyze each verification specification and extract information on whether each functional block 110 can be stopped for each specification (corresponding to each of columns of verificationA to verificationF).

[0089] In another aspect, verification system 200 may analyze a single verification specification describing specifications for a plurality of functions to determine whether each functional block 110 can be stopped. For example, assume that a single verification specification describing specifications for all functions (corresponding to each of verificationA to verificationF) implemented in semiconductor 100 has been created. In this case, verification system 200 may analyze the single verification specification and extract information regarding whether each functional block 110 can be stopped for each specification (corresponding to each of columns of verificationA to verificationF).

[0090] The validation specification may be text data, HTML data, XML data, or data expressed in any other format.

[0091] In another aspect, the verification system 200 may execute a test in auto mode and generate information to be stored in the second stoppability determination table 700 from an execution log of the test. For example, assume that a test in a verification mode (verificationA) is specified in the test bench 400. Also assume that the second stoppability determination table 700 does not have a column for verificationA or that the column for verificationA is empty. In this case, the verification system 200 operates all the function blocks 110 in accordance with the test bench 400 to execute the test. Then, the verification system 200 may generate stoppability information of each function block 110 during execution of the verificationA test from the execution log, and store the stoppability information in the column for verificationA.

[0092] The function block name item 701 is a name or identifier for uniquely identifying the function block 110. Taking the semiconductor 100 as an example, funcA to funcG correspond to the function block name item 701.

[0093] The verification specification mode item 710 indicates whether each function block 110 can be stopped in a test based on each verification specification. In the example of Fig. 7, when a test based on verificationA, which is one of the verification specification modes, is executed, funcA must operate (cannot be stopped), and funcB, funcC, funcD, funcE, funcF, and funcG do not have to operate (can be stopped). Similarly, when a test based on verificationB, which is one of the verification specification modes, is executed, funcB must operate (cannot be stopped), and funcA, funcC, funcD, funcE, funcF, and funcG do not have to operate (can be stopped).

[0094] When a test in a verification mode and a verification specification mode (verification A to verification G) to be used for the test are specified in the test bench 400, the verification system 200 can determine the functional blocks 110 that can be stopped in the specified verification specification mode by referring to the second stoppability determination table 700.

[0095] (b. An example of how to use each setting information) Next, a description will be given of typical procedures for using the function block table 300, the test bench 400, the stop target table 500, the first stop possibility determination table 600, and the second stop possibility determination table 700 in the verification system 200. Note that the procedures for using each table below are merely examples, and the verification system 200 may refer to each table in any order or simultaneously in parallel.

[0096] First, the verification system 200 refers to the test bench 400 to determine the functional block 110 to be verified, the test mode, the test contents such as the input signals to be used for the test, and the like.

[0097] Next, the verification system 200 refers to the stop target table 500 to distinguish between the stoppable function blocks 110 and the non-stoppable function blocks 110. Note that the stoppability information stored in the stop target table 500 indicates whether each function block 110 can be stopped as specified by the user or the system. In contrast, the stoppability information stored in the first stoppability discrimination table 600 and the second stoppability discrimination table 700 indicates whether it affects the test (the operation of the function block 110 to be verified).

[0098] Next, when the spec mode is selected as the manual mode in the test bench 400, the verification system 200 refers to the first stoppability discrimination table 600 to distinguish the stoppable function blocks 110 during the spec mode test. Alternatively, when the verification mode is selected as the manual mode in the test bench 400, the verification system 200 refers to the second stoppability discrimination table 700 to distinguish the stoppable function blocks 110 during the verification mode test.

[0099] Next, the verification system 200 refers to the function block table 300 to distinguish the clock signal and the reset signal (or the clock pin and the reset pin) of the stoppable function blocks 110 during the spec mode or verification mode test.

[0100] The verification system 200 can stop one or more function blocks 110 unnecessary for the test by turning off the clock signal and the reset signal of each stoppable function block 110, thereby shortening the test time.

[0101] <D. Verification Process of Logic Circuit> Next, an example of an internal processing procedure of verification system 200 will be described with reference to Figures 8 to 10. In one aspect, processor 201 may load a program for performing the processes of Figures 8 to 10 from storage 203 into memory 202 and execute the program. In another aspect, some or all of the processes may be realized as a combination of circuit elements configured to perform each process.

[0102] FIG. 8 is a diagram showing an example of a procedure for a verification process of a logic circuit (semiconductor) by the verification system 200. As shown in FIG.

[0103] In step S805, the verification system 200 reads the circuit data to be verified. As an example, the circuit data to be verified is a code written in a hardware description language. In one aspect, the verification system 200 may acquire the circuit data to be verified via the external device IF 204, the input IF 205, or the communication IF 207. Alternatively, the verification system 200 may refer to the circuit data to be verified stored in the storage 203.

[0104] In step S810, the verification system 200 reads the test bench 400. As an example, the verification system 200 may read the test bench 400 stored in the storage 203 into the memory 202 and refer to it.

[0105] In step S815, the verification system 200 refers to the test bench 400 and determines whether the high-speed test function is ON or OFF. The high-speed test function is a function that stops the functional block 110 that does not affect the operation of the functional block 110 to be verified during test execution. More specifically, the verification system 200 determines that the high-speed test function is OFF when the control mode item 402 is the high-speed control OFF mode. When the high-speed test function is ON, the verification system 200 transfers control to step S825. When the high-speed test function is OFF, the verification system 200 transfers control to step S820.

[0106] In step S820, the verification system 200 executes a test (simulation) by operating all the function blocks 110. Taking Fig. 1 as an example, the verification system 200 executes a test of funcA, which is the function block 110 to be verified, by operating all the function blocks 110, funcA to funcG.

[0107] In step S825, the verification system 200 executes a process of extracting the clock and reset signals of each function block 110. Details of step S825 will be described with reference to Fig. 9. The verification system 200 generates or refers to the function block table 300 by executing the process of step S825.

[0108] In step S830, the verification system 200 refers to the test bench 400 and determines whether the control mode is the manual mode (MANUAL) or the auto mode (AUTO). More specifically, when the control mode item 402 is MANUAL, the verification system 200 determines that the control mode is the manual mode. Also, when the control mode item 402 is AUTO, the verification system 200 determines that the control mode is the auto mode. When the verification system 200 determines that the control mode is the manual mode, it transfers control to step S835. When the verification system 200 determines that the control mode is the auto mode (i.e., when the control mode is set not to use the stop possibility determination table), it transfers control to step S850.

[0109] In step S835, verification system 200 selects a table to be used for high-speed control in manual mode. More specifically, verification system 200 selects first stop feasibility determination table 600 based on the setting item 403 of manual mode being specification mode (SPEC). Also, verification system 200 selects second stop feasibility determination table 700 based on the setting item 403 of manual mode being verification mode (VERIFICATION). When verification system 200 selects first stop feasibility determination table 600, it transfers control to step S840. When verification system 200 selects second stop feasibility determination table 700, it transfers control to step S845.

[0110] In step S840, the verification system 200 executes a test in the spec mode based on the function block table 300 and the first halt possibility determination table 600. More specifically, the verification system 200 executes the test in a state where the clock signal and the reset signal to one or more function blocks 110 that do not affect the operation of the function block 110 to be verified are stopped.

[0111] Taking an example of executing a test of specA on funcA of semiconductor 100, verification system 200 refers to the column of specA in first haltability determination table 600 and determines that funcB, funcD, and funcE can be halted. Next, verification system 200 refers to function block table 300 to obtain information on the clock pins and reset pins of funcB, funcD, and funcE. Based on the obtained information on the clock pins and reset pins, verification system 200 halts the operations of funcB, funcD, and funcE.

[0112] In step S845, the verification system 200 executes the test in the verification mode based on the function block table 300 and the second halt determination table 700. More specifically, the verification system 200 executes the test in a state where the clock signals and reset signals to one or more function blocks 110 that do not affect the operation of the function block 110 to be verified are stopped.

[0113] Taking an example of executing a verificationA test on funcA of semiconductor 100, verification system 200 refers to the verificationA column of second haltability determination table 700 and determines that funcB, funcC, funcD, funcE, funcF, and funcG can be halted. Next, verification system 200 refers to function block table 300 to obtain information on the clock pins and reset pins of funcB, funcC, funcD, funcE, funcF, and funcG. Based on the obtained information on the clock pins and reset pins, verification system 200 halts the operations of funcB, funcC, funcD, funcE, funcF, and funcG.

[0114] In step S850, the verification system 200 executes a trial process. The trial process is a process for automatically determining the stoppable functional block 110 from the execution result of the test using the test bench 400. Details of the trial process will be described with reference to FIG. 10. By executing the process of step S850, the verification system 200 may obtain information on the stoppable functional block 110 and store the information in the trial result file 1400. When re-executing a test based on the test bench 400, the verification system 200 may use the previously generated trial result file 1400. In a certain aspect, the verification system 200 may store information on the stoppable functional block 110 in the first stoppability determination table 600 or the second stoppability determination table 700.

[0115] In step S855, the verification system 200 executes the test in auto mode based on the function block table 300 and the trial result file 1400. More specifically, the verification system 200 executes the test in a state where the clock signals and reset signals to one or more function blocks 110 that do not affect the operation of the function block 110 to be verified are stopped.

[0116] It is assumed that in step S850, the verification system 200 stores information on the stoppable function block 110 in the first stoppable / non-stoppable determination table 600 or the second stoppable / non-stoppable determination table 700. In this case, the verification system 200 may refer to the first stoppable / non-stoppable determination table 600 or the second stoppable / non-stoppable determination table 700 in step S855.

[0117] Fig. 9 is a diagram showing an example of a procedure for extracting the clock and reset signals of each functional block 110. The process of Fig. 9 is executed as a subroutine of step S825.

[0118] In step S910, the verification system 200 reads the function block table 300. The verification system 200 may read the function block table 300 from the storage 203 to the memory 202 and refer to the function block table 300.

[0119] In step S920, the verification system 200 determines whether or not the clock signal and the reset signal have been stored in the function block table 300. If the verification system 200 determines that the clock signal and the reset signal have been stored in the function block table 300 (YES in step S920), the verification system 200 ends the process and returns control to step S825 together with the data stored in the function block table 300. If not (NO in step S920), the verification system 200 transfers control to step S930.

[0120] In step S930, the verification system 200 extracts a clock signal. More specifically, the verification system 200 analyzes the circuit data to be verified acquired in step S805, and extracts information on a clock signal (clock pin) of one functional block 110 defined in the circuit data to be verified. For example, the verification system 200 can extract information on the clock signal (clock pin) of the functional block 110 from the circuit data to be verified in the procedure described with reference to FIG. 2.

[0121] In step S940, the verification system 200 extracts a reset signal. More specifically, the verification system 200 analyzes the circuit data to be verified acquired in step S805, and extracts information on a reset signal (reset pin) of a certain functional block 110 defined in the circuit data to be verified. For example, the verification system 200 can extract information on the reset signal (reset pin) of the functional block 110 from the circuit data to be verified in the procedure described with reference to FIG. 2.

[0122] In step S950, the verification system 200 determines whether the processes of steps S930 and S940 have been repeated the number of times corresponding to all of the function blocks 110. If the verification system 200 determines that the processes of steps S930 and S940 have been repeated the number of times corresponding to all of the function blocks 110 (YES in step S950), the verification system 200 transfers control to step S960. If not (NO in step S950), the verification system 200 transfers control to step S930.

[0123] In one aspect, in step S930, the verification system 200 may collectively extract information on clock signals (clock pins) of all the functional blocks 110 defined in the circuit data to be verified. Similarly, in step S940, the verification system 200 may collectively extract information on reset signals (reset pins) of all the functional blocks 110 defined in the circuit data to be verified. In this case, the process of step S950 may not be executed.

[0124] In step S960, the verification system 200 stores information on the clock signal (clock pin) and reset signal (reset pin) of each functional block 110 in the functional block table 300. The verification system 200 also returns control to step S825 together with the data stored in the functional block table 300.

[0125] 10 is a diagram showing an example of a procedure of the trial process. The process of FIG. 10 is executed as a subroutine of step S850.

[0126] In step S1005, the verification system 200 determines whether or not the trial result file 1400 exists. As an example, the verification system 200 may store past trial result files 1400 in the storage 203. In this case, the verification system 200 may refer to the storage 203 and determine whether or not the trial result file 1400 exists that can be used for the current test bench 400. If the verification system 200 determines that the trial result file 1400 exists (YES in step S1005), it transfers control to step S1010. If not (NO in step S1005), the verification system 200 transfers control to step S1015.

[0127] In step S1010, the verification system 200 executes the test by reusing the past trial result file 1400. The verification system 200 leaves a test execution log in the memory 202 or the storage 203.

[0128] In one aspect, the verification system 200 may accept, from a user, an operation to edit the past trial result file 1400. For example, when a user adds a new function to an existing circuit, the user can use the past trial processing result for the current test by modifying a part of the past trial result file 1400 (such as changing whether or not some of the functional blocks 110 can be stopped).

[0129] In another aspect, when the verification system 200 stores the trial results in the first stoppable / non-stoppable determination table 600 or the second stoppable / non-stoppable determination table 700, the verification system 200 may use the information contained in the first stoppable / non-stoppable determination table 600 or the second stoppable / non-stoppable determination table 700 as the past trial result file 1400.

[0130] In step S1015, the verification system 200 executes the test without using the past trial result file 1400. As an example, the verification system 200 may execute the test in the speed-up control OFF mode.

[0131] In step S1020, the verification system 200 refers to the execution log to confirm and list changes in the input signals of all the functional blocks 110. As an example, the verification system 200 generates a list 1300 (see FIG. 13). The list 1300 indicates changes in the input signals of all the functional blocks 110 included in the semiconductor to be verified. Taking the semiconductor 100 as an example, the list 1300 includes information on changes in the input signals of each of funcA to funcG.

[0132] In step S1025, the verification system 200 checks for a change in the input signal of the functional block 110 to be verified, by referring to the list 1300 or the execution log.

[0133] In step S1030, the verification system 200 determines whether or not there is a change in the input signal of the functional block 110 to be verified (e.g., funcA). If the verification system 200 determines that there is a change in the input signal of the functional block 110 to be verified (YES in step S1030), the verification system 200 transfers control to step S1035. If not (NO in step S1030), the verification system 200 transfers control to step S1050.

[0134] In step S1035, the verification system 200 determines whether a signal (input signal or output signal) of a certain functional block 110 affects the operation of the functional block 110 to be verified. As an example, the verification system 200 selects one of the signals (or one of the wirings 120 transmitting the signal) that is changing from the list 1300. Then, the verification system 200 determines whether the selected signal affects the operation of the functional block 110 to be verified.

[0135] The verification system 200 can determine whether or not the selected signal affects the operation of the functional block 110 to be verified by referring to the row including the selected signal and the output signal of the functional block 110 to be verified from the execution log of the trial process. Taking the semiconductor 100 as an example, the verification system 200 can determine that the output signal of funcC affects the operation of funcA (the functional block 110 to be verified).

[0136] If the verification system 200 determines that a signal of a certain functional block 110 affects the operation of the functional block 110 to be verified (YES in step S1035), the verification system 200 transfers control to step S1040. If not (NO in step S1035), the verification system 200 transfers control to step S1050.

[0137] In step S1040, the verification system 200 adds the function block 110 (the certain function block 110 in step S1035) to the unstoppable list.

[0138] In step S1045, the verification system 200 determines whether or not there is a signal that may cause a change in the output signal of the function block 110 registered in the unstoppable list in step S1040. For example, assume that the output signal of funcC affects the operation of funcA (the output signal of funcA). In this case, the verification system 200 determines whether or not the input signal (upstream signal) to funcC affects the operation of funcC. The verification system 200 can make this determination by referring to the execution log of the trial process.

[0139] If the verification system 200 determines that there is a signal that may cause a change in the output signal of the function block 110 that was added to the unstoppable list in step S1040 (YES in step S1045), the verification system 200 transfers control to step S1040. Otherwise (NO in step S1045), the verification system 200 transfers control to step S1050.

[0140] For example, assume that the output signal of the upstream functional block 110 of funcC affects the operation of funcC. In this case, the output signal of the upstream functional block 110 indirectly affects the operation of funcA (the output signal of funcA). Therefore, the verification system 200 adds not only funcC but also the upstream functional block 110 to the unstoppable list.

[0141] In step S1050, the verification system 200 determines whether or not the processing from step S1030 onwards has been executed for the number of input signals that have changed (in the functional block 110 to be verified). That is, the verification system 200 determines whether or not all signals that affect the operation (output signals) of the functional block 110 to be verified have been detected. If the verification system 200 determines that the processing from step S1030 onwards has been executed for the number of input signals that have changed (in the functional block 110 to be verified) (YES in step S1050), the verification system 200 transfers control to step S1055. If not (NO in step S1050), the verification system 200 transfers control to step S1030.

[0142] In step S1055, the verification system 200 stores the result of the trial process in the trial result file 1400 (stop determination table). In a certain situation, the verification system 200 may store the result of the trial process in the first stop determination table 600 or the second stop determination table 700.

[0143] <E. Trial Process> Next, the method for determining whether each function block 110 in the trial process can be stopped, and the lists 1300 and trial result file 1400 generated during the trial process will be described.

[0144] FIG. 11 is a diagram showing an example of the result of the trial process. In the example of FIG. 11, the verification system 200 determines that in the test of funcA in the result of the trial process, funcB, funcD, and funcE can be stopped. Generally speaking, there are two types of function blocks 110 that can be stopped.

[0145] The first type is the function block 110 that does not affect the operation of the function block 110 to be verified. In the example of FIG. 11, funcB corresponds to the function block 110 that does not affect the operation of the function block 110 (funcA) to be verified. The output signal of funcB (the input signal to funcA) may change, but the output signal of funcB does not affect the operation of funcA.

[0146] The second type is the function block 110 whose output signal does not change. In the example of FIG. 11, funcD corresponds to the function block 110 whose output signal does not change. The output signal of funcD (the input signal to funcA) may change, but the output signal of funcD does not affect the operation of funcA.

[0147] In addition, functional blocks 110 (funcE, etc.) located upstream of the functional block 110 (funcA), such as funcB and funcD, that do not affect the operation of the functional block 110 (funcA) to be verified can also be stopped.

[0148] 12 is a diagram showing an example of a criterion for determining whether or not an input signal has an effect on the functional block 110. There are three types of signals 1201, 1202, and 1203 input to the functional block 110 (funcA) to be verified.

[0149] Signal 1201 is an unchanging signal (the signal is always fixed at 0 (LOW) or 1 (HIGH)). Signal 1201 does not affect the operation of functional block 110 to be verified. Therefore, verification system 200 determines that functional block 110 that outputs signal 1201 can be stopped. For example, funcD in FIG. 11 corresponds to functional block 110 that outputs signal 1201.

[0150] Signal 1202 is a signal that may change but does not affect the operation of functional block 110 to be verified. For example, a signal that is not used inside functional block 110 to be verified corresponds to signal 1202. Signal 1202 also does not affect the operation of functional block 110 to be verified. Therefore, verification system 200 determines that functional block 110 that outputs signal 1202 can be stopped. For example, funcB in FIG. 11 corresponds to functional block 110 that outputs signal 1202.

[0151] Signal 1203 is a signal that changes and is used inside functional block 110 to be verified (a signal that affects the operation of functional block 110 to be verified). Therefore, verification system 200 determines that functional block 110 that outputs signal 1203 cannot be stopped. For example, funcC, funcF, and funcG in FIG. 11 correspond to functional block 110 that outputs signal 1203.

[0152] 13 is a diagram showing an example of a list 1300 indicating whether or not there is a change in the input signals of all the function blocks 110 included in the semiconductor to be verified. The verification system 200 creates the list 1300 from an execution log of the trial process. Taking the semiconductor 100 as an example, the verification system 200 assigns an identifier to each input signal of all the function blocks 110 (funcA to funcG) and records the identifier and whether or not there is a change in the state of each input signal in the list 1300.

[0153] Each signal recorded in list 1300 is given a uniquely identifiable identifier such as signal 1, signal 2, etc. List 1300 also records information indicating whether or not each signal has changed in association with the identifier of each signal. As an example, signal 1 is YES (signal change). Signal 2 is NO (no signal change (fixed at 0)). Signal 3 is NO (no signal change (fixed at 1)).

[0154] FIG. 14 is a diagram showing an example of the trial result file 1400. The trial result file 1400 stores information indicating whether each function block 110 can be stopped during test execution. More specifically, the trial result file 1400 stores information indicating whether each function block 110 can be stopped in a test based on the test bench 400 referred to in the trial process. For example, it is assumed that the test bench 400 includes a setting of a spec mode (specA). In this case, the trial result file 1400 stores information indicating whether each function block 110 can be stopped in a test in the spec mode (specA). In the example of FIG. 14, funcA, funcC, funcF, and funcG are ON (unstoppable), and funcB, funcD, and funcE are OFF (stoppable).

[0155] In one aspect, in a trial process, the verification system 200 may execute tests based on all test benches 400 (specA to specG, verificationA to verificationG, etc.) that have been input to the verification system 200 in advance, and generate trial result files 1400 corresponding to all test benches 400. The verification system 200 may use the trial result file 1400 when re-executing a test based on a test bench 400. The verification system 200 may reuse the trial result file 1400 when executing a test based on another test bench 400. At that time, the verification system 200 may accept editing of the trial result file 1400 from a user.

[0156] As described above, the verification system 200 according to the present embodiment can automatically determine whether each function block 110 can be stopped during test execution by analyzing the design specification, analyzing the verification specification, or performing trial processing. In this way, the verification system 200 can speed up the test by stopping the function blocks 110 that are not required for the test.

[0157] Furthermore, even if a user who executes a test does not have sufficient knowledge about the semiconductor 100 (logic circuit), the user can easily speed up the test by using trial processing. Alternatively, the user who executes a test can easily speed up the test without needing knowledge about the semiconductor 100 (logic circuit) by having the verification system 200 analyze various specifications that have been created in advance by a designer or a person in charge of verification.

[0158] The verification system 200 also provides the user with a function for reusing a past trial result file 1400 for a new test. This allows the user to instantly speed up the test when there is a reusable trial result file 1400. Furthermore, when there is a design change in the semiconductor 100, the user can rewrite a part of the past trial result file 1400 and use it.

[0159] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is indicated by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims. In addition, the disclosure contents described in the embodiments and each modified example are intended to be implemented, as far as possible, either alone or in combination. [Explanation of symbols]

[0160] 100 semiconductor, 110 function block, 120 wiring, 200 verification system, 201 processor, 202 memory, 203 storage, 204 external device IF, 205 input IF, 206 output IF, 207 communication IF, 208 internal bus, 210 simulator, 211 signal extraction section, 212 test bench acquisition section, 213 stop possibility determination section, 214 test execution section, 220 code, 300 function block table, 301, 501, 601, 701 function block name item, 302 module name item, 303 clock pin item, 304 reset pin item, 400, 400A test bench, 401 verification target item, 402 control mode item, 403, 502 manual mode setting item, 404 spec mode setting item, 405 verification mode item, 500 Stop target table, 503 auto mode setting item, 600 first stop possibility determination table, 610 design specification mode item, 700 second stop possibility determination table, 710 verification specification mode item, 900 information processing device, 1201, 1202, 1203 signals, 1300 list, 1400 trial result file.

Claims

1. A method for verifying a logic circuit, comprising: extracting a clock signal and a reset signal input to each of a plurality of functional blocks included in the logic circuit; referencing a test bench; A step of referring to a stop possibility determination table storing information indicating whether each of the plurality of functional blocks can be stopped in a test using the test bench; stopping the clock signal and the reset signal to one or more functional blocks that do not affect the operation of the functional block to be verified in accordance with the information obtained from the stoppability determination table, and performing a test of the functional block to be verified based on the test bench.

2. the stoppage possibility determination table includes a first stoppage possibility determination table storing information indicating whether each of the plurality of functional blocks is stoppable or not determined based on a design specification of the logic circuit, The verification method includes: reading a design specification of the logic circuit; extracting mutual connection relationships between the plurality of functional blocks described in the design specification; The verification method according to claim 1 , further comprising: updating the first stop possibility determination table based on the connection relationship.

3. the stoppage possibility determination table includes a second stoppage possibility determination table storing information indicating whether each of the plurality of functional blocks is stoppable or not determined based on a verification specification of the logic circuit, The verification method includes: reading a verification specification for the logic circuit; extracting from the verification specification a description of one or more of the function blocks to be verified in each of a plurality of tests; The verification method according to claim 1 , further comprising: updating the second stop possibility determination table based on the description.

4. executing a test using all of the plurality of functional blocks based on a setting in the test bench that does not use the stop possibility determination table; extracting the plurality of functional blocks that do not affect the operation of the functional block to be verified based on a result of execution of a test using all of the plurality of functional blocks; 2. The method according to claim 1, further comprising the step of newly storing the plurality of functional blocks that do not affect the operation of the functional block to be verified in the haltability determination table.

5. When executing the test bench again or when executing another test bench, referring to the information newly registered in the stop possibility determination table; stopping the clock signal and the reset signal to a part of the plurality of functional blocks based on information newly registered in the stop possibility determination table; and executing a test based on the other test bench.

6. 6. The verification method according to claim 5, further comprising the step of: accepting a change operation of the information newly stored in the stoppable / non-stoppable determination table after referring to the information newly stored in the stoppable / non-stoppable determination table when executing the other test bench.

7. A program for causing a computer to execute the method according to any one of claims 1 to 6.

8. A storage device storing the program according to claim 7; and a processor for executing the program.

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