Display device

Abstract

To provide a semiconductor device having a thin film transistor using an oxide semiconductor layer, in which a low power consumption semiconductor device is provided, and to provide a highly reliable semiconductor device in the semiconductor device having a thin film transistor using the oxide semiconductor layer.SOLUTION: In the semiconductor device, a gate electrode layer (gate wiring layer) and a wiring layer that electrically connects to a source electrode layer or a drain electrode layer intersect with each other via an insulating layer covering the oxide semiconductor layer of the thin film transistor and a gate insulating layer present in between. It is possible to reduce the parasitic capacitance formed by the laminated structure of the gate electrode layer, the gate insulating layer, and the source electrode layer or the drain electrode layer, and it is possible to realize low power consumption of the semiconductor device.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used The technology of constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as C and electro-optical devices, especially in switching of image display devices. Metal oxides exist in a wide variety of forms and are used for a wide range of purposes. Indium oxide is a well-known material that is needed for applications such as liquid crystal displays. It is used as a transparent electrode material.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin-film transistors that use metal oxides as channel formation regions and that exhibit excellent semiconductor properties are already known. (See Patent Documents 1 and 2.)

[0005] Electrical devices using thin-film transistors include mobile phones, notebook personal computers, etc. For such portable electronic devices, The problem of power consumption, which affects continuous operation time, is a big one. It is important for any device manufacturer to curb the increase in power consumption that accompanies larger device sizes. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0007] In a semiconductor device having a thin film transistor using an oxide semiconductor layer, One of the objects of the present invention is to provide a conductor device.

[0008] In a semiconductor device having a thin film transistor using an oxide semiconductor layer, One of the objects of the present invention is to provide a conductor device. [Means for solving the problem]

[0009] In a semiconductor device, a gate electrode layer (gate wiring layer) and a source electrode layer or a drain electrode layer The wiring layer electrically connected to the insulating layer and the oxide semiconductor layer of the thin film transistor The gate electrode layer and the source electrode of the thin film transistor are intersected with each other through the gate insulating layer. The gate electrode layer, the gate electrode layer, and the drain electrode layer are not overlapped with each other except for being partially overlapped with each other on the oxide semiconductor layer. The semiconductor device does not have a laminated structure including a base insulating layer, and a source electrode layer or a drain electrode layer.

[0010] Therefore, a stacked structure of a gate electrode layer, a gate insulating layer, and a source electrode layer or a drain electrode layer This reduces the parasitic capacitance formed by the Cut.

[0011] One embodiment of the configuration of the invention disclosed in this specification includes a gate electrode layer and a gate insulator on the gate electrode layer. An oxide semiconductor layer is formed on the insulating layer, and a source electrode layer and a drain electrode layer are formed on the oxide semiconductor layer. The source electrode layer and the drain electrode layer are provided with an oxide insulating layer in contact with the oxide semiconductor layer. a wiring layer electrically connected to the source electrode layer or the drain electrode layer on the oxide insulating layer; an opening reaching the source electrode layer or the drain electrode layer is provided in the oxide insulating layer; The line layer is in contact with the source electrode layer or the drain electrode layer at the opening, and is connected to the gate electrode layer and the wiring layer. is a semiconductor device in which a gate insulating layer and an oxide semiconductor layer are interposed therebetween.

[0012] The source electrode layer and the drain electrode layer are preferably thin, with a thickness of 0.1 nm to 50 nm. The source electrode layer and the drain electrode layer are made of a thin conductive film. Therefore, the parasitic capacitance with the gate electrode layer can be reduced.

[0013] The source electrode layer and the drain electrode layer are made of a material containing a metal with high oxygen affinity. The metal having high oxygen affinity is preferably titanium, aluminum, or manganese. , magnesium, zirconium, beryllium, or thorium. In this embodiment, the source electrode layer and the drain electrode layer are preferably made of a material having a thickness of 100 nm or less. A titanium film is used as the substrate.

[0014] When an oxide semiconductor layer is brought into contact with a metal layer having a high oxygen affinity and heat treatment is performed, the oxide semiconductor Oxygen atoms move from the semiconductor layer to the metal layer, increasing the carrier density near the interface. As a result, a low-resistance region is formed near the interface, and the oxide semiconductor layer and the source electrode layer and the drain electrode layer are The contact resistance with the inner electrode layer can be reduced.

[0015] Further, a heat-resistant conductive material may be used for the source electrode layer and the drain electrode layer. When the material is used, the source electrode layer and the drain electrode layer can be formed without any problem even if a heat treatment is performed after the formation of the source electrode layer and the drain electrode layer. This can prevent the gate electrode layer and the drain electrode layer from being altered or deteriorated.

[0016] Heat-resistant conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), Choose from molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). The elements mentioned above, or alloys containing the above elements or combinations of the above elements A film or a nitride containing the above-mentioned elements can be used. The above heat-resistant conductive materials are combined with low-resistance conductive materials such as aluminum (Al) and copper (Cu). Alternatively, a conductive film having improved heat resistance due to heating may be used.

[0017] The source and drain electrode layers may also include a metal oxide layer. For example, a metal oxide layer may include a semiconductor layer. A structure having a titanium oxide film between a conductor layer and a titanium film, or a titanium film (for example, a film thickness of 0.1 A titanium oxide film (for example, a film thickness of 1 nm to 20 nm) is placed between the oxide insulating layer and the titanium oxide film. The structure may have a thickness of 1 nm or less.

[0018] In addition, when the source electrode layer and the drain electrode layer are thin enough to transmit light, The source electrode layer and the drain electrode layer have a light-transmitting property.

[0019] The wiring layer is formed using a conductive film having a lower resistance than the source electrode layer and the drain electrode layer. Aluminum, copper, chromium, tantalum, molybdenum, tungsten, titanium, neodymium, Using metal materials such as scandium or alloy materials mainly composed of these, it is possible to form a single layer or multilayer. In this embodiment, the first wiring layer is made of aluminum. A laminated structure of a silicon film for the first wiring layer and a titanium film for the second wiring layer is used.

[0020] In another embodiment of the invention disclosed in this specification, a gate electrode layer is formed, and a gate electrode A gate insulating layer is formed on the electrode layer, an oxide semiconductor layer is formed on the gate insulating layer, and an oxide semiconductor After dehydrating or dehydrogenating the oxide semiconductor layer, water or hydrogen is removed from the oxide semiconductor layer without contacting it with the air. and forming a source electrode layer and a drain electrode layer on the oxide semiconductor layer. The oxide semiconductor layer is provided on the source electrode layer and the drain electrode layer. An oxide insulating layer is formed, and an opening reaching the source electrode layer or the drain electrode layer is formed in the oxide insulating layer. The opening is in contact with the source electrode layer or the drain electrode layer, and the gate electrode layer, the gate insulating layer, and A wiring layer is formed so as to overlap the source electrode layer and the drain electrode layer with an oxide insulating layer interposed therebetween. This is a method for manufacturing a semiconductor device in which the thickness is thinner than that of an electrode layer and the resistance is low.

[0021] Each of the above configurations solves at least one of the above problems.

[0022] The oxide semiconductor layer is InMO3(ZnO) m (m>0) A thin film transistor is fabricated using the thin film as an oxide semiconductor layer. , Ga, Fe, Ni, Mn and Co. For example, M can be Ga, Ga and Ni, Ga and Fe, etc. In the oxide semiconductor, M may contain any of the above metal elements other than a. In addition to the metallic elements contained in the steel, impurity elements include Fe, Ni and other transition metal elements, or In this specification, the oxide of the transition metal is InMO3(Zn O) m Among oxide semiconductor layers having a structure represented by (m>0), those having a structure containing Ga as M The oxide semiconductor is called the In-Ga-Zn-O oxide semiconductor, and the thin film is called the In-Ga-Zn It is also called nO-based non-single crystal film.

[0023] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-O, I n-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga -Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al- Zn-O, In-O, Sn-O, and Zn-O metal oxides can be used. Further, the oxide semiconductor layer made of the above metal oxide may contain silicon oxide.

[0024] Dehydration or dehydrogenation is also performed using inert gases such as nitrogen or noble gases (argon, helium, etc.). 400°C to 750°C in a reactive gas atmosphere, preferably 425°C or higher and below the strain point of the substrate The heat treatment is performed for 10 minutes to reduce impurities such as moisture contained in the oxide semiconductor layer. This prevents re-impregnation of the material with water (H2O).

[0025] The heat treatment for dehydration or dehydrogenation is preferably carried out in a nitrogen atmosphere with H2O of 20 ppm or less. It is also preferable to carry out the treatment in ultra-dry air with an H2O concentration of 20 ppm or less.

[0026] Heat treatment for dehydration or dehydrogenation is carried out using a heating method using an electric furnace or a method using heated gas. Gas Rapid Thermal Anneal (GRTA) method or lamp light LRTA (Lamp Rapid Thermal Anneal) method using instantaneous A method such as a short heating method can be used.

[0027] The oxide semiconductor layer that has been dehydrated or dehydrogenated is Even when TDS was measured up to 450°C for the layer, two peaks of water and at least 300 The heat treatment conditions are set so that a peak that appears around 100 °C is not detected. The TDS test showed that the thin-film transistor using the oxide semiconductor layer that was dehydrogenated or dehydrogenated had a thermal conductivity of 45 Even when measurements are taken down to 0°C, the water peak that appears around 300°C is not detected.

[0028] The heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated is changed to The oxide semiconductor layer is cooled slowly without being exposed to the air in the same furnace in which the hydrogenation or dehydrogenation was performed. It is important to prevent the re-incorporation of hydrogen into the oxide semiconductor layer. Low resistance, i.e. N-type (N - , N + After that, the oxide semiconductor is made high-resistance and made I-type. When a thin-film transistor is fabricated using a conductor layer, the threshold voltage value of the thin-film transistor can be programmed. A so-called normally-off switching element can be realized. The transistor gate voltage forms a channel at a positive threshold voltage as close as possible to 0V. It is desirable for the display device to have a negative threshold voltage value. When the gate voltage is 0V, current flows between the source and drain electrodes. In an active matrix display device, the circuit The electrical characteristics of the thin film transistor are important and determine the performance of the display device. Of the electrical characteristics of thin film transistors, the threshold voltage (Vth) is particularly important. Even if the effective mobility is high, the threshold voltage is high, or the threshold voltage is negative. It is difficult to control the threshold voltage as a circuit. In the case of a thin-film transistor with a large capacitance, when the driving voltage is low, the transistor functions as a switch. The transistor may not be able to perform its function and may become a load. In the case of a transistor, a channel is formed only when a positive voltage is applied to the gate voltage, and the drain voltage A transistor in which current flows out is desirable. A channel does not form unless the driving voltage is high. Transistors in which a channel is formed and drain current flows even under negative voltage conditions However, such a thin film transistor is not suitable for use in circuits.

[0029] In addition, the gas atmosphere used to lower the temperature from T is different from the gas atmosphere used to raise the temperature to T. A gas atmosphere may be switched to, for example, air in the same furnace where dehydration or dehydrogenation was performed. The inside of the furnace is filled with high-purity oxygen gas or N2O gas, ultra-dry air (dew point Cooling is performed by filling the container with water at a temperature of -40°C or less, preferably -60°C or less.

[0030] The moisture content in the film is reduced by a heat treatment for dehydration or dehydrogenation, and then the film is Cool slowly (or cool) in an atmosphere that is not prone to dew (dew point is -40°C or less, preferably -60°C or less). The oxide semiconductor film is used to improve the electrical characteristics of thin film transistors and to facilitate mass production. This will realize thin-film transistors that are both reliable and high performance.

[0031] In this specification, the method is carried out under an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.). This heat treatment is called a heat treatment for dehydration or dehydrogenation. Dehydrogenation does not only mean that hydrogen is released as H2 by the hydrogenation process, but also means that H For convenience, this process is referred to as dehydration or dehydrogenation, which also includes the elimination of OH and other groups.

[0032] Heat treatment is performed under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.). In this case, the oxide semiconductor layer becomes oxygen-deficient and has low resistance, that is, becomes N-type ( N - To make something (e.g., convert it into something new).

[0033] In addition, the drain electrode layer overlaps with the oxygen-deficient high-resistance drain region (HRD). A resistance drain region is also formed. The oxygen-deficient high-resistance source region (HRS) overlaps the layer. e Source region) is formed.

[0034] Specifically, the carrier concentration in the high-resistance drain region is 1×10 18 / cm 3 Within the above range and the carrier concentration in the channel formation region is at least (1×10 18 / cm 3 Less than The carrier concentration in this specification is calculated from Hall effect measurements at room temperature. This refers to the carrier concentration value measured.

[0035] Then, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer is brought into an oxygen-excess state. By this, the resistance is further increased, that is, the I-type is formed, and a channel forming region is formed. The treatment for bringing the hydrated or dehydrogenated oxide semiconductor layer into an oxygen-excess state can be performed by dehydration or The oxide insulating film in contact with the dehydrogenated oxide semiconductor layer is formed by sputtering. or by heat treatment after the formation of an oxide insulating film, or by performing heat treatment in an atmosphere containing oxygen. Heat treatment, or heating in an inert gas atmosphere followed by cooling in an oxygen atmosphere, ultra-drying This is done by cooling with air (dew point below -40°C, preferably below -60°C) .

[0036] In addition, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer (which overlaps with the gate electrode layer) is In order to make the channel formation region in the region where the oxygen is present, a high resistance is achieved by selectively creating an oxygen-excess state. The oxide semiconductor layer may be in contact with the dehydrated or dehydrogenated oxide semiconductor layer. The source electrode layer and the drain electrode layer are formed of a metal electrode such as Ti. The exposed area that does not overlap with the drain electrode layer is selectively made into an oxygen-excessive state to form a channel formation area. When the oxygen-excess state is selectively created, a high A resistive source region and a high-resistive drain region overlapping the drain electrode layer are formed, The region between the source region and the high resistance drain region is the channel formation region. The channel length of the formation region is self-aligned with the source and drain electrode layers.

[0037] This allows the fabrication of a semiconductor device having thin film transistors with good electrical characteristics and high reliability. It will be possible to provide such information.

[0038] Note that a high-resistance drain region is formed in the oxide semiconductor layer overlapping with the drain electrode layer. This makes it possible to improve the reliability of the drive circuit. By forming a resistive drain region, the drain electrode layer, the high-resistance drain region, and the channel It is possible to form a structure in which the conductivity can be changed stepwise over the formation region. Therefore, when the drain electrode layer is connected to a wiring that supplies a high power supply potential VDD, Even if a high electric field is applied between the drain electrode layer and the drain electrode layer, the high resistance drain region acts as a buffer. This prevents a local high electric field from being applied, improving the breakdown voltage of the thin film transistor. It is possible.

[0039] In addition, in the oxide semiconductor layer overlapping with the drain electrode layer and the source electrode layer, By forming a high-resistance source region and a high-resistance in-region, the channel Specifically, the high resistance drain region can be formed by By forming the gate insulating film, the leakage current of the transistor flowing between the drain electrode layer and the source electrode layer is reduced. The drain electrode layer, the high-resistance drain region on the drain electrode layer side, and the channel-shaped The order is the channel region, the high resistance source region on the source electrode layer side, and the source electrode layer. In the drain formation region, the leakage current flows from the high-resistance drain region on the drain electrode layer side to the channel region. The gate insulating layer and the channel formation region interface, which has high resistance when the transistor is off, are The back channel (channel away from the gate electrode layer) can be concentrated in the vicinity of the gate electrode. It is possible to reduce leakage current in a portion of the surface of the formation region.

[0040] In addition, a high resistance source region overlapping the source electrode layer and a high resistance drain region overlapping the drain electrode layer are The gate region overlaps a part of the gate electrode layer via the gate insulating layer, depending on the width of the gate electrode layer. As a result, the electric field intensity in the vicinity of the end portion of the drain electrode layer can be more effectively reduced.

[0041] Further, an oxide conductive layer is formed between the oxide semiconductor layer and the source electrode layer and the drain electrode layer. The oxide conductive layer preferably contains zinc oxide as a component, and more preferably contains indium oxide. For example, zinc oxide, zinc aluminum oxide, oxynitride, Aluminum zinc oxide, zinc gallium oxide, or the like can be used. Resistance drain region (LRN(Low Resistance N-type conduit) ctivity region and LRD (Low Resistance Drain) region. Specifically, the carrier concentration in the low-resistance drain region is Larger than the rain region (HRD region), e.g. 1×10 20 / cm 3 More than 1×10 21 / cm 3 The oxide conductive layer is preferably in the range of 100 to 2000 nm. By providing the insulating layer between the drain electrode layer and the insulating layer, the contact resistance can be reduced, and the transistor can operate at high speed. This makes it possible to improve the frequency characteristics of the peripheral circuits (drive circuits). Cut.

[0042] The oxide conductive layer and the metal layer for forming the source electrode layer and the drain electrode layer are successively formed. It is possible.

[0043] The first and second wirings are formed by oxidizing the first and second wirings to function as LRN or LRD. Alternatively, the wiring may be a laminated wiring composed of the same material as the conductive layer and a metal material. By stacking conductive layers, the coverage of steps such as overcoming lower wiring and openings is improved. This reduces the wiring resistance. It is expected that this will have the effect of preventing high resistance and disconnection, making it possible to provide highly reliable semiconductor devices. can.

[0044] In addition, when the first wiring and the second wiring are connected as described above, the oxide conductive layer is sandwiched between them. By connecting the two parts together, an insulating oxide is formed on the metal surface of the connection part (contact part). It is expected that this will prevent the increase in contact resistance due to the contacts being damaged, resulting in highly reliable semiconductor equipment. Locations can be provided.

[0045] In addition, since thin-film transistors are easily damaged by static electricity, etc., For the line, a protection circuit for protecting the thin film transistor in the pixel area can be provided on the same substrate. The protection circuit is preferably formed using a nonlinear element using an oxide semiconductor layer. It is.

[0046] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. In addition, the specific names used in this specification are not intended to identify the invention. This does not indicate the

[0047] In addition, thin film transistors using oxide semiconductor layers are used in electronic devices and optical devices. For example, the switching element of a liquid crystal display device or the switching element of a light emitting device can be used. Thin film transistors using oxide semiconductor layers are being used for electronic devices and switching elements for electronic paper. It can be used.

[0048] In addition, the present invention is not limited to display devices, but also includes insulated gate semiconductor devices for controlling high power, particularly power MOS devices. It is also possible to fabricate semiconductor devices called power MOS devices. Examples include MOSFETs and IGBTs. Effect of the Invention

[0049] Reducing parasitic capacitance in a semiconductor device having a thin film transistor using an oxide semiconductor layer Furthermore, a semiconductor device with low power consumption can be provided.

[0050] In a semiconductor device having a thin film transistor using an oxide semiconductor layer, A conductor device can be provided. [Brief description of the drawings]

[0051] [Figure 1] 1A to 1C are diagrams illustrating a semiconductor device. [Diagram 2] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 3] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Diagram 5] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 7] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 8] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 9] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 10] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 11] 1A and 1B are diagrams illustrating a pixel equivalent circuit of a semiconductor device. [Figure 12] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 13]1A to 1C are diagrams illustrating a semiconductor device. [Figure 14] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 15] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 16] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 17] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 18] 1A and 1B are diagrams illustrating a pixel equivalent circuit of a semiconductor device. [Figure 19] 1A to 1C are diagrams illustrating a semiconductor device. [Figure 20] FIG. [Figure 21] FIG. [Figure 22] FIG. [Figure 23] FIG. [Figure 24] FIG. [Diagram 25] FIG. 4 is a diagram for explaining a multi-tone mask. [Figure 26] FIG. [Figure 27] FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0052] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0053] (Embodiment 1) One embodiment of a semiconductor device and a manufacturing method thereof will be described with reference to FIGS. .

[0054] FIG. 1 shows an example of a planar and cross-sectional structure of a semiconductor device. The transistor 410 is one of the bottom gate structures called channel etch type, and has an inverted staggered They are also called thin film transistors.

[0055] FIG. 1(A1) shows the gate wiring layer (formed in the same process as the gate electrode layer) and the source wiring layer ( (A2) is a plan view of the intersection with the channel etch type FIG. 1B is a plan view of a thin film transistor 410, and FIG. 1B is a plan view of a thin film transistor 410 along line C1-C in FIG. C2 and a cross-sectional view along line D1-D2.

[0056] The thin film transistor 410 is a channel-etch type thin film transistor having an insulating surface. On a substrate 400, a gate electrode layer 411, a gate insulating layer 402, and at least a channel forming layer are formed. The oxide layer 413 has a high-resistance source region 414a and a high-resistance drain region 414b. The semiconductor layer 412, the source electrode layer 415a, and the drain electrode layer 415b. The oxide insulating layer 407 covers the thin film transistor 410 and is in contact with the channel formation region 413. A protective insulating layer 408 is provided thereon.

[0057] The oxide insulating layer 407 and the protective insulating layer 408 are covered with a source electrode layer 415a and a drain electrode An opening (contact hole) is formed that reaches the layer 415b, and the wiring layers 417a and 4 On the other hand, at the intersection, the gate wiring layers 17b, 418a, and 418b are formed. 421 and source wiring layers 422 and 423 are formed by the gate insulating layer 402, the oxide insulating layer 407, and The layers are laminated with a protective insulating layer 408 interposed therebetween.

[0058] In this manner, the gate electrode layer (gate wiring layer) and the source electrode layer or the drain electrode layer are electrically connected to each other. The wiring layer that is electrically connected is an insulating layer that covers the oxide semiconductor layer of the thin film transistor and a gate insulating layer. The gate electrode layer and the source electrode layer of the thin film transistor are intersected with an edge layer. The gate electrode layer and the gate insulating layer are formed on the oxide semiconductor layer except that they are partially overlapped with each other. The semiconductor device does not have a stacked structure of a gate insulating layer, a source electrode layer, and a drain electrode layer.

[0059] Therefore, a stacked structure of a gate electrode layer, a gate insulating layer, and a source electrode layer or a drain electrode layer This reduces the parasitic capacitance formed by the Cut.

[0060] In addition, the thin film transistor 410 is described using a thin film transistor having a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A filter can also be formed.

[0061] Hereinafter, the steps of manufacturing a thin film transistor 410 on a substrate will be described with reference to FIGS. explain.

[0062] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 411 and a gate wiring layer 421 are formed by the process. The resist mask may be formed by an inkjet method. Since no photomask is used, manufacturing costs can be reduced.

[0063] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface. In either case, it is necessary for the barium phosphate to have sufficient heat resistance to withstand subsequent heat treatment. A glass substrate such as borosilicate glass or aluminoborosilicate glass can be used.

[0064] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. For the glass substrate, for example, aluminosilicate glass, alumina Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. By containing more barium oxide (BaO) than boric acid, it is possible to produce a more practical heat-resistant gas. For this reason, it is preferable to use a glass substrate containing more BaO than B2O3. Desired

[0065] Instead of the above glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may be used. Alternatively, crystallized glass or the like may be used.

[0066] An insulating film serving as a base film is provided between the substrate 400 and the gate electrode layer 411 and between the gate wiring layer 421. The base film has a function of preventing diffusion of impurity elements from the substrate 400. One or more selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film The insulating film may be formed as a single layer or a laminated structure.

[0067] The gate electrode layer 411 and the gate wiring layer 421 are made of molybdenum, titanium, quartz, or the like. Metallic materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium It can be formed in a single layer or a multilayer structure using a material or an alloy material mainly composed of the material. do.

[0068] Next, a gate insulating layer 402 is formed on the gate electrode layer 411 and the gate wiring layer 421. do.

[0069] The gate insulating layer 402 is a silicon oxide layer formed by using a plasma CVD method, a sputtering method, or the like. , a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer, For example, the deposition gas is SiH4, oxygen, and nitrogen. A silicon oxynitride layer may be formed by plasma CVD. The thickness is 100 nm to 500 nm. In the case of a multilayer structure, the thickness is, for example, 50 nm to 2 A first gate insulating layer having a thickness of 000 nm or less, and a second gate insulating layer having a thickness of 5 nm or more and 300 nm or less on the first gate insulating layer. The second gate insulating layer has a thickness of 1 m or less.

[0070] In this embodiment, the gate insulating layer 402 is formed by a plasma CVD method to a thickness of 200 nm or more. A bottom silicon nitride layer is formed.

[0071] Next, an oxide semiconductor film 44 with a thickness of 2 nm to 200 nm is formed over the gate insulating layer 402. After the oxide semiconductor film 440 is formed, heat treatment for dehydration or dehydrogenation is performed. In order to make the oxide semiconductor film amorphous even if the oxide semiconductor film is subjected to the etching treatment, the thickness of the oxide semiconductor film is set to be as thin as 50 nm or less. It is preferable that the oxide semiconductor layer is thinned so that the heat treatment after the formation of the oxide semiconductor layer is not required. When the mixture is cured, crystallization can be suppressed.

[0072] Note that before the oxide semiconductor film 440 is formed by a sputtering method, argon gas is introduced. The reverse sputtering is performed by introducing the metal into the gate insulating layer 402 to generate plasma. It is preferable to remove the dust that is generated by the sputtering. In an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. In addition, nitrogen, helium, oxygen, etc. can be used instead of argon atmosphere. Either may be used.

[0073] The oxide semiconductor film 440 is an In-Ga-Zn-O based non-single crystal film, an In-Sn-Zn-O based , In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn- Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O Based on the above, a Sn-O based or Zn-O based oxide semiconductor film is used.

[0074] In this embodiment, the oxide semiconductor film 440 is an In—Ga—Zn—O-based oxide semiconductor film. The cross section at this stage is shown in Figure 2(A). The oxide semiconductor film 440 is heated under a rare gas (typically, argon) atmosphere with oxygen. Sputtering is performed under a nitrogen atmosphere or under an atmosphere of rare gas (typically argon) and oxygen. In addition, when using the sputtering method, SiO2 is formed by % by weight or more and 10% by weight or less. The inclusion of SiOx (X>0) inhibits crystallization, and prevents dehydration or dehydrogenation in the subsequent process. It is preferable to suppress crystallization during the heat treatment for the purpose of the present invention.

[0075] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[atom ratio ]) was used, the distance between the substrate and the target was 100 mm, the pressure was 0.2 Pa, and the direct current (D C) Power supply 0.5 kW, argon and oxygen (argon:oxygen = 30 sccm:20 sccm The film is formed in an atmosphere of 40% oxygen flow rate. This is preferable because it reduces dust and makes the film thickness distribution uniform. The thickness of the crystal film is greater than or equal to 5 nm and less than or equal to 200 nm. As a result, the In-Ga-Zn-O oxide semiconductor target was used for sputtering. In-Ga-Zn-O non-single crystal film with a thickness of 20 nm is formed. As an oxide semiconductor target containing In and Zn, In:Ga:Zn=1:1:1[atom ratio], or a target having a composition ratio of In:Ga:Zn=1:1:2 [atom ratio] It can also be used.

[0076] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and D There is also the C sputtering method, which uses a pulsed bias. The RF sputtering method is mainly used to deposit insulating films, while the DC sputtering method is The deposition method is mainly used when forming a metal film.

[0077] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0078] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. The ECR device uses a plasma generated by microwaves instead of glow discharge. There is a sputtering device that uses the sputtering method.

[0079] In addition, as a method for forming a film using a sputtering method, a target material and a sputtering gas are interposed during film formation. Reactive sputtering method to form a compound thin film by chemically reacting with the silicon component. There is also a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0080] Next, the oxide semiconductor film 440 is processed into an island-shaped oxide semiconductor film by a second photolithography process. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is applied to the ink. If the resist mask is formed by the inkjet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0081] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and an oxide semiconductor is The layer was heated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to air. Therefore, water or hydrogen is prevented from being recontaminated into the oxide semiconductor layer, and the oxide semiconductor layer 441 is obtained. See Figure 2(B).

[0082] The following reaction pathway was analyzed as an example of the mechanism of water desorption from an oxide semiconductor film. (In the oxide semiconductor film, the reaction occurs not only as water but also as OH or H.) An In-Ga-Zn-O amorphous film was used as the conductor film.

[0083] In addition, the optimal molecular structure in the ground state of the computational model was calculated using density functional theory (DFT). The total energy of DFT is calculated by the potential energy, the electrostatic energy between electrons, and the electric field. It is expressed as the sum of the kinetic energy of the electrons and the exchange-correlation energy that includes all the complex interactions between electrons. In DFT, the exchange-correlation interaction is expressed as a generalized function of the one-electron potential represented by the electron density. Since the function is approximated by a function of a function, the calculation is fast and highly accurate. Using the composite functional B3LYP, we calculate the weights of the parameters related to the exchange and correlation energies. In addition, the basis functions for indium, gallium and zinc atoms are Lan L2DZ (a basis set that adds a split valence basis set to the effective shell potential of the Ne shell) For the other atoms, 6-311 (three contraction functions are used for each valence orbital) The basis functions of the triple split valence basis set mentioned above were applied. For example, for hydrogen atoms, the 1s to 3s orbitals are considered, and for oxygen In the case of atoms, the orbitals 1s to 4s and 2p to 4p are taken into account. To improve accuracy, p-functions were added to the hydrogen atoms and d-functions to the oxygen atoms as polarization basis sets. .

[0084] The quantum chemical calculation program used was Gaussian03. The experiment was carried out using a high-performance computer (SGI, Altix 4700).

[0085] By heat treatment for dehydration or dehydrogenation, -OH groups in the oxide semiconductor film are bonded to each other. It is thought that the reaction produces H2O. Therefore, the water production and desorption mechanism shown in Figure 26 is In Figure 26, since Zn is divalent, in the case of M=Zn, One MO bond in Figure 26 has been deleted.

[0086] In Figure 26, M represents a metal atom, and there are three types of metal atoms: In, Ga, and Zn. Initial state 1 In transition state 2, -OH forms a coordinate bond to bridge M1 and M2. The H of H is transferred to another -OH. In intermediate 3, the generated H2O molecule is bonded to the metal atom. A coordinate bond is formed. In the final state 4, the H2O molecule is detached and moves away to infinity.

[0087] The total combinations of (M1-M2) are: 1. In-In, 2. Ga-Ga, 3. Zn-Zn, There are six combinations: 4. In-Ga, 5. In-Zn, and 6. Ga-Zn. In this calculation, M' was replaced with H for the sake of simplicity. This was performed using a cluster calculation with a computational model.

[0088] In the calculation, the energy diagram corresponding to the reaction path in Figure 26 was obtained. As a representative combination of M1-M2, the calculation results for the case of 1. In-In are shown in Figure 27. vinegar.

[0089] From Figure 27, it was found that the activation energy for water production was 1.16 eV. When a water molecule is removed, the energy becomes unstable by about 1.58 eV.

[0090] Conversely, when the reaction in FIG. 27 proceeds from right to left, water enters the oxide semiconductor film. This can be seen as follows. Then, the water coordinated to the metal is hydrolyzed, creating two OH groups. The activation energy for this reaction is 0.47 eV.

[0091] Similarly, the reaction pathways for other combinations of (M1-M2) were analyzed. 1-6 Table 1 shows the activation energy (Ea [eV]) of the water production reaction for the case.

[0092] [Table 1]

[0093] From Table 1, it can be seen that the water generation reaction is likely to occur in 1.In-In and 4.In-Ga. On the other hand, the water-producing reaction is unlikely to occur in the Zn-Zn system. It is speculated that the water-producing reaction via the ion exchange membrane tends to be less likely to occur.

[0094] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Annealing equipment such as RTA (Rapid Thermal Annealing) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gas is used.

[0095] For example, the first heat treatment is performed by subjecting the substrate to a base in an inert gas heated to a high temperature of 650° C. to 700° C. The plate is moved and placed in the oven, heated for a few minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. Using GRTA, high-temperature heat treatment can be performed in a short time. become.

[0096] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the concentration of impurities is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to keep the concentration of the ion exchange resin at 0.1 ppm or less.

[0097] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized and microcrystalline. For example, the crystallinity may be 90% or more, or 80% or more. In addition, depending on the conditions of the first heat treatment or the amount of the acid, the oxide semiconductor film may become a microcrystalline oxide semiconductor film. Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor film that does not contain crystalline components. In addition, there are cases where a microcrystalline portion (grain size 1 nm or more and 20 nm or less (typically In some cases, the oxide semiconductor film may have a thickness of 2 nm or more and 4 nm or less. When high-temperature heat treatment is performed using RTA (GRTA, LRTA), the surface of the oxide semiconductor film In some cases, needle-like crystals may appear on the side of the film in the vertical direction (film thickness direction).

[0098] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 440 may be subjected to the first heat treatment. In that case, the semiconductor film 440 may be heated by the heating device after the first heat treatment. The substrate is taken out and a photolithography process is performed.

[0099] The heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer is performed after the formation of the oxide semiconductor layer. After the source electrode and the drain electrode are laminated on the semiconductor layer, the source electrode and the drain electrode After forming a protective insulating film thereon, the above-mentioned step may be performed.

[0100] In addition, when a contact hole is formed in the gate insulating layer 402, the process is performed using an oxide semiconductor This may be done before or after the membrane 440 is subjected to a dehydration or dehydrogenation treatment.

[0101] The oxide semiconductor layer is preferably an oxide semiconductor containing In, more preferably In, In order to make the oxide semiconductor layer i-type (intrinsic), Hydration or dehydrogenation is effective.

[0102] Note that the etching of the oxide semiconductor film here is not limited to wet etching and may be dry etching. Etching may also be used.

[0103] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0104] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0105] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0106] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide water: 28% by weight ammonia water: water = 5:2:2) Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0107] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium, etc. contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0108] In order to etch the desired shape, the etching conditions (etching Adjust the etching conditions (liquid, etching time, temperature, etc.) as appropriate.

[0109] Next, a metal conductive film is formed over the gate insulating layer 402 and the oxide semiconductor layer 441. A resist mask is formed by a third photolithography process, and selective etching is performed. After forming the source electrode layer 415a and the drain electrode layer 415b, a resist mask is Remove (see Figure 2(C)).

[0110] Note that the oxide semiconductor layer 441 is etched so as not to be removed when the metal conductive film is etched. The materials and etching conditions are adjusted accordingly.

[0111] In this embodiment, a Ti film is used as the metal conductive film, and an In- Using Ga-Zn-O oxide, and using ammonia hydrogen peroxide as an etchant (ammonia, A mixture of water and hydrogen peroxide is used.

[0112] The source electrode layer and the drain electrode layer are preferably thin, with a thickness of 0.1 nm to 50 nm. The source electrode layer and the drain electrode layer are made of a thin conductive film. Therefore, the parasitic capacitance with the gate electrode layer can be reduced.

[0113] The source electrode layer and the drain electrode layer are made of a material containing a metal with high oxygen affinity. The metal having high oxygen affinity is preferably titanium, aluminum, or manganese. , magnesium, zirconium, beryllium, or thorium. In this embodiment, the source electrode layer and the drain electrode layer are preferably made of a material having a thickness of 100 nm or less. A titanium film is used as the substrate.

[0114] When an oxide semiconductor layer is brought into contact with a metal layer having a high oxygen affinity and heat treatment is performed, the oxide semiconductor Oxygen atoms move from the semiconductor layer to the metal layer, increasing the carrier density near the interface. As a result, a low-resistance region is formed near the interface, and the oxide semiconductor layer and the source electrode layer and the drain electrode layer are The contact resistance with the inner electrode layer can be reduced.

[0115] Further, a heat-resistant conductive material may be used for the source electrode layer and the drain electrode layer. When the material is used, the source electrode layer and the drain electrode layer can be formed without any problem even if a heat treatment is performed after the formation of the source electrode layer and the drain electrode layer. This can prevent the gate electrode layer and the drain electrode layer from being altered or deteriorated.

[0116] Heat-resistant conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), Choose from molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). The elements mentioned above, or alloys containing the above elements or combinations of the above elements A film or a nitride containing the above-mentioned elements can be used. The above heat-resistant conductive materials are combined with low-resistance conductive materials such as aluminum (Al) and copper (Cu). Alternatively, a conductive film having improved heat resistance due to heating may be used.

[0117] The source and drain electrode layers may also include a metal oxide layer. For example, a metal oxide layer may include a semiconductor layer. A structure having a titanium oxide film between a conductor layer and a titanium film, or a titanium film (for example, a film thickness of 0.1 A titanium oxide film (for example, a film thickness of 1 nm to 20 nm) is placed between the oxide insulating layer and the titanium oxide film. The structure may have a thickness of 1 nm or less.

[0118] In addition, when the source electrode layer and the drain electrode layer are thin enough to transmit light, The source electrode layer and the drain electrode layer have a light-transmitting property.

[0119] Note that in the third photolithography step, the oxide semiconductor layer 441 is only partially etched. In some cases, the source electrode layer 4 is formed as an oxide semiconductor layer having a groove (a recess). 15a, and a resist mask for forming the drain electrode layer 415b is formed by inkjet printing. If the resist mask is formed by the inkjet method, a photomask can be used. Since no additional wiring is required, manufacturing costs can be reduced.

[0120] In order to reduce the number of photomasks and steps used in the photolithography process, The resist pattern is formed by a multi-tone mask, which is an exposure mask that allows the light to be projected at multiple intensities. The etching process may be performed using a resist mask formed using a multi-tone mask. The mask has a shape with multiple film thicknesses, and the shape can be further deformed by etching. This allows for multiple etching processes to be performed to create different patterns. Therefore, one multi-tone mask can handle at least two different patterns. Therefore, the number of exposure masks can be reduced. Since the corresponding photolithography process can also be eliminated, the process can be simplified.

[0121] Next, a plasma treatment is performed using a gas such as N2O, N2, or Ar. The annealing process removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor layer. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0122] After the plasma treatment, the protective insulating film in contact with a part of the oxide semiconductor layer is removed without being exposed to the air. An oxide insulating layer 407 serving as an insulating film is formed.

[0123] The oxide insulating layer 407 has a thickness of at least 1 nm and is formed by an oxide insulating method such as a sputtering method. The edge layer 407 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed in. When hydrogen is contained in the oxide insulating layer 407, the hydrogen may enter the oxide semiconductor layer or the hydrogen may be released from the oxide semiconductor layer. The oxygen in the oxide semiconductor layer is extracted by the hydrogen, and the back channel of the oxide semiconductor layer is formed. The resistance of the oxide insulating layer 40 becomes low (N-type), and a parasitic channel is formed. It is important not to use hydrogen in the deposition method so that the film contains as little hydrogen as possible. be.

[0124] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering as the oxide insulating layer 407. The film is formed using the ring method. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering using a rare gas. (typically argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) The deposition can be carried out under an oxygen atmosphere. For example, a silicon target can be used to irradiate oxygen and A silicon oxide film can be formed by sputtering in a nitrogen atmosphere. The oxide insulating layer 407 formed in contact with the oxide semiconductor layer is resistant to moisture, hydrogen ions, , O.H. - Inorganic insulation that does not contain impurities such as these and blocks their intrusion from the outside A film is used, typically a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or a nitride oxide film. Aluminum oxide, etc., is used.

[0125] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. For example, the heating is performed in a nitrogen atmosphere. The second heat treatment is performed at 250° C. for 1 hour under atmospheric pressure. A part of the semiconductor layer (channel formation region) is heated in a state where the part is in contact with the oxide insulating layer 407 .

[0126] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor film is selectively As a result, the channel formation region 413 overlapping with the gate electrode layer 411 has an I-type structure. The high resistance source region 414a overlapping the source electrode layer 415a and the drain electrode layer 41 By the above steps, a thin A membrane transistor 410 is formed.

[0127] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By this heat treatment, the oxide insulating film is removed from the oxide semiconductor layer. Hydrogen is incorporated into the edge layer, resulting in a normally-off thin-film transistor. This makes it possible to improve the reliability of the semiconductor device.

[0128] Note that the oxide semiconductor layer overlapping with the drain electrode layer 415b (and the source electrode layer 415a) forming a high-resistance drain region 414b (and a high-resistance source region 414a) in As a result, the reliability of the thin film transistor can be improved. By forming the drain region 414b, the high-resistance drain region 4 14b. A structure capable of gradually changing the conductivity in the channel forming region. Therefore, the drain electrode layer 415b is connected to a wiring that supplies a high power supply potential VDD. When the transistor is operated continuously, a high electric field is generated between the gate electrode layer 411 and the drain electrode layer 415b. Even if a high electric field is applied, the high-resistance drain region acts as a buffer and a high electric field is not applied locally. This allows for a configuration that improves the breakdown voltage of the transistor.

[0129] The high-resistance source region or the high-resistance drain region in the oxide semiconductor layer is preferably an oxide semiconductor. When the thickness of the oxide layer is thin, 15 nm or less, it is formed throughout the thickness direction. When the thickness of the conductor layer is thicker, 30 nm or more and 50 nm or less, a part of the oxide semiconductor layer, The region in contact with the source electrode layer or the drain electrode layer and its vicinity have low resistance, forming a high resistance source region. Alternatively, a high-resistance drain region is formed, and a region of the oxide semiconductor layer close to the gate insulating film is It can also be type I.

[0130] A protective insulating layer may be further formed on the oxide insulating layer 407. For example, RF sputtering The RF sputtering method is excellent for mass production, so it is safe to use. This is a preferred method for forming a protective insulating layer. The protective insulating layer is formed by absorbing moisture, hydrogen ions, and OH - etc. The inorganic insulating film is free of impurities such as nitrogen and blocks their intrusion from the outside. A silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, or the like is used. In this embodiment mode, the protective insulating layer 408 is formed using a silicon nitride film. (See Figure 2(D)).

[0131] Next, a resist mask is formed by a fourth photolithography process and selectively etched. The oxide insulating layer 407 and the protective insulating layer 408 are partially removed by etching to form the source electrode layer 4 15a, openings 442a and 442b reaching the drain electrode layer 415b are formed (FIG. 2(E) )reference.).

[0132] Openings 442a and 442b are formed so as to contact the source electrode layer 415a and the drain electrode layer 415b. A laminated conductive layer is formed on the substrate by sputtering or vacuum deposition, and a fifth photolithography is performed. A resist mask is formed by a etching process. The laminated conductive layer is selectively etched to form the wiring layer 4. 17a, 417b, 418a, 418b, at the intersections, source wiring layers 422, 423 (See FIG. 2(F).)

[0133] The wiring layers 417a, 417b, 418a, and 418b are formed from the source electrode layer and the drain electrode layer. A conductive film with low resistance is used. Specifically, aluminum, copper, chromium, tantalum, molybdenum, etc. Metallic materials such as tungsten, titanium, neodymium, scandium, etc., or materials containing these as the main components The insulating film can be formed as a single layer or a stacked layer using an alloy material having the above structure. A laminated structure is used as the wiring layer, and the first wiring layers 417a and 417b are made of aluminum. The first wiring layer 418a and the second wiring layer 418b are made of titanium films.

[0134] A planarization insulating layer for planarization may be provided over the protective insulating layer 408. FIG. 6A shows an example of such a structure. In FIG. 6A, a planarizing insulating layer 409 is formed on a protective insulating layer 408. The wiring layers 417a, 417b, 418a, and 418b are formed on the oxide insulating layer 407. The semiconductor device is formed in an opening provided in the protective insulating layer 408 and the planarizing insulating layer 409. The wiring layers 422 and 423 are formed on the planarized insulating layer 409. By providing the gate wiring layer 421, the distance between the gate wiring layer 421 and the source wiring layers 422 and 423 becomes longer. Therefore, the parasitic capacitance can be further reduced.

[0135] The planarization insulating layer 409 may be made of polyimide, acrylic, benzocyclobutene, or polyamide. In addition to the above organic materials, organic materials having heat resistance such as epoxy can be used. Low-k materials, siloxane resins, PSG (phosphorus glass), BP SG (silicon boron glass) can be used. The planarization insulating layer 409 may be formed by stacking a plurality of insulating films.

[0136] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0137] The method for forming the planarization insulating layer 409 is not particularly limited. Depending on the material, a sputtering method may be used. , spin coating method, dipping method, spray coating method, droplet ejection method (inkjet method, Screen printing, offset printing, etc.), roll coating method, curtain coating method, knife coating method The method, etc. can be used.

[0138] In addition, as shown in FIG. 6B, a protective insulating layer is not provided, and a wiring layer, a sawtooth layer, and a semiconductor layer are formed on the oxide insulating layer 407. In FIG. 6B, a source wiring layer may be formed on the oxide insulating layer 407. 422 is provided, and wiring layers 417a and 417b are provided in the openings formed in the oxide insulating layer 407. In this manner, the wiring layer may also have a single-layer structure.

[0139] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, It is possible to provide a semiconductor device with reduced parasitic capacitance and low power consumption.

[0140] In addition, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, Therefore, a high-performance semiconductor device can be provided.

[0141] (Embodiment 2) In this embodiment, a semiconductor device having a thin film transistor with a structure different from that of the first embodiment is used. An example of this will be described below.

[0142] FIG. 3 shows an example of a planar and cross-sectional structure of a semiconductor device. The 450 transistor is a bottom gate type called a channel protection type (also called a channel stop type). This is one of the gate structures and is also called an inverted staggered thin film transistor.

[0143] FIG. 3(A1) shows a gate wiring layer (formed in the same process as the gate electrode layer) and a source wiring layer ( (A1) is a plan view of the intersection with the channel protection type thin film (formed in the same process as the wiring layer). FIG. 3B is a plan view of the membrane transistor 450 along the line C3-C in FIG. 3A. 4 and a cross-sectional view taken along line D3-D4.

[0144] The thin film transistor 450 is a channel-protected thin film transistor having an insulating surface. On a substrate 400, a gate electrode layer 451, a gate insulating layer 402, and at least a channel forming region are formed. 453, a high-resistance source region 454a, and a high-resistance drain region 454b. The semiconductor layer 452, the source electrode layer 455a, and the drain electrode layer 455b are included. The film transistor 450 is covered, the film transistor 450 is in contact with the channel forming region 413, and functions as a channel protection layer. A functional oxide insulating layer 456 is provided, and a protective insulating layer 408 is provided thereon. do.

[0145] The protective insulating layer 408 has openings reaching the source electrode layer 455a and the drain electrode layer 455b. (contact holes) are formed in the openings, and wiring layers 457a, 457b, 458a, 45 On the other hand, at the intersection, the gate wiring layer 421 and the source wiring layer 4 22 and 423 are formed between the gate insulating layer 402, the oxide insulating layer 459, and the protective insulating layer 408. The layers are stacked in a layered manner.

[0146] Although it is not necessary to provide the oxide insulating layer 459 at the intersection, the oxide insulating layer 459 By providing the gate wiring layer 421, the source wiring layers 422 and 423 can be spaced apart from each other. Therefore, the parasitic capacitance can be further reduced.

[0147] The oxide insulating layer 456 and the oxide insulating layer 459 are formed by processing the oxide insulating layer by etching. The material and the manufacturing method of the oxide insulating layer 407 described in Embodiment 1 can be similar to those of the oxide insulating layer 407. In this embodiment, an oxide insulating layer is formed by a sputtering method, and a photolithography method is performed. The oxide insulating layer 456 and the oxide insulating layer 459 are formed by a lithography process.

[0148] In this manner, the gate electrode layer (gate wiring layer) and the source electrode layer or the drain electrode layer are electrically connected to each other. The wiring layer that electrically connects the thin film transistor is a protective insulating layer and a gate insulating layer that cover the thin film transistor. The gate electrode layer, the source electrode layer, and the drain electrode layer of the thin film transistor are intersected. The electrode layer includes a gate electrode layer, a gate insulating layer, and a source electrode layer, except for a portion overlapping the oxide semiconductor layer. The semiconductor device does not have a laminated structure of a source electrode layer and a drain electrode layer.

[0149] Therefore, a stacked structure of a gate electrode layer, a gate insulating layer, and a source electrode layer or a drain electrode layer This reduces the parasitic capacitance formed by the Cut.

[0150] In addition, the thin film transistor 450 is described using a thin film transistor having a single gate structure. However, if necessary, a thin-film transistor having a multi-gate structure having multiple channel formation regions may be used. A filter can also be formed.

[0151] Hereinafter, the process of manufacturing a thin film transistor 450 on a substrate will be described with reference to FIGS. explain.

[0152] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography process is performed. A gate electrode layer 451 and a gate wiring layer 421 are formed by the process. The resist mask may be formed by an inkjet method. Since no photomask is used, manufacturing costs can be reduced.

[0153] The gate electrode layer 451 and the gate wiring layer 421 are formed of molybdenum, titanium, quartz, or the like. Metallic materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium It can be formed in a single layer or a multilayer structure using a material or an alloy material mainly composed of the material. do.

[0154] Next, a gate insulating layer 402 is formed over the gate electrode layer 451 and the gate wiring layer 421. do.

[0155] In this embodiment, the gate insulating layer 402 is formed by a plasma CVD method to a thickness of 200 nm or more. A bottom silicon nitride layer is formed.

[0156] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the gate insulating layer 402. The oxide semiconductor layer is then processed into an island shape by a second photolithography process. In this embodiment, an In-Ga-Zn-O oxide semiconductor target is used as the oxide semiconductor film. The film is formed by a sputtering method.

[0157] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and 750° C. or lower, preferably 400° C. or higher to prevent distortion of the substrate. Here, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and an oxide semiconductor is The layer was heated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to air. Therefore, water or hydrogen is prevented from being recontaminated into the oxide semiconductor layer, and the oxide semiconductor layer 441 is obtained. See Figure 4(A).

[0158] Next, a plasma treatment is performed using a gas such as N2O, N2, or Ar. The annealing process removes adsorbed water and other substances adhering to the exposed surface of the oxide semiconductor layer. Alternatively, the plasma treatment may be performed using a mixed gas of oxygen and argon.

[0159] Next, an oxide insulating layer was formed over the gate insulating layer 402 and the oxide semiconductor layer 441. After that, a resist mask is formed by a third photolithography process, and selective etching is performed. After the oxide insulating layer 456 and the oxide insulating layer 459 are formed, the resist mask is removed. do.

[0160] In this embodiment, the oxide insulating layer 456 and the oxide insulating layer 459 are formed of a 200-nm-thick oxide insulating film. The silicon oxide film is formed by sputtering. The substrate temperature during film formation is 300°C above room temperature. The temperature is set to 100° C. in this embodiment. The deposition is carried out under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas ( Typically, the reaction can be carried out under an atmosphere of argon and oxygen. A silicon oxide target or a silicon target can be used as the target. Using a get, a silicon oxide film is formed by sputtering in an oxygen and nitrogen atmosphere. The oxide insulating layer 456 formed in contact with the low-resistance oxide semiconductor layer can be Water, hydrogen ions, and OH - It does not contain impurities such as these, and prevents them from entering from the outside. A blocking inorganic insulating film is used, typically a silicon oxide film, a silicon nitride oxide film, or an aluminum oxide film. Aluminium film, or aluminum oxynitride, etc., is used.

[0161] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower). For example, A second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. The oxide semiconductor layer is heated while a part of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 456. do.

[0162] In this embodiment, an oxide semiconductor The oxide insulating layer 441 is subjected to heat treatment in a nitrogen or inert gas atmosphere or under reduced pressure. The exposed region of the oxide semiconductor layer 441 that is not covered by the insulating layer 56 is filled with nitrogen, an inert gas, or the like. The resistance can be reduced by performing a heat treatment in a nitrogen atmosphere or under reduced pressure. Heat treatment is carried out in an atmosphere at 250° C. for 1 hour.

[0163] Heat treatment in a nitrogen atmosphere on the oxide semiconductor layer 441 provided with the oxide insulating layer 456 As a result, the exposed region of the oxide semiconductor layer 441 has a low resistance, and the region with a different resistance (FIG. 4(B) ) is an oxide semiconductor layer 452 having a diagonal line region and a white region.

[0164] Then, a gold film was formed over the gate insulating layer 402, the oxide semiconductor layer 452, and the oxide insulating layer 456. After forming the metal conductive film, a resist mask is formed by a fourth photolithography process. Selective etching was performed to form the source electrode layer 455a and the drain electrode layer 455b. Thereafter, the resist mask is removed (see FIG. 4(C)).

[0165] The source electrode layer 455a and the drain electrode layer 455b have a thickness of 0.1 nm to 50 nm. The thickness of the source electrode layer and the drain electrode layer is preferably as thin as 100 nm or less, and is thinner than the thickness of the wiring layer. Since the conductive film is a thin film, the parasitic capacitance with the gate electrode layer can be reduced.

[0166] The source electrode layer 455a and the drain electrode layer 455b each contain a metal having high oxygen affinity. It is preferable to use a material having a high oxygen affinity. Any one of nium, manganese, magnesium, zirconium, beryllium, and thorium In this embodiment, the source electrode layer 45 is preferably made of a material selected from the group consisting of 1 or more. A titanium film is used as the gate electrode layer 5a and the drain electrode layer 455b.

[0167] When an oxide semiconductor layer is brought into contact with a metal layer having a high oxygen affinity and heat treatment is performed, the oxide semiconductor Oxygen atoms move from the semiconductor layer to the metal layer, increasing the carrier density near the interface. As a result, a low-resistance region is formed near the interface, and the oxide semiconductor layer and the source electrode layer and the drain electrode layer are The contact resistance with the inner electrode layer can be reduced.

[0168] In addition, a heat-resistant conductive material may be used for the source electrode layer 455a and the drain electrode layer 455b. When a heat-resistant conductive material is used, the source electrode layer 455a and the drain electrode layer 455b can be formed. Even if heat treatment is performed after the formation of the source electrode layer 455a and the drain electrode layer 455b, the source electrode layer 455a and the drain electrode layer 455b are not changed or deteriorated. can be prevented.

[0169] Heat-resistant conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), Choose from molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). The elements mentioned above, or alloys containing the above elements or combinations of the above elements A film or a nitride containing the above-mentioned elements can be used. The above heat-resistant conductive materials are combined with low-resistance conductive materials such as aluminum (Al) and copper (Cu). A conductive film having improved heat resistance due to heating may be used.

[0170] The source electrode layer 455a and the drain electrode layer 455b may include a metal oxide layer. For example, a structure having a titanium oxide film between an oxide semiconductor layer and a titanium film, or a structure having a titanium film ( For example, a titanium oxide film (e.g., a film having a thickness of 0.1 nm to 5 nm) is placed between the oxide insulating layer and the titanium oxide film (e.g., a film having a thickness of 0.1 nm to 5 nm). The thickness may be 1 nm or more and 20 nm or less.

[0171] In addition, the source electrode layer 455a and the drain electrode layer 455b have a small thickness so as to transmit light. In that case, the source electrode layer 455a and the drain electrode layer 455b have a light-transmitting property.

[0172] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor film is selectively As a result, a channel formation region 453 overlapping with the gate electrode layer 451 has an i-type structure. A high-resistance source region 454a overlapping the source electrode layer 455a and a drain electrode layer 45 By the above steps, a thin A membrane transistor 450 is formed.

[0173] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By this heat treatment, the oxide insulating film is removed from the oxide semiconductor layer. Hydrogen is incorporated into the edge layer, resulting in a normally-off thin-film transistor. This makes it possible to improve the reliability of the semiconductor device.

[0174] Note that the oxide semiconductor layer overlapping with the drain electrode layer 455b (and the source electrode layer 455a) forming a high-resistance drain region 454b (and a high-resistance source region 454a) in As a result, the reliability of the thin film transistor can be improved. By forming the drain region 454b, the high-resistance drain region 4 54b, a structure capable of gradually changing the conductivity toward the channel forming region. Therefore, the drain electrode layer 415b is connected to a wiring that supplies a high power supply potential VDD. When the transistor is operated continuously, a high electric field is applied between the gate electrode layer 451 and the drain electrode layer 455b. Even if a high electric field is applied, the high-resistance drain region acts as a buffer and a high electric field is not applied locally. This allows for a configuration that improves the breakdown voltage of the transistor.

[0175] A source electrode layer 455a, a drain electrode layer 455b, an oxide insulating layer 456, and an oxide insulating layer 4 A protective insulating layer 408 is formed on the insulating film 59. For example, a silicon nitride film is formed by RF sputtering. Since the RF sputtering method is suitable for mass production, it is used as the method for forming the protective insulating layer 408. The protective insulating layer 408 is preferably formed by absorbing moisture, hydrogen ions, and OH ions. - Impurities such as The inorganic insulating film is free of silicon nitride and blocks these substances from entering from the outside. An aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, or the like is used. In this embodiment, the protective insulating layer 408 is formed using a silicon nitride film (see FIG. 4D).

[0176] The source electrode layer 455a, the drain electrode layer 455b, the oxide insulating layer 456, and the oxide insulating layer 457 are An oxide insulating layer is further formed on the edge layer 459, and a protective insulating layer 408 is laminated on the oxide insulating layer. Alternatively, a planarizing insulating layer 409 as shown in FIG. When the insulating layer 409 is provided, the distance between the gate wiring layer 421 and the source wiring layers 422 and 423 is Since the length of the wiring becomes longer, the parasitic capacitance can be further reduced.

[0177] Next, a resist mask is formed by a fifth photolithography process and selectively etched. A part of the protective insulating layer 408 is removed by etching to form a source electrode layer 455a and a drain electrode Openings 467a and 467b are formed reaching layer 455b (see FIG. 4(E)).

[0178] Openings 467a and 467b are formed so as to contact the source electrode layer 455a and the drain electrode layer 455b. A laminated conductive layer is formed on the substrate by a sputtering method or a vacuum deposition method, and a sixth photolithography is performed. A resist mask is formed by a etching process. The laminated conductive layer is selectively etched to form the wiring layer 4. 57a, 457b, 458a, 458b, at the intersections, the source wiring layers 422, 423 (See FIG. 4(F)).

[0179] The wiring layers 457a, 457b, 458a, and 458b are formed from the source electrode layer and the drain electrode layer. A conductive film with low resistance is used. Specifically, aluminum, copper, chromium, tantalum, molybdenum, etc. Metallic materials such as tungsten, titanium, neodymium, scandium, etc., or materials containing these as the main components The insulating film can be formed as a single layer or a stacked layer using an alloy material having the above structure. A laminated structure is used as the wiring layer, and the first wiring layers 457a and 457b are made of aluminum. The first wiring layer 458a and the second wiring layer 458b are made of titanium films.

[0180] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, It is possible to provide a semiconductor device with reduced parasitic capacitance and low power consumption.

[0181] In addition, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, Therefore, a high-performance semiconductor device can be provided.

[0182] (Embodiment 3) In this embodiment mode, a part of a manufacturing process of a semiconductor device having a thin film transistor is Another example different from 1 is shown in Fig. 5. Fig. 5 is the same as Fig. 1 and Fig. 2 except for some differences in the process. Therefore, the same reference numerals are used for the same parts, and detailed explanations of the same parts will be omitted. In the embodiment, a mask layer formed by a multi-tone mask in a photolithography process is Use.

[0183] The mask layer formed using the multi-tone mask has a shape with multiple film thicknesses. The shape can be further modified by etching the metal into different patterns. It can be used for multiple etching processes. Thus, mask layers corresponding to at least two different patterns can be formed. This reduces the number of exposure masks and the corresponding photolithography steps. This makes it possible to simplify the process.

[0184] According to the first embodiment, a gate wiring is formed on a substrate 400 by a first photolithography process. A line layer 421 and a gate electrode layer 481 are formed, and a gate insulating layer 402 is laminated. An oxide semiconductor film is formed over the layer 402. In this embodiment, the oxide semiconductor film is formed of In The film is formed by sputtering using a Ga-Zn-O based oxide semiconductor target.

[0185] For dehydration or dehydrogenation, the substrate is introduced into an electric furnace, which is a type of heat treatment device, and an oxide is formed. The semiconductor layer was heat-treated at 450°C for 1 hour in a nitrogen atmosphere, and then exposed to air. The oxide semiconductor film 465 is obtained by preventing water or hydrogen from re-entering the oxide semiconductor layer without any damage. do.

[0186] Next, a metal conductive film 466 is formed over the oxide semiconductor film 465 by a sputtering method or a vacuum evaporation method. (See FIG. 5(A)).

[0187] The metal conductive film 466 is a conductive film to be a source electrode layer and a drain electrode layer. The drain electrode layer is preferably a thin layer having a thickness of 0.1 nm to 50 nm. Since the source and drain electrode layers are thin conductive films, The parasitic capacitance between the gate electrode layer and the gate electrode layer can be reduced.

[0188] The source electrode layer and the drain electrode layer are made of a material containing a metal with high oxygen affinity. The metal having high oxygen affinity is preferably titanium, aluminum, or manganese. , magnesium, zirconium, beryllium, or thorium. In this embodiment, the source electrode layer and the drain electrode layer are preferably made of a material having a thickness of 100 nm or less. A titanium film is used as the substrate.

[0189] When an oxide semiconductor layer is brought into contact with a metal layer having a high oxygen affinity and heat treatment is performed, the oxide semiconductor Oxygen atoms move from the semiconductor layer to the metal layer, increasing the carrier density near the interface. As a result, a low-resistance region is formed near the interface, and the oxide semiconductor layer and the source electrode layer and the drain electrode layer are The contact resistance with the inner electrode layer can be reduced.

[0190] Further, a heat-resistant conductive material may be used for the source electrode layer and the drain electrode layer. When the material is used, the source electrode layer and the drain electrode layer can be formed without any problem even if a heat treatment is performed after the formation of the source electrode layer and the drain electrode layer. This can prevent the gate electrode layer and the drain electrode layer from being altered or deteriorated.

[0191] Heat-resistant conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), Choose from molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). The elements mentioned above, or alloys containing the above elements or combinations of the above elements A film or a nitride containing the above-mentioned elements can be used. The above heat-resistant conductive materials are combined with low-resistance conductive materials such as aluminum (Al) and copper (Cu). Alternatively, a conductive film having improved heat resistance due to heating may be used.

[0192] The source and drain electrode layers may also include a metal oxide layer. For example, a metal oxide layer may include a semiconductor layer. A structure having a titanium oxide film between a conductor layer and a titanium film, or a titanium film (for example, a film thickness of 0.1 A titanium oxide film (for example, a film thickness of 1 nm to 20 nm) is placed between the oxide insulating layer and the titanium oxide film. The structure may have a thickness of 1 nm or less.

[0193] In addition, when the source electrode layer and the drain electrode layer are thin enough to transmit light, The source electrode layer and the drain electrode layer have a light-transmitting property.

[0194] A second photolithography process is performed to remove the oxide semiconductor film 465 and the metal conductive film 466. A resist mask 460 is formed on the resulting film.

[0195] In this embodiment, exposure using a high-contrast mask is performed to form the resist mask 460. An example of this is shown below. A resist is formed to form a resist mask 460. The resist is A positive resist or a negative resist can be used. The resist may be formed by spin coating or by inkjet printing. If the resist is selectively formed by the inkjet method, the resist is not applied to unnecessary areas. Since the resist formation can be reduced, waste of materials can be reduced.

[0196] Next, the resist is irradiated with light using a multi-tone mask 81 as an exposure mask. is exposed.

[0197] Here, exposure using the multi-tone mask 81 will be described with reference to FIG.

[0198] A multi-tone mask has three exposure levels for the exposed, intermediate and unexposed parts. This is an exposure mask that allows multiple exposures, and the transmitted light has multiple intensities. A resist mask having multiple (typically two) thickness regions formed by the light and development process Therefore, by using a multi-tone mask, the number of exposure masks can be reduced. It is possible to reduce the number.

[0199] A typical example of a multi-tone mask is a gray-tone mask 81a as shown in FIG. There is a half-tone mask 81b as shown in FIG.

[0200] As shown in FIG. 25(A), the gray-tone mask 81a is made of a light-transmitting substrate 83 and a The light shielding portion 84 is formed on the substrate 10 and a diffraction grating 85. On the other hand, the diffraction grating 85 has slits, dots, meshes, and other light transmitting portions. The light transmittance is controlled by setting the interval to be equal to or less than the resolution limit of the light used for exposure. The diffraction grating 85 may be a periodic slit, dot, mesh, or non-periodic grating. Periodic slits, dots, or meshes can both be used.

[0201] The light-transmitting substrate 83 may be a light-transmitting substrate such as quartz. The grating 85 can be formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. Cut.

[0202] When the gray-tone mask 81a is irradiated with exposure light, as shown in FIG. In the case of 84, the light transmittance 86 is 0%, and the light shielding portion 84 and the diffraction grating 85 are provided. In the area where no light is emitted, the light transmittance 86 is 100%. The light transmittance of the diffraction grating 85 can be adjusted within a range of 70%. This is possible by adjusting the spacing and pitch of the slits, dots, or meshes.

[0203] As shown in FIG. 25(C), the half-tone mask 81b is made of a light-transmitting substrate 83 and a The semi-transmitting portion 87 is made of MoSiN, and the light-shielding portion 88 is made of the semi-transmitting portion 87. MoSi, MoSiO, MoSiON, CrSi, etc. can be used. can be formed using a light-shielding material that absorbs light, such as chromium or chromium oxide.

[0204] When the halftone mask 81b is irradiated with exposure light, as shown in FIG. In the case of 88, the light transmittance 89 is 0%, and the light shielding portion 88 and the semi-transmitting portion 87 are provided. In the non-transparent region, the light transmittance 89 is 100%. The light transmittance of the semi-transmitting portion 87 can be adjusted within a range of 70%. It can be adjusted using 7 materials.

[0205] By exposing the film using a multi-tone mask and then developing it, a film with different thicknesses is obtained as shown in Figure 5(B). A resist mask 460 having an area corresponding to the etched portion can be formed.

[0206] Next, a first etching step is performed using the resist mask 460, and the oxide semiconductor film 46 5. The metal conductive film 466 is etched to form an island shape. As a result, the oxide semiconductor layer 461 Then, a metal conductive layer 462 can be formed (see FIG. 5B).

[0207] Next, the resist mask 460 is ashed. As a result, the area of ​​the resist mask (3D In terms of fundamental volume, the thickness of the resist film decreases. The resist of the mask (the area overlapping a part of the gate electrode layer 481) is removed, and the separated Resist masks 463a, 463b can be formed.

[0208] Using resist masks 463a and 463b, unnecessary portions are removed by etching to form a semiconductor substrate. A source electrode layer 485a and a drain electrode layer 485b are formed (see FIG. 5C).

[0209] Note that the oxide semiconductor layer 461 is not removed when the metal conductive layer 462 is etched. The materials and etching conditions are appropriately adjusted.

[0210] In this embodiment, a Ti film is used as the metal conductive layer 462, and a Ti film is used as the oxide semiconductor layer 461. Using In-Ga-Zn-O oxide, ammonia water (ammonia) was used as an etchant. A mixture of niacin, water, and hydrogen peroxide is used.

[0211] Note that the etching of the metal conductive film and the oxide semiconductor film is not limited to wet etching. Alternatively, dry etching may be used.

[0212] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0213] In addition, gases containing fluorine (fluorine-based gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF 6), nitrogen fluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr ), oxygen (O2), and rare gases such as helium (He) and argon (Ar) Additive gases, etc. can be used.

[0214] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A combined plasma etching method can be used. It is possible to etch into the desired shape. The etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set so that The amount of power used, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0215] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide water: 28% by weight ammonia water: water = 5:2:2) Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0216] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium, etc. contained in the oxide semiconductor layer may be reused from the waste liquid after the etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0217] In order to etch the desired shape, the etching conditions (etching Adjust the etching conditions (liquid, etching time, temperature, etc.) as appropriate.

[0218] Next, the resist masks 463a and 463b are removed, and a protective layer in contact with the oxide semiconductor layer 461 is An oxide insulating layer 407 which serves as an insulating film is formed. In this embodiment, the oxide insulating layer 407 Then, a silicon oxide film having a thickness of 200 nm is formed by sputtering.

[0219] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. For example, the heating is performed in a nitrogen atmosphere. The second heat treatment is performed at 250° C. for 1 hour under atmospheric pressure. A part of the semiconductor layer (channel formation region) is heated in a state where the part is in contact with the oxide insulating layer 407 .

[0220] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor film is selectively As a result, a channel formation region 483 overlapping with the gate electrode layer 481 has an I-type structure. A high resistance source region 484a overlapping the source electrode layer 485a and a drain electrode layer 48 By the above steps, a thin A membrane transistor 480 is formed.

[0221] Furthermore, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By this heat treatment, the oxide insulating film is removed from the oxide semiconductor layer. Hydrogen is incorporated into the edge layer, resulting in a normally-off thin-film transistor. This makes it possible to improve the reliability of the semiconductor device.

[0222] A protective insulating layer 408 is formed over the oxide insulating layer 407. In this embodiment, Then, a protective insulating layer 408 is formed using a silicon nitride film (see FIG. 5D).

[0223] Next, a resist mask is formed by a third photolithography process and selectively etched. The oxide insulating layer 407 and the protective insulating layer 408 are partially removed by etching to form the source electrode layer 4 85a, and openings 464a and 464b reaching the drain electrode layer 485b are formed (FIG. 5(E) )reference.).

[0224] Openings 464a and 464b are formed so as to contact the source electrode layer 485a and the drain electrode layer 485b. A laminated conductive layer is formed on the substrate by sputtering or vacuum deposition, and a fourth photolithography is performed. A resist mask is formed by a etching process. The laminated conductive layer is selectively etched to form the wiring layer 4. 87a, 487b, 488a, 488b, at the intersections, the source wiring layers 422, 423 (See FIG. 5(F)).

[0225] The wiring layers 487a, 487b, 488a, and 488b are formed from the source electrode layer and the drain electrode layer. A conductive film with low resistance is used. Specifically, aluminum, copper, chromium, tantalum, molybdenum, etc. Metallic materials such as tungsten, titanium, neodymium, scandium, etc., or materials containing these as the main components The insulating film can be formed as a single layer or a stacked layer using an alloy material having the above structure. A laminated structure is used as the wiring layer, and the first wiring layers 487a and 487b are made of aluminum. The first wiring layer 488a and the second wiring layer 488b are made of titanium films.

[0226] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, It is possible to provide a semiconductor device with reduced parasitic capacitance and low power consumption.

[0227] In addition, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, Therefore, a high-performance semiconductor device can be provided.

[0228] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0229] (Embodiment 4) In this embodiment mode, a light-transmitting conductive material is used for the gate electrode layer in Embodiment 1. An example in which the above is done is shown in FIG. 7. Therefore, the rest of the process can be carried out in the same manner as in the first embodiment. The description of the same parts or parts having similar functions and the repetition of steps will be omitted. FIG. 7 is the same as FIG. 1 and FIG. 2 except for some steps, and therefore the same parts are designated by the same reference numerals. Reference numbers will be used and detailed explanations of the same parts will be omitted.

[0230] The thin film transistor 430 shown in FIG. 7 is a channel-etch type thin film transistor. On a substrate 400 having a surface, a gate electrode layer 431, a gate insulating layer 402, and at least A channel forming region 433, a high resistance source region 434a, and a high resistance drain region 434b are formed. The oxide semiconductor layer 432 has a source electrode layer 435a and a drain electrode layer 435b. In addition, the oxide insulating layer 430 is formed on the thin film transistor 430 and is in contact with the channel forming region 433. 07 is provided, and a protective insulating layer 408 is provided thereon.

[0231] The oxide insulating layer 407 and the protective insulating layer 408 have an opening (conduit) that reaches the source electrode layer 435a. A contact hole is formed, and wiring layers 437 and 438 are formed in the opening. In the difference portion, the gate wiring layer 421 and the source wiring layers 422 and 423 are connected to the gate insulating layer 4 7, an oxide insulating layer 407 and a protective insulating layer 408 are interposed between the oxide insulating layer 402 and the protective insulating layer 408. 4, an opening reaching the source electrode layer 435a and wiring layers 437 and 438 provided in the opening are provided. In this way, the opening and the wiring layer may be provided in a region that does not overlap with the oxide semiconductor layer 432.

[0232] In this manner, the gate electrode layer (gate wiring layer) and the source electrode layer or the drain electrode layer are electrically connected to each other. The wiring layer that is electrically connected is an insulating layer that covers the oxide semiconductor layer of the thin film transistor and a gate insulating layer. The gate electrode layer and the source electrode layer of the thin film transistor are intersected with an edge layer. The gate electrode layer and the gate insulating layer are formed on the oxide semiconductor layer except that they are partially overlapped with each other. The semiconductor device does not have a stacked structure of a gate insulating layer, a source electrode layer, and a drain electrode layer.

[0233] Therefore, a stacked structure of a gate electrode layer, a gate insulating layer, and a source electrode layer or a drain electrode layer This reduces the parasitic capacitance formed by the Cut.

[0234] A planarizing insulating layer 409 is formed on the wiring layer 438, the source wiring layer 423, and the protective insulating layer 408. A pixel electrode layer 427 is provided on the planarization insulating layer 409. The thin film transistor 404 is in contact with the wiring layer 438 through an opening formed in the planarizing insulating layer 409. The transistor 430 and the pixel electrode layer 427 are electrically connected via wiring layers 437 and 438. do.

[0235] The source electrode layer 435a and the drain electrode layer 435b are light-transmitting conductive films. The conductive film may have the following structure.

[0236] In FIG. 7, the gate electrode layer 431 of the thin film transistor 430 is also a conductive film having a light-transmitting property. A conductive membrane is used.

[0237] The material of the gate electrode layer 431 is a conductive material that is transparent to visible light, such as In-S nO series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O series , Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn- Applying metal oxides of O, Al-Zn-O, In-O, Sn-O, and Zn-O systems The thickness of the gate electrode layer is appropriately selected within the range of 50 nm to 300 nm. The metal oxide film deposition method used in 431 is the sputtering method or the vacuum deposition method (electron beam evaporation). The method is arc discharge ion plating or spraying. When using the targeting method, a target containing SiO2 of 2% by weight or more and 10% by weight or less is used. The conductive film is then formed by adding SiOx (X>0) which inhibits crystallization. In addition, crystallization during the heat treatment for dehydration or dehydrogenation in the subsequent process is suppressed. It is preferable to control

[0238] Therefore, the thin film transistor 430 can be a light-transmitting thin film transistor. .

[0239] In addition, in the pixel where the thin film transistor 430 is arranged, a pixel electrode layer 427 or other The electrode layer (such as the capacitance electrode layer) and other wiring layers (such as the capacitance wiring layer) are transparent to visible light. A display device having a high aperture ratio is realized by using a conductive film having optical transparency. The insulating layer 402, the oxide insulating layer 407, and the protective insulating layer 408 are also made of a film that transmits visible light. It is preferable that

[0240] In this specification, a film that is transparent to visible light has a visible light transmittance of 75 to 100 %, and if the film is conductive, it is also called a transparent conductive film. Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes A conductive film that is semi-transparent to visible light is used as a metal oxide for the wiring layer and other wiring layers. Translucent to visible light means that the transmittance of visible light is 50 to 75%. .

[0241] Since the thin film transistor 430 has a light-transmitting property, the aperture ratio can be improved. In small LCD panels of 10 inches or less, the number of gate wiring is increased to In order to achieve high resolution in displayed images, a high aperture ratio can be achieved even if the pixel dimensions are miniaturized. In addition, by using a light-transmitting film as a component of the thin film transistor 430, A high aperture ratio is achieved even when one pixel is divided into multiple sub-pixels to achieve a desired viewing angle. In other words, it is possible to obtain a large aperture ratio even when a high density group of thin film transistors is arranged. This allows a sufficient area for the display area to be secured. In the case of a pixel having sub-pixels, the thin film transistor has light-transmitting properties, improving the aperture ratio. In addition, the same materials can be used in the same process as the components of the thin film transistor. When a capacitance is formed, the storage capacitance can also be made transparent, which further improves the aperture ratio. It is possible.

[0242] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0243] (Embodiment 5) In this embodiment, a manufacturing process of a thin film transistor is partially different from that in Embodiment 1. Figure 8 is the same as Figures 1 and 2 except for some differences in the process, so the same parts are used. The same reference numerals are used, and detailed explanations of the same parts will be omitted.

[0244] According to the first embodiment, a gate wiring layer 421 and a gate electrode layer 471 are formed on a substrate 400. Then, a gate insulating layer 402 is laminated.

[0245] Next, an oxide semiconductor film is formed, and the oxide semiconductor film is formed into an island shape by a photolithography process. The oxide semiconductor layer is processed into an oxide semiconductor layer.

[0246] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400° C. or higher and 750° C. or lower, preferably 425° C. or higher. If the temperature is 425°C or higher, the heat treatment time may be 1 hour or less. In this case, the heat treatment time is set to be longer than one hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to heat treatment in a nitrogen atmosphere. After this, the oxide semiconductor layer is prevented from being exposed to the air, and water and hydrogen are prevented from re-mixing into the oxide semiconductor layer. After that, high-purity oxygen gas, high-purity NO gas, or ultra-dry gas are used in the same furnace. Dry air (dew point below -40℃, preferably below -60℃) is introduced for cooling. It is preferable that the N2O gas does not contain water, hydrogen, etc. The purity of the oxygen gas or N2O gas introduced into the device is preferably 6N (99.9999%) or more. or 7N (99.99999%) or more (i.e. impurity concentration in oxygen gas or N2O gas) It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0247] The heat treatment device is not limited to an electric furnace, and may be, for example, a GRTA (Gas Rapid Th thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Using RTA (Rapid Thermal Anneal) equipment such as LRTA devices can be used with halogen lamps, metal halide lamps, xenon Arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure mercury lamps, etc. This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp. TA devices use heat conduction or radiation from heating elements such as resistance heating elements as well as lamps. The GRTA is a gas processing system that uses high-temperature gas to heat the object to be processed. This is a method of performing heat treatment. The gas used is a rare gas such as argon, or a heating gas such as nitrogen. An inert gas that does not react with the material to be treated is used. Heat treatment may be performed at a temperature of from 0.degree. C. to 750.degree. C. for several minutes.

[0248] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or heat treatment at a temperature between 200℃ and 300℃ in an oxygen gas or N2O gas atmosphere. The theory may also be carried out.

[0249] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. In this case, the substrate is removed from the heating device after the first heat treatment. The substrate is then taken out and subjected to a photolithography process.

[0250] By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, and thus a high resistance Thus, the entire oxide semiconductor layer 472 is made i-type.

[0251] Next, a resist mask is formed over the oxide semiconductor layer 472 by a photolithography process. Then, selective etching is performed to form a source electrode layer 475a and a drain electrode layer 475b. Then, an oxide insulating layer 407 is formed by a sputtering method.

[0252] Next, in order to reduce the variation in the electrical characteristics of the thin-film transistors, Alternatively, heat treatment (preferably at 150°C or higher and lower than 350°C) is performed under a nitrogen gas atmosphere. For example, a heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0253] In addition, heat treatment is performed in air at 100°C to 200°C for 1 hour to 30 hours. In this embodiment, heat treatment is performed at 150° C. for 10 hours. The heating temperature may be maintained, or the temperature may be increased from room temperature to 100°C or higher, up to 200°C. The heating and cooling from the heating temperature to room temperature may be repeated several times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. By this heat treatment, the oxide insulating film is removed from the oxide semiconductor layer. Hydrogen is incorporated into the edge layer, resulting in a normally-off thin-film transistor. This makes it possible to improve the reliability of the semiconductor device.

[0254] Next, a protective insulating layer 408 is formed over the oxide insulating layer 407.

[0255] Next, a resist mask is formed by a photolithography process, and selective etching is performed. Then, a part of the oxide insulating layer 407 and the protective insulating layer 408 are removed to form the source electrode layer 475a. Then, an opening reaching the drain electrode layer 475b is formed.

[0256] The source electrode layer 475a and the drain electrode layer 475b are formed in the openings by sputtering. A laminated conductive layer is formed by a method such as vacuum deposition, and a resist mask is formed by a photolithography process. The laminated conductive layers are selectively etched to form wiring layers 477a, 477b, and 478. a, 478b, source wiring layers 422, 423 are formed at the intersections (see FIG. 8). .

[0257] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, It is possible to provide a semiconductor device with reduced parasitic capacitance and low power consumption.

[0258] In addition, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, Therefore, a high-performance semiconductor device can be provided.

[0259] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0260] (Embodiment 6) In this embodiment, the oxide semiconductor layer and the source electrode layer or the drain electrode layer in Embodiment 1 are FIG. 9 shows an example in which an oxide conductive layer is provided between an electrode layer and a source region and a drain region. Therefore, other aspects can be carried out in the same manner as in the first embodiment, and the same parts or the same components as in the first embodiment can be used. The description of the parts having the same functions and the repetition of the steps will be omitted. Since this is the same as Figure 2 except for some differences in the process, the same symbols are used for the same parts and A detailed description of the location will be omitted.

[0261] The thin film transistor 469 shown in FIG. 9 is a channel-etch type thin film transistor. A gate electrode layer 411, a gate insulating layer 402, and at least a thimble are formed on a substrate 400 having a surface. A channel forming region 413, a high-resistance source region 414a, and a high-resistance drain region 414b are formed. The oxide semiconductor layer 412, the oxide conductive layers 416a and 416b, and the source electrode layer 415a The thin film transistor 469 is also covered with a drain electrode layer 415b. An oxide insulating layer 407 is provided in contact with the formation region 413, and a protective insulating layer 40 is further provided thereon. 8 is provided.

[0262] According to the first embodiment, a gate wiring layer 421 and a gate electrode layer 411 are formed on a substrate 400. Then, a gate insulating layer 402 is stacked. An oxide semiconductor film is formed over the gate insulating layer 402. A dehydrated or dehydrogenated oxide semiconductor layer is formed.

[0263] The oxide conductive layers 416a and 416b are formed over the dehydrated or dehydrogenated oxide semiconductor layer. In this embodiment, the oxide conductive layers 416a and 416b are formed using the same photoresist as the oxide semiconductor layers. An example of processing the shape by a lithography process is shown. The shape of the source electrode layer and the drain electrode layer is processed by the same photolithography process. This is also fine.

[0264] The oxide conductive layers 416a and 416b are formed by a sputtering method or a vacuum deposition method (electron beam deposition). The coating is then applied to the metal by a variety of methods, including vapor deposition, arc discharge ion plating, and spraying. The material of the conductive layers 416a and 416b is preferably one containing zinc oxide as a component. It is preferable that the oxide conductive layer 416 does not contain indium oxide. a, 416b, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, oxide Zinc gallium, etc. can be used. The film thickness is within the range of 50 nm to 300 nm. In addition, when the sputtering method is used, SiO2 is selected from 2% by weight to 10% by weight. The film is formed using a target containing SiOx (X>0) is added, and crystallization occurs during the heat treatment for dehydration or dehydrogenation in the subsequent process. It is preferable to suppress the deterioration of the crystalline structure.

[0265] In this embodiment, the oxide conductive layers 416a and 416b are formed using the same photolithography method as the oxide semiconductor layers. After processing the shape by a roughening process, the source electrode layer 415a and the drain electrode layer 415b are The oxide conductive layer is further etched using the mask to form oxide conductive layers 416a and 416b. The oxide conductive layers 416a and 416b containing zinc oxide are formed by, for example, a resist. It can be easily etched using an alkaline solution such as the stripper.

[0266] A channel region is formed by utilizing the difference in etching rate between an oxide semiconductor layer and an oxide conductive layer. In order to perform the etching process, the oxide conductive layer is divided. The oxide conductive layer on the oxide semiconductor layer is formed by utilizing the fact that the ionization rate of the oxide conductive layer is faster than that of the oxide semiconductor layer. The layer is selectively etched.

[0267] Therefore, the resist mask used for forming the source electrode layer 415a and the drain electrode layer 415b The removal of the film is preferably performed by an ashing process. In this case, the etching is performed so that the oxide conductive layer and the oxide semiconductor layer are not excessively etched. The etching conditions (type of etchant, concentration, etching time) are adjusted appropriately.

[0268] An oxide semiconductor layer 412 is provided between the oxide semiconductor layer 412 and the drain electrode layer 415b made of a metal material. The conductive layer 416b is a low resistance drain region (LRN (Low Resistance N- type conductivity) region, LRD (Low Resistance) region Similarly, the oxide semiconductor layer 412 and the metal material The oxide conductive layer 416a provided between the source electrode layers 415a made of a material is a low resistance drain layer. Low Resistance N-type conduction region (LRN) ty (also called LRS (Low Resistance Source) region) The drain electrode is made of an oxide semiconductor layer, a low-resistance drain region, and a metal material. By using a layered structure, the breakdown voltage of the transistor can be further improved. In general, the carrier concentration in the low-resistance drain region is higher than that in the high-resistance drain region (HRD region). is also large, for example 1×10 20 / cm 3 More than 1×10 21 / cm 3 Within the following range preferable.

[0269] The oxide conductive layer is formed as a source region and a drain region, and the oxide semiconductor layer is formed as a source electrode layer and a drain region. By providing the source region and the drain electrode layer, the resistance of the source region and the drain region can be reduced. This allows the transistor to operate at high speed. The use of an oxide conductive layer as a gate insulating layer improves the frequency characteristics of the peripheral circuits (drive circuits). This is effective for preventing the formation of oxide semiconductor layers. This is because the contact between the conductive layer and the oxide layer can reduce the contact resistance.

[0270] In addition, molybdenum (Mo), which is used as part of the wiring material in semiconductor devices (e.g. , Mo / Al / Mo), the problem was that the contact resistance with the oxide semiconductor layer was high. However, Mo is less likely to oxidize than Ti, and therefore has a weaker effect of extracting oxygen from the oxide semiconductor layer. This is because the contact interface between the oxide semiconductor layer and the oxide semiconductor layer does not become n-type. an oxide conductive layer is interposed between the oxide semiconductor layer and the source and drain electrode layers; This reduces the contact resistance and improves the frequency characteristics of the peripheral circuits (drive circuits).

[0271] Since the channel length of the thin film transistor is determined during etching of the oxide conductive layer, For example, the channel length L can be shortened to 0.1 μm or more and 2 μm or less. The operating speed can be increased.

[0272] Although the first embodiment has been described as an example, this embodiment may be appropriately combined with other embodiments. It is possible to implement this.

[0273] As described above, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, It is possible to provide a semiconductor device with reduced parasitic capacitance and low power consumption.

[0274] In addition, in a semiconductor device having a thin film transistor using an oxide semiconductor layer, Therefore, a high-performance semiconductor device can be provided.

[0275] (Embodiment 7) In this embodiment, an example in which an oxide semiconductor layer is surrounded by a nitride insulating film as viewed from a cross section is shown in FIG. FIG. 10 is different from FIG. 1 in the top surface shape and end position of the oxide insulating layer, and in the gate insulating layer. Since the present embodiment is the same except for the difference in configuration, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are provided. The explanation will be omitted.

[0276] The thin film transistor 410 is a channel-etch type thin film transistor having an insulating surface. A gate electrode layer 411 and a first gate insulating layer 49 made of a nitride insulating film are formed on a substrate 400. 2a, a second gate insulating layer 492b made of an oxide insulating film, at least a channel forming region 413, an oxide semiconductor having a high-resistance source region 414a, and a high-resistance drain region 414b. The thin film transistor includes a conductor layer 412, a source electrode layer 415a, and a drain electrode layer 415b. An oxide insulating film that covers the transistor 410 and is in contact with a channel formation region of the oxide semiconductor layer 412 is formed on the oxide insulating film 412. A protective insulating layer 498 is further formed on the oxide insulating layer 497b. has been formed.

[0277] The oxide insulating layer 497b and the protective insulating layer 498 are covered with a source electrode layer 415a and a drain electrode layer 415b. An opening (contact hole) reaching the electrode layer 415b is formed. On the other hand, at the intersection, the gate wiring The layer 421 and the source wiring layers 422 and 423 are connected to the gate insulating layer 402 and the oxide insulating layer 497a. 498 is laminated therebetween.

[0278] In this embodiment, in the thin film transistor 410, the gate insulating layer is A nitride insulating film and an oxide insulating film are stacked on top of each other. An opening is formed in the oxide insulating layer. At the same time, the oxide insulating film of the second gate insulating layer is also selectively removed so that the nitride insulating film is exposed. Process into sea urchin.

[0279] At least the oxide insulating layer 497b and the second gate insulating layer 492b have a top surface shape similar to that of an oxide semiconductor. The upper surface shape is wider than the upper surface shape of the conductor layer 412 and covers the thin film transistor 410. is preferred.

[0280] The oxide insulating layer 497b is formed on the upper surface and the side surface of the first gate insulating layer 492a. A protective insulating layer 498 made of a nitride insulating film is formed in contact with the nitride insulating film.

[0281] The protective insulating layer 498 and the first gate insulating layer 492a are formed by sputtering. Silicon nitride film, silicon oxynitride film, and aluminum nitride film obtained by the etching method and plasma CVD method , moisture in aluminum oxide nitride film, hydrogen ions, OH - Does not contain impurities such as An inorganic insulating film is used to block these substances from entering from the outside.

[0282] In this embodiment, the oxide semiconductor layer 41 is used as the protective insulating layer 498 made of a nitride insulating film. The top and sides of the 2 were covered with a 100 nm thick silicon nitride film by RF sputtering. A protective insulating layer 498 is formed on the first gate insulating layer 49 made of a nitride insulating film. It is configured to be in contact with 2a.

[0283] By forming the structure shown in FIG. 10, the manufacturing process after forming the protective insulating layer 498 made of a nitride insulating film In the process, it is possible to prevent moisture from entering from the outside. For example, even after the device is completed as a liquid crystal display device, it will continue to prevent moisture from entering from the outside for a long period of time. This makes it possible to improve the long-term reliability of the device.

[0284] In addition, in this embodiment, a configuration in which one thin film transistor is surrounded by a nitride insulating film has been shown. However, the present invention is not limited to the above, and a configuration in which a plurality of thin film transistors are surrounded by a nitride insulating film may be used. A plurality of thin film transistors in the region may be surrounded by a nitride insulating film. A protective insulating layer 498 and a first gate electrode 499 are formed so as to surround the periphery of the pixel portion of the active matrix substrate. A region in contact with the insulating layer 492a may be provided.

[0285] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0286] (Embodiment 8) In this embodiment mode, in the semiconductor device shown in any of the embodiments 1 to 7, and a light-emitting element that utilizes electroluminescence, An example of manufacturing a light-emitting display device will be described.

[0287] Light-emitting elements that utilize electroluminescence are characterized by the fact that the light-emitting material is either an organic compound or an inorganic compound. Generally, the former are organic EL elements and the latter are inorganic EL elements. It is called.

[0288] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0289] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0290] FIG. 11 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0291] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The figure shows an n-channel transistor that uses an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0292] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, The light emitting element 6404 and the capacitor element 6403 are included. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on the substrate.

[0293] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0294] The capacitor 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. It is also possible to set the gate capacitance of the driving transistor 6402 as follows: A capacitance may be formed between the gate electrode and the second electrode.

[0295] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is The driving transistor 6402 is in two states, either fully on or fully off. A video signal is inputted, that is, the driving transistor 6402 is operated in a linear region. In order to operate the driving transistor 6402 in a linear region, the voltage of the power supply line 6407 must be higher than that of the driving transistor 6402. A high voltage is applied to the gate of the driving transistor 6402. A voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied.

[0296] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 11 can be used.

[0297] In the case of performing analog gradation driving, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or higher than the forward voltage of the light emitting element 6401 plus the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and should be at least 100% forward voltage. In addition, the video transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The gate potential of the light emitting element 6402 is set higher than that of the gate of the transistor 6403. Analog gradation drive can be performed by passing a current corresponding to a video signal through 6404.

[0298] Note that the pixel configuration shown in FIG. 11 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0299] Next, the configuration of the light emitting element will be described with reference to FIG. 12. Here, the driving TFT is The cross-sectional structure of a pixel will be described using the example of the type shown in Figure 12(A), (B), and (C). The driving TFTs 7001, 7011, and 7021 used in the semiconductor device are the same as those in the fourth embodiment. The thin film transistor can be manufactured in the same manner as the thin film transistor shown in FIG. Here is an example using the

[0300] The light-emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite to the substrate. The structure has a top emission structure that emits light from the top surface, a bottom emission structure that emits light from the surface on the substrate side, and a structure that emits light from the substrate side and the substrate. There are light-emitting elements with a double-sided emission structure that emits light from the opposite side. The present invention can also be applied to light emitting devices having such a structure.

[0301] A light emitting element having a bottom emission structure will be described with reference to FIG.

[0302] The driving TFT 7011 is an n-type TFT, and the light emitted from the light emitting element 7012 is incident on the first electrode 701. FIG. 12(A) shows a cross-sectional view of a pixel when light is emitted to the driving TFT 7011. The drain electrode layer is electrically connected to wiring layers 7018a and 7018b. A planarization insulating layer 7036 is formed thereon. In the opening formed in 036, the conductive film 7017 having light-transmitting properties is in contact with the driving The TFT 7011 and a light-transmitting conductive film 7017 are electrically connected to each other. A first electrode 7013 of the light-emitting element 7012 is formed over a conductive film 7017. An EL layer 7014 and a second electrode 7015 are laminated in this order on a first electrode 7013 .

[0303] The light-transmitting conductive film 7017 can be formed of indium oxide containing tungsten oxide, oxide Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide, indium zinc oxide, oxide carbide A light-transmitting conductive film such as indium tin oxide to which indium is added can be used. Cut.

[0304] In addition, various materials can be used for the first electrode 7013 of the light-emitting element. When the electrode 7013 is used as a cathode, a material having a small work function, specifically, For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, and alloys containing these (Mg:Ag, Al:Li, etc.), as well as rare earth metals such as Yb and Er. In FIG. 12A, the film thickness of the first electrode 7013 is set to a value that allows light to pass therethrough (preferably For example, an aluminum film having a thickness of 20 nm is used. is used as the first electrode 7013.

[0305] After a light-transmitting conductive film and an aluminum film are laminated, the film is selectively etched. In this case, the light-transmitting conductive film 7017 and the first electrode 7013 may be formed. This is preferable because the same mask can be used for etching.

[0306] The periphery of the first electrode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimide. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, and organic polysiloxanes. The partition wall 7019 is formed by using a photosensitive resin material. 13, and an opening is formed on the surface of the substrate 13, and the side wall of the opening is an inclined surface having a continuous curvature. In the case where a photosensitive resin material is used as the partition wall 7019, In this case, the step of forming a resist mask can be omitted.

[0307] The EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is at least It is sufficient to include a light-emitting layer, and the light-emitting device may be composed of a single layer or may be composed of multiple layers stacked together. When the EL layer 7014 is composed of a plurality of layers, An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole transport layer, and a hole transport layer are formed on a first electrode 7013 that functions as a light emitting layer. It is not necessary to provide all of these layers.

[0308] In addition, the stacking order is not limited to the above, and the first electrode 7013 may function as an anode. A hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are laminated on top of 7013 in this order. However, when comparing power consumption, the first electrode 7013 may function as a cathode. On the first electrode 7013, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer, and a By stacking the layers in the order of insertion, it is possible to suppress the voltage rise in the drive circuit section and reduce power consumption. Therefore, it is preferable.

[0309] In addition, the second electrode 7015 formed on the EL layer 7014 can be made of various materials. For example, when the second electrode 7015 is used as an anode, a material with a large work function can be used. Materials such as ZrN, Ti, W, Ni, Pt, Cr, ITO, IZO, ZnO, etc. A transparent conductive material is preferable. In addition, a shielding film 7016, for example, a film for blocking light, is provided on the second electrode 7015. A light-shielding metal, a light-reflecting metal, or the like is used. In this embodiment mode, the second electrode 7015 and An ITO film is used as the shielding film 7016, and a Ti film is used as the shielding film 7017.

[0310] An EL layer 7014 including a light-emitting layer is sandwiched between a first electrode 7013 and a second electrode 7015. In the case of the element structure shown in FIG. Light emitted from 7012 is emitted to the first electrode 7013 side as shown by the arrow.

[0311] In FIG. 12A, a light-transmitting conductive film is used as a gate electrode layer, and a source This shows an example in which a light-transmitting thin film is used for the electrode layer and the drain electrode layer. The light emitted from 7012 passes through the color filter layer 7033 and exits through the substrate. It can be done.

[0312] The color filter layer 7033 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using graphic technology.

[0313] The color filter layer 7033 is covered with an overcoat layer 7034, which is a protective insulating layer. In FIG. 12A, the overcoat layer 7034 is thin. As shown in FIG. 7, the overcoat layer 7034 has irregularities caused by the color filter layer 7033. It has the function of flattening the surface.

[0314] In addition, a protective insulating layer 7035, an insulating layer 7032, and an insulating layer 7031 are formed, and the The contact hole reaching the rain electrode layer is disposed at a position overlapping with the partition wall 7019 .

[0315] Next, a light emitting element having a dual emission structure will be described with reference to FIG.

[0316] In FIG. 12B, the wiring layer electrically connected to the drain electrode layer of the driving TFT 7021 is 7028a and 7028b are formed, and a planarizing insulating layer 7046 is formed thereon. The wiring layer 7028b has a light-transmitting property in an opening formed in the planarization insulating layer 7046. The conductive film 7027 is in contact with the driving TFT 7021 and the conductive film 702 The light-emitting element 7022 is electrically connected to the conductive film 7027 having a light-transmitting property. A first electrode 7023 is formed, and an EL layer 7024 and a second Electrodes 7025 are stacked in order.

[0317] The light-transmitting conductive film 7027 can be formed using indium oxide containing tungsten oxide, Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, indium tin oxide, indium zinc oxide, oxide carbide A light-transmitting conductive film such as indium tin oxide to which indium is added can be used. Cut.

[0318] In addition, various materials can be used for the first electrode 7023. For example, When using 23 as a cathode, a material with a small work function, specifically, for example, Li or Cs Alkaline metals such as Mg, Ca, Sr, and alkaline earth metals including these In addition to alloys (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. In the embodiment, the first electrode 7023 is used as a cathode, and its film thickness is set to a level that allows light to pass through. (Preferably, about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm is A ZnO film is used as the cathode.

[0319] After a light-transmitting conductive film and an aluminum film are laminated, the film is selectively etched. In this case, the light-transmitting conductive film 7027 and the first electrode 7023 may be formed by the same method. It is preferable that the same mask be used for etching.

[0320] The periphery of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is made of polyimide. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, and organic polysiloxanes. The partition wall 7029 is formed by using a photosensitive resin material. 23, and an opening is formed on the surface of the substrate 23, and the side wall of the opening is an inclined surface having a continuous curvature. In the case where a photosensitive resin material is used as the partition wall 7029, In this case, the step of forming a resist mask can be omitted.

[0321] In addition, the EL layer 7024 formed over the first electrode 7023 and the partition wall 7029 includes a light-emitting layer. It is sufficient if the material is made up of a single layer or multiple layers are laminated. Either is acceptable. When the EL layer 7024 is composed of multiple layers, it functions as a cathode. On the first electrode 7023, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer It is not necessary to provide all of these layers.

[0322] In addition, the stacking order is not limited to the above. The first electrode 7023 may be used as an anode, and a hole may be formed on the anode. The injection layer, the hole transport layer, the light emitting layer, the electron transport layer, and the electron injection layer may be laminated in this order. When comparing power consumption, the first electrode 7023 is used as a cathode, and an electron injection layer 7024 is provided on the cathode. The power consumption is reduced by stacking the electron transport layer, light emitting layer, hole transport layer, and hole injection layer in that order. It is preferable because it is small.

[0323] In addition, the second electrode 7025 formed on the EL layer 7024 can be made of various materials. For example, when the second electrode 7025 is used as an anode, a material with a large work function can be used. A transparent conductive material such as ITO, IZO, or ZnO can be preferably used. In this embodiment, the second electrode 7025 is used as an anode, and an ITO film containing silicon oxide is used as the anode. Form.

[0324] An EL layer 7024 including a light-emitting layer is sandwiched between a first electrode 7023 and a second electrode 7025. In the case of the element structure shown in FIG. The light emitted from 7022 is incident on the second electrode 7025 side and the first electrode 70 as shown by the arrow. 23 It is fired on both sides.

[0325] In FIG. 12B, a light-transmitting conductive film is used as a gate electrode layer, and a source This shows an example in which a light-transmitting thin film is used for the electrode layer and the drain electrode layer. The light emitted from the first electrode 7022 to the first electrode 7023 passes through the color filter layer 7043. and can be ejected through the substrate.

[0326] The color filter layer 7043 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using graphic technology.

[0327] The color filter layer 7043 is covered with an overcoat layer 7044, which is a protective insulating layer. Covered by layer 7045 .

[0328] In addition, a protective insulating layer 7045, an insulating layer 7042, and an insulating layer 7041 are formed, and the The contact hole reaching the rain electrode layer is disposed at a position overlapping with the partition wall 7029 .

[0329] However, when using a light-emitting element with a dual-side emission structure and making both display surfaces full color display, Since the light from the second electrode 7025 side does not pass through the color filter layer 7043, a separate color filter is used. It is preferable that a sealing substrate having a -filter layer is provided above the second electrode 7025.

[0330] Next, a light emitting element having a top emission structure will be described with reference to FIG.

[0331] In FIG. 12C, the driving TFT 7001 is an n-type TFT, and the light emitted from the light emitting element 7002 is FIG. 12C shows a cross-sectional view of a pixel when the driving electrode 7005 is inserted. Wiring layers 7008a and 7008b electrically connected to the drain electrode layer of the TFT 7001 are A planarization insulating layer 7056 is formed on the wiring layer 7008b. In the opening formed in the planarization insulating layer 7056, the first electrode 700 of the light emitting element 7002 is 3, and connects the driving TFT 7001 and the first electrode 7003 of the light emitting element 7002 to each other. An EL layer 7004 and a second electrode 7005 are disposed on a first electrode 7003 in this order. The layers are stacked on top of each other.

[0332] In addition, various materials can be used for the first electrode 7003. For example, When using 03 as a cathode, a material with a small work function, specifically, for example, Li or Cs Alkaline metals such as Mg, Ca, Sr, and alkaline earth metals including these In addition to alloys (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferable.

[0333] The periphery of the first electrode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of polyimide. Organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, and organic polysiloxanes. The partition wall 7009 is formed by using a photosensitive resin material. 03, an opening is formed on the surface, and the side wall of the opening is an inclined surface formed with a continuous curvature. In the case where a photosensitive resin material is used as the partition wall 7009, In this case, the step of forming a resist mask can be omitted.

[0334] The EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is at least It is sufficient to include a light-emitting layer, and the light-emitting device may be composed of a single layer or may be composed of multiple layers stacked together. When the EL layer 7004 is composed of a plurality of layers, On the first electrode 7003 used for the above-mentioned purpose, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, a hole It is not necessary to provide all of these layers.

[0335] The stacking order is not limited to the above, and the hole injection layer 7002 may be formed on the first electrode 7003 used as an anode. Alternatively, the layer may be laminated in the following order: a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer.

[0336] In FIG. 12(C), a hole injection was performed on a laminated film in which a Ti film, an aluminum film, and a Ti film were laminated in this order. The electron injection layer, hole transport layer, light emitting layer, electron transport layer, and electron injection layer are laminated in that order, and Mg:A A laminate of a g-alloy thin film and ITO is formed.

[0337] However, when the driving TFT 7001 is an n-type, an electron injection layer and an electron The order of stacking the transport layer, light-emitting layer, hole transport layer, and hole injection layer is advantageous in terms of the driving circuit. This is preferable because it is possible to suppress a voltage rise and reduce power consumption.

[0338] The second electrode 7005 is formed using a light-transmitting conductive material, for example, an oxide. Indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide , indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Permeable materials such as indium tin oxide, indium zinc oxide, and indium tin oxide doped with silicon oxide A conductive film having optical properties may be used.

[0339] An EL layer 7004 including a light-emitting layer is sandwiched between a first electrode 7003 and a second electrode 7005. In the case of the element structure shown in FIG. 12C, the light-emitting element 7 Light emitted from 002 is emitted to the second electrode 7005 side as shown by the arrow.

[0340] In FIG. 12C, the drain electrode layer of the driving TFT 7001 is an oxide insulating layer. 7051, a protective insulating layer 7052, a planarizing insulating layer 7056, a planarizing insulating layer 7053, and an insulating Electrically connected to the first electrode 7003 through a contact hole provided in the edge layer 7055 The planarizing insulating layers 7036, 7046, 7053, and 7056 are made of polyimide and acrylic. Resin materials such as benzocyclobutene, polyamide, and epoxy can be used. In addition to the above resin materials, low-k materials, siloxane resins, PSG (lithium sulphide) For example, boron phosphorus glass (BPSG) and boron phosphate glass (BPSG) can be used. By laminating a plurality of insulating films made of the same material, planarizing insulating layers 7036, 7046, and 70 53, 7056 may be formed. The method for forming the layer 6 is not particularly limited, and may be a sputtering method, a spin coating method, or the like, depending on the material. , dipping method, spray coating method, droplet ejection method (inkjet method, screen printing, Offset printing, roll coating, curtain coating, knife coating, etc. This can be done.

[0341] In addition, a partition wall 700 is provided to insulate the first electrode 7003 from the first electrodes of adjacent pixels. The partition wall 7009 is made of an organic resin such as polyimide, acrylic, polyamide, or epoxy. The partition wall 7009 is formed by using an oil film, an inorganic insulating film, or an organic polysiloxane. An opening is formed on the first electrode 7003 using a photosensitive resin material, and the side wall of the opening is It is preferable to form the partition wall 700 so as to have an inclined surface having a continuous curvature. When a photosensitive resin material is used as 9, the step of forming a resist mask can be omitted. can be done.

[0342] In the structure of FIG. 12C, when a full-color display is performed, for example, the light-emitting element 70 02 is a green light emitting element, one adjacent light emitting element is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is also added, making a total of four. A light-emitting display device capable of full-color display may be manufactured using a variety of light-emitting elements.

[0343] In the structure of FIG. 12C, all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full color display may be manufactured. By forming a material and combining it with a color filter and a color conversion layer, a full color display is achieved. It is possible.

[0344] The source electrode layer and the drain electrode layer are the source electrode layer 415a and the drain electrode layer shown in Embodiment 1. The wiring layer 700 can be formed in the same process and with the same materials as the inner electrode layer 415b. 8a, 7008b, 7018a, 7018b, 7028a, and 7028b are also in the first embodiment. The wiring layers 417a, 417b, 418a, and 418b shown in FIG. It is possible.

[0345] The source electrode layer and the drain electrode layer are preferably thin, with a thickness of 0.1 nm to 50 nm. The source electrode layer and the drain electrode layer are made of a thin conductive film. Therefore, the parasitic capacitance between the oxide semiconductor layer and the gate electrode layer can be reduced. A semiconductor device having a thin film transistor using the above-mentioned compound semiconductor layer and consuming less power can be provided.

[0346] Of course, a single-color display may be used. For example, a lighting device may be formed using white light. Alternatively, monochromatic light may be used to form an area color type light emitting device.

[0347] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0348] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0349] In addition, the thin film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically However, a current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the input / output terminals are connected to each other.

[0350] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0351] (Embodiment 9) In this embodiment mode, the appearance and cross section of a light-emitting display panel (also called a light-emitting panel) will be described with reference to FIG. FIG. 13 shows a thin film transistor and a light emitting element formed on a first substrate. FIG. 13 is a plan view of a panel in which an element is sealed between a second substrate and the panel by a sealant. (B) corresponds to a cross-sectional view taken along line HI in FIG. 13(A).

[0352] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0353] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 13B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0354] The highly reliable thin film transistor including the oxide semiconductor layer described in any of Embodiments 1 to 7 is used as a pixel. The thin film transistor 4510 for the driver circuit can be used as the thin film transistor 4510 for the driver circuit. The transistor 4509 is a transistor having a channel of an oxide semiconductor layer of the thin film transistor described in Embodiment 1. In this embodiment, a conductive layer is provided in a position overlapping with a thin film transistor forming region. Transistors 4509 and 4510 are n-channel thin film transistors.

[0355] An oxide semiconductor of a thin film transistor 4509 for a driver circuit is formed on an oxide insulating layer 4542. A conductive layer 4540 is provided in a position overlapping with a channel formation region of the conductive layer 4540. By providing the oxide semiconductor layer in a position overlapping with a channel formation region, In this case, the amount of change in the threshold voltage of the thin film transistor 4509 can be reduced. In addition, the conductive layer 4540 may have the same potential as the gate electrode layer of the thin film transistor 4509. However, it may be different and may function as a second gate electrode layer. The potential of the electric layer 4540 may be GND, 0V, or may be in a floating state.

[0356] In addition, an oxide insulating layer 4542 is formed to cover the oxide semiconductor layer of the thin film transistor 4510. The source electrode layer or the drain electrode layer of the thin film transistor 4510 is a thin film transistor. In the opening formed in the oxide insulating layer 4542 and the insulating layer 4551 provided on the The wiring layer 4550 is electrically connected to the first electrode 4517. The thin film transistor 4510 and the first electrode 4517 are connected via a wiring layer 4550. The electrodes are electrically connected to each other.

[0357] The source electrode layer and the drain electrode layer are the source electrode layer 415a and the drain electrode layer shown in Embodiment 1. The wiring layer 455 can be formed in the same process and with the same material as the inner electrode layer 415b. 0 is also fabricated by the same process as the wiring layers 417a, 417b, 418a, and 418b shown in the first embodiment. and materials.

[0358] The source electrode layer and the drain electrode layer are preferably thin, with a thickness of 0.1 nm to 50 nm. The source electrode layer and the drain electrode layer are made of a thin conductive film. Therefore, the parasitic capacitance between the oxide semiconductor layer and the gate electrode layer can be reduced. A semiconductor device having a thin film transistor using the above-mentioned compound semiconductor layer and consuming less power can be provided.

[0359] The oxide insulating layer 4542 was formed using a material and a method similar to those of the oxide insulating layer 407 described in Embodiment 1. It may be formed as follows.

[0360] A color filter layer 4545 is disposed on the insulating layer 455 so as to overlap the light-emitting region of the light-emitting element 4511. Formed on 1.

[0361] In addition, it functions as a planarizing insulating film to reduce the surface unevenness of the color filter layer 4545. It is covered with an overcoat layer 4543 .

[0362] In addition, an insulating layer 4544 is formed on the overcoat layer 4543. The protective insulating layer 408 may be formed in a manner similar to that of the protective insulating layer 408 described in Embodiment 1. For example, the protective insulating layer 408 may be formed using a silicon nitride film. can be formed by sputtering.

[0363] Also, 4511 corresponds to a light emitting element, and the first electrode 4511 is a pixel electrode of the light emitting element 4511. 517 is a source electrode layer or drain electrode layer of the thin film transistor 4510 and a wiring layer 45 The light emitting element 4511 is electrically connected to the first electrode 451 via the first electrode 451. 7, a laminated structure of an electroluminescent layer 4512 and a second electrode 4513, but is not limited to the configuration shown. The configuration of the light emitting element 4511 is determined according to the direction of the light to be extracted from the light emitting element 4511. can be changed appropriately.

[0364] The partition 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode 4517, and the sidewall of the opening is continuous. It is preferable to form the inclined surface so as to have a continuous curvature.

[0365] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0366] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 4511, the second electrode 45 A protective film may be formed on the insulating film 13 and the partition wall 4520. The protective film may be a silicon nitride film, a nitride A silicon oxide film, DLC film, etc. can be formed.

[0367] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0368] The connection terminal electrode 4515 is made of the same conductive film as the first electrode 4517 of the light-emitting element 4511. The terminal electrode 4516 is a source electrode layer and a drain electrode layer of the thin film transistor 4509. It is formed from the same conductive film as the electrode layer.

[0369] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0370] The second substrate located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In that case, use a glass plate, a plastic plate, a polyester film or an acrylic plate. A light-transmitting material such as a film is used.

[0371] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's good.

[0372] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0373] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0374] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0375] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0376] (Embodiment 10) The appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. FIG. 14 shows thin film transistors 4010 and 4011 and a liquid crystal element 4013. A first substrate 4001 and a second substrate 4006 are sealed with a sealant 4005. FIG. 14(B) is a plan view of the panel, and FIG. 14(B) is a plan view of the panel in MN of FIG. 14(A) or FIG. 14(C). This corresponds to a cross-sectional view in

[0377] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0378] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 14(A) shows 14C is an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which the signal line driver circuit 4003 is implemented by method B.

[0379] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 14B, the thin film transistor included in the pixel portion 4002 A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 Insulating layers 4041 and 4042 are formed on the thin film transistors 4010 and 4011. 2, 4020, and 4021 are provided.

[0380] The thin film transistors 4010 and 4011 each include the oxide semiconductor layer described in any of Embodiments 1 to 7. Thin film transistors with high reliability, including thin film transistors for driving circuits, can be used. The thin film transistor 4011 and the thin film transistor 4010 for the pixel may be the same as those shown in any of the embodiments 1 to 7. In this embodiment, a thin film transistor 4010 and 4011 are n-channel thin film transistors.

[0381] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is formed on the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the gate insulating film at a position overlapping the channel formation region of the nitride semiconductor layer, In addition, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as the second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0382] In addition, the pixel electrode layer 4030 of the liquid crystal element 4013 is The source electrode layer or the drain electrode layer is electrically connected to the source electrode layer or the drain electrode layer through a wiring layer 4050. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The overlapping portion of the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 is The pixel electrode layer 4030 and the counter electrode layer 4031 correspond to the liquid crystal element 4013. Insulating layers 4032 and 4033 functioning as alignment films are provided. A liquid crystal layer 4008 is sandwiched between the first and second electrodes 4002 and 4003.

[0383] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film A film can be used.

[0384] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the counter electrode layer 40 to the conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0385] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. Since the liquid crystal display is optically isotropic, no alignment treatment is required, and the viewing angle dependency is small.

[0386] In addition to the transmission type liquid crystal display device, the present invention can also be applied to a semi-transmission type liquid crystal display device.

[0387] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and a colored layer and a display element are provided on the inner side. In the example shown, the polarizing plate is disposed on the inner side of the substrate. In addition, the laminated structure of the polarizing plate and the coloring layer is not limited to the present embodiment, and the materials and The conditions may be appropriately set according to the manufacturing process conditions. A light-shielding film that functions as a light-shielding film may be provided.

[0388] An insulating layer 4041 is provided over the thin film transistors 4011 and 4010 in contact with the oxide semiconductor layer. The insulating layer 4041 is formed using a material similar to that of the oxide insulating layer 407 described in Embodiment 1. Here, the insulating layer 4041 is formed by the same method as in the embodiment 1. A silicon oxide film is formed by sputtering. The protective insulating layer 4042 is formed by the same method as in the first embodiment. It may be formed in the same manner as 408, and for example, a silicon nitride film may be used. A planarizing insulating film is formed on the edge layer 4042 to reduce the surface unevenness of the thin film transistor. The insulating layer 4021 covers the semiconductor device.

[0389] In addition, an insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. are used. In addition, by stacking a plurality of insulating films made of these materials, an insulating layer can be formed. 4021 may be formed.

[0390] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a sintering method, or the like, depending on the material. Pin coat method, dipping method, spray coating method, droplet ejection method (inkjet method, screen lean printing, offset printing, etc.), roll coating method, curtain coating method, knife coating method The baking process of the insulating layer 4021 and the annealing of the semiconductor layer can be performed in the same process. Therefore, it becomes possible to manufacture a semiconductor device efficiently.

[0391] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A light-transmitting conductive material can be used.

[0392] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode thus fabricated has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity be 0.1 Ω·cm or less.

[0393] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0394] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0395] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0396] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0397] In FIG. 14, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. The embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0398] In addition, the LCD module is available in TN (Twisted Nematic) mode, IP S (In-Plane-Switching) mode, FFS (Fringe Field d Switching) mode, MVA (Multi-domain Vertica) l Alignment) mode, PVA(Patterned Vertical A) lignment) mode, ASM (Axially Symmetric align ed Micro-cell) mode, OCB (Optical Compensate) d Birefringence mode, FLC (Ferroelectric Li quid Crystal) mode, AFLC(AntiFerroelectric Liquid Crystal mode can be used.

[0399] An example of a VA type liquid crystal display device is shown below.

[0400] A VA type liquid crystal display device is a type of display that controls the alignment of liquid crystal molecules in a liquid crystal display panel. In a VA type liquid crystal display device, when no voltage is applied, the liquid crystal molecules are aligned relative to the panel surface. In this embodiment, the pixels are divided into several regions. The device is designed to divide the image into sub-pixels, each of which tilts the molecules in a different direction. This is called multi-domain or multi-domain design. In the following explanation, multi-domain A liquid crystal display device with carefully designed features will be described.

[0401] 15 and 16 show the pixel structure of a VA type liquid crystal display panel. FIG. 15 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The following description will refer to both figures.

[0402] In this pixel structure, one pixel has multiple pixel electrodes, each of which is connected to a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independent. The device has a configuration for controlling the above.

[0403] The pixel electrode layer 624 is connected to the wiring 6 through the contact holes 623 and 660. 62, it is connected to the source electrode layer or drain electrode layer 618 of the TFT 628. The pixel electrode layer 626 is formed on the insulating layer 620 and the insulating layer 622 that covers the insulating layer 620. In the contact hole 627 and the contact hole 661, the TFT 6 The gate wiring of the TFT 628 is connected to the source electrode layer or drain electrode layer 619 of the TFT 628. Different gate signals can be applied to the line 602 and the gate wiring 603 of the TFT 629. On the other hand, the source electrode layer or the drain electrode layer which functions as the data line The polar layer 616 is used in common in the TFT 628 and the TFT 629. The thin film transistor FT629 can be any one of the thin film transistors according to the first to seventh embodiments. Cut.

[0404] The source and drain electrode layers 616, 618, and 619 are the source and drain electrode layers shown in Embodiment 1. The electrode layer 415a and the drain electrode layer 415b can be formed using a process and a material similar to those of the electrode layer 415a and the drain electrode layer 415b. The wirings 662 and 663 are also the same as the wiring layers 417a, 417b, and 417c shown in the first embodiment. It can be formed by the same process and material as 8a and 418b.

[0405] The source electrode layer and the drain electrode layer are preferably thin, with a thickness of 0.1 nm to 50 nm. The source electrode layer and the drain electrode layer are made of a conductive film having a small thickness. Therefore, the parasitic capacitance between the oxide semiconductor layer and the gate electrode layer can be reduced. A semiconductor device having a thin film transistor using the above method can have low power consumption.

[0406] In addition, a capacitance wiring 690 is provided, and the stack of the gate insulating layer 606 is used as a dielectric, and the pixel electrode Alternatively, a storage capacitor is formed together with a capacitance electrode electrically connected to the pixel electrode.

[0407] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes and are separated by a slit 625. The pixel electrode layer 626 is arranged so as to surround the outside of the pixel electrode layer 624 that spreads in a V shape. The timing of applying voltages to the pixel electrode layer 624 and the pixel electrode layer 626 is set as follows: The alignment of the liquid crystal is controlled by varying the TFT 628 and the TFT 629. The equivalent circuit of this pixel structure is shown in FIG. T629 is connected to the gate wiring 603. The gate wiring 602 and the gate wiring 603 are different. By applying different gate signals, the operation timing of TFT628 and TFT629 can be made different. It is possible to do so.

[0408] On the opposing substrate 601, a light-shielding film 632, a second colored film 636, and an opposing electrode layer 640 are formed. In addition, a layer called an overcoat film is provided between the second color film 636 and the counter electrode layer 640. A flattening film 637 is formed on the opposing substrate side to prevent the alignment of the liquid crystal from being disturbed. The counter electrode layer 640 is an electrode shared between different pixels, but it is a slip The slit 641, the pixel electrode layer 624 and the pixel electrode layer 6 By arranging the slits 625 on the 26 side so that they interdigitate with each other, the oblique electric field is effectively This allows the liquid crystal to be oriented in a specific direction. This allows the display to be adjusted to different viewing angles, thereby widening the viewing angle.

[0409] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a first liquid crystal pixel. In addition, the pixel electrode layer 626, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped. The first liquid crystal element and the second liquid crystal element are formed by combining them. The liquid crystal display has a multi-domain structure in which the liquid crystal elements are arranged.

[0410] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0411] (Embodiment 11) In this embodiment, an example of an electronic paper is shown as a semiconductor device according to an embodiment of the present invention. vinegar.

[0412] FIG. 19 shows an active matrix semiconductor device as an example of a semiconductor device to which an embodiment of the present invention is applied. The semiconductor device is a thin film transistor 581. The thin film transistor according to any one of the first to seventh embodiments can be used as appropriate.

[0413] The electronic paper in FIG. 19 is an example of a display device that uses the twisting ball display method. The spherical display method uses black and white spherical particles as the display element and an electrode layer. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0414] A thin film transistor 581 provided on a substrate 580 is a thin film transistor of a bottom gate structure. The source electrode layer or the drain electrode layer is formed by an oxide insulating layer 583 and a protective insulating layer 584. The wiring layer 589a and the wiring layer 589b are electrically connected to each other through an opening formed in the wiring layer 589a. 89b is a first electrode layer 587 in an opening formed in an insulating layer 585 provided above. The thin film transistor 581 and the first electrode layer 587 are provided in contact with each other. 9a and 589b.

[0415] The source electrode layer and the drain electrode layer are the source electrode layer 415a and the drain electrode layer shown in Embodiment 1. The wiring layer 589 can be formed in the same process and with the same materials as the inner electrode layer 415b. a, 589b are the same as the wiring layers 417a, 417b, 418a, 418b shown in the first embodiment. It can be formed using similar processes and materials.

[0416] The source electrode layer and the drain electrode layer are preferably thin, with a thickness of 0.1 nm to 50 nm. The source electrode layer and the drain electrode layer are made of a thin conductive film. Therefore, the parasitic capacitance between the oxide semiconductor layer and the gate electrode layer can be reduced. A semiconductor device having a thin film transistor using the above-mentioned compound semiconductor layer and consuming less power can be provided.

[0417] Between the first electrode layer 587 and the second electrode layer 588, there are a black region 590a and a white region 590b. 0b and including a cavity 594 filled with liquid therearound. The spherical particles are filled with a filler 595 such as resin (see FIG. 19). In this embodiment, the first electrode layer 587 corresponds to a pixel electrode and is provided on the opposing substrate 596. The second electrode layer 588 corresponds to a common electrode.

[0418] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions, allowing the display to be white or black. A display element that applies this principle is an electrophoretic display element, commonly known as electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display, the image that was displayed can be retained. Therefore, a semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0419] Through the above steps, electronic paper having high reliability as a semiconductor device can be manufactured. .

[0420] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0421] (Embodiment 12) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames; mobile phones (also called mobile phones or mobile phone devices); Examples include game machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. do.

[0422] FIG. 20A shows an example of a mobile phone 1100. The mobile phone 1100 has a housing. In addition to the display unit 1102 incorporated in the 1101, the operation buttons 1103 and the external connection port 11 04, a speaker 1105, a microphone 1106, etc.

[0423] In the mobile phone 1100 shown in FIG. 20A, information is displayed by touching a display unit 1102 with a finger or the like. In addition, operations such as making a phone call or sending an e-mail can be performed by using the display. This can be done by touching 1102 with a finger or the like.

[0424] The screen of the display unit 1102 has three main modes. The first is a display mode that is mainly used for displaying images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. This is a display + input mode that combines the display mode and the input mode.

[0425] For example, when making a call or composing an e-mail, the display unit 1102 is used to input characters. The main character input mode is to input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1102. I wish.

[0426] In addition, the mobile phone 1100 may include a sensor for detecting tilt, such as a gyro or an acceleration sensor. By providing a detection device having the above configuration, the orientation of the mobile phone 1100 (portrait or landscape) can be determined and the display The screen display of the display unit 1102 can be automatically switched.

[0427] The screen mode can be changed by touching the display unit 1102 or by operating the housing 1101. This is done by operating the button 1103. Also, depending on the type of image displayed on the display unit 1102, For example, the image signal to be displayed on the display unit is a moving image. If it is data, the mode is switched to display mode, and if it is text data, the mode is switched to input mode.

[0428] In the input mode, the optical sensor of the display unit 1102 detects a signal and displays If there is no input by touch operation of the unit 1102 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0429] The display unit 1102 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to image finger veins, palm veins, etc.

[0430] The display portion 1102 includes the thin film transistor shown in Embodiment 1 as a switching element of a pixel. Place multiple stars.

[0431] FIG. 20(B) is also an example of a mobile phone. The portable information terminal shown in FIG. 20(B) is It can have multiple functions. For example, in addition to the telephone function, it can have a built-in computer and perform various functions. It can also be equipped with various data processing functions.

[0432] The portable information terminal shown in FIG. 20B includes two housings, a housing 1800 and a housing 1801. The housing 1800 includes a display panel 1802, a speaker 1803, a microphone, and a microphone array. Phone 1804, pointing device 1806, camera lens 1807, external connection The housing 1801 is equipped with a keyboard 1810, an external memory slot, etc. The housing 1801 includes a built-in antenna.

[0433] The display panel 1802 is equipped with a touch panel, and in FIG. A plurality of operation keys 1805 are indicated by dotted lines.

[0434] In addition to the above configuration, a non-contact IC chip, a small recording device, etc. may be built in.

[0435] The light emitting device can be used in a display panel 1802, and the display direction can be appropriately adjusted according to the usage mode. In addition, a camera lens 1807 is provided on the same surface as the display panel 1802. A speaker 1803 and a microphone 1804 are used for audio. Not only voice calls, but also video calls, recording, playback, etc. are possible. The body 1801 slides and changes from the unfolded state to the overlapped state as shown in FIG. 20(B). The device can be made compact and portable.

[0436] The external connection terminal 1808 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. By inserting a recording medium into the memory slot 1811, it is possible to store and transfer a larger amount of data. do.

[0437] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0438] FIG. 21A shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In addition, the stand 9605 supports the housing 9601. This shows a configuration in which the above is supported.

[0439] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0440] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0441] The display portion 9603 includes the thin film transistor shown in Embodiment 1 as a switching element of a pixel. Place multiple stars.

[0442] FIG. 21B shows a digital photo frame 9700 as an example of a digital photo frame. For example, a digital photo frame 9700 includes a display unit 9701 and a housing 9701. The display unit 9703 is capable of displaying various images. For example, by displaying image data taken with a digital camera, it can be used in the same way as a regular photo frame. It can be made to function in the same way.

[0443] The display portion 9703 includes the thin film transistor shown in Embodiment 1 as a switching element of a pixel. Place multiple stars.

[0444] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have one as it improves the design. For example, the Digital Photo Frame 9700 Insert a memory that stores image data taken with a digital camera into the recording medium insertion section of the Image data can be captured and the captured image data can be displayed on the display unit 9703. do.

[0445] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0446] FIG. 22 shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 includes a display unit 988 and a connector 9893 for connecting the display unit 988 to the housing 9881 in an openable and closable manner. 2 is incorporated in the housing 9891, and a display unit 9883 is incorporated in the housing 9891.

[0447] The display portion 9883 includes the thin film transistor shown in Embodiment 1 as a switching element of a pixel. Place multiple stars.

[0448] In addition, the portable game machine shown in FIG. 22 also includes a speaker unit 9884 and a recording medium insertion unit 98 86, LED lamp 9890, input means (operation keys 9885, connection terminal 9887, sensor 9888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature , chemicals, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, Equipped with a microphone 9889) and other equipment, including a function to measure vibration, odor, or infrared rays Of course, the configuration of the portable gaming machine is not limited to the above, and at least It is sufficient that the device has the thin film transistor disclosed in the document, and other auxiliary equipment is provided as appropriate. The portable game machine shown in FIG. The function of reading out programs or data and displaying them on the display unit, as well as wireless communication with other portable gaming machines, The portable gaming machine shown in FIG. 22 has the following functions: is not limited thereto and can have various functions.

[0449] FIG. 24 shows a light emitting device formed by applying the above embodiment as an indoor lighting device 3001. The light emitting device shown in the fourth or fifth embodiment can be made large in area. Since the above-described embodiment is capable of displaying a large-area light, the device can be used as a lighting device having a large area. The light emitting device can also be used as a desk lamp 3000. In addition to ceiling-mounted lighting fixtures and tabletop lighting fixtures, we also offer wall-mounted lighting fixtures, in-car lighting, This also includes emergency exit lights.

[0450] As described above, the thin film transistor described in any one of Embodiments 1 to 7 has the above-described The thin film transistor can be placed on the display panel of various electronic devices such as the above. By using it as a switching element in a semiconductor device, it is possible to provide highly reliable electronic equipment. can.

[0451] (Embodiment 13) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, train rides, etc. It can be used for in-car advertising, display on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 23.

[0452] FIG. 23 shows an example of an electronic book 2700. 00 is composed of two housings, housing 2701 and housing 2703. Housing 2701 The housing 2703 is integrated with a shaft portion 2711. This configuration allows the book to be opened and closed like a paper book. This makes it possible.

[0453] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 23) and An image can be displayed on the display unit 2707 in FIG.

[0454] FIG. 23 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a display board, a pointing device, etc. On the front side, there is a terminal for external connection (earphone terminal, USB terminal, or AC adapter and USB cable). A terminal that can be connected to various cables such as a USB cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. Good too.

[0455] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0456] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

Claims

1. A pixel portion and a scanning line driver circuit portion are included. The scanning line driving circuit unit is a display device having at least one transistor, a first conductive layer having a function as a gate electrode of the transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of the transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and serving as the other of the source electrode and drain electrode of the transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the second conductive layer, a region in contact with an upper surface of the oxide semiconductor layer, a region in contact with an upper surface of the third conductive layer, and a region in contact with a side surface of the third conductive layer; a fourth conductive layer having a region located above the second insulating layer and functioning as wiring; a fifth conductive layer having a region located above the second insulating layer and functioning as wiring; the fourth conductive layer has a region in contact with the second conductive layer through a first opening of the second insulating layer; the fifth conductive layer has a region in contact with the third conductive layer through the second opening of the second insulating layer; the fourth conductive layer has a laminated structure, the fifth conductive layer has a laminated structure, a thickness of the second conductive layer is smaller than a thickness of the fourth conductive layer; A display device, wherein a thickness of the third conductive layer is smaller than a thickness of the fifth conductive layer.

2. A pixel portion and a scanning line driver circuit portion are included. The scanning line driving circuit unit is a display device having at least one transistor, a first conductive layer having a function as a gate electrode of the transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of the transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and serving as the other of the source electrode and drain electrode of the transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the second conductive layer, a region in contact with an upper surface of the oxide semiconductor layer, a region in contact with an upper surface of the third conductive layer, and a region in contact with a side surface of the third conductive layer; a fourth conductive layer having a region located above the second insulating layer and functioning as wiring; a fifth conductive layer having a region located above the second insulating layer and functioning as wiring; the fourth conductive layer has a region in contact with the second conductive layer through a first opening of the second insulating layer; the fifth conductive layer has a region in contact with the third conductive layer through the second opening of the second insulating layer; the fourth conductive layer has a laminated structure, the fifth conductive layer has a laminated structure, a thickness of the second conductive layer is smaller than a thickness of the fourth conductive layer; a thickness of the third conductive layer is smaller than a thickness of the fifth conductive layer; A display device, wherein, in a plan view, the fourth conductive layer has a region extending in a first direction intersecting a channel length direction of the transistor, and the fifth conductive layer has a region extending in the first direction.

3. A pixel portion and a scanning line driver circuit portion are included. The scanning line driving circuit unit is a display device having at least one transistor, a first conductive layer having a function as a gate electrode of the transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of the transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and serving as the other of the source electrode and drain electrode of the transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the second conductive layer, a region in contact with an upper surface of the oxide semiconductor layer, a region in contact with an upper surface of the third conductive layer, and a region in contact with a side surface of the third conductive layer; a fourth conductive layer having a region located above the second insulating layer and functioning as wiring; a fifth conductive layer having a region located above the second insulating layer and functioning as wiring; the fourth conductive layer has a region in contact with the second conductive layer through a first opening of the second insulating layer; the fifth conductive layer has a region in contact with the third conductive layer through the second opening of the second insulating layer; the fourth conductive layer has a laminated structure, the fifth conductive layer has a laminated structure, a thickness of the second conductive layer is smaller than a thickness of the fourth conductive layer; a thickness of the third conductive layer is smaller than a thickness of the fifth conductive layer; the fourth conductive layer overlaps with the oxide semiconductor layer with the second conductive layer interposed therebetween.

4. A pixel portion and a scanning line driver circuit portion are included. The scanning line driving circuit unit is a display device having at least one transistor, a first conductive layer having a function as a gate electrode of the transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region located over the first insulating layer and including a channel formation region of the transistor; a second conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region in contact with a top surface of the oxide semiconductor layer, a region in contact with a side surface of the oxide semiconductor layer, and a region in contact with a top surface of the first insulating layer, and serving as the other of the source electrode and drain electrode of the transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the second conductive layer, a region in contact with an upper surface of the oxide semiconductor layer, a region in contact with an upper surface of the third conductive layer, and a region in contact with a side surface of the third conductive layer; a fourth conductive layer having a region located above the second insulating layer and functioning as wiring; a fifth conductive layer having a region located above the second insulating layer and functioning as wiring; the fourth conductive layer has a region in contact with the second conductive layer through a first opening of the second insulating layer; the fifth conductive layer has a region in contact with the third conductive layer through the second opening of the second insulating layer; the fourth conductive layer has a laminated structure, the fifth conductive layer has a laminated structure, a thickness of the second conductive layer is smaller than a thickness of the fourth conductive layer; a thickness of the third conductive layer is smaller than a thickness of the fifth conductive layer; When viewed in a plan view, the fourth conductive layer has a region extending in a first direction intersecting a channel length direction of the transistor, and the fifth conductive layer has a region extending in the first direction; the fourth conductive layer overlaps with the oxide semiconductor layer with the second conductive layer interposed therebetween.

5. In any one of claims 1 to 4, a thickness of the second conductive layer is smaller than a thickness of the oxide semiconductor layer; a thickness of the third conductive layer is smaller than a thickness of the oxide semiconductor layer; a thickness of the oxide semiconductor layer is smaller than a thickness of the fourth conductive layer; a thickness of the oxide semiconductor layer is smaller than a thickness of the fifth conductive layer.

6. In any one of claims 1 to 4, the second conductive layer has a single layer structure, The display device, wherein the third conductive layer has a single layer structure.

Images