Transistor

Abstract

To provide a semiconductor device having a configuration capable of suppressing degradation of electrical characteristics associated with its miniaturization.SOLUTION: A semiconductor device includes: stacked layers on an insulating surface, formed of a first oxide semiconductor layer and a second oxide semiconductor layer in this order; and a third oxide semiconductor layer formed so as to cover a part of the surface of the stacked layer. The third oxide semiconductor layer has a first layer in contact with the stacked layers and a second layer on the first layer. The first layer is formed of a microcrystalline layer, and the second layer is formed of a crystalline layer in which its c-axis is oriented in a vertical direction with respect to the surface of the first layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, As examples of the present invention, the present invention relates to a device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof. Some examples include:

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device or an electronic device may include a semiconductor device. [Background technology]

[0004] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology for constructing thin-film transistors (also called thin-film transistors (TFTs)) is attracting attention. It is widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. As another material for this, oxide semiconductors have been attracting attention.

[0005] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. There are. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0007] The miniaturization of transistors is an essential technology for increasing the density of integrated circuits. As transistors become smaller, their electrical characteristics can deteriorate and variations can occur. It is known that the yield of integrated circuits decreases as transistors are miniaturized. The adhesion is likely to decrease.

[0008] Therefore, one embodiment of the present invention is a structure capable of suppressing deterioration of electrical characteristics that becomes significant with miniaturization. Another object of the present invention is to provide a semiconductor device having a high manufacturing yield. It is an object of the present invention to provide a semiconductor device having a structure capable of suppressing the lowering of the semiconductor device. Another object is to provide a semiconductor device with a high degree of integration. Another object of the present invention is to provide a semiconductor device that reduces deterioration. It is an object of the present invention to provide a semiconductor device having high reliability. Another object of the present invention is to provide a semiconductor device that retains data even when the power supply is cut off. Another object of the present invention is to provide a novel semiconductor device. It shall be one.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention relates to a semiconductor device including stacked oxide semiconductor layers.

[0011] One embodiment of the present invention is a semiconductor device having a first oxide semiconductor layer and a second oxide semiconductor layer formed in this order over an insulating surface. A laminate formed by the above method, a part of the side surface of the laminate, a part of the top surface, and a part of the side surface opposite to the side surface of the laminate, and a third oxide semiconductor layer formed to cover the first oxide semiconductor layer, the third oxide semiconductor layer being a stack of a first layer in contact with the substrate and a second layer on the first layer, the first layer being formed of a microcrystalline layer The second layer is formed of a crystalline layer whose c-axis is oriented perpendicular to the surface of the first layer. The semiconductor device is characterized in that

[0012] Another embodiment of the present invention is a semiconductor device including a first oxide semiconductor layer, a second oxide semiconductor layer, and a second oxide semiconductor layer over an insulating surface. A stack formed in this order, and a source electrode layer and a drain electrode layer in contact with a part of the stack. and a second insulating layer, a second insulating layer, a first insulating layer, a second insulating layer, a first insulating layer, a second insulating layer, a first insulating layer, a third oxide semiconductor layer formed on the first oxide semiconductor layer and a gate insulating film formed on the third oxide semiconductor layer; a gate electrode layer formed on the gate insulating film; a source electrode layer; a drain electrode layer; and an insulating layer formed over the gate electrode layer. The third oxide semiconductor layer is in contact with the stack. and a second layer on the first layer, the first layer being formed of a microcrystalline layer. The second layer is formed of a crystalline layer whose c-axis is oriented perpendicular to the surface of the first layer. The semiconductor device is characterized in that

[0013] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It should be noted that the numbers are added for the purpose of illustration only and are not intended to be limiting.

[0014] the first oxide semiconductor layer has a crystal layer whose c-axis is oriented in a direction perpendicular to an insulating surface; The second oxide semiconductor layer has a c-axis oriented in a direction perpendicular to an upper surface of the first oxide semiconductor layer. It is preferable that the crystal layer has a crystal structure.

[0015] In addition, in a region where the stack and the third oxide semiconductor layer are in contact with each other, The surface preferably has a curved surface.

[0016] In addition, the first oxide semiconductor layer and the third oxide semiconductor layer are thicker than the second oxide semiconductor layer. It is also found that the energy of the conduction band minimum is close to the vacuum level in the range of 0.05 eV to 2 eV. preferable.

[0017] The first to third oxide semiconductor layers are In-M-Zn oxide layers (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf), and the first oxide semiconductor The conductor layer and the third oxide semiconductor layer have an atomic ratio of M to In that is equal to that of the second oxide semiconductor It is preferably larger than the layer. Effect of the Invention

[0018] By using one embodiment of the present invention, it is possible to suppress deterioration of electrical characteristics that becomes significant with miniaturization. It is possible to provide a semiconductor device having such a configuration that the decrease in yield due to miniaturization can be suppressed. It is possible to provide a semiconductor device having a structure that can achieve high integration. Alternatively, a semiconductor device in which deterioration of on-current is reduced can be provided. Alternatively, a semiconductor device with low power consumption can be provided. In addition, it is possible to provide a highly reliable semiconductor device. It is possible to provide a semiconductor device in which the data is held. It is possible.

[0019] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. Effects other than these may also be included. The above is self-evident from the description, drawings, claims, etc. Other effects can be extracted from the claims and other descriptions. [Brief description of the drawings]

[0020] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a transistor. [Diagram 2] FIG. 1 is a cross-sectional view of a transistor. [Diagram 3] 1A to 1C are diagrams illustrating band structures of oxide semiconductor layers. [Figure 4] 1A and 1B are diagrams illustrating a crystal structure of part of a stack of oxide semiconductor layers. [Diagram 5] FIG. 1 is an enlarged cross-sectional view of a transistor. [Figure 6] FIG. 1 is a cross-sectional view of a transistor. [Figure 7] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 8] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 9] 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device. [Figure 10] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 11] 1A and 1B are a circuit diagram and a cross-sectional view of a semiconductor device. [Figure 12] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 13] 1A to 1C are diagrams illustrating electronic devices to which a semiconductor device can be applied. [Figure 14] 1 is a cross-sectional view of a sample for observing a stacked state of oxide semiconductor layers. [Figure 15] Cross-sectional TEM image of an oxide semiconductor layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The following explanations may be omitted.

[0022] In this specification, when it is explicitly stated that X and Y are connected, When X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are This includes the case where X and Y are directly connected. Here, X and Y are objects (e.g. For example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc. In this case, the present invention is not limited to a specific connection relationship, for example, a connection relationship shown in a drawing or a sentence, but may be applied to any other connection relationship shown in a drawing or a sentence. This also includes connections other than those shown in the text.

[0023] An example of a case where X and Y are electrically connected is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more elements (such as an electrode, a display element, a light-emitting element, or a load) can be connected between X and Y. It is possible. The switch has a function that allows it to be turned on and off. A switch can be in a conductive state (on state) or a non-conductive state (off state) and can either pass current or not. The switch has the function of controlling whether or not current flows. It has the function of switching between these modes.

[0024] An example of a case where X and Y are functionally connected is a case where a functional connection between X and Y is possible. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the potential level of signals, etc.) , voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more devices (such as a memory circuit, a control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if

[0025] In addition, when it is explicitly stated that X and Y are connected, it means that X and Y are electrically connected. (That is, there is another element or circuit between X and Y.) X and Y are functionally connected (i.e., there is another circuit between X and Y) When X and Y are functionally connected through a wire, and when X and Y are directly connected (i.e. , when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it should simply be "" is the same as if it were expressly stated that the

[0026] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are the same, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the function of the wiring and The function of both components is combined with the function of the electrode. Electrical connection means that one conductive film has the functions of multiple components. cases are also included in this category.

[0027] For example, the source (or the first terminal, etc.) of the transistor is connected via Z1 (or The drain (or second terminal, etc.) of the transistor is electrically connected to Z 2 (or not), it may be electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0028] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor The terminals of the transistor (or the first terminal, etc.) are electrically connected to each other, and X, the source of the transistor (or the first terminal, etc.) 1 terminal, etc.), the drain (or second terminal, etc.) of the transistor, and Y. "The source (or the third) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of a transistor. The transistor is electrically connected to Y via a drain (or a second terminal, etc.) and a transistor is electrically connected to X via a drain (or a second terminal, etc.). The source (or first terminal, etc.) of a resistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this connection order. By using a simple expression method and specifying the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the object (e.g., the device , elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0029] In this specification and the like, transistors can be formed using various substrates. The type of substrate is not limited to a specific one. An example of the substrate is a semiconductor substrate. Substrates (e.g. single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Includes plastic substrates, metal substrates, stainless steel substrates, and stainless steel foil. Substrates for bonding, tungsten substrates, substrates with tungsten foil, flexible substrates, bonding Examples include laminated films, paper containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. An example of a flexible substrate is polyethylene terephthalate (PET). ), polyethylene naphthalate (PEN), and polyethersulfone (PES). The materials used are plastics that can be used for bonding, and synthetic resins that have flexibility, such as acrylic. Examples of films include polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Examples of base films include polyester, polyamide, polyvinyl chloride, etc. In particular, semiconductor substrates, single crystal substrates, Alternatively, by manufacturing transistors using SOI substrates, etc., the characteristics, size, We manufacture small-sized transistors with little variation in shape and current capacity. When a circuit is constructed using such transistors, the circuit can consume low power. This allows for increased power and higher circuit integration.

[0030] In addition, a flexible substrate may be used as the substrate, and a transistor may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate having poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be, for example, an inorganic film of a tungsten film and a silicon oxide film. The laminated structure of the above-mentioned, or a structure in which an organic resin film such as polyimide is formed on a substrate, etc. may be used. This can be done.

[0031] That is, a transistor is formed using one substrate, and then the transistor is transferred to another substrate. The transistor may be placed on one substrate and the transistor may be placed on another substrate. Examples include substrates on which the above-mentioned transistors can be formed, as well as paper substrates, ceramic substrates, etc. Fan board, aramid film board, polyimide film board, stone board, wood board, cloth board Board (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or Mostly recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), leather The substrates used are leather and rubber. By using these substrates, Formation of transistors, formation of transistors with low power consumption, manufacturing of devices that are not easily damaged, heat resistance It is possible to provide a thinner, lighter, or thinner device.

[0032] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0033] 1A, 1B, and 1C are a top view and a cross-sectional view of a transistor of one embodiment of the present invention. FIG. 1(A) is a top view, and the cross section taken along the dashed line A1-A2 shown in FIG. FIG. 1(C) is a cross-sectional view taken along the dashed line A3-A4 in FIG. 1(A). In the top view of FIG. 1(A), some elements are omitted for clarity. The dashed line A1-A2 direction is the channel length direction, and the dashed line A3-A4 direction is the channel This is sometimes referred to as the width direction of the panel.

[0034] The transistor 100 shown in FIGS. 1A, 1B, 1C and 2 is formed on a substrate 110. A base insulating film 120 formed on the base insulating film and a first oxide semiconductor layer 1 formed on the base insulating film. A stack of a first oxide semiconductor layer 31, a second oxide semiconductor layer 132, and a second oxide semiconductor layer 133 is formed in this order. The source electrode layer 140 and the drain electrode layer 150 formed as above, the base insulating film 120, The stacked layers include a first electrode layer 140 and a second electrode layer 150, which are in contact with each other. a third oxide semiconductor layer 133 and a gate insulating film 1 formed on the third oxide semiconductor layer 60, a gate electrode layer 170 formed on the gate insulating film, a source electrode layer 140, The semiconductor device has an insulating layer 180 formed on the drain electrode layer 150 and the gate electrode layer 170 .

[0035] Here, the first oxide semiconductor layer 131 has a c-axis perpendicular to the surface of the base insulating film 120. The second oxide semiconductor layer 132 is disposed on the first oxide semiconductor layer 131. It is preferable to have a crystal layer with the c-axis oriented perpendicular to the surface.

[0036] The third oxide semiconductor layer 133 is a first layer in contact with the stack and a second oxide semiconductor layer on the first layer. The first layer is a microcrystalline layer and the second layer is a The first layer is formed of a crystalline layer whose c-axis is oriented perpendicular to the surface of the first layer.

[0037] In addition, an insulating layer 185 made of an oxide may be formed on the insulating layer 180. The insulating layer 185 may be provided as necessary, and another insulating layer may be formed on top of it. In addition, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer The oxide semiconductor layers 133 are collectively referred to as oxide semiconductor layers 130.

[0038] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of the current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" are used interchangeably. It is possible to use it.

[0039] In addition, in the transistor of one embodiment of the present invention, the oxide semiconductor layer (the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132) overlapping the source electrode layer 140 or the drain electrode layer In 150, the source electrode layer 1 is formed from one end of the oxide semiconductor layer shown in the top view of FIG. 40 or the drain electrode layer 150 to one end (ΔW) is 50 nm or less, preferably By reducing ΔW, the amount of oxygen contained in the base insulating film 120 can be reduced. The amount of diffusion into the metal material constituting the source electrode layer 140 or the drain electrode layer 150 is suppressed. Therefore, oxygen contained in the base insulating film 120, especially excessive oxygen, Therefore, unnecessary release of oxygen can be suppressed, and the base insulating film 120 can be formed on the oxide semiconductor layer. This allows for efficient supply of oxygen.

[0040] Next, components of the transistor 100 of one embodiment of the present invention will be described in detail.

[0041] The substrate 110 is not limited to being a simple support substrate, but may also be a substrate on which other devices such as transistors are formed. In this case, the gate electrode layer 170 of the transistor 100, the source electrode At least one of the layers 140 and the drain electrode layer 150 is electrically connected to the other devices described above. The input / output terminals may be electrically connected to each other.

[0042] The base insulating film 120 has a role of preventing the diffusion of impurities from the substrate 110 and also prevents oxidation. Therefore, the base insulating film 1 can serve to supply oxygen to the organic semiconductor layer 130. 20 is preferably an insulating film containing oxygen, and the insulating film contains more oxygen than the stoichiometric composition. As described above, the substrate 110 is preferably a thin film. In the case of a substrate having such a structure, the base insulating film 120 also functions as an interlayer insulating film. CMP (Chemical Mechanical Polishing) is used to make the surface flat. It is preferable to perform a planarization process by a method such as a shingle method.

[0043] In addition, in a region where a channel of the transistor 100 is formed, the oxide semiconductor layer 130 From the substrate 110 side, a first oxide semiconductor layer 131, a second oxide semiconductor layer 132, a third oxide semiconductor layer 133, and a The oxide semiconductor layer 133 is stacked on the oxide semiconductor layer 132. As shown in the cross-sectional view in the axial direction, the third oxide semiconductor layer 133 has a first oxide semiconductor layer in a channel formation region. The side and top surfaces of a stack of the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 Therefore, in the channel forming region, The second oxide semiconductor layer 132 is a semiconductor layer including the first oxide semiconductor layer 131 and the third oxide semiconductor layer. It has a structure surrounded by a conductor layer 133 .

[0044] Here, for example, the second oxide semiconductor layer 132 is a first oxide semiconductor layer 131. and has a higher electron affinity (energy density from the vacuum level to the bottom of the conduction band) than the third oxide semiconductor layer 133. The electron affinity is the distance between the vacuum level and the top of the valence band. From the energy difference (ionization potential), the energy between the bottom of the conduction band and the top of the valence band It can be calculated by subtracting the difference (energy gap).

[0045] The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are The layer 132 includes one or more metal elements, and the energy of the conduction band minimum is, for example, The oxide semiconductor layer 132 has a refractive index of 0.05 eV, 0.07 eV, 0.1 eV, and 0.15 eV. and in the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV or less. It is preferable that the insulating film be formed using an oxide semiconductor having a temperature close to a vacuum level in the vicinity of the insulating film.

[0046] In such a structure, when an electric field is applied to the gate electrode layer 170, the oxide semiconductor layer 13 0, the second oxide semiconductor layer 132 has the smallest energy at the bottom of the conduction band. That is, a first oxide semiconductor layer 132 is formed between the second oxide semiconductor layer 132 and the gate insulating film 160. The third oxide semiconductor layer 133 is formed, so that the channel of the transistor is The structure is such that it does not come into contact with the insulating film.

[0047] The first oxide semiconductor layer 131 contains the metal element constituting the second oxide semiconductor layer 132. Since the second oxide semiconductor layer 132 and the base insulating film 120 are bonded to each other, The interface between the second oxide semiconductor layer 132 and the first oxide semiconductor layer 131 is different from that in the case of the first oxide semiconductor layer 131. The interface state is unlikely to be formed at the interface. The interface state may form a channel. Therefore, the threshold voltage of the transistor may vary. By providing the layer 131, the variation in electrical characteristics such as the threshold voltage of the transistor can be reduced. In addition, the reliability of the transistor can be improved.

[0048] The third oxide semiconductor layer 133 contains the metal element constituting the second oxide semiconductor layer 132. Since the second oxide semiconductor layer 132 and the gate insulating film 160 are formed by containing one or more of The interface between the second oxide semiconductor layer 132 and the third oxide semiconductor layer 13 Therefore, the third oxide semiconductor layer 3 is less likely to cause carrier scattering at the interface with the third oxide semiconductor layer 3. By providing the region 133, the field effect mobility of the transistor can be increased.

[0049] A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor layer 13 3 is at least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn When the first oxide is an In-M-Zn oxide layer containing a metal such as In, La, Ce or Hf, The In or Zn in the oxide semiconductor layer 131 and the third oxide semiconductor layer 133 The atomic ratio of M is preferably higher than that of the second oxide semiconductor layer 132. Specifically, the atomic ratio is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. Since M bonds more strongly with oxygen than In or Zn, oxygen vacancies form in oxide semiconductors. That is, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 have a function of suppressing the generation of the oxide semiconductor layer. The third oxide semiconductor layer 133 is less likely to have oxygen vacancies than the second oxide semiconductor layer 132. It can be said that.

[0050] Note that the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor The layer 133 is made of at least indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr In the case of an In-M-Zn oxide layer containing a metal such as In, Sn, La, Ce or Hf, The oxide semiconductor layer 131 of the first oxide semiconductor layer 131 is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 132 of the second oxide semiconductor layer 131 is In:M:Zn=x1:y1:z1 [atomic ratio]. The oxide semiconductor layer 132 is In:M:Zn=x2:y2:z2 [atomic ratio], and the third oxide semiconductor When the conductor layer 133 has an atomic ratio of In:M:Zn=x3:y3:z3, y1 / x1 and It is preferable that y1 / x1 and y3 / x3 are greater than y2 / x2. x3 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, than y2 / x2 In this case, in the second oxide semiconductor layer 132, when y2 is equal to or larger than x2, However, if y2 is more than three times larger than x2, In order to prevent this, the field effect mobility of the transistor is reduced. Therefore, y2 should be less than three times x2. is preferred.

[0051] Note that in this specification, the atomic ratio used to describe the composition of an oxide semiconductor layer is based on the atomic ratio of the base material. The film is formed by sputtering using an oxide semiconductor material as a target. In this case, the deposition efficiency depends on the sputtering gas species and their ratio, the target density, and the deposition conditions. The composition of the oxide semiconductor layer may differ from that of the base material target. Therefore, in this specification, the atomic ratio describing the composition of the oxide semiconductor layer is based on the atomic ratio of the base material. For example, when the sputtering method is used for film formation, the atomic ratio is 1:1. The In-Ga-Zn oxide film with an atomic ratio of 1:1:1 is an In-Ga-Zn oxide film with an atomic ratio of 1:1:1. This can be rephrased as an In-Ga-Zn oxide film formed using the material as a target. .

[0052] Zn and O in the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 When In and M are excluded, the atomic ratio of In and M is preferably less than 50 atomic %. 50 atomic % or more, more preferably In is less than 25 atomic % and M is 75 atomic % or more. % or more in the second oxide semiconductor layer 132. In the case where the In and M atoms are present, the atomic ratio of In is preferably 25 atomic % or more and M is preferably 7 atomic % or more. 5 atomic %, more preferably In is 34 atomic % or more and M is 66 atomic % or more. Less than omic percent.

[0053] The thickness of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 is 1 nm or more. The thickness of the second oxide semiconductor layer is preferably 3 nm to 50 nm. The thickness of 132 is 1 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably More preferably, it is 3 nm or more and 50 nm or less.

[0054] A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor The layer 133 is made of, for example, an oxide semiconductor containing indium, zinc, and gallium. In particular, when the second oxide semiconductor layer 132 contains indium, the carrier This is preferred because it increases the mobility.

[0055] Therefore, the oxide semiconductor layer 130 is divided into a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132. The stacked structure of the second oxide semiconductor layer 132 and the third oxide semiconductor layer 133 is 132, which has high field-effect mobility and stable electrical properties. A transistor having such a structure can be formed.

[0056] A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor layer 13 In the band structure of 3, the energy of the conduction band edge changes continuously. The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133 This can also be understood from the fact that oxygen easily diffuses between the materials due to the similar composition. , a first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor layer 1 Although 33 is a laminate of layers with different compositions, it can also be said to be physically continuous. In the figure, the interfaces of the laminate are indicated by dotted lines.

[0057] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, a U-shaped junction in which the energy of the conduction band edge changes continuously between layers) In other words, trap centers and recombination centers are formed at the interfaces of each layer. The laminated structure is formed so that there are no impurities that would form defect levels such as centers. If impurities are present between the stacked oxide semiconductor layers, the energy band Continuity is lost, and carriers are trapped or recombined at the interface and disappear.

[0058] For example, the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 may include In:Ga :Zn=1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:6:4 or 1:9: 6 (atomic ratio), and the second oxide semiconductor layer 132 has In:Ga:Zn=1:1:1, 5: Use In-Ga-Zn oxide with an atomic ratio of 5:6 or 3:1:2. can be done.

[0059] The second oxide semiconductor layer 132 in the oxide semiconductor layer 130 serves as a well, and In the transistor using the oxide semiconductor layer 130, the channel is formed by the second oxide semiconductor layer 1 The oxide semiconductor layer 130 has a conduction band minimum energy that changes continuously. It can also be called a U Shape Well. A channel formed in this manner may be called a buried channel.

[0060] The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are made of silicon oxide. Trap levels due to impurities and defects can be formed near the interface with an insulating film such as a silicon film. The first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are provided. This can distance the second oxide semiconductor layer 132 from the trap states.

[0061] However, the conduction band minimums of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are When the difference between the energy of the first oxide semiconductor layer 132 and the energy of the bottom of the conduction band of the second oxide semiconductor layer 132 is small, In this case, electrons in the second oxide semiconductor layer 132 exceed the energy difference and reach the trap level. When electrons are captured in the trap level, a negative fixed charge is generated at the interface of the insulating film. This causes the threshold voltage of the transistor to shift in the positive direction.

[0062] Therefore, in order to reduce the variation in the threshold voltage of the transistor, the first oxide semiconductor layer The energies of the conduction band minimums of the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 and the second oxide semiconductor layer 132 are It is necessary to provide a certain difference between the energy of the conduction band minimum of the conductor layer 132 and the energy of the conductive layer 132. The respective energy differences are preferably 0.1 eV or more, more preferably 0.15 eV or more. preferable.

[0063] The first oxide semiconductor layer 131, the second oxide semiconductor layer 132 and the third oxide semiconductor layer The conductor layer 133 preferably includes a crystal layer oriented along the c-axis. By using such a film, stable electrical characteristics can be imparted to a transistor.

[0064] When an In-Ga-Zn oxide is used for the oxide semiconductor layer 130, the gate insulation of In is In order to prevent diffusion to the insulating film, the third oxide semiconductor layer 133 is It is preferable that the composition contains less In than the above.

[0065] In addition to having the buried channel described above, the transistor according to one embodiment of the present invention has a structure shown in FIG. As shown in the figure, the third oxide semiconductor layer 133 is a semiconductor layer including the first oxide semiconductor layer 131 and the second oxide semiconductor layer. A microcrystalline layer 133a in contact with the stack of the conductor layer 132 and the base insulating film 120, and the microcrystalline layer The crystal layer 133b has a c-axis oriented perpendicular to the surface.

[0066] The band structure of the oxide semiconductor layer (corresponding to the B1-B2 direction in Figure 2) in this structure is The figure shows the energy of the vacuum level, Evac, and EcI1 and EcI2. The energy of the conduction band minimum of the silicon film, EcS1 is the conduction band minimum of the first oxide semiconductor layer 131. EcS2 is the energy of the conduction band minimum of the second oxide semiconductor layer 132. EcS3 is the energy of the bottom of the conduction band of the third oxide semiconductor layer 133.

[0067] The energy changes rapidly between EcS1 and EcS2, and between EcS3 and EcS2. Instead, at the beginning and end of the change, the slope changes gradually.

[0068] This is because the interface between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 and the interface between the third oxide semiconductor layer 133 and the third oxide semiconductor layer 134 are At the interface between the first oxide semiconductor layer 133 and the second oxide semiconductor layer 132, the composition interdiffuses. the composition between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, or A region having a composition between the third oxide semiconductor layer 133 and the second oxide semiconductor layer 132 is formed. This is to achieve this.

[0069] Therefore, as shown in FIG. 3, the channel formed in the second oxide semiconductor layer 132 is A small area is formed from the interface between the third oxide semiconductor layer 133 and the second oxide semiconductor layer 132 toward the center of the film. and a position farther from the interface between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. It is formed in the region 132b between the position slightly away from the center of the film. Even if there are defects or impurities at any of the interfaces, carrier trapping and recombination are suppressed. It is possible to do so.

[0070] In addition, in the third oxide semiconductor layer 133, the first oxide semiconductor layer 131 and the second oxide semiconductor layer The region in contact with the stack of the organic semiconductor layer 132 is a microcrystalline layer 133a. Since the density of the second oxide semiconductor layer is smaller than that of the crystal layer 133b formed in the second oxide semiconductor layer, The composition of the third oxide semiconductor layer 132 is easily diffused toward the third oxide semiconductor layer 133. The region having the composition between the first oxide semiconductor layer 133 and the second oxide semiconductor layer 132 increases. Therefore, the channel formed in the second oxide semiconductor layer 132 is a channel formed in the third oxide semiconductor layer 132. A position further away from the interface between the oxide semiconductor layer 133 and the second oxide semiconductor layer 132 toward the center of the film. This effectively prevents the above-mentioned problems caused by defects or impurities at the interface. can be done.

[0071] In addition, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are crystals oriented along the c-axis. In the case where the layer is made of a microcrystalline layer, the microcrystalline layer 133a has a lower density than the crystalline layer. Therefore, the microcrystalline layer 133a serves as a path through which the underlying insulating film 133 can diffuse oxygen. To efficiently supply oxygen from the film 120 to the second oxide semiconductor layer 132 which serves as a channel. This allows oxygen deficiency to be compensated for with oxygen.

[0072] The crystal layer 133b of the third oxide semiconductor layer 133 is a surface of the microcrystalline layer 133a. Therefore, the surface of the second oxide semiconductor layer 132 is curved. The channel of the second oxide semiconductor layer 132 is formed to have a c-axis oriented crystal. It can densely cover the area.

[0073] FIG. 4A shows a first embodiment of a transistor having a curved surface in the channel width direction. a second oxide semiconductor layer 132; a microcrystalline layer 133a covering the second oxide semiconductor layer; FIG. 1 is a schematic cross-sectional view of a crystal structure in a portion of a stack of crystal layers 133b formed on a crystal layer; Here, the second oxide semiconductor layer 132 is a first oxide semiconductor layer 131 (not shown). ) is a crystal layer oriented with its c-axis perpendicular to the surface.

[0074] As shown in the figure, the surface of the second oxide semiconductor layer 132 is formed to have a curved surface. A dense crystal layer having a c-axis orientation perpendicular to the curved surface is formed through a microcrystalline layer 133a. The third oxide semiconductor layer 133 having the oxide semiconductor layer 133b can be formed. The effect of the third oxide semiconductor layer 133 in suppressing oxygen desorption from the second oxide semiconductor layer 132 As a result, the effect of trapping oxygen released from the base insulating film 120 can be enhanced. Oxygen vacancies in the second oxide semiconductor layer 132 can be efficiently filled with oxygen.

[0075] In addition, in the case where the second oxide semiconductor layer 132 is not formed to have a curved surface, As shown in FIG. 1B, in the third oxide semiconductor layer 133, the second oxide semiconductor layer 132 In the region where the crystal layer 133b formed on the top and the crystal layer 133b formed on the side of A sparsely crystalline region 233 is formed. Therefore, the acid of the second oxide semiconductor layer 132 is The oxygen supplied from the base insulating film 120 to the second oxide semiconductor layer 132 is supplied to the region 2 Therefore, oxygen vacancies in the second oxide semiconductor layer 132 are reduced. Therefore, it becomes difficult to efficiently replenish oxygen.

[0076] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, The present invention relates to a method for manufacturing an oxide semiconductor layer, comprising: reducing an impurity concentration in the oxide semiconductor layer to make the oxide semiconductor layer intrinsic or substantially intrinsic; Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is But 1×10 17 / cm 3 Preferably less than 1 × 10 15 / cm 3 is less than More preferably, 1×10 13 / cm 3 It means that it is less than.

[0077] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements become impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels can become traps and degrade the electrical characteristics of a transistor. Therefore, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132 and the third oxide semiconductor layer The impurity concentration in the oxide semiconductor layer 133 and at the interface between the oxide semiconductor layer 133 and the oxide semiconductor layer 133 can be reduced. preferable.

[0078] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, a secondary ion beam (SIMS) In the case of oxide semiconductors, for example, The silicon concentration at a certain depth in the semiconductor layer or in a certain region of the oxide semiconductor layer is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1×10 18 atoms / cm 3 The fact that it has a portion that is less than In addition, the hydrogen concentration is preferably adjusted at a certain depth in the oxide semiconductor layer or at a certain concentration in the oxide semiconductor layer. In a certain region of the nitride semiconductor layer, 20 atoms / cm3 Less than or equal to 5, preferably ×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below Lower, and more preferably 5×10 18 atoms / cm 3 The following parts are included: In addition, the nitrogen concentration is preferably, for example, at a certain depth in the oxide semiconductor layer or In a region of the oxide semiconductor layer, 19 atoms / cm 3 Less than, preferably 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 It has the following parts: is preferred.

[0079] In addition, when the oxide semiconductor layer contains crystals and contains silicon or carbon at a high concentration, the oxide In order to prevent the crystallinity of the oxide semiconductor layer from being reduced, For example, at a certain depth in the oxide semiconductor layer or in a certain region of the oxide semiconductor layer In this case, the silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than In addition, for example, at a certain depth of the oxide semiconductor layer, , the carbon concentration in a certain region of the oxide semiconductor layer is set to 1×10 19atoms / cm 3 less than , preferably 5 x 10 18 atoms / cm 3 less than 1×10 18 at oms / cm 3 It is sufficient that the part is less than

[0080] In addition, a transistor using the purified oxide semiconductor layer as described above for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V, 5 V or approximately 10V, the off-state current normalized by the transistor channel width It is possible to reduce the current density to several yA / μm to several zA / μm.

[0081] In addition, since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not contact the gate insulating film like a gate insulating film is preferable. When a channel is formed at the interface between the insulating film and the oxide semiconductor layer, carriers are scattered at the interface. This can cause a decrease in the field effect mobility of the transistor. It is preferable that the region of the oxide semiconductor layer that serves as a channel is separated from the gate insulating film. .

[0082] The source electrode layer 140 and the drain electrode layer 150 are made of a conductive material that easily bonds with oxygen. For example, it is preferable to use Al, Cr, Cu, Ta, Ti, Mo, W, etc. Among the above materials, Ti, which is particularly prone to bonding with oxygen, and the subsequent process temperature are comparatively low. It is more preferable to use W, which has a high melting point, because it can be used to increase the thermal conductivity of the material. Conductive materials that are easily bonded also include materials through which oxygen easily diffuses.

[0083] When a conductive material that easily bonds with oxygen is brought into contact with an oxide semiconductor layer, the oxygen in the oxide semiconductor layer However, the oxygen diffuses into the conductive material, which is more likely to bond with oxygen. The above phenomenon occurs remarkably because the manufacturing process of a transistor includes a heating step. The oxide semiconductor layer has an oxygen vacancy in a region adjacent to the source electrode layer or the drain electrode layer. The oxygen vacancies are then combined with the hydrogen contained in the film, and the area is Therefore, the region that has been made n-type acts as the source or drain of the transistor. It can be made to act by

[0084] The n-type region is shown in the enlarged cross-sectional view of the transistor in FIG. 1, in the vicinity of the source electrode layer 140). A boundary 135 indicated by a dotted line in the n-type semiconductor layer 132 is a boundary between an intrinsic semiconductor region and an n-type semiconductor region. In the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, The region in contact with the source electrode layer 140 is an n-type region. The diagram is a schematic illustration and may not be clear in practice. A part of 135 is located so as to extend laterally in the second oxide semiconductor layer 132. However, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are not shown in FIG. In some cases, the entire area between the base electrode layer 140 and the base insulating film 120 may become n-type. do.

[0085] In addition, when forming a transistor with an extremely short channel length, the occurrence of the oxygen vacancies causes The shaped region may extend in the channel length direction of the transistor. In this case, The electrical characteristics of a transistor include the shift of the threshold voltage and the ability to control on / off by the gate voltage. Therefore, a transistor with a very short channel length is formed. In this case, a conductive material that easily bonds to oxygen is used for the source electrode layer and the drain electrode layer. However, this is not necessarily desirable.

[0086] In such a case, the source electrode layer 140 and the drain electrode layer 150 are made of the above-mentioned materials. It is also possible to use a conductive material that is less likely to bond with oxygen than the conductive material. For example, materials containing tantalum nitride, titanium nitride, gold, platinum, palladium or ruthenium. Note that when the conductive material is in contact with the second oxide semiconductor layer 132, In this case, the source electrode layer 140 and the drain electrode layer 150 are formed of the conductive material and the above-mentioned oxygen. Alternatively, a conductive material that is easily bonded to the conductive material may be laminated.

[0087] The gate insulating film 160 may be formed of aluminum oxide, magnesium oxide, silicon oxide, or nitride oxide. Silicon oxide, silicon nitride, silicon oxide, gallium oxide, germanium oxide, Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and The insulating film 160 may be made of a material containing at least one type of tantalum oxide. It may also be a laminate of the above materials.

[0088] The gate electrode layer 170 may include any of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, and Ru. A conductive film of Ag, Ta, W, or the like can be used. The gate electrode layer may be a laminate of the above materials. It's fine.

[0089] An insulating layer 180 is formed on the gate insulating film 160 and the gate electrode layer 170. It is preferable that the insulating layer is made of aluminum oxide. The aluminum membrane is a barrier that does not allow impurities such as hydrogen and moisture, as well as oxygen, to pass through the membrane. Therefore, the aluminum oxide film is used during and after the transistor manufacturing process. Later, the oxides of impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors, Prevents contamination of the semiconductor layer 130 with oxygen, which is the main component of the oxide semiconductor layer 130. Preventing emission from the oxide semiconductor layer and preventing unnecessary emission of oxygen from the base insulating film 120 In addition, the acid contained in the aluminum oxide film is suitable for use as a protective film having the above structure. Alternatively, the element can be diffused into the oxide semiconductor layer.

[0090] In addition, it is preferable that an insulating layer 185 is formed on the insulating layer 180. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride , gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0091] Here, the insulating layer 185 preferably contains excess oxygen. The insulating layer containing excess oxygen is This refers to an insulating layer that can release oxygen by heat treatment, etc. For example, when the surface temperature is 1 The heating temperature is from 00°C to 700°C, preferably from 100°C to 500°C. Thermal desorption spectroscopy analysis showed that the amount of oxygen released was 1.0 x 10 19 at oms / cm 3 The oxygen released from the insulating layer is transferred to the gate insulating film 16. 0 and can be diffused into the channel formation region of the oxide semiconductor layer 130. Therefore, even if oxygen vacancies are formed in the channel formation region, oxygen can be compensated for. Therefore, stable electrical characteristics of the transistor can be obtained.

[0092] In order to increase the integration density of semiconductor devices, it is essential to miniaturize transistors. It is known that the electrical characteristics of transistors deteriorate as the channel width decreases. The reduction in on-current, which is a direct result of the reduction in size, is significant.

[0093] However, in the transistor according to one embodiment of the present invention, as described above, A third oxide semiconductor layer 133 is formed so as to cover a region of the oxide layer 132 where a channel is to be formed. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface between the channel forming layer and the gate insulating film, The field effect mobility of the transistor can be increased.

[0094] In addition, a transistor of one embodiment of the present invention has a channel width direction as shown in a cross-sectional view in FIG. The length of the upper surface of the second oxide semiconductor layer 132 in the channel width direction (W T ) is the oxide In a structure where the thickness of the semiconductor layer is reduced to the same extent, it is particularly important to improve electrical characteristics. This can be done.

[0095] For example, in a transistor as shown in FIG. T If is small as above, the game The electric field applied to the side surface of the second oxide semiconductor layer 132 from the second electrode layer 170 Since the second oxide semiconductor layer 132 is entirely covered with the second oxide semiconductor layer 132, the second oxide semiconductor layer 132 is also formed on its side surface and upper surface. A channel equivalent to the channel that is being

[0096] W T For transistors with small channel width, W T and the second oxide in the channel width direction The length of the side of the compound semiconductor layer 132 (W S1 , W S2 ) (W T +W S1 +W S2 ) is defined as The on-current flows through the transistor according to the channel width. T, W T When the capacitance is extremely small, a current flows through the entire second oxide semiconductor layer 132. do.

[0097] That is, W using one embodiment of the present invention T In transistors with small capacitance, carrier scattering is suppressed. This has the effect of increasing the channel width and increasing the capacitance, so it is more efficient than conventional transistors. The on-current can be increased.

[0098] In addition, W S1 =W S2 =W S When the on-state current of the transistor is increased, 0.3W S ≦W T ≦3W S (W T is 0.3W S More than 3W S (hereinafter) In addition, Or W T / W S = 0.5 to 1.5, and more preferably W T / W S =0.7 or more 1.3 or less. W T / W S If it is >3, the S value and off-state current may increase.

[0099] Therefore, the transistor of one embodiment of the present invention has a high performance when miniaturized. Even if the MOSFET is turned on, a sufficiently high on-current can be obtained.

[0100] In the transistor of one embodiment of the present invention, the second oxide semiconductor layer 132 is By forming the second oxide semiconductor layer on the conductor layer 131, it is possible to prevent the formation of an interface state. By making the layer 132 the middle layer of the three-layer structure, the influence of impurities from above and below can be eliminated. Therefore, the second oxide semiconductor layer 132 has a similar effect to the first oxide semiconductor layer. The above-described transistor is surrounded by the oxide semiconductor layer 131 and the third oxide semiconductor layer 133. In addition to improving the on-state current, it is possible to stabilize the threshold voltage and reduce the S value. Therefore, Icut (current when the gate voltage VG is 0V) can be reduced, and the semiconductor device This reduces the power consumption of the device. In addition, the threshold voltage of the transistor is stabilized. As a result, the long-term reliability of the semiconductor device can be improved.

[0101] In addition, the transistor of one embodiment of the present invention includes an oxide semiconductor layer 130 and a substrate as shown in FIG. A conductive film 172 may be provided between the gate electrode 110 and the gate electrode 110. The conductive film is used as a second gate electrode. By using it, it is possible to further increase the on-current and control the threshold voltage. In order to increase the gate current, for example, the gate electrode layer 170 and the conductive film 172 are set to the same potential, and In order to control the threshold voltage, In this case, a constant potential different from that of the gate electrode layer 170 may be supplied to the conductive film 172 .

[0102] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0103] (Embodiment 2) In this embodiment, the method for manufacturing the transistor 100 illustrated in FIG. This will be described with reference to FIG. 7 and FIG.

[0104] The substrate 110 may be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate can be used. Substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On In It is also possible to use a quartz crystal integrator substrate, on which semiconductor elements are mounted. The provided one may be used.

[0105] The base insulating film 120 is formed by depositing aluminum oxide by plasma CVD or sputtering. Magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide , yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxide insulating films such as tantalum oxide, silicon nitride, silicon nitride oxide, and aluminum nitride. The insulating film is made of a nitride such as niobium, aluminum oxide nitride, or a mixture of the above materials. The above-mentioned materials may be laminated, and the insulating layer may be formed of at least an oxide semiconductor. The upper layer in contact with the oxide semiconductor layer 130 is a source of oxygen for the oxide semiconductor layer 130. It is preferable to form the insulating film from a material containing

[0106] In addition, the insulating base film 120 is subjected to ion implantation, ion doping, plasma immersion ion implantation, etc. Oxygen may be added by using an on-implantation method or the like. This makes it easier to supply oxygen from the base insulating film 120 to the oxide semiconductor layer 130. It is possible.

[0107] Note that the surface of the substrate 110 is an insulator, and impurities are diffused into the oxide semiconductor layer 130 to be provided later. If there is no effect of diffusion, the base insulating film 120 may not be provided.

[0108] Next, a first oxide semiconductor film 3 which will become a first oxide semiconductor layer 131 is formed on the base insulating film 120. 31 and a second oxide semiconductor film 332 which will become the second oxide semiconductor layer 132 are formed by sputtering. The film is formed by the deposition method, the CVD method, the MBE method, the ALD method or the PLD method (see FIG. 7(A)). see).

[0109] Next, the first oxide semiconductor film 331 and the second oxide semiconductor film 332 are selectively etched. The first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are formed by etching. (See FIG. 7(B)). At this time, as shown in the figure, the base insulating film 120 is slightly over-etched. By excessively etching the base insulating film 120, the gate This makes it easier to cover the second oxide semiconductor layer 132 with the electrode. In the cross section in the channel width direction, The shape has a curvature toward the center.

[0110] Note that the first oxide semiconductor film 331 and the second oxide semiconductor film 332 are selectively etched. When performing the etching, a hard mask such as a metal film may be used in place of a photoresist. Alternatively, an organic resin may be formed on the metal film. For example, the metal film may be formed with a thickness of about 5 nm. A tungsten film or the like can be used.

[0111] In addition, the etching method may be a method for etching the first oxide semiconductor film 331 and the second oxide semiconductor film 332. It is preferable to use a dry etching method in which the difference in etching rate of the semiconductor film 332 is small. It is nice.

[0112] A continuous junction is formed in the stack of the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. In order to form the film, a multi-chamber deposition apparatus equipped with a load lock chamber (e.g. It is preferable to use a sputtering device to continuously laminate each layer without exposing them to the air. Each chamber in the sputtering device is designed to be free of water and other impurities that can affect oxide semiconductors. In order to remove as much as possible, high vacuum evacuation is performed using an adsorption type vacuum evacuation pump such as a cryopump. Ki (5 x 10 -7 Pa or more 1×10 -4 Pa or less), and the film formed It is preferable that the substrate can be heated to 100° C. or higher, preferably 500° C. or higher. A turbo molecular pump and a cold trap are combined to remove carbon components from the exhaust system into the chamber. It is preferable to prevent gas containing moisture and the like from flowing backward.

[0113] In order to obtain a high-purity intrinsic oxide semiconductor, not only is it necessary to evacuate the chamber to a high vacuum, but also to It is also necessary to increase the purity of the sputtering gas. , the dew point is -40°C or less, preferably -80°C or less, more preferably -100°C or less By using a highly purified gas, moisture or the like is prevented from being taken into the oxide semiconductor layer as much as possible. This can be prevented.

[0114] The first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and a thin film formed in a later step The third oxide semiconductor layer 133 can be formed using the material described in Embodiment 1. For example, the first oxide semiconductor layer 131 may have a composition of In:Ga:Zn=1:3:6, 1:3:4, In-Ga-Zn oxide with an atomic ratio of 1:3:3 or 1:3:2, the second oxide semiconductor The layer 132 is made of In-Ga with an atomic ratio of In:Ga:Zn=1:1:1 or 5:5:6. a-Zn oxide, and the third oxide semiconductor layer 133 has In:Ga:Zn=1:3:6, 1:3 Use In-Ga-Zn oxide with an atomic ratio of 1:4, 1:3:3 or 1:3:2. can be done.

[0115] In addition, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the third oxide semiconductor layer The oxide semiconductor that can be used as the semiconductor layer 133 contains at least indium (In It is preferable that the alloy contains In (In) or zinc (Zn). Alternatively, the alloy may contain both In and Zn. In addition, in order to reduce variation in electrical characteristics of a transistor using the oxide semiconductor, Therefore, it is preferable to include a stabilizer therewith.

[0116] The stabilizers are gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, with other stabilizers The lanthanides lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0117] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and In-Zn oxide. , Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In- Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, I n-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al -Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, I n-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn oxide In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al -Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn oxide It is possible.

[0118] In addition, for example, In-Ga-Zn oxide is a material with In, Ga, and Zn as the main components. It means that the oxide contains metal elements other than In, Ga, and Zn. In this specification, a film made of In-Ga-Zn oxide is referred to as an IGZO film. Also called.

[0119] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It denotes a metal element or elements. Also, In2SnO5(ZnO) n (n>0, and and n is an integer) may be used.

[0120] However, as described in detail in the first embodiment, the first oxide semiconductor layer 131 and the third The oxide semiconductor layer 133 is formed so as to have a smaller electron affinity than the second oxide semiconductor layer 132. Select the material accordingly.

[0121] Note that the oxide semiconductor layer is preferably formed by a sputtering method. For this purpose, RF sputtering, DC sputtering, AC sputtering, etc. can be used.

[0122] A first oxide semiconductor layer 131, a second oxide semiconductor layer 132, and a third oxide semiconductor layer 13 When In-Ga-Zn oxide is used as 3, the atomic ratio of In, Ga, and Zn is as follows: For example, In:Ga:Zn=1:1:1, In:Ga:Zn=2:2:1, In:Ga: Zn=3:1:2, In:Ga:Zn=5:5:6, In:Ga:Zn=1:3:2, I n:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4, In:Ga:Zn=1: 3:6, In:Ga:Zn=1:4:3, In:Ga:Zn=1:5:4, In:Ga: Zn=1:6:6, In:Ga:Zn=2:1:3, In:Ga:Zn=1:6:4, I n:Ga:Zn=1:9:6, In:Ga:Zn=1:1:4, In:Ga:Zn=1: The first oxide semiconductor layer 131 and the third oxide semiconductor layer 132 are made of either one of the materials having a ratio of 1:2. The electron affinity of the layer 133 may be smaller than that of the second oxide semiconductor layer 132. .

[0123] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with the atomic ratio of In:Ga:Zn=A:B:C (A+B+C = 1), a, b, and c are in the vicinity of the oxide composition (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 It means that the following condition is satisfied. For example, r can be set to 0.05. The same is true for other oxides.

[0124] The second oxide semiconductor layer 132 is a semiconductor layer including the first oxide semiconductor layer 131 and the third oxide semiconductor layer. The indium content is preferably higher than that of the semiconductor layer 133. The s orbitals of heavy metals contribute to carrier conduction, and by increasing the In content, Since more s orbitals overlap, oxides with a composition in which In is more abundant than Ga have the same composition as In and Ga. The mobility is higher compared to oxides with equal or lesser composition. Therefore, the second oxide By using an oxide with a high indium content for the semiconductor layer 132, a transistor with high mobility can be obtained. It is possible to realize the above-mentioned.

[0125] The structure of the oxide semiconductor film will be described below.

[0126] In this specification, "parallel" means that the angle between two straight lines is between -10° and 10°. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0127] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0128] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor). Talline Oxide Semiconductor film, polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0129] First, we will explain the CAAC-OS film.

[0130] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so large that it fits inside a cube with one side less than 100 nm. Therefore, CAAC The crystal parts contained in the -OS film are cubic with one side less than 10 nm, 5 nm, or 3 nm. This includes cases where the size is small enough to fit inside the body.

[0131] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed under a ferromagnetic microscope, clear boundaries between the crystals, i.e., crystal boundaries, were observed. It is not possible to confirm the grain boundary. It can be said that the AC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0132] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation ) It can be confirmed that the metal atoms are arranged in layers in the crystal part. Each layer has a surface on which the CAAC-OS film is formed (also called a surface on which the film is formed) or a top surface having irregularities. The shape of the CAAC-OS film reflects this, and the CAAC-OS film is aligned parallel to the surface on which the film is formed or the top surface.

[0133] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (planar TEM). When the metal atoms were observed, they were found to be arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal parts. stomach.

[0134] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It is clear that there are

[0135] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. This indicates that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is generally aligned on the surface on which the film is formed or on the upper surface. It can be seen that it is oriented in a substantially vertical direction.

[0136] On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This peak is This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane equivalent to the (110) plane is In contrast, in the case of the CAAC-OS film, the 2θ is set to 5 Even when the φ is fixed at around 6° and scanned, no clear peak appears.

[0137] From the above, it is considered that the a-axis and b-axis orientations are inconsistent between different crystal regions in the CAAC-OS film. The crystal is regular, but has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of metal atoms arranged in a plane is parallel to the ab plane of the crystal.

[0138] The crystalline portion is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned along the surface on which the CAAC-OS film is formed or along the surface on which the CAAC-OS film is formed. is oriented in a direction parallel to the normal vector of the top surface. When the shape of the CAAC-OS film is changed by etching, the c-axis of the crystal is changed to the shape of the CAAC-OS film. It may not be parallel to the normal vector of the top or bottom surface.

[0139] In addition, the degree of crystallinity in the CAAC-OS film may not be uniform. When the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The adjacent regions may have a higher degree of crystallinity than the regions adjacent the surface to be formed. When impurities are added to a C-OS film, the crystallinity of the region to which the impurities are added changes, resulting in partial In some cases, regions of differing crystallinity may be formed.

[0140] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferred that the spectrum exhibits a peak and does not exhibit a peak at 2θ of around 36°.

[0141] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The impurities include hydrogen, carbon, and The elements are other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that form the oxide semiconductor film, such as arsenic, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius of Since the molecular radius is large, when the cation is contained in the oxide semiconductor film, the The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement and cause a decrease in crystallinity. Objects can act as carrier traps or carrier generation sources.

[0142] The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a carrier source.

[0143] A material with a low impurity concentration and a low defect level density (few oxygen vacancies) is called a high-purity intrinsic or The term "substantially high-purity intrinsic" refers to a highly-purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has electrical characteristics in which the threshold voltage is negative ( Also called normally-on.) In addition, high purity intrinsic or substantially high purity The highly intrinsic oxide semiconductor film has few carrier traps. The transistors using the thin film have small fluctuations in electrical characteristics and are highly reliable. Note that it takes a certain time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time when the charge is released is long, and it may behave as if it is a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0144] In addition, the electrical characteristics of transistors using CAAC-OS films were improved by irradiation with visible light or ultraviolet light. The fluctuation is small.

[0145] Next, a microcrystalline oxide semiconductor film will be described.

[0146] In the microcrystalline oxide semiconductor film, crystal parts can be clearly seen in the TEM image. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or less. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 nm or less and 3 nm or less. The oxide semiconductor film having Al was formed by The nc-OS film is called a TE semiconductor film. In the M image, the grain boundaries may not be clearly visible.

[0147] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the peaks indicating the probe size were not detected in the nc-OS film. Electron beam diffraction (also called selected area electron beam diffraction) uses an electron beam with a diameter (for example, 50 nm or more). ) a halo-like diffraction pattern is observed. On the other hand, the probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm to 30 nm). When electron beam diffraction (also called nanobeam electron beam diffraction) is performed using an electron beam of In addition, when nanobeam electron diffraction is performed on the nc-OS film, a circular pattern is observed. In addition, a bright area (ring-shaped) may be observed for the nc-OS film. When nanobeam electron diffraction is performed, multiple spots are observed within the ring-shaped region. There is.

[0148] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher density of defect states than the CAAC-OS film.

[0149] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a CA The AC-OS film may be a laminate film having two or more kinds of films.

[0150] The CAAC-OS film can be formed, for example, by using a polycrystalline oxide semiconductor sputtering target. The film can be formed by sputtering. Ions collide with the sputtering target. When the sputtering target is heated, the crystal region in the sputtering target cleaves from the ab plane and is parallel to the ab plane. The particles may peel off as flat or pellet-like sputtered particles with a smooth surface. In this case, the plate-shaped or pellet-shaped sputtered particles are charged and do not agglomerate in the plasma. Therefore, the crystal state can be maintained while the metal oxide reaches the substrate and a CAAC-OS film can be formed.

[0151] The second oxide semiconductor layer 132 is an In-M-Zn oxide layer (wherein M is Ga, Y, Zr, La, In the case of Ce or Nd), the sputtering agent used to deposit the second oxide semiconductor layer 132 is In the target for the quartz crystal, the atomic ratio of the metal elements is In:M:Zn=a1:b1:c1. And 、 a1 / b1 is 1 / 3 or more and 6 or less, or even 1 or more and 6 or less, and c1 / b1 is , c1 / b1 is preferably 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. When the ratio is set to 1 or more and 6 or less, a CAAC-OS film is formed as the second oxide semiconductor layer 132. A typical example of the atomic ratio of the metal elements in the target is In:M:Zn= Examples include 1:1:1, In:M:Zn=3:1:2, In:M:Zn=5:5:6, etc.

[0152] When the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133 are In-M-Zn oxide layers (M is Ga, Y, Zr, La, Ce, or Nd), for the sputtering target used to form the first oxide semiconductor layer 1 31 and the third oxide semiconductor layer 133, when the atomic ratio of the metal elements is In:M:Zn = a2:b2:c2 then 、 a2 / b2 < a1 / b1, and c2 / b2 is 1 / 3 or more and 6 or less, further preferably 1 or more and 6 or less is preferred. By setting c2 / b2 to 1 or more and 6 or less, a CAAC-OS film is likely to be formed as the first oxide semiconductor layer 131 and the third oxide semiconductor layer 133. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:2, I n:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6 etc.

[0153] After the formation of the second oxide semiconductor layer 132, the first heat treatment may be performed. The first heat treatment is performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. Also, the atmosphere of the first heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas to supplement the desorbed oxygen after heat treatment in an inert gas atmosphere. By the first heat treatment the crystallinity of the second oxide semiconductor layer 132 can be enhanced, and furthermore, impurities such as hydrogen and water can be removed from the underlying insulating film 120 and the first oxide semiconductor layer 131. Note that the first heating step may be performed before the etching for forming the second oxide semiconductor layer 132.

[0154] ​Next, a source electrode layer is formed on the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. A first conductive film is formed to become the drain electrode layer 140 and the drain electrode layer 150. The material is Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy material whose main component is these. For example, a titanium film of 100 nm is formed by sputtering or the like. Alternatively, the tungsten film may be formed by a CVD method.

[0155] Next, the first conductive film is etched so as to be divided on the second oxide semiconductor layer 132. A source electrode layer 140 and a drain electrode layer 150 are formed (see FIG. 7(C)). However, due to excessive etching of the first conductive film, a part of the second oxide semiconductor layer 132 is etched. It may also be in a chipped shape.

[0156] Next, the first oxide semiconductor layer 131, the second oxide semiconductor layer 132, and the source electrode layer 140 On the drain electrode layer 150, a third oxide semiconductor layer to be the third oxide semiconductor layer 133 is formed. At this time, the second oxide semiconductor layer of the third oxide semiconductor film 333 is formed. The vicinity of the interface with 132 is a microcrystalline layer, and the area above the microcrystalline layer is a crystal layer oriented along the c-axis.

[0157] Note that a second heat treatment may be performed after the third oxide semiconductor film 333 is formed. The heat treatment can be carried out under the same conditions as the first heat treatment. Impurities such as hydrogen and water can be removed from the third oxide semiconductor film 333. Hydrogen, water, and the like are further released from the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. Impurities can be removed.

[0158] Next, an insulating film 360 which is to become the gate insulating film 160 is formed on the third oxide semiconductor film 333. The insulating film 360 may be made of aluminum oxide, magnesium oxide, silicon oxide, or oxynitride. Silicon, silicon oxide nitride, silicon nitride, gallium oxide, germanium oxide, indium oxide tritium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxide The insulating film 360 may be a laminate of the above materials. The insulating film 360 may be formed by a method such as a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method. It can be formed using the above.

[0159] Next, a second conductive film 370 which will become the gate electrode layer 170 is formed on the insulating film 360 (FIG. 8). The second conductive film 370 may be made of Al, Ti, Cr, Co, Ni, Cu, Y, or the like. , Zr, Mo, Ru, Ag, Ta, W, or alloy materials containing these as main components. The second conductive film 370 can be formed by a sputtering method, a CVD method, or the like. In addition, the second conductive film 370 may be a conductive film containing nitrogen. Alternatively, a laminate of a conductive film containing a material and a conductive film containing nitrogen may be used.

[0160] Next, the second conductive film 37 is formed using a resist mask for forming the gate electrode layer 170. 0 is selectively etched to form a gate electrode layer 170.

[0161] Next, the insulating film 360 is selected using the resist mask or the gate electrode layer 170 as a mask. Selective etching is performed to form the gate insulating film 160 .

[0162] Next, the third oxide semiconductor is formed using the resist mask or the gate electrode layer 170 as a mask. The oxide semiconductor film 333 is etched to form the third oxide semiconductor layer 133 (see FIG. 8B). .

[0163] The second conductive film 370, the insulating film 360, and the third oxide semiconductor film 333 are etched. The etching may be performed for each layer or continuously. Either dry etching or wet etching may be used, and an appropriate etching method is selected for each layer. may be selected.

[0164] Next, an insulating layer is formed on the source electrode layer 140, the drain electrode layer 150, and the gate electrode layer 170. The insulating layer 180 and the insulating layer 185 are formed (see FIG. 8(C)). The insulating film 185 can be formed using the same material and method as the base insulating film 120. It is particularly preferred to use aluminum oxide for the insulating layer 180 .

[0165] In addition, the insulating layer 180 is subjected to ion implantation, ion doping, plasma immersion ion implantation, etc. Oxygen may be added by implantation or the like. This makes it easier to supply oxygen from the insulating layer 180 to the oxide semiconductor layer 130. Cut.

[0166] Next, a third heat treatment may be performed under the same conditions as the first heat treatment. The third heat treatment can be performed by the following steps. Excess oxygen is easily released from the insulating layer 180, and oxygen vacancies in the oxide semiconductor layer 130 are reduced. It can be reduced.

[0167] Through the above steps, the transistor 100 illustrated in FIG. 1 can be manufactured.

[0168] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0169] (Embodiment 3) In this embodiment, a transistor according to one embodiment of the present invention is used, and a transistor is A semiconductor device (memory device) that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. An example of the device will be described with reference to the drawings.

[0170] FIG. 9A shows a cross-sectional view of the semiconductor device, and FIG. 9B shows a circuit diagram of the semiconductor device.

[0171] The semiconductor device shown in FIG. 9(A) and FIG. 9(B) has a transistor using a first semiconductor material in the lower part. A transistor 3300 using a second semiconductor material on the top, and The transistor 3300 includes a capacitor 3400. The transistor 100 described above can be used.

[0172] The capacitor 3400 has one electrode connected to the source electrode layer or the drain electrode layer of the transistor 3300. The other electrode is the gate electrode layer of the transistor 3300, and the dielectric is the transistor The same material as the gate insulating film 160 and the third oxide semiconductor layer 133 of the By using this structure, the transistor 3300 can be formed at the same time.

[0173] Here, the first semiconductor material and the second semiconductor material have different energy gaps. For example, it is preferable that the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon). and the second semiconductor material may be the oxide semiconductor described in Embodiment 1. Transistors using materials other than oxide semiconductors can easily operate at high speed. In addition, transistors using oxide semiconductors have electrical characteristics of low off-state current, which allows them to be charged for a long time. Allows retention.

[0174] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. In order to hold the resistance, a transistor including an oxide semiconductor as described in Embodiment 1 is used. Others include specific configurations of semiconductor devices, such as materials used in the semiconductor device and the structure of the semiconductor device. need not be limited to those shown here.

[0175] The transistor 3200 in FIG. 9A is made of a semiconductor material (e.g., crystalline silicon, etc. A channel formation region is provided on a substrate 3000 including the An impurity region, an intermetallic compound region in contact with the impurity region, and a channel forming region and a gate electrode layer provided on the gate insulating film. In addition, in the drawings, the source electrode layer and the drain electrode layer may not be explicitly shown. For convenience, this state may be referred to as a transistor. In order to explain the connection relationship of the transistor, the source electrode layer including the source region and drain region is That is, in this specification, the term “source electrode layer” is sometimes referred to as a “drain electrode layer.” The description may include a source region.

[0176] An element isolation insulating layer 3100 is provided on a substrate 3000 so as to surround a transistor 3200. An insulating layer 3150 is provided to cover the transistor 3200. The element isolation insulating layer 3100 is formed by LOCOS (Local Oxidation of Silicon licon) and STI (Shallow Trench Isolation) It can be formed by using element isolation technology.

[0177] For example, when a crystalline silicon substrate is used, the transistor 3200 can operate at high speed. Therefore, by using the transistor as a readout transistor, The readout can be performed at high speed.

[0178] A transistor 3300 is provided on the insulating layer 3150, and its source electrode layer or drain The wiring electrically connected to the gate electrode layer serves as one electrode of the capacitor 3400. In addition, the wiring is electrically connected to the gate electrode layer of the transistor 3200.

[0179] The transistor 3300 illustrated in FIG. 9A has a top surface where a channel is formed in an oxide semiconductor layer. The transistor 3300 is a p-gate transistor. Since the off-state current of the transistor 3300 is small, By using the REFLECTION function, it is possible to retain memory contents for a long period of time. A semiconductor memory device that does not require a refresh operation or requires a refresh operation very infrequently. Since it is possible to provide a single device, power consumption can be reduced sufficiently.

[0180] In addition, an electrode 3250 is provided so as to overlap with the transistor 3300 with an insulating layer 3150 interposed therebetween. By applying an appropriate potential to this electrode as the second gate electrode, The threshold voltage of the transistor 3300 can be controlled. The long-term reliability can be improved. By operating the electrode 325 at the same potential as the electrode 325, the on-current can be increased. It is also possible to configure the number 0 not to be set.

[0181] As shown in FIG. 9A, a transistor 330 is formed on a substrate on which a transistor 3200 is formed. 0 and the capacitor element 3400 can be formed, so that the degree of integration of the semiconductor device can be increased. This can be done.

[0182] An example of a circuit configuration corresponding to FIG. 9(A) is shown in FIG. 9(B).

[0183] In FIG. 9B, a first wiring 3001 is electrically connected to a source electrode layer of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode layer of the transistor 3200. The third wiring 3003 is connected to the source electrode layer of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrode layers of the transistor 330. 0. The gate electrode layer of the transistor 3200 is electrically connected to the The other of the source electrode layer and the drain electrode layer of the transistor 3300 is a capacitor. The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. The element corresponding to the electrode 3250 is not shown in the figure. not present.

[0184] In the semiconductor device shown in FIG. 9B, the potential of the gate electrode layer of the transistor 3200 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0185] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode layer of the transistor 3200 and and the capacitor 3400. That is, the gate electrode layer of the transistor 3200 A certain charge is applied (write). Here, two different potential levels are applied. Either a low-level charge or a high-level charge is given. After that, the potential of the fourth wiring 3004 is set to a value that turns off the transistor 3300. By applying a potential to the transistor 3300 to turn it off, the transistor 3200 The charge applied to the gate electrode layer is retained (retention).

[0186] Since the off-state current of the transistor 3300 is extremely small, the gate voltage of the transistor 3200 The charge in the pole layer is retained for a long period of time.

[0187] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, the transistor Depending on the amount of charge held in the gate electrode layer of the capacitor 3200, the second wiring 3002 has different potentials. In general, if the transistor 3200 is an n-channel type, then the transistor 320 The apparent threshold voltage V when a high-level charge is applied to the gate electrode layer of th_H In the figure, a low-level charge is applied to the gate electrode layer of the transistor 3200. The apparent threshold voltage V th_L This is because the apparent The low voltage is the voltage required to turn on the transistor 3200. Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential V0 between For example, in writing, a high-level charge is applied. In this case, the potential of the fifth wiring 3005 is V0 (>V th_H ) Then, Trans If a low level charge is applied, the fifth The potential of the wiring 3005 is V0( <V th_L ), transistor 3200 is "off" Therefore, by determining the potential of the second wiring 3002, The information stored in the memory can be read out.

[0188] When memory cells are arranged in an array, only the information in a desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 3200 is in the "off state" regardless of th_ H A smaller potential may be applied to the fifth wiring 3005. Regardless of the potential, transistor 3200 is in the "on" state, i.e., V th_L A larger potential may be applied to the fifth wiring 3005 .

[0189] In the semiconductor device described in this embodiment, an off-state current is low when an oxide semiconductor is used for a channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is possible. This allows the frequency of operation to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is preferable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0190] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem with degradation of the capacitance. For example, unlike conventional non-volatile memory, the floating gate Since there is no need to inject electrons into the floating gate or extract electrons from the floating gate, Problems such as deterioration of the gate insulating film are unlikely to occur. In this device, there is no limit to the number of times that can be rewritten, which is an issue with conventional non-volatile memory, and it is reliable. Furthermore, the on and off states of transistors allow the writing and reading of information to be performed Since the data is written into the memory, high speed operation can be easily achieved.

[0191] As described above, a semiconductor device that realizes miniaturization and high integration and has excellent electrical characteristics is developed. An apparatus can be provided.

[0192] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0193] (Embodiment 4) In this embodiment, a transistor according to one embodiment of the present invention is used, and a transistor is A semiconductor device that can retain memory contents even under certain conditions and has no limit on the number of times it can be written to. A semiconductor device having a structure different from that shown in the third embodiment will be described.

[0194] FIG. 10 is an example of a circuit configuration of a semiconductor device. In the semiconductor device, the first wiring 4 The source electrode layer of the transistor 4300 is electrically connected to the second wiring 460. 0 and the gate electrode layer of the transistor 4300 are electrically connected to each other, and the transistor 4300 The drain electrode layer and the first terminal of the capacitor 4400 are electrically connected to each other. The transistor 4300 included in the semiconductor device may be the transistor described in Embodiment 1. The first wiring 4500 is a bit line, and the second wiring Line 4600 may function as a word line.

[0195] The semiconductor device (memory cell 4250) includes a transistor 3300 and a capacitor 3301 shown in FIG. The connection configuration can be the same as that of the element 3400. Therefore, the capacitor element 4400 has the following configuration: In the manufacturing process of the transistor 4300, similar to the capacitor 3400 described in Embodiment 3, The two can be simultaneously produced.

[0196] Next, data is written and held in the semiconductor device (memory cell 4250) shown in FIG. The following describes how to do this.

[0197] First, a potential that turns on the transistor 4300 is supplied to the second wiring 4600. The transistor 4300 is turned on. As a result, the potential of the first wiring 4500 is The potential of the second wiring 4600 is then applied to the first terminal of the first wiring 4400 (write). is set as a potential at which the transistor 4300 is turned off, By setting the potential at the first terminal of the capacitor 4400 in this state, the potential at the first terminal of the capacitor 4400 is held (retained).

[0198] The transistor 4300 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 4300 is turned off, the capacitor 4400 The potential of the first terminal (or the charge stored in the capacitor 4400) is kept constant for an extremely long time. It is possible to hold the signal for a long time.

[0199] Next, reading of information will be described. When the transistor 4300 is turned on, The first wiring 4500 in the free state and the capacitor element 4400 are electrically connected to each other. Charge is redistributed between the capacitors 4400. As a result, the potential of the first wiring 4500 changes. The change in the potential of the first wiring 4500 is proportional to the change in the potential of the first terminal of the capacitor 4400 ( Alternatively, it takes a different value depending on the charge stored in the capacitor element 4400.

[0200] For example, the potential of the first terminal of the capacitance element 4400 is V, the capacitance of the capacitance element 4400 is C, The capacitance component of the first wiring 4500 before the charge is redistributed is CB. If the potential is VB0, the potential of the first wiring 4500 after the charge is redistributed is (CB× VB0+C×V) / (CB+C). Therefore, the state of memory cell 4250 is Assume that the potential of the first terminal of the capacitance element 4400 has two states, V1 and V0 (V1>V0). Then, the potential of the first wiring 4500 when the potential V1 is held is (=(CB×VB0+C ×V1) / (CB+C) is the potential of the first wiring 4500 when the potential V0 is maintained. It can be seen that it is higher than (=(CB×VB0+C×V0) / (CB+C)).

[0201] Then, the potential of the first wiring 4500 is compared with a predetermined potential, thereby reading out information. can be done.

[0202] In this manner, the semiconductor device (memory cell 4250) shown in FIG. Since the off-state current of the capacitor 4400 is extremely small, the charge stored in the capacitor 4400 is That is, no refresh operation is required, or The frequency of refresh operations can be reduced significantly, significantly reducing power consumption. In addition, even if there is no power supply, the contents stored in the memory can be preserved for a long period of time. It is possible to retain it.

[0203] The memory cell 4250 shown in FIG. 10 includes a drive circuit for driving the memory cell 4250. It is preferable to stack a substrate on which the memory cell 4250 and the driver circuit are formed. In this way, the semiconductor device can be miniaturized. The number of driving circuits is not limited.

[0204] The transistors included in the driver circuit are made of a different semiconductor material from the transistor 4300. For example, silicon, germanium, silicon germanium, silicon carbide, It is preferable to use a single crystal semiconductor. A transistor using such a semiconductor material is a transistor using an oxide semiconductor. This allows for faster operation than the conventional MOS transistor, and is suitable for use in configuring a drive circuit for the memory cell 4250. is doing.

[0205] As described above, a semiconductor device that realizes miniaturization and high integration and has excellent electrical characteristics is developed. An apparatus can be provided.

[0206] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0207] (Embodiment 5) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in FIG. This will be described with reference to the following.

[0208] FIG. 11(A) shows a circuit diagram of the semiconductor device, and FIGS. 11(C) and 11(D) show cross-sectional views of the semiconductor device. 11(C) and (D) show the channel of transistor 2100 on the left side, respectively. A cross-sectional view in the longitudinal direction is shown on the right, and a cross-sectional view in the channel width direction is shown on the right. To clarify that the transistor uses an oxide semiconductor, the word "OS" is added. It is attached.

[0209] The semiconductor device shown in FIG. 11(C) and (D) has a transistor using a first semiconductor material in the lower part. The second semiconductor material is used as the second semiconductor material. In this embodiment, the transistor 2100 using the second semiconductor material is the transistor 2100 shown in FIG. An example in which the transistor 100 is applied will be described.

[0210] Here, the first semiconductor material and the second semiconductor material have different energy gaps. For example, it is preferable that the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon). Con, germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. ) and the second semiconductor material can be the oxide semiconductor described in Embodiment 1. Transistors using single crystal silicon or other materials other than oxide semiconductors can operate at high speed. On the other hand, a transistor including an oxide semiconductor has a low off-state current.

[0211] Here, the transistor 2200 will be described as a p-channel transistor. However, it goes without saying that different circuits can be constructed using n-channel transistors. In addition to using a transistor including an oxide semiconductor as described in Embodiment 1, The specific configuration of a semiconductor device, such as the materials used in the semiconductor device and the structure of the semiconductor device, is described here. It is not necessary to be limited to those shown in .

[0212] The configurations shown in Figures 11(A), (C), and (D) are p-channel transistors and n-channel A CMO is a type of transistor that is connected in series and has its gates connected together. 1 shows an example of the configuration of an S circuit.

[0213] The on-state current of a transistor including an oxide semiconductor according to one embodiment of the present invention is increased. This enables the circuit to operate at high speed.

[0214] In the structure shown in FIG. 11C, a transistor 2200 is provided with an insulating layer 2201 therebetween. A transistor 2100 is provided. Also, a transistor 2200 and a transistor 2 A plurality of wirings 2202 are provided between the electrodes 100. In addition, a plurality of wirings 2202 are embedded in various insulating layers. The wiring and electrodes provided on the upper and lower parts are electrically connected by a number of plugs 2203. In addition, an insulating layer 2204 covering the transistor 2100 and a The wiring 2205 and the wiring 2202 formed by processing the same conductive film as the pair of electrodes of the transistor. 206 and are provided.

[0215] In this way, by stacking two transistors, the area occupied by the circuit is reduced, This allows multiple circuits to be arranged at a higher density.

[0216] In FIG. 11C, one of the source and drain of the transistor 2100 and the transistor Either the source or drain of the capacitor 2200 is electrically connected to the The gate of the transistor 2100 is connected to a wiring 2205 and a wiring 2206. 06, the gate of the transistor 2200 is connected via the plug 2203 and the wiring 2202, etc. The connector is electrically connected to the

[0217] In the structure shown in FIG. 11D, a plug 2203 is formed in the gate insulating film of the transistor 2100. An opening for embedding is provided, and the gate of the transistor 2100 and the plug 2203 are This structure makes it easy to integrate circuits, In addition, the number and length of wiring and plugs to be passed through can be reduced compared to the configuration shown in FIG. This allows the circuit to operate at higher speeds.

[0218] Here, in the configurations shown in FIGS. 11C and 11D, the transistor 2100 and the transistor By changing the connection configuration of the electrodes of the capacitor 2200, various circuits can be configured. For example, as shown in FIG. 11(B), the source and drain of each transistor are connected. By connecting the two circuits, it can function as an analog switch. Cut.

[0219] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0220] (Embodiment 6) In this embodiment, an image sensor for reading information on an object using a transistor according to one embodiment of the present invention will be described. A semiconductor device having a range sensor function will now be described.

[0221] FIG. 12 shows an example of an equivalent circuit of a semiconductor device having an image sensor function.

[0222] The photodiode 610 has one electrode connected to a photodiode reset signal line 661 and the other One electrode of the transistor 640 is electrically connected to the gate of the transistor 640. In the example shown in FIG. 1, one of the source and drain is connected to the photosensor reference signal line 672, and the other of the source and drain is connected to the photosensor reference signal line 673. The other input is electrically connected to one of the source and drain of the transistor 650. The transistor 650 has a gate connected to a gate signal line 662 and a source or drain connected to a The photo sensor output signal line 671 is electrically connected to the photo sensor output signal line 672 .

[0223] The photodiode 610 includes, for example, a semiconductor layer having a p-type conductivity and a high-resistance (i A pin-type semiconductor layer is laminated with a semiconductor layer having a n-type conductivity. A photodiode may be applied.

[0224] By detecting the light incident on the photodiode 610, information on the detected object is read. When reading the information of the detected object, a light source such as a backlight is used. It is also possible.

[0225] The transistors 640 and 650 are formed by using the oxidizer described in the first embodiment. A transistor 100 having a channel formed in a solid semiconductor can be used. It is clearly understood that the transistor 640 and the transistor 650 include an oxide semiconductor. To make it easier to understand, the symbols for the transistors are marked with "OS." Transistor 640 and The transistor 650 has a high on-state current and is electrically stable with reduced fluctuation in electrical characteristics. By including the transistor, the image sensor function shown in FIG. As a result, it is possible to provide a highly reliable semiconductor device having such a structure.

[0226] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0227] (Embodiment 7) The transistors described in the first and second embodiments are applicable to display devices, memory devices, CPUs, DSPs, etc. (Digital Signal Processor), Custom LSI, PLD(P programmable logic device), RF-ID (Radio Frequency Identification io Frequency Identification), inverter, image sensor In this embodiment, the semiconductor device can be applied to a semiconductor device such as a semiconductor device having a An example of such an electronic device will be described.

[0228] Examples of electronic devices having the semiconductor device include televisions, display devices such as monitors, lighting devices, and photovoltaic devices. Personal computers, word processors, image reproduction devices, portable audio players Radios, tape recorders, stereos, telephones, cordless telephones, mobile phones, car phones , transceivers, radios, game consoles, calculators, personal digital assistants, electronic organizers, electronic books, electronic translations Translators, voice input devices, video cameras, digital still cameras, electric shavers, IC chips , microwave ovens and other high-frequency heating devices, electric rice cookers, electric washing machines, vacuum cleaners, air conditioners air conditioning equipment such as hair dryers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators refrigerators, electric freezers, electric refrigerator-freezers, freezers for DNA storage, radiation measuring devices, dialysis machines, X-ray Medical equipment such as diagnostic equipment, etc. Smoke detectors, heat detectors, gas alarms, Examples of such devices include alarm devices such as burglar alarm devices. In addition, emergency exit lights, traffic lights, conveyor belts, Examples of industrial equipment include elevators, escalators, industrial robots, and power storage systems. In addition, the vehicle is propelled by an engine using fuel or an electric motor using power from a non-aqueous secondary battery. The electronic device also includes moving objects that move around. , electric vehicles (EV), hybrid vehicles (HEV) that combine internal combustion engines and electric motors, Hybrid electric vehicles (PHEVs), tracked vehicles that use these tires and wheels as tracks, Motorized bicycles including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, Small or large ships, submarines, helicopters, aircraft, rockets, satellites, space probes Examples of electronic devices include spacecraft, planetary probes, and spacecraft. Some specific examples of these electronic devices are shown in Figure 13.

[0229] A television set 8000 shown in FIG. 13A includes a housing 8001 and a display unit 8002. It displays images on a display unit 8002 and outputs audio from a speaker unit 8003. The memory device including the transistor of one embodiment of the present invention can be used in the display unit 80. It is possible to use the device in a driver circuit for operating the .02.

[0230] The television device 8000 also includes a CPU 8004 for performing information communication and a memory. The CPU 8004 or the memory may include a transistor according to one embodiment of the present invention. A CPU and a storage device can be used.

[0231] The alarm device 8100 shown in FIG. 13(A) is a residential fire alarm, and includes a smoke or heat detection unit. 8102 and an example of an electronic device using a microcomputer 8101. The computer 8101 includes a memory device having a transistor according to one embodiment of the present invention and a CPU. .

[0232] In addition, an air conditioner having an indoor unit 8200 and an outdoor unit 8204 shown in FIG. The sensor may be an electronic device including a transistor, a memory device, a CPU, or the like described in the above embodiment. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CP In FIG. 13A, the CPU 8203 is In the illustrated example, the CPU 8203 is provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. The transistor according to one embodiment of the present invention may be used in a CPU of an air conditioner. This can reduce power consumption.

[0233] In addition, the electric refrigerator-freezer 8300 shown in FIG. 13A is a transistor shown in the above embodiment. Specifically, an electric freezer / refrigerator is an example of an electronic device that includes a processor, a memory device, or a CPU. The storage 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, and a CPU 830. In FIG. 13A, a CPU 8304 is provided inside a housing 8301. The transistor of one embodiment of the present invention is used for a CPU 8304 of an electric refrigerator-freezer 8300. This can help save power.

[0234] 13B and 13C show an example of an electric vehicle, which is an example of an electronic device. The power supply 9701 is supplied to the circuit 97 The output is adjusted by the circuit 9702 and supplied to the driver 9703. The present invention is controlled by a processing unit 9704 having a ROM, RAM, CPU, etc. By using the transistor of one embodiment in the CPU of the electric vehicle 9700, power saving can be achieved. can be.

[0235] The driving device 9703 is a DC motor or an AC motor alone, or a motor and an internal combustion engine, The processing device 9704 is configured by combining the above. Information on driving (acceleration, deceleration, stopping, etc.) and information on driving (uphill and downhill slopes, etc., Based on input information (load information, etc.), the circuit 9702 outputs a control signal. The electric energy supplied from the secondary battery 9701 is controlled by a control signal from the processor 9704. The output of the drive unit 9703 is controlled by adjusting the speed. Although not shown, it also has a built-in inverter that converts direct current to alternating current.

[0236] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible. EXAMPLES

[0237] In this example, the stacked state of the oxide semiconductor layers described in Embodiment 1 was observed. The details will be explained below.

[0238] FIG. 14 is a cross-sectional view showing the structure of a sample used in this example. 10, a base insulating film 420, a first oxide semiconductor layer 431 and a second oxide semiconductor layer 432 on the base insulating film a stack of the oxide semiconductor layer 432 and a third oxide semiconductor layer 433 formed thereon; The first oxide semiconductor layer 431 and the second oxide semiconductor layer 432 are The third oxide semiconductor layer 433 is the same as the first oxide semiconductor layer 1 described in Embodiment 1. 31, the second oxide semiconductor layer 132, and the third oxide semiconductor layer 133, do.

[0239] Next, a method for producing the sample shown in FIG. 14 will be described.

[0240] First, a silicon wafer is used as the substrate 410, and the silicon wafer is thermally oxidized. Thus, a silicon oxide film serving as the insulating base film 420 was formed.

[0241] Next, a first In-type semiconductor layer having an atomic ratio of In:Ga:Zn=1:3:4 was formed on the insulating base film 420. Ga-Zn oxide film, In:Ga:Zn=1:1:1 (atomic ratio) second In-Ga- The first In-Ga-Zn oxide film was then deposited on the first In-Ga-Zn oxide film by sputtering. The thicknesses of the first In-Ga-Zn oxide film and the second In-Ga-Zn oxide film were 20 nm and 15 nm, respectively.

[0242] The deposition conditions for the first In-Ga-Zn oxide film were In:Ga:Zn=1:3:4 (atomic number (comparison) φ8 inch In-Ga-Zn oxide target, sputtering gas argon: Oxygen = 2:1 (flow ratio), deposition pressure 0.4 Pa, input power 0.5 kW (DC), The get-to-substrate distance was 60 mm, and the substrate temperature was 200°C.

[0243] The deposition conditions for the second In-Ga-Zn oxide film were In:Ga:Zn=1:1:1 ( The target was an In-Ga-Zn oxide with a diameter of 8 inches and a sputtering gas of Al. Gas:oxygen = 2:1 (flow ratio), deposition pressure 0.4 Pa, input power 0.5 kW (DC) The target-substrate distance was 60 mm, and the substrate temperature was 300°C.

[0244] Next, the first In-Ga-Zn oxide film and the second In-Ga-Zn oxide film were heated at 450 Heat treatment at 450°C for 1 hour in a nitrogen atmosphere, then heat treatment at 450°C for 1 hour in an oxygen atmosphere. was carried out.

[0245] Next, a 5 nm tungsten film and a 20 nm ZnO film were deposited on the second In-Ga-Zn oxide film. A photoresist was formed on the substrate, and a resist mask was formed by electron beam exposure.

[0246] Then, the organic resin and the tungsten film are selectively removed using the resist mask. The etching method was a two-step process using an inductively coupled dry etching device. Etching was carried out.

[0247] For the first etching step, the etching gas was 100% carbon tetrafluoride and the pressure was 0.67 Pa, input power 2000W, bias power 50W, substrate temperature -10℃, etching The etching time was 12 seconds. The second etching step was performed with four fl oz of etching gas. Carbon fluoride: oxygen = 3:2 (flow ratio), pressure 2.0 Pa, input power 1000 W, substrate The conditions used were a bias power of 25 W, a substrate temperature of -10°C, and an etching time of 8 seconds.

[0248] Next, the first In-Ga-Zn oxide film is formed using the organic resin and tungsten film as a mask. and selectively etching the second In-Ga-Zn oxide film to form the first oxide semiconductor layer. A stack of a first oxide semiconductor layer 431 and a second oxide semiconductor layer 432 was formed. A dry etching apparatus was used, and the etching gas was methane:argon = 1:2 (flow ratio). ), pressure 1.0 Pa, input power 600 W, substrate bias power 100 W, substrate temperature The etching conditions were 70° C. and the etching time was 82 seconds.

[0249] Next, the organic resin and the tungsten film were etched. A dry etching apparatus was used, and the etching gas was carbon tetrafluoride: oxygen = 3:2 (flow rate Ratio), pressure 2.0 Pa, input power 1000 W, substrate bias power 25 W, substrate temperature The etching temperature was -10°C and the etching time was 6 seconds.

[0250] Then, 10 A third oxide semiconductor layer 433 with a thickness of 1 nm was formed by a sputtering method.

[0251] The third oxide semiconductor layer 433 was formed under the following conditions: In:Ga:Zn=1:3:4 (atomic ratio). The target was an In-Ga-Zn oxide of φ8 inches, and the sputtering gas was argon:oxygen. = 2:1 (flow ratio), deposition pressure 0.4 Pa, input power 0.5 kW (DC), target The substrate distance was 60 mm and the substrate temperature was 200°C.

[0252] A cross-sectional TEM photograph of the region surrounded by the dotted line in FIG. 14 is shown in FIG. 15(A). No crystal lattice was observed in a region of several nm from the base insulating film 420 side of the compound semiconductor layer 431. However, lattice stripes were observed in the upper part of the second oxide semiconductor layer 432. The lattice fringes were confirmed to be similar to those of the first oxide semiconductor layer 431. Most of the second oxide semiconductor layer 431 and the entire second oxide semiconductor layer 432 are crystalline layers, and the orientation of the lattice stripes is From this, it was found that the CAAC-OS film had its c-axis oriented perpendicular to the deposition surface. Ta.

[0253] In addition, the third oxide semiconductor layer 433 may be formed by removing the first oxide semiconductor layer 431 or the second oxide semiconductor layer 432. No crystal lattice is observed in the region of several nm on the conductor layer 432 side, but the lattice is not observed in the upper part of the region. Stripes were observed. That is, the third oxide semiconductor layer 433 was divided into a microcrystalline layer 433a and a crystalline layer 433b. It was confirmed to be 33b.

[0254] The lattice fringes observed in the crystal layer 433b are due to the upper portion of the second oxide semiconductor layer 432 and the upper portion of the first oxide semiconductor layer 432. The orientation is different at the side of the oxide semiconductor layer 431 or the second oxide semiconductor layer 432. It was found that the CAAC-OS film had its c-axis oriented perpendicular to the deposition surface.

[0255] Also, as is clear from FIG. 15(B), which is an enlarged view of the dotted frame in FIG. 15(A), The oxide semiconductor layer 432 is provided on a curved region at an end portion thereof with a microcrystalline layer 433a interposed therebetween. Lattice fringes of the crystal layer 433b with its c-axis oriented perpendicular to the curved surface were observed.

[0256] The results of this example show that the stacked structure of oxide semiconductor layers according to one embodiment of the present invention can be fabricated. It was confirmed that this is possible.

[0257] This embodiment can be appropriately combined with the embodiment modes shown in this specification. [Explanation of symbols]

[0258] 100 Transistors 110 Substrate 120 Undercoat insulating film 130 Oxide semiconductor layer 131 First oxide semiconductor layer 132 Second oxide semiconductor layer 132b area 133 Third oxide semiconductor layer 133a Microcrystalline layer 133b Crystal layer 135 Boundary 140 Source electrode layer 150 Drain electrode layer 160 Gate insulating film 170 Gate electrode layer 172 Conductive Film 180 Insulating layer 185 Insulating Layer 233 areas 331 First oxide semiconductor film 332 Second oxide semiconductor film 333 Third oxide semiconductor film 360 Insulating Film 370 Second conductive film 410 Substrate 420 Undercoat insulating film 431 First oxide semiconductor layer 432 Second oxide semiconductor layer 433 Third oxide semiconductor layer 433a Microcrystalline layer 433b Crystal layer 610 Photodiode 640 Transistor 650 Transistors 661 Photodiode reset signal line 662 Gate signal line 671 Photo sensor output signal line 672 Photosensor reference signal line 2100 Transistor 2200 Transistor 2201 Insulating layer 2202 Wiring 2203 Plug 2204 Insulating layer 2205 Wiring 2206 Wiring 3000 boards 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3100 Element isolation insulating layer 3150 Insulation layer 3200 Transistors 3250 electrode 3300 Transistors 3400 Capacitive element 4250 memory cells 4300 Transistors 4400 Capacitive element 4500 Wiring 4600 Wiring 8000 Television Equipment 8001 Case 8002 Display section 8003 Speaker section 8004 CPU 8100 Alarm device 8101 Microcomputer 8102 Detector 8200 indoor unit 8201 Case 8202 Ventilator 8203 CPU 8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Case 8302 Refrigerator door 8303 Freezer door 8304 CPU 9700 Electric Vehicle 9701 Secondary battery 9702 Circuit 9703 Drive unit 9704 Processing Equipment

Claims

1. A first conductive film; an insulating film having a region above the first conductive film; an oxide semiconductor layer having a region above the insulating film; a second conductive film and a third conductive film having a region in contact with the oxide semiconductor layer, the oxide semiconductor layer is a stacked body and contains indium, gallium, and zinc; the oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer having a region in contact with an upper surface of the first oxide semiconductor layer; an atomic ratio of gallium to indium in the second oxide semiconductor layer is higher than an atomic ratio of gallium to indium in the first oxide semiconductor layer; the first oxide semiconductor layer is a microcrystalline layer, the second oxide semiconductor layer has a first crystalline region having a c-axis orientation and a second crystalline region having a c-axis orientation; In a cross-sectional observation, a direction of lattice fringes of the first crystal region is observed in a film thickness direction of the second oxide semiconductor layer overlapping an upper surface of the first conductive film; A transistor, wherein, upon cross-sectional observation, the direction of lattice fringes of the second crystalline region is different from the direction of lattice fringes of the first crystalline region.

2. In claim 1, the second conductive film and the third conductive film comprise copper.

Images