Semiconductor memory device

Abstract

Nanosheets (21-23) are formed side by side in the order of the nanosheets (21-23) in the X-direction. Nanosheets (24-26) are formed side by side in the order of the nanosheets (24-26) in the X-direction. In an embedded wiring layer, a power supply wire (11) is formed between the nanosheets (22, 25) in plan view. The nanosheet (22) has a first-side surface on one side in the X-direction which is exposed from a gate wire (32). The nanosheet (25) has a second-side surface on the other side in the X-direction which is exposed from a gate wire (35).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor memory device equipped with a nanosheet field effect transistor (FET), and in particular to a layout structure of a one-port static random access memory (SRAM) cell (hereinafter simply referred to as a cell) using a nanosheet FET. [Background technology]

[0002] SRAM is widely used in semiconductor integrated circuits.

[0003] Furthermore, transistors, which are the basic building blocks of LSIs, have achieved increased integration, lower operating voltages, and faster operating speeds through the reduction of gate length (scaling). In recent years, however, excessive scaling has caused problems with off-current and the resulting dramatic increase in power consumption. To solve this problem, there has been active research into three-dimensional transistors, in which the transistor structure has been changed from the conventional planar type to a three-dimensional type. Nanosheet FETs (nanowire FETs) are one type of three-dimensional transistor that has attracted attention.

[0004] Among nanosheet FETs, a fork sheet transistor with a fork-shaped gate electrode has been proposed. Non-Patent Documents 1 and 2 disclose the layout of an SRAM cell using a fork sheet transistor, which realizes a reduction in the area of ​​a semiconductor memory device. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] P. Weckx et al., “Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm”, 2017 IEEE International Electron Devices Meeting (IEDM), December 2017, IEDM17-505~508 [Non-Patent Document 2] P. Weckx et al., “Novel forksheet device architecture as ultimate logic scaling device towards 2nm”, 2019 IEEE International Electron Devices Meeting (IEDM), December 2019, IEDM19-871~874 Summary of the Invention [Problem to be solved by the invention]

[0006] In this specification, a nanosheet FET having a fork-shaped gate electrode is referred to as a fork-sheet transistor following the conventional technology.

[0007] However, in Non-Patent Document 1, only the structure of the arrangement of each transistor in a one-port SRAM cell is shown, and no detailed consideration is given including wiring.

[0008] An object of the present disclosure is to increase the speed and improve the write characteristics of a semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device in a layout structure of a one-port SRAM cell using a fork sheet transistor. [Means for solving the problem]

[0009] In a first aspect of the present disclosure, there is provided a semiconductor memory device including a one-port SRAM cell, the one-port SRAM cell comprising: a first transistor having one node connected to a first power supply supplying a first voltage, the other node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, the other node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node and the other node connected to a second power supply supplying a second voltage different from the first voltage, and a gate connected to the second node; a fourth transistor having one node connected to the second node, the other node connected to the second power supply, and a gate connected to the first node; a fifth transistor having one node connected to a first bit line, the other node connected to the first node, and a gate connected to a word line; and a sixth transistor having one node connected to a second bit line forming a complementary bit line pair with the first bit line, the other node connected to the second node, and a gate connected to the word line. The first to sixth transistors each include a first to sixth nanosheet extending in a first direction, and a first to sixth gate wiring respectively surrounding the first to sixth nanosheets in a second direction perpendicular to the first direction and a third direction perpendicular to the first and second directions. The first, third and sixth nanosheets are formed in the second direction in the order of the sixth, first and third nanosheets. The second, fourth and fifth nanosheets are formed in the second direction in the order of the fourth, second and fifth nanosheets. The first to sixth nanosheets have surfaces on either side in the second direction exposed from the first to sixth gate wirings. A first power supply wiring is formed below the first to sixth transistors, extending in the first direction between the first nanosheet and the second nanosheet in a plan view, and supplying the first voltage. The first nanosheet has a second side surface, which is the side opposite to a first side on which the first power supply wiring is formed, exposed from the first gate wiring in the second direction.The second nanosheet has a first side surface, which is opposite to the second side on which the first power supply wiring is formed, exposed from the second gate wiring in the second direction.

[0010] According to the present disclosure, a first power supply wiring for supplying a first voltage is formed in a layer below the first to sixth transistors. Therefore, for example, the width of the wiring for supplying the first voltage can be reduced (or omitted) in a layer above the first to sixth transistors. This allows the width of the wiring for the first and second bit lines to be increased, thereby improving the speed and write characteristics of the semiconductor memory device.

[0011] Moreover, the first power supply wiring is formed between the first nanosheet and the second nanosheet in plan view. The first and second nanosheets have surfaces that face each other in the second direction that are not exposed from the first and second gate wirings, respectively. That is, the first power supply wiring is formed between the first transistor and the second transistor, which are spaced apart from each other by a large distance in the second direction, in plan view. This makes it possible to suppress an increase in the area of ​​the semiconductor memory device.

[0012] Therefore, in the layout structure of a one-port SRAM cell using a fork sheet transistor, it is possible to increase the speed and improve the write characteristics of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0013] In a second aspect of the present disclosure, there is provided a semiconductor memory device including a one-port SRAM cell, the one-port SRAM cell comprising: a first transistor having one node connected to a first power supply supplying a first voltage, the other node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, the other node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node and the other node connected to a second power supply supplying a second voltage different from the first voltage, and a gate connected to the second node; a fourth transistor having one node connected to the second node, the other node connected to the second power supply, and a gate connected to the first node; a fifth transistor having one node connected to a first bit line, the other node connected to the first node, and a gate connected to a word line; and a sixth transistor having one node connected to a second bit line forming a complementary bit line pair with the first bit line, the other node connected to the second node, and a gate connected to the word line. The first to sixth transistors each include a first to sixth nanosheet extending in a first direction, and a first to sixth gate wirings respectively surrounding the first to sixth nanosheets in a second direction perpendicular to the first direction and a third direction perpendicular to the first and second directions. The first, third and sixth nanosheets are formed side by side in the second direction in the order of the sixth, first and third nanosheets. The second, fourth and fifth nanosheets are formed side by side in the second direction in the order of the fourth, second and fifth nanosheets. The first to sixth nanosheets have surfaces on either side in the second direction exposed from the first to sixth gate wirings. The first nanosheet has a surface on a first side facing the second nanosheet in the second direction exposed from the first gate wiring. The second nanosheet has a second side surface facing the first nanosheet in the second direction, the second side surface being exposed from the second gate wiring. A first power supply wiring is formed below the first to sixth transistors, extending in the first direction on the second side of the first nanosheet in a plan view, and supplying the first voltage or the second voltage.A second power supply wiring that supplies the first voltage or the second voltage is formed below the first to sixth transistors and extends in the first direction on the second side of the second nanosheet in a plan view.

[0014] According to the present disclosure, a first power supply wiring for supplying a first voltage or a second voltage is formed in a layer below the first to sixth transistors. A second power supply wiring for supplying a first voltage or a second voltage is formed in a layer below the first to sixth transistors. Therefore, for example, in a layer above the first to sixth transistors, the width of the wiring for supplying the first voltage or the second voltage can be reduced (or omitted). This allows the width of the wiring that becomes the first and second bit lines to be increased, thereby enabling the speed and write characteristics of the semiconductor memory device to be improved.

[0015] Moreover, the first power supply wiring is formed on the first side of the second nanosheet in a plan view. The second power supply wiring is formed on the second side of the first nanosheet in a plan view. The second nanosheet has a first side surface that is not exposed from the second gate wiring. The first nanosheet has a second side surface that is not exposed from the first gate wiring. That is, the first power supply wiring is formed on the first side of the second transistor where the distance between the transistors in the second direction is larger in a plan view. The second power supply wiring is formed on the second side of the first transistor where the distance between the transistors in the second direction is larger in a plan view. This makes it possible to suppress an increase in the area of ​​the semiconductor memory device.

[0016] Therefore, in the layout structure of a one-port SRAM cell using a fork sheet transistor, it is possible to increase the speed and improve the write characteristics of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0017] In a third aspect of the present disclosure, there is provided a semiconductor memory device including a one-port SRAM cell, the one-port SRAM cell comprising: a first transistor having one node connected to a first power supply supplying a first voltage, the other node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, the other node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node and the other node connected to a second power supply supplying a second voltage different from the first voltage, and a gate connected to the second node; a fourth transistor having one node connected to the second node, the other node connected to the second power supply, and a gate connected to the first node; a fifth transistor having one node connected to a first bit line, the other node connected to the first node, and a gate connected to a word line; and a sixth transistor having one node connected to a second bit line forming a complementary bit line pair with the first bit line, the other node connected to the second node, and a gate connected to the word line. The first and second transistors each include a first and second nanosheet extending in a first direction, and a first and second gate wiring respectively surrounding the first and second nanosheets in a second direction perpendicular to the first direction and a third direction perpendicular to the first and second directions. The third to sixth nanosheets each include a plurality of third to sixth nanosheets extending in the first direction, and a third to sixth gate wiring respectively surrounding the plurality of third to sixth nanosheets in the second and third directions. The first nanosheet, the plurality of third nanosheets, and the plurality of sixth nanosheets are formed side by side in the second direction in the order of the plurality of sixth nanosheets, the first nanosheets, and the plurality of third nanosheets. The second nanosheets, the plurality of fourth nanosheets, and the plurality of fifth nanosheets are formed side by side in the second direction in the order of the plurality of fourth nanosheets, the second nanosheets, and the plurality of fifth nanosheets. The first and second nanosheets have surfaces on either side in the second direction that are exposed from the first and second gate wirings, respectively.The third nanosheets each have a surface on one side in the second direction exposed from the third gate wiring. The fourth nanosheets each have a surface on one side in the second direction exposed from the fourth gate wiring. The fifth nanosheets each have a surface on one side in the second direction exposed from the fifth gate wiring. The sixth nanosheets each have a surface on one side in the second direction exposed from the sixth gate wiring. A plurality of power supply wirings extending in the first direction and supplying the second voltage are formed in a layer below the first to sixth transistors. The third nanosheets include a third nanosheet on which at least one of the power supply wirings is formed on the side opposite to the side exposed from the third gate wiring in the second direction in a plan view. The fourth nanosheets include a fourth nanosheet on which at least one of the power supply wirings is formed on the side opposite to the side exposed from the fourth gate wiring in the second direction in a plan view. The plurality of fifth nanosheets include a fifth nanosheet on which at least one of the plurality of power supply wirings is formed on a side opposite to a side exposed from the fifth gate wiring in the second direction in a plan view. The plurality of sixth nanosheets include a sixth nanosheet on which at least one of the plurality of power supply wirings is formed on a side opposite to a side exposed from the sixth gate wiring in the second direction in a plan view.

[0018] According to the present disclosure, a plurality of power supply wirings that supply the first voltage or the second voltage are formed in a layer below the first to sixth transistors. Therefore, for example, in a layer above the first to sixth transistors, the width of the wiring that supplies the first voltage or the second voltage can be reduced (or omitted), and the width of the wiring that becomes the first and second bit lines can be increased. This can increase the speed and improve the write characteristics of the semiconductor memory device.

[0019] Further, the plurality of third nanosheets includes a third nanosheet having a power wiring formed on a side not exposed from the third gate wiring in the second direction in a plan view. The plurality of fourth nanosheets includes a fourth nanosheet having a power wiring formed on a side not exposed from the fourth gate wiring in the second direction in a plan view. The plurality of fifth nanosheets includes a fifth nanosheet having a power wiring formed on a side not exposed from the fifth gate wiring in the second direction in a plan view. The plurality of sixth nanosheets includes a sixth nanosheet having a power wiring formed on a side not exposed from the sixth gate wiring in the second direction in a plan view. That is, the power wiring is formed at a position where the distance between the transistors in the second direction is large in a plan view. This makes it possible to suppress an increase in the area of ​​the semiconductor memory device.

[0020] Therefore, in the layout structure of a one-port SRAM cell using a fork sheet transistor, it is possible to increase the speed and improve the write characteristics of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device. Effect of the Invention

[0021] According to the present disclosure, in a layout structure of a one-port SRAM cell using a fork sheet transistor, it is possible to increase the speed and improve the write characteristics of a semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device. [Brief description of the drawings]

[0022] [Figure 1] FIG. 2 is a plan view showing an example of a layout structure of a 1-port SRAM cell according to the first embodiment. [Diagram 2] 1 is a cross-sectional view showing an example of a layout structure of a 1-port SRAM cell according to the first embodiment. [Diagram 3] 1 is a cross-sectional view showing an example of a layout structure of a 1-port SRAM cell according to the first embodiment. [Figure 4] 1 is a circuit diagram showing a configuration of a 1-port SRAM cell according to a first embodiment. [Diagram 5] FIG. 4 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the first embodiment. [Figure 6] FIG. 4 is a cross-sectional view showing another example of the layout structure of the 1-port SRAM cell according to the first embodiment. [Figure 7] FIG. 4 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the first embodiment. [Figure 8] FIG. 11 is a plan view showing an example of a layout structure of a 1-port SRAM cell according to the second embodiment. [Figure 9] FIG. 11 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the second embodiment. [Figure 10] FIG. 13 is a plan view showing an example of a layout structure of a 1-port SRAM cell according to the third embodiment. [Figure 11] FIG. 13 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the third embodiment. [Figure 12] FIG. 13 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the third embodiment. [Figure 13] FIG. 13 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the third embodiment. [Figure 14] A diagram showing the basic structure of a fork seat FET. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, the embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor memory device includes a plurality of SRAM cells (in this specification, simply referred to as cells as appropriate), and at least some of the plurality of SRAM cells include fork sheet transistors with a fork-shaped gate electrode among nanosheet FETs (nanowire FETs). A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which a current flows. The nanosheet is formed of, for example, silicon. In addition, in a semiconductor integrated circuit device, some of the nanosheet FETs are fork sheet FETs with a fork-shaped gate electrode.

[0024] In addition, in the present disclosure, the semiconductor layer portions formed on both ends of the nanosheet and constituting the terminals serving as the source or drain of the nanosheet FET are referred to as "pads." In addition, in the following description, in plan views such as FIG. 1, the vertical direction of the drawing is the Y direction (corresponding to the first direction), the horizontal direction of the drawing is the X direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the third direction).

[0025] (Fork seat structure) 14 shows the basic structure of a fork-sheet FET, where (a) is a plan view and (b) is a cross-sectional view taken along line Y-Y' in (a). In the basic structure of FIG. 14, two transistors TR1 and TR2 are arranged side by side with a gap S therebetween in the Y direction. A gate wiring 531 serving as the gate of transistor TR1 and a gate wiring 532 serving as the gate of transistor TR2 both extend in the Y direction and are arranged at the same position in the X direction.

[0026] A channel portion 521 that becomes the channel region of the transistor TR1 and a channel portion 526 that becomes the channel region of the transistor TR2 are composed of nanosheets. In FIG. 14, the channel portions 521 and 526 are each composed of a nanosheet having a three-sheet structure that overlaps in a plan view. Pads 522a and 522b that become the source region or drain region of the transistor TR1 are formed on both sides of the channel portion 521 in the X direction. Pads 527a and 527b that become the source region or drain region of the transistor TR2 are formed on both sides of the channel portion 526 in the X direction. The pads 522a and 522b are formed by epitaxial growth from the nanosheet that constitutes the channel portion 521. The pads 527a and 527b are formed by epitaxial growth from the nanosheet that constitutes the channel portion 526.

[0027] The gate wiring 531 surrounds the outer periphery in the Y direction and Z direction of the channel section 521 made of the nanosheet via a gate insulating film (not shown). However, the surface of the nanosheet constituting the channel section 521 on the side of the transistor TR2 in the Y direction is not covered by the gate wiring 531 and is exposed from the gate wiring 531. That is, in the cross-sectional view of FIG. 14(b), the gate wiring 531 does not cover the right side of the nanosheet constituting the channel section 521 in the drawing, but covers the upper side, left side, and lower side in the drawing. The gate wiring 531 overlaps the nanosheet constituting the channel section 521 on the opposite side of the transistor TR2 in the Y direction by a length OL.

[0028] The gate wiring 532 surrounds the outer periphery in the Y direction and Z direction of the channel section 526 made of the nanosheet via a gate insulating film (not shown). However, the surface of the nanosheet constituting the channel section 526 on the side of the transistor TR1 in the Y direction is not covered by the gate wiring 532 and is exposed from the gate wiring 532. That is, in the cross-sectional view of FIG. 14(b), the gate wiring 532 does not cover the left side of the nanosheet constituting the channel section 526 in the drawing, but covers the upper side, right side, and lower side in the drawing. The gate wiring 532 overlaps the nanosheet constituting the channel section 526 on the opposite side of the transistor TR1 in the Y direction by a length OL.

[0029] If the width (size in the Y direction) of each nanosheet is W and its height (size in the Z direction) is H, then the effective gate width Weff is Weff=2×W+H Since the channel portions 521 and 526 of the transistors TR1 and TR2 are formed of three nanosheets, the effective gate widths of the transistors TR1 and TR2 are 3×(2×W+H) It becomes.

[0030] 14, the gate wiring 531 does not overlap the nanosheet constituting the channel portion 521 on the side of the transistor TR2 in the Y direction. Also, the gate wiring 532 does not overlap the nanosheet constituting the channel portion 526 on the side of the transistor TR1 in the Y direction. This allows the transistors TR1 and TR2 to be closer to each other, thereby realizing a smaller area.

[0031] The number of nanosheets constituting the channel portion of the transistor is not limited to three. That is, the nanosheet may be composed of a single sheet structure, or may be composed of a plurality of sheets overlapping in a plan view. In addition, in FIG. 14(b), the cross-sectional shape of the nanosheet is illustrated as a rectangle, but is not limited thereto, and the cross-sectional shape of the nanosheet may be, for example, a square, a circle, an ellipse, or the like.

[0032] Furthermore, a semiconductor integrated circuit device may contain a mixture of fork-sheet FETs and nanosheet FETs in which the gate wiring surrounds the entire periphery of the nanosheet.

[0033] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In addition, in this specification, expressions such as "same wiring width" that mean the width is the same, include the range of manufacturing variations.

[0034] In this specification, the semiconductor layer portions formed on both ends of the nanosheet and constituting the terminals that serve as the source or drain of the transistor are referred to as "pads".

[0035] In addition, in the plan views and cross-sectional views of the following embodiments, the description of each insulating film may be omitted. In addition, in the plan views and cross-sectional views of the following embodiments, the nanosheet and the pads on both sides thereof may be depicted in a simplified linear shape. In addition, in this specification, expressions such as "same size" that mean that the size is the same, include the range of manufacturing variations.

[0036] In addition, in this specification, the source and drain of a transistor are appropriately referred to as a "node" of the transistor. In other words, one node of a transistor refers to the source or drain of the transistor, and both nodes of a transistor refer to the source and drain of the transistor.

[0037] In addition, in the following embodiments and their modified examples, the same components and the like are denoted by the same reference numerals and descriptions thereof may be omitted.

[0038] (First embodiment) 1 to 3 are diagrams showing an example of the layout structure of a 1-port SRAM cell according to the first embodiment, in which Fig. 1(a) and (b) are plan views, and Fig. 2(a) to (c) and Fig. 3(a) and (b) are cross-sectional views in the horizontal direction in plan view. Specifically, Fig. 1(a) shows the upper part of the cell, which is the M1 and M2 wiring layers, and Fig. 1(b) shows the lower part of the cell, which is a layer below the M1 and M2 wiring layers and includes a nanosheet FET. Fig. 2(a) is a cross section along line X1-X1', Fig. 2(b) is a cross section along line X2-X2', Fig. 2(c) is a cross section along line X3-X3', Fig. 3(a) is a cross section along line X4-X4', and Fig. 3(b) is a cross section along line X5-X5'.

[0039] Fig. 4 is a circuit diagram showing the configuration of a 1-port SRAM cell according to the first embodiment. As shown in Fig. 4, the 1-port SRAM cell includes load transistors PU1 and PU2, drive transistors PD1 and PD2, and access transistors PG1 and PG2 to form a 1-port SRAM circuit. The load transistors PU1 and PU2 are P-type FETs, and the drive transistors PD1 and PD2 and the access transistors PG1 and PG2 are N-type FETs.

[0040] The load transistor PU1 is provided between a power supply VDD and a first node NA, and the drive transistor PD1 is provided between the first node NA and a power supply VSS. The load transistor PU1 and the drive transistor PD1 have gates connected to a second node NB, and constitute an inverter INV1. The load transistor PU2 is provided between a power supply VDD and a second node NB, and the drive transistor PD2 is provided between the second node NB and a power supply VSS. The load transistor PU2 and the drive transistor PD2 have gates connected to the first node NA, and constitute an inverter INV2. That is, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0041] The access transistor PG1 is provided between the bit line BL and a first node NA, and has a gate connected to the word line WL. The access transistor PG2 is provided between the bit line BLB and a second node NB, and has a gate connected to the word line WL. The bit lines BL and BLB form a complementary bit line pair.

[0042] In a one-port SRAM circuit, when the bit lines BL and BLB constituting a complementary bit line pair are driven to a high level and a low level, respectively, and the word line WL is driven to a high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the bit lines BL and BLB are driven to a low level and a high level, respectively, and the word line WL is driven to a high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the word line WL is driven to a low level while data is written to the first and second nodes NA and NB, respectively, the latch state is determined and the data written to the first and second nodes NA and NB is held.

[0043] Also, when the bit lines BL and BLB are precharged to a high level and the word line WL is driven to a high level, the states of the bit lines BL and BLB are determined according to the data written to the first and second nodes NA and NB, respectively, so that data can be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the bit line BL is held at a high level and the bit line BLB is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the bit line BL is discharged to a low level and the bit line BLB is held at a high level.

[0044] As described above, the one-port SRAM cell has the functions of writing data to the SRAM cell, holding data, and reading data from the SRAM cell by controlling the bit lines BL, BLB and word lines WL.

[0045] In the following description, the solid lines running vertically and horizontally in plan views such as FIG. 1 and the solid lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for arranging components during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid intervals may be the same or different in the X and Y directions. The grid intervals may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid. However, from the viewpoint of suppressing manufacturing variations, it is preferable to arrange the components on the grid.

[0046] In addition, the dotted line surrounding the cell in the plan view of FIG. 1 indicates the cell frame of the 1-port SRAM cell (the outer edge of the 1-port SRAM cell). The 1-port SRAM cell is arranged so that the cell frame is in contact with the cell frame of the adjacent cell in the X or Y direction.

[0047] 1 and other plan views, a 1-port SRAM cell is arranged on each side of the 1-port SRAM cell in the X direction, with the 1-port SRAM cell inverted in the X direction. A 1-port SRAM cell is arranged on each side of the 1-port SRAM cell in the Y direction, with the 1-port SRAM cell inverted in the Y direction.

[0048] As shown in FIG. 1(b), power supply wirings 11 to 13 are formed extending in the Y direction from the top to the bottom of the cell in the drawing. The power supply wirings 11 to 13 are buried power supply wirings (BPR: Buried Power Rail) formed in a buried wiring layer. The power supply wiring 11 is formed near the center of the cell in the drawing, and the power supply wirings 12 and 13 are formed at the left and right ends of the cell in the drawing, respectively. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wirings 12 and 13 supply a power supply voltage VSS.

[0049] As shown in FIG. 1(b), nanosheets 21 to 26 are formed extending in the X and Y directions. The nanosheets 21 to 23 are aligned in the X direction in the order of nanosheets 21 to 23. The nanosheets 24 to 26 are aligned in the X direction in the order of nanosheets 24 to 26. The nanosheets 21 and 24 are aligned in the Y direction. The nanosheets 23 and 26 are aligned in the Y direction.

[0050] Moreover, the width of nanosheets 21, 23, 24, and 26 in the X direction is twice the width of nanosheets 22 and 25 in the X direction.

[0051] Moreover, nanosheets 21 and 24 are formed adjacent to the cell boundary on the left side of the drawing, and nanosheets 23 and 26 are formed adjacent to the cell boundary on the right side of the drawing.

[0052] The nanosheets 21 to 26 form the channel portions of the access transistor PG2, the load transistor PU1, the drive transistor PD1, the drive transistor PD2, the load transistor PU2, and the access transistor PG1, respectively.

[0053] The gate wirings (Gate) 31 to 36 extend in the X direction and the Z direction. The gate wirings 31 to 33 are lined up in the X direction, and the gate wirings to 36 are lined up in the X direction.

[0054] Moreover, the gate wirings 31 to 36 overlap with the nanosheets 21 to 26, respectively, in a plan view.

[0055] The gate wiring 31 serves as the gate of the access transistor PG2. The gate wiring 32 serves as the gate of the load transistor PU1. The gate wiring 33 serves as the gate of the drive transistor PD1. The gate wiring 34 serves as the gate of the drive transistor PD2. The gate wiring 35 serves as the gate of the load transistor PU2. The gate wiring 36 serves as the gate of the access transistor PG1.

[0056] The gate wirings 32 and 33 are connected to each other via a bridge portion 131 extending in the X direction. The gate wirings 34 and 35 are connected to each other via a bridge portion 132 extending in the X direction.

[0057] Pads 40 to 45 doped with an N-type semiconductor are formed at the top of nanosheet 21 in the drawing, between nanosheets 21 and 24, at the bottom of nanosheet 24 in the drawing, at the top of nanosheet 23 in the drawing, between nanosheets 23 and 26, and at the bottom of nanosheet 26 in the drawing. Pads 40 and 41 form a node of access transistor PG2. Pads 41 and 42 form a node of drive transistor PD2. Pads 43 and 44 form a node of drive transistor PD1. Pads 44 and 45 form a node of access transistor PG1.

[0058] That is, the nanosheet 21, the gate wiring 31, and the pads 40, 41 form the access transistor PG2. The nanosheet 23, the gate wiring 33, and the pads 43, 44 form the drive transistor PD1. The nanosheet 24, the gate wiring 34, and the pads 41, 42 form the drive transistor PD2. The nanosheet 26, the gate wiring 36, and the pads 44, 45 form the access transistor PG1.

[0059] Pads 46 to 49 doped with a P-type semiconductor are formed at the upper end of nanosheet 22 in the drawing, the lower end of nanosheet 22 in the drawing, the upper end of nanosheet 25 in the drawing, and the lower end of nanosheet 25 in the drawing. Pads 46 and 47 form a node of load transistor PU1. Pads 48 and 49 form a node of load transistor PU2.

[0060] That is, the nanosheet 22, the gate wiring 32, and the pads 46 and 47 form a load transistor PU1. The nanosheet 25, the gate wiring 35, and the pads 48 and 49 form a load transistor PU2.

[0061] Therefore, the access transistor PG2, the load transistor PU1, and the drive transistor PD1 are formed side by side in the X direction. The drive transistor PD2, the load transistor PU2, and the access transistor PG1 are formed side by side in the X direction. Also, the access transistor PG2 and the drive transistor PD2 are formed side by side in the Y direction. The drive transistor PD1 and the access transistor PG1 are formed side by side in the Y direction.

[0062] With this arrangement, each transistor is arranged symmetrically with respect to the center point of the cell. Specifically, the load transistors PU1 and PU2 are arranged symmetrically with respect to the center point of the cell. The drive transistors PD1 and PD2 are arranged symmetrically with respect to the center point of the cell. The access transistors PG1 and PG2 are arranged symmetrically with respect to the center point of the cell.

[0063] In the local wiring layer, local wirings (LI: Local Interconnect) 51 to 58 extending in the X direction are formed. Local wiring 51 is connected to pad 40. Local wiring 52 is connected to pad 46. Local wiring 53 is connected to pad 43. Local wiring 54 is connected to pads 41 and 48. Local wiring 55 is connected to pads 47 and 44. Local wiring 56 is connected to pad 42. Local wiring 57 is connected to pad 49. Local wiring 58 is connected to pad 45.

[0064] Local wiring 52 is connected to power supply wiring 11 via contact (Via) 111. Local wiring 53 is connected to power supply wiring 13 via contact 112. Local wiring 56 is connected to power supply wiring 12 via contact 113. Local wiring 57 is connected to power supply wiring 11 via contact 114.

[0065] The local wiring 54 is connected to the gate wiring 32 via a shared contact 61. The local wiring 55 is connected to the gate wiring 35 via a shared contact 62. The gate wirings 34 and 35, the bridge portion 132, the local wiring 55, and the shared contact 62 correspond to a first node NA. The gate wirings 32 and 33, the bridge portion 131, the local wiring 54, and the shared contact 61 correspond to a second node NB.

[0066] As shown in FIG. 1(a), wirings 71 to 75 are formed in the M1 wiring layer, extending in the Y direction from the top to the bottom of the cell in the drawing. In addition, wirings 76 and 77 are formed extending in the Y direction. The wiring 71 supplies a power supply voltage VDD. The wirings 72 and 73 supply a power supply voltage VSS. The wirings 74 and 75 correspond to bit lines BLB and BL, respectively. In addition, the wirings 74 and 75 are arranged symmetrically with respect to the center line of the cell in the X direction.

[0067] The wirings 71 to 75 are arranged in the X direction in the order of wirings 72, 74, 71, 75, and 73. That is, the wiring 71 is provided between the wirings 74 and 75.

[0068] The wiring 71 is connected to the local wiring 52 via a contact (Via) 81, and is connected to the local wiring 57 via a contact 82. The wiring 72 is connected to the local wiring 56 via a contact 83. The wiring 73 is connected to the local wiring 53 via a contact 84. The wiring 74 is connected to the local wiring 51 via a contact 85. The wiring 75 is connected to the local wiring 58 via a contact 86. The wiring 76 is connected to the gate wiring 31 via a contact (gate-contact) 87. The wiring 77 is connected to the gate wiring 36 via a contact 88.

[0069] In the M2 wiring layer, which is an upper layer of the M1 wiring layer, wirings 91 to 93 are formed, which extend in the X direction from the left to the right ends of the cell in the drawing. The wirings 91 and 93 supply a power supply voltage VSS. The wiring 92 corresponds to the word line WL. The wiring 92 is formed between the wirings 91 and 93.

[0070] Wiring 91 is connected to wiring 72 via contact 101, and is connected to wiring 73 via contact 102. Wiring 92 is connected to wiring 76 via contact 103, and is connected to wiring 77 via contact 104. Wiring 93 is connected to wiring 72 via contact 105, and is connected to wiring 73 via contact 106.

[0071] As shown in Fig. 2(b) and Fig. 3(a), each of the nanosheets 21 to 26 is composed of three sheet-shaped semiconductors (nanosheets). The nanosheets constituting each of the nanosheets 21 to 26 are arranged so as to overlap in a plan view, and are formed to be spaced apart in the Z direction. That is, each of the nanosheet FETs configured in the one-port SRAM cell according to this embodiment includes three nanosheets.

[0072] Further, the outer periphery of each of the nanosheets 21 to 26 in the X and Z directions is surrounded by the gate wiring. Here, a part of the outer periphery of each of the nanosheets 21 to 26 in the X and Z directions is not covered by the gate wiring and is exposed from the gate wiring.

[0073] Specifically, the surfaces of the nanosheets 21, 22, and 24 on the right side in the drawing are not covered by the gate wirings 31, 32, and 34, respectively, and are exposed from the gate wirings 31, 32, and 34, respectively. The surfaces of the nanosheets 23, 25, and 26 on the left side in the drawing are not covered by the gate wirings 33, 35, and 36, respectively, and are exposed from the gate wirings 33, 35, and 36, respectively.

[0074] That is, the nanosheets 22 and 23 have their surfaces facing each other in the X direction exposed from the gate wirings 32 and 33, respectively. The nanosheets 24 and 25 have their surfaces facing each other in the X direction exposed from the gate wirings 34 and 35, respectively.

[0075] The surfaces of the nanosheets 21, 22, and 24 on the left side in the drawing are covered by the gate wirings 31, 32, and 34, respectively, and are not exposed from the gate wirings 31, 32, and 34. The surfaces of the nanosheets 23, 25, and 26 on the right side in the drawing are covered by the gate wirings 33, 35, and 36, respectively, and are not exposed from the gate wirings 33, 35, and 36, respectively.

[0076] Moreover, the nanosheet 22 is formed above the right side of the nanosheet 25 in the figure. That is, the surfaces of the nanosheets 22 and 25 that face each other in the X direction are not exposed from the gate wirings 32 and 35, respectively.

[0077] As shown in Fig. 1, nanosheets 22 and 25 are arranged at different positions in the Y direction, but are arranged close to each other in the X direction, and therefore, in this specification, nanosheets 22 and 25 are said to face each other in the X direction. Therefore, the surface of nanosheet 22 on the left side of the drawing is the surface facing nanosheet 25. The surface of nanosheet 25 on the right side of the drawing is the surface facing nanosheet 22. The same applies in the following description.

[0078] Moreover, the nanosheets 21 and 24 are formed close to the cell boundary on the left side of the drawing. The nanosheets 23 and 26 are formed close to the cell boundary on the right side of the drawing. In the 1-port SRAM cell of FIG. 1, the 1-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the 1-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21 facing each other in the X direction are not exposed from the gate wiring 31. The surfaces of the nanosheets 23 facing each other in the X direction are not exposed from the gate wiring 33. The surfaces of the nanosheets 24 facing each other in the X direction are not exposed from the gate wiring 34. The surfaces of the nanosheets 26 facing each other in the X direction are not exposed from the gate wiring 36.

[0079] 1, power supply wiring 11 is formed between nanosheets 22 and 25 in plan view. Power supply wiring 12 and 13 are formed at the cell boundaries on the left and right sides of the drawing, respectively, in plan view.

[0080] 1(a), the width in the X direction of the wirings 74 and 75 is wider than the width in the X direction of the wirings 76 and 77. The wirings 76 and 77 are the wirings with the smallest width in the X direction in the M1 wiring layer. That is, the wirings 74 and 75 are formed so as to have a wider width in the X direction than the wiring with the smallest width in the X direction in the M1 wiring layer.

[0081] With the above configuration, the load transistor PU1 has a pad 46 connected to the wiring 71 that supplies a power supply voltage VDD, a pad 47 connected to the local wiring 55 (first node NA), and a gate wiring 32 connected to the shared contact 61 (second node NB). The load transistor PU2 has a pad 49 connected to the wiring 71 that supplies a power supply voltage VDD, a pad 48 connected to the local wiring 54 (second node NB), and a gate wiring 35 connected to the shared contact 62 (first node NA). The drive transistor PD1 has a pad 44 connected to the local wiring 55 (first node NA), a pad 43 connected to the wiring 73 that supplies a power supply voltage VSS, and a gate wiring 33 connected to the shared contact 61 (second node NB). The drive transistor PD2 has a pad 41 connected to the local wiring 54 (second node NB), a pad 42 connected to the wiring 72 that supplies a power supply voltage VSS, and a gate wiring 34 connected to the shared contact 62 (first node NA). In the access transistor PG1, the pad 45 is connected to the wiring 75 (bit line BL), the pad 44 is connected to the local wiring 55 (first node NA), and the gate wiring 36 is connected to the wiring 92 (word line WL). In the access transistor PG2, the pad 40 is connected to the wiring 74 (bit line BLB), the pad 41 is connected to the local wiring 54 (second node NB), and the gate wiring 31 is connected to the wiring 92 (word line WL).

[0082] The load transistors PU1, PU2, the drive transistors PD1, PD2, and the access transistors PG1, PG2 each include a nanosheet 22, 25, 23, 24, 26, 21 extending in the Y direction, and a gate wiring 32, 35, 33, 34, 36, 31. The nanosheets 21 to 23 are formed side by side in the X direction in the order of the nanosheets 21 to 23. The nanosheets 24 to 26 are formed side by side in the X direction in the order of the nanosheets 24 to 26. The gate wiring 31 to 36 surround the outer periphery of the nanosheets 21 to 26 in the X direction and the Z direction, respectively. The surfaces of the nanosheets 21, 22, 24 on the right side of the drawing are exposed from the gate wiring 31, 32, 34, respectively. The surfaces of the nanosheets 23, 25, 26 on the left side of the drawing are exposed from the gate wiring 33, 35, 36, respectively. In plan view, the nanosheet 22 is formed above the right side of the nanosheet 25. In the embedded wiring layer, a power supply wiring 11 is formed, which extends in the Y direction and is provided between the nanosheets 21 and 25 in plan view and supplies a power supply voltage VDD.

[0083] That is, the load transistors PU1 and PU2, the drive transistors PD1 and PD2, and the access transistors PG1 and PG2 are each configured with a fork sheet transistor, thereby realizing a one-port SRAM cell using a fork sheet transistor.

[0084] Furthermore, the surfaces of the nanosheets 22 and 23 that face each other in the X direction are exposed from the gate wirings 32 and 33, respectively. The surfaces of the nanosheets 24 and 25 that face each other in the X direction are exposed from the gate wirings 34 and 35, respectively. This makes it possible to reduce the distance d1 in the X direction between the load transistor PU1 and the drive transistor PD1, and the distance d1 in the X direction between the drive transistor PD2 and the load transistor PU2, thereby making it possible to reduce the area of ​​the semiconductor memory device.

[0085] Furthermore, by forming the power supply wiring 11 in the buried wiring layer, the width in the X direction of the wiring 71 that supplies the power supply voltage VDD in the M1 wiring layer can be reduced, and therefore the width in the X direction of the wirings 75 and 74 that become the bit lines BL and BLB can be increased, respectively. This makes it possible to increase the speed and improve the write characteristics of the semiconductor memory device.

[0086] Moreover, the power supply wiring 11 is formed between the nanosheets 22 and 25 in plan view. Moreover, the surfaces of the nanosheets 22 and 25 facing each other in the X direction are not exposed from the gate wirings 32 and 35, respectively. Therefore, the power supply wiring 11 is formed between the load transistors PU1 and PU2 whose distance in the X direction is greater than the distance d1 in plan view. That is, the power supply wiring 11 can be easily formed without widening the distance in the X direction between the load transistors PU1 and PU2. This makes it possible to suppress an increase in the area of ​​the semiconductor memory device.

[0087] Therefore, in a semiconductor memory device including a one-port SRAM cell using a fork sheet transistor, it is possible to increase the speed and improve the write characteristics while suppressing an increase in area.

[0088] In addition, by forming the power supply wirings 12 and 13 for supplying the power supply voltage VSS in the buried wiring layer, the width in the X direction of the wirings 72 and 73 for supplying the power supply voltage VSS in the M1 wiring layer can be reduced, and therefore the width in the X direction of the wirings 75 and 74 serving as the bit lines BL and BLB can be increased, respectively. This makes it possible to increase the speed and improve the write characteristics of the semiconductor memory device.

[0089] Moreover, the power supply wirings 12 and 13 are formed at the cell boundaries on the left and right sides of the drawing in plan view. Moreover, in the 1-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21 facing each other in the X direction are not exposed from the gate wiring 31. The surfaces of the nanosheets 23 facing each other in the X direction are not exposed from the gate wiring 33. The surfaces of the nanosheets 24 facing each other in the X direction are not exposed from the gate wiring 34. The surfaces of the nanosheets 26 facing each other in the X direction are not exposed from the gate wiring 36. Therefore, the power supply wiring 12 is formed between the drive transistors PD2 and between the access transistors PG2 whose distance in the X direction is greater than the distance d1 in plan view. The power supply wiring 13 is formed between the drive transistors PD1 and between the access transistors PG1 whose distance in the X direction is greater than the distance d1 in plan view. That is, the power supply wiring 12 can be easily formed without increasing the distance in the X direction between the access transistors PG2 and the distance in the X direction between the drive transistors PD2. The power supply wiring 13 can be easily formed without increasing the distance in the X direction between the drive transistors PD1 and the distance in the X direction between the access transistors PG1. This makes it possible to suppress an increase in the area of ​​the semiconductor memory device.

[0090] Therefore, in a semiconductor memory device including a one-port SRAM cell using a fork sheet transistor, it is possible to increase the speed and improve the write characteristics while suppressing an increase in area.

[0091] Also, in the M1 wiring layer, a wiring 71 that supplies a power supply voltage VDD and wirings 72, 73 that form a power supply voltage VSS are formed. That is, wirings that supply power supply wirings VDD, VSS are formed in the M1 wiring layer and the buried wiring layer, respectively. This makes it possible to reduce the width in the X direction of the wirings that supply the power supply wirings VDD, VSS in the M1 wiring layer, while reducing the resistance value of the wirings that supply the power supply voltages VDD, VSS in the buried wiring layer. Therefore, it is possible to increase the speed of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0092] Moreover, in the M2 wiring layer, wirings 91 and 93 for supplying a power supply voltage VSS are formed. A wiring 92 (word line WL) is formed between the wirings 91 and 93. In the 1-port SRAM cell of FIG. 1, 1-port SRAM cells inverted in the Y direction are arranged on both the top and bottom of the drawing. That is, in the 1-port SRAM cells arranged side by side in the Y direction, the wiring 91 or wiring 93 is formed between the wirings 92. This strengthens the supply of power to the 1-port SRAM cells, and the shielding effect of the wirings 91 and 93 can prevent crosstalk between the word lines.

[0093] Moreover, the width in the X direction of the wirings 74 and 75 is wider than the width in the X direction of the wirings 76 and 77. The wirings 76 and 77 are the wirings with the smallest width in the X direction in the M1 wiring layer. That is, the wirings 74 and 75 are formed so that their width in the X direction is wider than the wiring with the smallest width in the X direction in the M1 wiring layer. This can increase the speed of writing and reading via the wirings 74 and 75 in the semiconductor memory device.

[0094] In addition, the load transistors PU1 and PU2 are arranged symmetrically with respect to the center point of the cell. The drive transistors PD1 and PD2 are arranged symmetrically with respect to the center point of the cell. The access transistors PG1 and PG2 are arranged symmetrically with respect to the center point of the cell. This aligns the characteristics of the bit lines BL and BLB, improving the operational stability and operating speed of the semiconductor memory device.

[0095] In addition, in the M1 wiring layer, the wirings 75 and 74 are arranged symmetrically with respect to the center line of the cell in the X direction. That is, the wirings corresponding to the bit lines BL and BLB are arranged symmetrically with respect to the center line of the cell in the X direction. This makes the characteristics of the bit lines BL and BLB uniform, improving the operational stability and operating speed of the semiconductor memory device.

[0096] The width in the X direction of nanosheets 21, 23, 24, and 26 is twice the width in the X direction of nanosheets 22 and 25, but is not limited to this. The width in the X direction of each of nanosheets 21 to 26 (i.e., the gate width of each transistor) may be determined taking into consideration the operational stability of the one-port SRAM circuit, etc.

[0097] Also, some of the wirings 71 to 73 may be omitted, and at least one is sufficient. This allows the width of the wirings 74 and 75 in the X direction to be increased, thereby improving the speed and write characteristics of the semiconductor memory device.

[0098] Furthermore, some of the power supply wirings 11 to 13 may be omitted, and at least one of them is sufficient.

[0099] (Variation 1) FIG. 5 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the first embodiment. FIG. 5 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the first embodiment. Specifically, FIG. 5(a) shows the upper part of the cell, and FIG. 5(b) shows the lower part of the cell. FIG. 7(a) is a cross section along line X6-X6', and FIG. 2(b) is a cross section along line X7-X7'. In FIG. 5, the surface of each nanosheet opposite to that of FIG. 1 in the X direction is exposed from the gate wiring. In addition, the power supply wiring 11 is omitted, and the arrangement of the power supply wirings 12 and 13 is different.

[0100] 5(b), the gate wiring 33 overlaps with the nanosheets 22 and 23 in a planar view. The gate wiring 34 overlaps with the nanosheets 24 and 25 in a planar view.

[0101] 5, the gate wiring 33 serves as the gates of the load transistor PU1 and the drive transistor PD1, and the gate wiring 34 serves as the gates of the drive transistor PD2 and the load transistor PU2.

[0102] The gate wiring 31 is connected to the gate wiring 31 of the 1-port SRAM cell arranged on the left side of the 1-port SRAM cell in the drawing via a bridge portion 133. The gate wiring 36 is connected to the gate wiring 36 of the 1-port SRAM cell arranged on the right side of the 1-port SRAM cell in the drawing via a bridge portion 134.

[0103] The wiring 76 is connected to the gate wiring 31 via a contact 87 and a bridge portion 133. The wiring 77 is connected to the gate wiring 36 via a contact 88 and a bridge portion 134.

[0104] 6(a) and (b), the surfaces of nanosheets 21, 22, and 24 on the left side of the drawing are not covered by gate wirings 31, 33, and 34, respectively, and are exposed from gate wirings 31, 33, and 34, respectively. The surfaces of nanosheets 23, 25, and 26 on the right side of the drawing are not covered by gate wirings 33, 34, and 36, respectively, and are exposed from gate wirings 33, 34, and 36, respectively.

[0105] Moreover, the nanosheets 21 and 24 are arranged close to the cell boundary on the left side of the drawing. The nanosheets 23 and 26 are arranged close to the cell boundary on the right side of the drawing. In the 1-port SRAM cell of FIG. 5, the 1-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the 1-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21 facing each other in the X direction are exposed from the gate wiring 31. The surfaces of the nanosheets 23 facing each other in the X direction are exposed from the gate wiring 33. The surfaces of the nanosheets 24 facing each other in the X direction are exposed from the gate wiring 34. The surfaces of the nanosheets 26 facing each other in the X direction are exposed from the gate wiring 36.

[0106] Moreover, the nanosheet 22 is formed above the right side of the nanosheet 25 in the figure. That is, the surfaces of the nanosheets 22 and 25 that face each other in the X direction are exposed from the gate wirings 33 and 34, respectively.

[0107] The surfaces of the nanosheets 21, 22, and 24 on the right side in the drawing are covered by the gate wirings 31, 33, and 34, respectively, and are not exposed from the gate wirings 31, 33, and 34. The surfaces of the nanosheets 23, 25, and 26 on the left side in the drawing are covered by the gate wirings 33, 34, and 36, respectively, and are not exposed from the gate wirings 33, 34, and 36, respectively.

[0108] That is, the surfaces of the nanosheets 22 and 23 that face each other in the X direction are not exposed from the gate wiring 33. The surfaces of the nanosheets 24 and 25 that face each other in the X direction are not exposed from the gate wiring 34.

[0109] 5, the power supply wiring 12 is formed between the nanosheets 24 and 25 in a plan view. The power supply wiring 13 is formed between the nanosheets 22 and 23 in a plan view.

[0110] According to the layout structure of FIG. 5, in the one-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21 facing each other in the X direction are exposed from the gate wiring 31. The surfaces of the nanosheets 23 facing each other in the X direction are exposed from the gate wiring 33. The surfaces of the nanosheets 24 facing each other in the X direction are exposed from the gate wiring 34. The surfaces of the nanosheets 26 facing each other in the X direction are exposed from the gate wiring 36. This makes it possible to reduce the distance d1 in the X direction between the access transistors PG2, the distance d1 in the X direction between the drive transistors PD1, the distance d1 in the X direction between the drive transistors PD2, and the distance d1 in the X direction between the access transistors PG1, and thus the area of ​​the semiconductor memory device can be reduced.

[0111] Furthermore, the nanosheets 22 and 25 have their opposing surfaces in the X direction exposed from the gate wirings 33 and 34. This allows the distance d1 in the X direction between the load transistors PU1 and PU2 to be reduced, thereby enabling the area of ​​the semiconductor memory device to be reduced.

[0112] In addition, the power supply wiring 12, 13 that supplies the power supply voltage VSS is formed in the buried wiring layer. The power supply wiring 12 is formed between the nanosheets 24, 25 in a plan view. The power supply wiring 13 is formed between the nanosheets 22, 23 in a plan view. In addition, the surfaces of the nanosheets 22, 23 that face each other in the X direction are not exposed from the gate wiring 33. The surfaces of the nanosheets 24, 25 that face each other in the X direction are not exposed from the gate wiring 34. Therefore, the power supply wiring 12 is formed between the load transistor PU2 and the drive transistor PD2 whose distance in the X direction is greater than the distance d1. The power supply wiring 13 is formed between the load transistor PU1 and the drive transistor PD1 whose distance in the X direction is greater than the distance d1. That is, the power supply wiring 12 can be easily formed without widening the distance in the X direction between the load transistor PU2 and the drive transistor PD2. The power supply wiring 13 can be easily formed without widening the distance in the X direction between the load transistor PU1 and the drive transistor PD1. This makes it possible to increase the speed of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0113] In addition, the same effects as those shown in FIG. 1 can be obtained.

[0114] A power supply wiring for supplying a power supply voltage VDD may be formed in place of either or both of the power supply wirings 12 and 13. In this case, the power supply wiring is connected to either or both of the pads 46 and 49 via local wiring and contacts.

[0115] Moreover, it is sufficient if either one of the power supply wirings 12 and 13 is provided.

[0116] (Variation 2) 7 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the first embodiment. Specifically, FIG. 7(a) shows the upper part of the cell, and FIG. 7(b) shows the lower part of the cell. In FIG. 7, the length in the X direction of some local wirings is shorter than in FIG. 1, and the width in the X direction of the shared contact is smaller.

[0117] For example, in FIG. 1(b), the local wiring 51 is formed so that its left end is aligned with the left end of the pad 40. In contrast to this, in FIG. 7(b), the local wiring 51 is formed so that its left end is located near the center of the pad 40 in the X direction. Therefore, the length of the local wiring 51 in the X direction is shorter in FIG. 7(b) than in FIG. 1(b). Similarly, the other local wirings are also formed so that at least one of their ends is located near the center of the pad, that is, between the left end and the right end of the pad. Therefore, the length of some of the local wirings in the X direction is shorter in FIG. 7(b) than in FIG. 1(b).

[0118] In FIG. 1(b), the shared contact 61 is formed so that its left end and right end are aligned with the left end and right end of the pad 48. The shared contact 62 is formed so that its left end and right end are aligned with the left end and right end of the pad 48. In contrast, in FIG. 7(b), the shared contact 61 is formed so that its left end is located to the right of the left end of the pad 47, and its right end is located to the left of the right end of the pad 47. The shared contact 62 is formed so that its left end is located to the right of the left end of the pad 48, and its right end is located to the left of the right end of the pad 47. For this reason, the width of the shared contacts 61 and 62 in the X direction is shorter in FIG. 7(b) than in FIG. 1(b).

[0119] According to the layout structure of Fig. 7, the length in the X direction of some local interconnects (such as local interconnect 51) is shorter than that of Fig. 1. Also, the width in the X direction of shared contacts 61, 62 is shorter than that of Fig. 1. This can reduce the parasitic capacitance in the semiconductor integrated circuit, thereby enabling the semiconductor memory device to operate at a higher speed.

[0120] In addition, the same effects as those shown in FIG. 1 can be obtained.

[0121] (Embodiment 2) FIG. 8 is a plan view showing an example of the layout structure of a 1-port SRAM cell according to the second embodiment. Specifically, FIG. 8(a) shows the lower part of the cell, and FIG. 8(b) shows the upper part of the cell. In the 1-port SRAM cell of FIG. 8, the 1-port SRAM circuit shown in FIG. 4 is configured by load transistors PU1 and PU2 and transistors PD11, PD12, PD21, PD22, PG11, PG12, PG21, and PG22. In FIG. 8, the drive transistors PD1 and PD2 and the access transistors PG1 and PG2 are each configured by two transistors. Specifically, the drive transistor PD1 is configured by the transistors PD11 and PD12. The drive transistor PD2 is configured by the transistors PD21 and PD22. The access transistor PG1 is configured by the transistors PG11 and PG12. The access transistor PG2 is configured by the transistors PG21 and PG22. In addition, in the 1-port SRAM cell of FIG. 8, 1-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing.

[0122] As shown in FIG. 8(b), power supply wirings 11 to 13 are formed in the buried wiring layer.

[0123] In addition, nanosheets 21a, 21b, 22, 23a, 23b, 24a, 24b, 25, 26a, and 26b are formed extending in the X direction and the Y direction. The nanosheets 21a, 21b, 22, 23a, and 23b are arranged in the X direction in the order of the nanosheets 21a, 21b, 22, 23a, and 23b. The nanosheets 24a, 24b, 25, 26a, and 26b are arranged in the order of the nanosheets 24a, 24b, 25, 26a, and 26b. In addition, the nanosheets 21a and 24a are arranged in the Y direction. The nanosheets 21b and 24b are arranged in the Y direction. The nanosheets 23a and 26a are arranged in the Y direction. The nanosheets 23b and 26b are arranged in the Y direction.

[0124] Moreover, the nanosheets 21a, 21b, 22, 23a, 23b, 24a, 24b, 25, 26a, and 26b have the same width in the X direction.

[0125] In FIG. 8, nanosheets 21a, 21b, 23a, 23b, 24a, 24b, 26a, and 26b serve as channel portions of transistors PG21, PG22, PD11, PD12, PD21, PD22, PG11, and PG12, respectively.

[0126] The gate wiring 31 overlaps with the nanosheets 21a and 21b in a planar view. The gate wiring 32 overlaps with the nanosheet 22 in a planar view. The gate wiring 33 overlaps with the nanosheets 23a and 23b in a planar view. The gate wiring 34 overlaps with the nanosheets 24a and 24b in a planar view. The gate wiring 35 overlaps with the nanosheet 25 in a planar view. The gate wiring 36 overlaps with the nanosheets 26a and 26b in a planar view.

[0127] In Fig. 8, the gate wiring 31 serves as the gates of the transistors PG21 and PG22. The gate wiring 32 serves as the gate of the load transistor PU1. The gate wiring 33 serves as the gates of the transistors PD11 and PD12. The gate wiring 34 serves as the gates of the transistors PD21 and PD22. The gate wiring 35 serves as the gate of the load transistor PU2. The gate wiring 36 serves as the gates of the transistors PG11 and PG12.

[0128] Gate wiring 31 is connected to gate wiring 31 of a 1-port SRAM cell arranged on the left side of the 1-port SRAM cell in the drawing via a bridge portion 133. Gate wirings 32 and 33 are connected to each other via a bridge portion 131. Gate wirings 34 and 35 are connected to each other via a bridge portion 132. Gate wiring 36 is connected to gate wiring 36 of a 1-port SRAM cell arranged on the right side of the 1-port SRAM cell in the drawing via a bridge portion 134.

[0129] Pads 40a, 41a, 42a, 40b, 41b, 42b, 43a, 44a, 45a, 43b, 44b, and 45b doped with an N-type semiconductor are formed on the upper side of the nanosheet 21a in the drawing, between the nanosheets 21a and 24a, the lower side of the nanosheet 24a in the drawing, the upper side of the nanosheet 21b in the drawing, between the nanosheets 21b and 24b, the lower side of the nanosheet 24b in the drawing, the upper side of the nanosheet 23a in the drawing, between the nanosheets 23a and 26a, the lower side of the nanosheet 26a in the drawing, the upper side of the nanosheet 23b in the drawing, between the nanosheets 23b and 26b, and the lower side of the nanosheet 26b in the drawing. The pads 40a and 41a form the nodes of the transistor PG21. The pads 41a and 42a form the nodes of the transistor PD21. The pads 40b and 41b form the nodes of the transistor PG22. The pads 41b and 42b form a node of the transistor PD22. The pads 43a and 44a form a node of the transistor PD11. The pads 44a and 45a form a node of the transistor PG11. The pads 43b and 44b form a node of the transistor PD12. The pads 44b and 45b form a node of the transistor PG12.

[0130] With this arrangement, in FIG. 8(b), each transistor is arranged point-symmetrically with respect to the center point of the cell. Specifically, the load transistors PU1 and PU2 are arranged point-symmetrically with respect to the center point of the cell. The transistors PD11 and PD22 are arranged point-symmetrically with respect to the center point of the cell. The transistors PD12 and PD21 are arranged point-symmetrically with respect to the center point of the cell. The transistors PG11 and PG22 are arranged point-symmetrically with respect to the center point of the cell. The transistors PG12 and PG21 are arranged point-symmetrically with respect to the center point of the cell.

[0131] The local wiring 51 is connected to the pads 40a and 40b. The local wiring 53 is connected to the pads 43a and 43b. The local wiring 54 is connected to the pads 41a, 41b, and 48. The local wiring 55 is connected to the pads 47, 44a, and 44b. The local wiring 56 is connected to the pads 42a and 42b. The local wiring 58 is connected to the pads 45a and 45b.

[0132] 7, some of the local wirings 51-58 are formed so that at least one of their ends is located between the left end and the right end of the pad to which they are connected. For example, the left end of the local wiring 51 is located between the left end and the right end of the pad 40a.

[0133] 7, shared contact 61 is formed so that its left end is located to the right of the left end of pad 48, and its right end is located to the left of the right end of pad 48. Shared contact 62 is formed so that its left end is located to the right of the left end of pad 47, and its right end is located to the left of the right end of pad 47, as in Fig. 7.

[0134] Here, the left surfaces of nanosheets 21a, 23a, 24a, 25, and 26a in the drawing are not covered by gate wirings 31, 33, 34, 35, and 36, respectively, and are exposed from gate wirings 31, 33, 34, 35, and 36, respectively. The right surfaces of nanosheets 21b, 22, 23b, 24b, and 26b in the drawing are not covered by gate wirings 31, 32, 33, 34, and 36, respectively, and are exposed from gate wirings 31, 32, 33, 34, and 36, respectively.

[0135] That is, the nanosheets 22 and 23a have surfaces that face each other in the X direction exposed from the gate wirings 32 and 33, respectively. The nanosheets 24b and 25 have surfaces that face each other in the X direction exposed from the gate wirings 34 and 35, respectively.

[0136] Moreover, the nanosheets 21a and 24a are formed close to the cell boundary on the left side of the drawing. The nanosheets 23b and 26b are formed close to the cell boundary on the right side of the drawing. In the 1-port SRAM cell of FIG. 8, the 1-port SRAM cell inverted in the X direction is arranged on the right side of the drawing. That is, in the 1-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are exposed from the gate wiring 31. The surfaces of the nanosheets 23b facing each other in the X direction are exposed from the gate wiring 33. The surfaces of the nanosheets 24a facing each other in the X direction are exposed from the gate wiring 34. The surfaces of the nanosheets 26b facing each other in the X direction are exposed from the gate wiring 36.

[0137] Further, the surfaces of nanosheets 21a, 23a, 24a, 25, and 26a on the right side in the drawing are covered by gate wirings 31, 33, 34, 35, and 36, respectively, and are not exposed from gate wirings 31, 33, 34, 35, and 36. The surfaces of nanosheets 21b, 22, 23b, 24b, and 26b on the left side in the drawing are covered by gate wirings 31, 32, 33, 34, and 36, respectively, and are not exposed from gate wirings 31, 32, 33, 34, and 36, respectively.

[0138] That is, the surfaces of the nanosheets 21a and 21b facing each other in the X direction are not exposed from the gate wiring 31. The surfaces of the nanosheets 23a and 23b facing each other in the X direction are not exposed from the gate wiring 33. The surfaces of the nanosheets 24a and 24b facing each other in the X direction are not exposed from the gate wiring 34. The surfaces of the nanosheets 26a and 26b facing each other in the X direction are not exposed from the gate wiring 36.

[0139] Moreover, the nanosheet 22 is formed above the right side of the nanosheet 25 in the figure. That is, the surfaces of the nanosheets 22 and 25 that face each other in the X direction are not exposed from the gate wirings 32 and 35, respectively.

[0140] 8, power supply wiring 11 is formed between nanosheets 22 and 25 in a plan view. Power supply wiring 12 is formed between nanosheets 21a and 21b and between nanosheets 24a and 24b in a plan view. Power supply wiring 13 is formed between nanosheets 23a and 23b and between nanosheets 26a and 26b in a plan view.

[0141] With the above configuration, in the 1-port SRAM cells formed side by side in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are exposed from the gate wiring 31. The surfaces of the nanosheets 23b facing each other in the X direction are exposed from the gate wiring 33. The surfaces of the nanosheets 24a facing each other in the X direction are exposed from the gate wiring 34. The surfaces of the nanosheets 26b facing each other in the X direction are exposed from the gate wiring 36. This makes it possible to reduce the distance d1 in the X direction between the transistors PG21, the distance d1 in the X direction between the transistors PD12, the distance d1 in the X direction between the transistors PD21, and the distance d1 in the X direction between the transistors PG12, and thus the area of ​​the semiconductor memory device can be reduced.

[0142] In addition, the power supply wiring 11 for supplying the power supply voltage VDD and the power supply wirings 12 and 13 for supplying the power supply voltage VSS formed in the buried wiring layer can reduce the width in the X direction of the wiring 71 for supplying the power supply voltage VDD and the width in the X direction of the wirings 72 and 73 for supplying the power supply voltage VSS in the M1 wiring layer, and therefore the width in the X direction of the wirings 75 and 74 which become the bit lines BL and BLB can be increased, respectively. This can increase the speed and improve the write characteristics of the semiconductor memory device.

[0143] Moreover, the power supply wiring 12 is formed between the nanosheets 21a and 21b and between the nanosheets 24a and 24b in a plan view. The power supply wiring 13 is formed between the nanosheets 23a and 23b and between the nanosheets 26a and 26b in a plan view. Moreover, the surfaces of the nanosheets 21a and 21b facing each other in the X direction are not exposed from the gate wiring 31. The surfaces of the nanosheets 23a and 23b facing each other in the X direction are not exposed from the gate wiring 33. The surfaces of the nanosheets 24a and 24b facing each other in the X direction are not exposed from the gate wiring 34. The surfaces of the nanosheets 26a and 26b facing each other in the X direction are not exposed from the gate wiring 36. Therefore, the power supply wiring 12 is formed between the transistors PG21 and PG22 and between the transistors PD21 and PD22, whose distance in the X direction is greater than the distance d1 in a plan view. The power supply wiring 13 is formed between the transistors PD11, PD12 and between the transistors PG11, PG12, whose distance in the X direction is greater than the distance d1 in a plan view. That is, the power supply wiring 12 can be easily formed without increasing the distance in the X direction between the transistors PG21, PG22 and the distance in the X direction between the transistors PD21, PD22. The power supply wiring 13 can be easily formed without increasing the distance in the X direction between the transistors PD11, PD12 and the distance in the X direction between the transistors PG11, PG12. This makes it possible to suppress an increase in the area of ​​the semiconductor memory device.

[0144] Therefore, in a semiconductor memory device including a one-port SRAM cell using a fork sheet transistor, it is possible to increase the speed and improve the write characteristics while suppressing an increase in area.

[0145] Furthermore, the nanosheets 21a, 21b, 22, 23a, 23b, 24a, 24b, 25, 26a, and 26b have the same width in the X direction, which makes it possible to uniformize the shapes of the nanosheets of the semiconductor memory device, thereby improving ease of manufacture.

[0146] It is sufficient to have at least one of the wirings 71 to 73. This allows the width of the wirings 74 and 75 in the X direction to be increased, thereby enabling the semiconductor memory device to operate at a higher speed and with improved write characteristics.

[0147] Moreover, it is sufficient that there is at least one of the power supply wirings 11 to 13.

[0148] (Modification) 9 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the second embodiment. Specifically, FIG. 9(a) shows the upper part of the cell, and FIG. 9(b) shows the lower part of the cell. In FIG. 9, the surface of each nanosheet opposite to that in FIG. 8 in the X direction is exposed from the gate wiring. Also, the arrangement of the power supply wiring formed in the buried wiring layer is different.

[0149] Power supply wirings 11 to 14 extending in the Y direction are formed in the buried wiring layer. The power supply wirings 11 and 14 supply a power supply voltage VDD. The power supply wirings 12 and 13 supply a power supply voltage VSS.

[0150] As shown in FIG. 9(b), gate wirings 31a, 31b, 32, 33a, 33b, 34a, 34b, 35, 36a, and 36b are formed extending in the X and Z directions. The gate wiring 31a overlaps with the nanosheet 21a in a planar view. The gate wiring 31b overlaps with the nanosheet 21b in a planar view. The gate wiring 33a overlaps with the nanosheets 22 and 23a in a planar view. The gate wiring 33b overlaps with the nanosheet 23b in a planar view. The gate wiring 34a overlaps with the nanosheet 24a in a planar view. The gate wiring 34b overlaps with the nanosheets 24b and 25 in a planar view. The gate wiring 36a overlaps with the nanosheet 26a in a planar view. The gate wiring 36b overlaps with the nanosheet 26b in a planar view.

[0151] In FIG. 9, the gate wiring 31a serves as the gate of the transistor PG21. The gate wiring 31b serves as the gate of the transistor PG22. The gate wiring 33a serves as the gate of the load transistor PU1 and the transistor PD11. The gate wiring 33b serves as the gate of the transistor PD12. The gate wiring 34a serves as the gate of the transistor PD21. The gate wiring 34b serves as the gate of the transistor PD22 and the load transistor PU2. The gate wiring 36a serves as the gate of the transistor PG11. The gate wiring 36b serves as the gate of the transistor PG12.

[0152] The gate wirings 31a and 31b are connected to each other via a bridge portion 135. The gate wirings 32 and 33a are connected to each other via a bridge portion 131. The gate wirings 33a and 33b are connected to each other via a bridge portion 136. The gate wirings 34a and 34b are connected to each other via a bridge portion 137. The gate wirings 34b and 35 are connected to each other via a bridge portion 132. The gate wirings 36a and 36b are connected to each other via a bridge portion 138.

[0153] The local wiring 52 is connected to the power supply wiring 14 via a contact 115. The local wiring 57 is connected to the power supply wiring 11 via a contact 114.

[0154] The wiring 76 is connected to the gate wiring 31a via a contact 87. The wiring 77 is connected to the gate wiring 36b via a contact 88.

[0155] 9, the surfaces of the nanosheets 21a, 23a, 24a, 25, and 26a on the right side of the drawing are not covered by the gate wirings 31a, 33a, 34a, 34b, and 36a, respectively, and are exposed from the gate wirings 31a, 33a, 34a, 34b, and 36a, respectively. The surfaces of the nanosheets 21b, 22, 23b, 24b, and 26b on the left side of the drawing are not covered by the gate wirings 31b, 33a, 33b, 34b, and 36b, respectively, and are exposed from the gate wirings 31b, 33a, 33b, 34b, and 36b, respectively.

[0156] That is, the surfaces of the nanosheets 21a and 21b that face each other in the X direction are exposed from the gate wirings 31a and 31b, respectively. The surfaces of the nanosheets 23a and 23b that face each other in the X direction are exposed from the gate wirings 33a and 33b, respectively. The surfaces of the nanosheets 24a and 24b that face each other in the X direction are exposed from the gate wirings 34a and 34b, respectively. The surfaces of the nanosheets 26a and 26b that face each other in the X direction are exposed from the gate wirings 36a and 36b, respectively.

[0157] Moreover, the nanosheet 22 is formed above the right side of the nanosheet 25 in the figure. That is, the surfaces of the nanosheets 22 and 25 that face each other in the X direction are exposed from the gate wirings 33a and 34b, respectively.

[0158] Here, the left surfaces of the nanosheets 21a, 23a, 24a, 25, and 26a are covered by the gate wirings 31a, 33a, 34a, 34b, and 36a, respectively, and are not exposed from the gate wirings 31a, 33a, 34a, 34b, and 36a, respectively. The right surfaces of the nanosheets 21b, 22, 23b, 24b, and 26b are covered by the gate wirings 31b, 33a, 33b, 34b, and 36b, respectively, and are not exposed from the gate wirings 31b, 33a, 33b, 34b, and 36b, respectively.

[0159] That is, the surfaces of the nanosheets 22 and 23a that face each other in the X direction are not exposed from the gate wiring 33a. The surfaces of the nanosheets 24b and 25 that face each other in the X direction are not exposed from the gate wiring 34b.

[0160] Moreover, the nanosheets 21a and 24a are arranged close to the cell boundary on the left side of the drawing. The nanosheets 23b and 26b are arranged close to the cell boundary on the right side of the drawing. In the 1-port SRAM cell of FIG. 9, the 1-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the 1-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are not exposed from the gate wiring 31a. The surfaces of the nanosheets 23b facing each other in the X direction are not exposed from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction are not exposed from the gate wiring 34a. The surfaces of the nanosheets 26b facing each other in the X direction are not exposed from the gate wiring 36b.

[0161] 9, power supply wiring 11 is formed between nanosheets 24b and 25 in plan view. Power supply wiring 12 is formed at the cell boundary on the left side of the drawing in plan view. Power supply wiring 13 is formed at the cell boundary on the right side of the drawing in plan view. Power supply wiring 14 is formed between nanosheets 22 and 23a in plan view.

[0162] According to the layout structure of FIG. 9, the surfaces of the nanosheets 21a and 21b facing each other in the X direction are exposed from the gate wirings 31a and 31b, respectively. The surfaces of the nanosheets 23a and 23b facing each other in the X direction are exposed from the gate wirings 33a and 33b, respectively. The surfaces of the nanosheets 24a and 24b facing each other in the X direction are exposed from the gate wirings 34a and 34b, respectively. The surfaces of the nanosheets 26a and 26b facing each other in the X direction are exposed from the gate wirings 36a and 36b, respectively. This makes it possible to reduce the distance d1 in the X direction between the transistors PG21 and PG22, the distance d1 in the X direction between the transistors PD11 and PD12, the distance d1 in the X direction between the transistors PD21 and PD22, and the distance d1 in the X direction between the transistors PG11 and PG12, respectively, and thus to reduce the area of ​​the semiconductor memory device.

[0163] In addition, the power supply wiring 11, 14 that supplies the power supply voltage VDD are formed in the buried wiring layer. The power supply wiring 11 is formed between the nanosheets 24b, 25 in a plan view. The power supply wiring 14 is formed between the nanosheets 22, 23a in a plan view. In addition, the surfaces of the nanosheets 22, 23a that face each other in the X direction are not exposed from the gate wiring 33a. The surfaces of the nanosheets 24b, 25 that face each other are not exposed from the gate wiring 34b. Therefore, the power supply wiring 11 is formed between the transistor PD22 and the load transistor PU2, whose distance in the X direction is greater than the distance d1 in a plan view. The power supply wiring 14 is formed between the load transistor PU1 and the transistor PD11, whose distance in the X direction is greater than the distance d1 in a plan view. That is, the power supply wiring 11 can be easily formed without widening the distance in the X direction between the transistor PD22 and the load transistor PU2. The power supply wiring 14 can be easily formed without widening the distance in the X direction between the load transistor PU1 and the transistor PD11. This makes it possible to increase the speed of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0164] In addition, power supply wiring 12, 13 for supplying a power supply voltage VSS are formed in the buried wiring layer. The power supply wiring 12, 13 are formed at the cell boundaries on the left side and the right side of the drawing in a plan view, respectively. In addition, in the 1-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are not exposed from the gate wiring 31a. The surfaces of the nanosheets 23b facing each other in the X direction are not exposed from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction are not exposed from the gate wiring 34a. The surfaces of the nanosheets 26b facing each other in the X direction are not exposed from the gate wiring 36b. Therefore, the power supply wiring 12 is formed between the transistors PG21 and between the transistors PD21 that are separated by a distance greater than the distance d1 in a plan view. The power supply wiring 13 is formed between the transistors PD12 and between the transistors PG12 that are separated by a distance greater than the distance d1 in a plan view. That is, the power supply wiring 12 can be easily formed without increasing the distance in the X direction between the transistors PG21 and between the transistors PD21. The power supply wiring 13 can be easily formed without increasing the distance in the X direction between the transistors PD12 and between the transistors PG12. This makes it possible to increase the speed of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0165] In addition, the same effects as those in FIG. 8 can be obtained.

[0166] At least one of the power supply wirings 11 to 14 is sufficient.

[0167] (Embodiment 3) FIG. 10 is a plan view showing an example of the layout structure of a 1-port SRAM cell according to the third embodiment. Specifically, FIG. 10(a) shows the lower part of the cell, and FIG. 10(b) shows the upper part of the cell. In the 1-port SRAM cell of FIG. 10, the 1-port SRAM circuit shown in FIG. 4 is configured by load transistors PU1 and PU2 and transistors PD11, PD12, PD13, PD21, PD22, PD23, PG11, PG12, PG13, PG21, PG22, and PG23. In FIG. 10, the drive transistors PD1 and PD2 and the access transistors PG1 and PG2 are each configured by three transistors. Specifically, the drive transistor PD1 is configured by transistors PD11, PD12, and PD13. The drive transistor PD2 is configured by transistors PD21, PD22, and PD23. The access transistor PG1 is configured by transistors PG11, PG12, and PG13. The access transistor PG2 is configured by transistors PG21, PG22, and PG23. Moreover, the 1-port SRAM cell in FIG. 10 has 1-port SRAM cells inverted in the X direction arranged on both the left and right sides of the drawing.

[0168] 10(b), power supply wirings 11 to 13, 15, and 16 extending in the Y direction are formed in the buried wiring layer. The power supply wiring 11 supplies a power supply voltage VDD. The power supply wirings 12, 13, 15, and 16 supply a power supply voltage VSS.

[0169] In addition, nanosheets 21a to 21c, 22, 23a to 23c, 24a to 24c, 25, and 26a to 26c are formed to extend in the X and Y directions. The nanosheets 21a to 21c, 22, and 23a to 23c are formed in the X direction in the order of nanosheets 21a, 21b, 21c, 22, 23a, 23b, and 23c. The nanosheets 24a to 24c, 25, and 26a to 26c are formed in the X direction in the order of nanosheets 24a, 24b, 24c, 25, 26a, 26b, and 26c. The nanosheets 21a, 21b, 21c, 23a, 23b, and 23c are formed in the Y direction in the order of nanosheets 24a, 24b, 24c, 26a, 26b, and 26c.

[0170] In FIG. 10, the nanosheets 21a to 21c, 22, 23a to 23c, 24a to 24c, 25, and 26a to 26c have the same width in the X direction.

[0171] In Figure 10, nanosheets 21a, 21b, 21c, 23a, 23b, 23c, 24a, 24b, 24c, 26a, 26b, and 26c serve as channel portions of transistors PG21, PG22, PG23, PD11, PD12, PD13, PD21, PD22, PD23, PG11, PG12, and PG13, respectively.

[0172] The gate wiring 31a overlaps with the nanosheet 21a in a planar view. The gate wiring 31b overlaps with the nanosheets 21b and 21c in a planar view. The gate wiring 32 overlaps with the nanosheet 22 in a planar view. The gate wiring 33a overlaps with the nanosheets 23a and 23b in a planar view. The gate wiring 33b overlaps with the nanosheet 23c in a planar view. The gate wiring 34a overlaps with the nanosheet 24a in a planar view. The gate wiring 34b overlaps with the nanosheets 24b and 24c in a planar view. The gate wiring 35 overlaps with the nanosheet 25 in a planar view. The gate wiring 36a overlaps with the nanosheets 26a and 26b in a planar view. The gate wiring 36b overlaps with the nanosheet 26c in a planar view.

[0173] In FIG. 10, gate wiring 31a serves as the gate of transistor PG21. Gate wiring 31b serves as the gate of transistors PG22 and PG23. Gate wiring 32 serves as the gate of load transistor PU1. Gate wiring 33a serves as the gate of transistors PD11 and PD12. Gate wiring 33b serves as the gate of transistor PD13. Gate wiring 34a serves as the gate of transistor PD21. Gate wiring 34b serves as the gate of transistors PD22 and PD23. Gate wiring 35 serves as the gate of transistor PU2. Gate wiring 36a serves as the gate of transistors PG11 and PG12. Gate wiring 36b serves as the gate of transistor PG13.

[0174] The gate wirings 31a and 31b are connected to each other via a bridge portion 135. The gate wirings 32 and 33a are connected to each other via a bridge portion 131. The gate wirings 33a and 33b are connected to each other via a bridge portion 136. The gate wirings 34a and 34b are connected to each other via a bridge portion 137. The gate wirings 34b and 35 are connected to each other via a bridge portion 132. The gate wirings 36a and 36b are connected to each other via a bridge portion 138.

[0175] Pads 40c, 41c, 42c, 43c, 44c, and 45c doped with an N-type semiconductor are formed on the upper side of nanosheet 21c in the figure, between nanosheets 21c and 24c, the lower side of nanosheet 24c in the figure, the upper side of nanosheet 23c in the figure, between nanosheets 23c and 26c, and the lower side of nanosheet 26c in the figure. Pads 40c and 41c form the node of transistor PG23. Pads 41c and 42c form the node of transistor PD23. Pads 43c and 44c form the node of transistor PD13. Pads 44c and 45c form the node of transistor PG13.

[0176] With this arrangement, in FIG. 10(b), each transistor is arranged point-symmetrically with respect to the center point of the cell. Specifically, the load transistors PU1 and PU2 are arranged point-symmetrically with respect to the center point of the cell. The transistors PD11 and PD23 are arranged point-symmetrically with respect to the center point of the cell. The transistors PD12 and PD22 are arranged point-symmetrically with respect to the center point of the cell. The transistors PD13 and PD21 are arranged point-symmetrically with respect to the center point of the cell. The transistors PG11 and PG23 are arranged point-symmetrically with respect to the center point of the cell. The transistors PG12 and PG22 are arranged point-symmetrically with respect to the center point of the cell. The transistors PG13 and PG21 are arranged point-symmetrically with respect to the center point of the cell.

[0177] The local wiring 51 is connected to the pads 40a, 40b, and 40c. The local wiring 53 is connected to the pads 43a, 43b, and 43c. The local wiring 54 is connected to the pads 41a, 41b, 41c, and 48. The local wiring 55 is connected to the pads 47, 44a, 44b, and 44c. The local wiring 56 is connected to the pads 42a, 42b, and 42c. The local wiring 58 is connected to the pads 45a, 45b, and 45c.

[0178] Furthermore, the local wiring 53 is connected to the power supply wiring 16 via a contact 116. The local wiring 56 is connected to the power supply wiring 15 via a contact 117.

[0179] 7, some of the local wirings 51-58 are formed so that at least one of their ends is located between the left end and the right end of the pad to which they are connected. For example, the left end of the local wiring 51 is located between the left end and the right end of the pad 40a.

[0180] 7, shared contact 61 is formed so that its left end is located to the right of the left end of pad 48, and its right end is located to the left of the right end of pad 48. Shared contact 62 is formed so that its left end is located to the right of the left end of pad 47, and its right end is located to the left of the right end of pad 47, as in Fig. 7.

[0181] Here, the left surfaces of the nanosheets 21b, 23a, 23c, 24b, 25, 26a, and 26c are not covered by the gate wirings 31b, 33a, 33b, 34b, 35, 36a, and 36b, respectively, and are exposed from the gate wirings 31b, 33a, 33b, 34b, 35, 36a, and 36b, respectively. The right surfaces of the nanosheets 21a, 21c, 22, 23b, 24a, 24c, and 26b are not covered by the gate wirings 31a, 31b, 32, 33a, 34a, 34b, and 36a, respectively, and are exposed from the gate wirings 31a, 31b, 32, 33a, 34a, 34b, and 36a, respectively.

[0182] That is, the surfaces of the nanosheets 21a and 21b facing each other in the X direction are exposed from the gate wirings 31a and 31b, respectively. The surfaces of the nanosheets 22 and 23a facing each other in the X direction are exposed from the gate wirings 32 and 33a, respectively. The surfaces of the nanosheets 23b and 23c facing each other in the X direction are exposed from the gate wirings 33a and 33b, respectively. The surfaces of the nanosheets 24a and 24b facing each other in the X direction are exposed from the gate wirings 34a and 34b, respectively. The surfaces of the nanosheets 24c and 25 facing each other in the X direction are exposed from the gate wirings 34b and 35, respectively. The surfaces of the nanosheets 26b and 26c facing each other in the X direction are exposed from the gate wirings 36a and 36b, respectively.

[0183] In addition, the surfaces of the nanosheets 21b, 23a, 23c, 24b, 25, 26a, and 26c on the right side of the drawing are covered by the gate wirings 31b, 33a, 33b, 34b, 35, 36a, and 36b, respectively, and are not exposed from the gate wirings 31b, 33a, 33b, 34b, 35, 36a, and 36b, respectively. The surfaces of the nanosheets 21a, 21c, 22, 23b, 24a, 24c, and 26b on the left side of the drawing are covered by the gate wirings 31a, 31b, 32, 33a, 34a, 34b, and 36a, respectively, and are not exposed from the gate wirings 31a, 31b, 32, 33a, 34a, 34b, and 36a, respectively.

[0184] That is, the surfaces of the nanosheets 21b and 21c facing each other in the X direction are not exposed from the gate wiring 31b. The surfaces of the nanosheets 23a and 23b facing each other in the X direction are not exposed from the gate wiring 33a. The surfaces of the nanosheets 24b and 24c facing each other in the X direction are not exposed from the gate wiring 34b. The surfaces of the nanosheets 26a and 26b facing each other in the X direction are not exposed from the gate wiring 36a.

[0185] Moreover, the nanosheet 22 is formed above the right side of the nanosheet 25 in the figure. That is, the surfaces of the nanosheets 22 and 25 that face each other in the X direction are not exposed from the gate wirings 32 and 35, respectively.

[0186] Moreover, the nanosheets 21a and 24a are formed close to the cell boundary on the left side of the drawing. The nanosheets 23c and 26c are formed close to the cell boundary on the right side of the drawing. In the 1-port SRAM cell of FIG. 10, 1-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the 1-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are not exposed from the gate wiring 31a. The surfaces of the nanosheets 23c facing each other in the X direction are not exposed from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction are not exposed from the gate wiring 34a. The surfaces of the nanosheets 26c facing each other in the X direction are not exposed from the gate wiring 36b.

[0187] In FIG. 10, power supply wiring 11 is formed between nanosheets 22 and 25 in plan view. Power supply wiring 12 is formed between nanosheets 21b and 21c and between nanosheets 24b and 24c in plan view. Power supply wiring 13 is formed between nanosheets 23a and 23b and between nanosheets 26a and 26b in plan view. Power supply wiring 15 is formed at the cell boundary on the left side of the drawing in plan view. Power supply wiring 16 is formed at the cell boundary on the right side of the drawing in plan view.

[0188] With the above configuration, the nanosheets 21a and 21b have their surfaces facing each other in the X direction exposed from the gate wirings 31a and 31b, respectively. The nanosheets 23b and 23c have their surfaces facing each other in the X direction exposed from the gate wirings 33a and 33b, respectively. The nanosheets 24a and 24b have their surfaces facing each other in the X direction exposed from the gate wirings 34a and 34b, respectively. The nanosheets 26b and 26c have their surfaces facing each other in the X direction exposed from the gate wirings 36a and 36b, respectively. This makes it possible to reduce the distance d1 in the X direction between the transistors PG21 and PG22, the distance d1 in the X direction between the transistors PD12 and PD13, the distance d1 in the X direction between the transistors PD21 and PD22, and the distance d1 in the X direction between the transistors PG12 and PG13, respectively, and thus to reduce the area of ​​the semiconductor memory device.

[0189] Furthermore, by forming the power supply wiring 11 for supplying the power supply voltage VDD and the power supply wirings 12, 13, 15, and 16 for supplying the power supply voltage VSS in the buried wiring layer, it is possible to reduce the width in the X direction of the wiring 71 for supplying the power supply voltage VDD and the width in the X direction of the wirings 72 and 73 for supplying the power supply voltage VSS in the M1 wiring layer. This allows the width in the X direction of the wirings 75 and 74 which become the bit lines BL and BLB to be respectively increased, thereby enabling the speedup and write characteristics of the semiconductor memory device to be improved.

[0190] Moreover, the power supply wirings 15 and 16 are formed at the cell boundaries on the left and right sides of the drawing in plan view. Moreover, in the 1-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are not exposed from the gate wiring 31a. The surfaces of the nanosheets 23c facing each other in the X direction are not exposed from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction are not exposed from the gate wiring 34a. The surfaces of the nanosheets 26c facing each other in the X direction are not exposed from the gate wiring 36b. Therefore, the power supply wiring 15 is formed between the transistors PG21 and between the transistors PD21, where the distance between the transistors in the X direction is larger than the distance d1 in plan view. The power supply wiring 16 is formed between the transistors PD13 and between the transistors PG13, where the distance between the transistors in the X direction is larger than the distance d1 in plan view. That is, the power supply wiring 15 can be easily formed without increasing the distance between the transistors PG21 in the X direction and the distance between the transistors PD21 in the X direction. The power supply wiring 13 can be easily formed without increasing the distance between the transistors PD13 in the X direction and the distance between the transistors PG13 in the X direction. This makes it possible to suppress an increase in the area of ​​the semiconductor memory device.

[0191] Therefore, in a semiconductor memory device including a one-port SRAM cell using a fork sheet transistor, it is possible to increase the speed and improve the write characteristics while suppressing an increase in area.

[0192] It should be noted that some of the power supply wirings 11 to 13, 15, and 16 may be omitted, and at least one of them is sufficient.

[0193] (Variation 1) 11 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the third embodiment. Specifically, FIG. 11(a) shows the upper part of the cell, and FIG. 11(b) shows the lower part of the cell. In FIG. 11, the surface of each nanosheet opposite to that in FIG. 10 in the X direction is exposed from the gate wiring. Also, the arrangement of the wiring formed in the buried wiring layer is different.

[0194] The buried wiring layer is formed with power supply wirings 11 to 14. The power supply wirings 11 and 14 supply a power supply voltage VDD. The power supply wirings 12 and 13 supply a power supply voltage VSS.

[0195] As shown in FIG. 11(b), gate wirings 31a, 31b, 32, 33a, 33b, 34a, 34b, 35, 36a, and 36b are formed. The gate wiring 31a overlaps with the nanosheets 21a and 21b in a planar view. The gate wiring 31b overlaps with the nanosheet 21c in a planar view. The gate wiring 33a overlaps with the nanosheets 22 and 23a in a planar view. The gate wiring 33b overlaps with the nanosheets 23b and 23c in a planar view. The gate wiring 34a overlaps with the nanosheets 24a and 24b in a planar view. The gate wiring 34b overlaps with the nanosheets 24c and 25 in a planar view. The gate wiring 36a overlaps with the nanosheet 26a in a planar view. The gate wiring 36b overlaps with the nanosheets 26b and 26c in a planar view.

[0196] In FIG. 11, the gate wiring 31a serves as the gates of the transistors PG21 and PG22. The gate wiring 31b serves as the gate of the transistor PG23. The gate wiring 33a serves as the gates of the load transistor PU1 and the transistor PD11. The gate wiring 33b serves as the gates of the transistors PD12 and PD13. The gate wiring 34a serves as the gates of the transistors PD21 and PD22. The gate wiring 34b serves as the gates of the transistor PD23 and the load transistor PU2. The gate wiring 36a serves as the gate of the transistor PG11. The gate wiring 36b serves as the gates of the transistors PG12 and PG13.

[0197] The gate wiring 31a is connected to the gate wiring 31a of the 1-port SRAM cell arranged on the left side of the 1-port SRAM cell in the drawing via a bridge portion 133. The gate wirings 31a and 31b are connected to each other via a bridge portion 135. The gate wirings 32 and 33a are connected to each other via a bridge portion 131. The gate wirings 33a and 33b are connected to each other via a bridge portion 136. The gate wirings 34a and 34b are connected to each other via a bridge portion 137. The gate wirings 34b and 35 are connected to each other via a bridge portion 132. The gate wirings 36a and 36b are connected to each other via a bridge portion 138. The gate wiring 36b is connected to the gate wiring 36b of the 1-port SRAM cell arranged on the right side of the 1-port SRAM cell in the drawing via a bridge portion 134.

[0198] The wiring 76 is connected to the gate wiring 31a via a contact 87 and a bridge portion 133. The wiring 77 is connected to the gate wiring 36b via a contact 88 and a bridge portion 134.

[0199] 11, the surfaces of the nanosheets 21b, 23a, 23c, 24b, 25, 26a, and 26c on the right side of the drawing are not covered by the gate wirings 31a, 33a, 33b, 34a, 34b, 36a, and 36b, respectively, and are exposed from the gate wirings 31a, 33a, 33b, 34a, 34b, 36a, and 36b, respectively. The surfaces of the nanosheets 21a, 21c, 22, 23b, 24a, 24c, and 26b on the left side of the drawing are not covered by the gate wirings 31a, 31b, 33a, 33b, 34a, 34b, and 36b, respectively, and are exposed from the gate wirings 31a, 31b, 33a, 33b, 34a, 34b, and 36b, respectively.

[0200] That is, the surfaces of the nanosheets 21b and 21c facing each other in the X direction are exposed from the gate wirings 31a and 31b, respectively. The surfaces of the nanosheets 23a and 23b facing each other in the X direction are exposed from the gate wirings 33a and 33b, respectively. The surfaces of the nanosheets 24b and 24c facing each other in the X direction are exposed from the gate wirings 34a and 34b, respectively. The surfaces of the nanosheets 26a and 26b facing each other in the X direction are exposed from the gate wirings 36a and 36b, respectively.

[0201] Moreover, the nanosheet 22 is formed above the right side of the nanosheet 25 in the figure. That is, the surfaces of the nanosheets 22 and 25 that face each other in the X direction are exposed from the gate wirings 33a and 34b, respectively.

[0202] Moreover, the nanosheets 21a and 24a are arranged close to the cell boundary on the left side of the drawing. The nanosheets 23c and 26c are arranged close to the cell boundary on the right side of the drawing. In the 1-port SRAM cell of FIG. 11, 1-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the 1-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are exposed from the gate wiring 31a. The surfaces of the nanosheets 23c facing each other in the X direction are exposed from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction are exposed from the gate wiring 34a. The surfaces of the nanosheets 26c facing each other in the X direction are exposed from the gate wiring 36b.

[0203] The left surfaces of the nanosheets 21b, 23a, 23c, 24b, 25, 26a, and 26c are covered by the gate wirings 31a, 33a, 33b, 34a, 34b, 36a, and 36b, respectively, and are not exposed from the gate wirings 31a, 33a, 33b, 34a, 34b, 36a, and 36b, respectively. The right surfaces of the nanosheets 21a, 21c, 22, 23b, 24a, 24c, and 26b are covered by the gate wirings 31a, 31b, 33a, 33b, 34a, 34b, and 36b, respectively, and are not exposed from the gate wirings 31a, 31b, 33a, 33b, 34a, 34b, and 36b, respectively.

[0204] That is, the surfaces of the nanosheets 21a and 21b that face each other in the X direction are not exposed from the gate wiring 31a. The surfaces of the nanosheets 22 and 23a that face each other in the X direction are not exposed from the gate wiring 33a. The surfaces of the nanosheets 23b and 23c that face each other in the X direction are not exposed from the gate wiring 33b. The surfaces of the nanosheets 24a and 24b that face each other in the X direction are not exposed from the gate wiring 34a. The surfaces of the nanosheets 24c and 25 that face each other in the X direction are not exposed from the gate wiring 34b. The surfaces of the nanosheets 26b and 26c that face each other in the X direction are not exposed from the gate wiring 36b.

[0205] 11, power supply wiring 12 is formed between nanosheets 21a and 21b and between nanosheets 24a and 24b in a plan view. Power supply wiring 11 is formed between nanosheets 24c and 25 in a plan view. Power supply wiring 14 is formed between nanosheets 22 and 23a in a plan view. Power supply wiring 13 is formed between nanosheets 23b and 23c and between nanosheets 26b and 26c in a plan view.

[0206] According to the layout structure of FIG. 11, in the 1-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21a facing each other in the X direction are exposed from the gate wiring 31a. The surfaces of the nanosheets 23c facing each other in the X direction are exposed from the gate wiring 33b. The surfaces of the nanosheets 24a facing each other in the X direction are exposed from the gate wiring 34a. The surfaces of the nanosheets 26c facing each other in the X direction are exposed from the gate wiring 36b. This makes it possible to reduce the distance d1 in the X direction between the transistors PG21, the distance d1 in the X direction between the transistors PD13, the distance d1 in the X direction between the transistors PD21, and the distance d1 in the X direction between the transistors PG13, and thus the area of ​​the semiconductor memory device can be reduced.

[0207] In addition, power supply wirings 12 and 13 for supplying a power supply voltage VSS are formed in the embedded wiring layer. The power supply wiring 12 is formed between the nanosheets 21a and 21b and between the nanosheets 24a and 24b in a plan view. The power supply wiring 13 is formed between the nanosheets 23b and 23c and between the nanosheets 26b and 26c in a plan view. In addition, the surfaces of the nanosheets 21a and 21b facing each other in the X direction are not exposed from the gate wiring 31a. The surfaces of the nanosheets 22 and 23a facing each other in the X direction are not exposed from the gate wiring 33a. The surfaces of the nanosheets 23b and 23c facing each other in the X direction are not exposed from the gate wiring 33b. The surfaces of the nanosheets 24a and 24b facing each other in the X direction are not exposed from the gate wiring 34a. The surfaces of the nanosheets 24c and 25 facing each other in the X direction are not exposed from the gate wiring 34b. The surfaces of the nanosheets 26b and 26c facing each other in the X direction are not exposed from the gate wiring 36b. Therefore, the power supply wiring 12 is formed between the transistors PG21 and PG22 and between the transistors PD21 and PD22, where the distance in the X direction of the transistors is greater than the distance d1 in a plan view. The power supply wiring 13 is formed between the transistors PD12 and PD13 and between the transistors PG12 and PG13, where the distance in the X direction of the transistors is greater than the distance d1 in a plan view. That is, the power supply wiring 12 can be easily formed without widening the distance in the X direction of the transistors PG21 and PG22 and the distance in the X direction of the transistors PD21 and PD22. The power supply wiring 13 can be easily formed without widening the distance in the X direction of the transistors PD12 and PD13 and the distance in the X direction of the transistors PG12 and PG13. This makes it possible to increase the speed of the semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device.

[0208] In addition, the same effects as those in FIG. 10 can be obtained.

[0209] (Variation 2) 12 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the third embodiment. Specifically, FIG. 12(a) shows the lower part of the cell, and FIG. 12(b) shows the upper part of the cell. In FIG. 12, compared with FIG. 10, the access transistors PG1 and PG2 are each composed of two transistors.

[0210] In Fig. 12, the nanosheets 21c and 26a and the pads 40c and 45a in Fig. 10 are omitted. That is, the access transistor PG2 is composed of transistors PG21 and PG22. The access transistor PG1 is composed of transistors PG12 and PG13.

[0211] The layout structure of FIG. 12 can provide the same effect as that of FIG.

[0212] (Variation 3) 13 is a plan view showing another example of the layout structure of the 1-port SRAM cell according to the third embodiment. Specifically, FIG. 13(a) shows the lower part of the cell, and FIG. 13(b) shows the upper part of the cell. Compared with FIG. 11, FIG. 13 shows that the access transistors PG1 and PG2 are each composed of two transistors. Also, the gate wirings 31a and 31b are not connected. The gate wirings 36a and 36b are not connected.

[0213] In Fig. 13, the nanosheets 21c and 26a and the pads 40c and 45a in Fig. 11 are omitted. That is, the access transistor PG2 is composed of transistors PG21 and PG22. The access transistor PG1 is composed of transistors PG12 and PG13.

[0214] 11 are omitted. That is, the gate wirings 31a and 31b are not connected. The gate wirings 36a and 36b are not connected.

[0215] 13, the gate wirings 31a and 31b are not connected. The gate wirings 36a and 36b are not connected. This allows the gate wirings 31b and 31a, which are not functioning as part of the transistor, to be separated from the circuit configured in the 1-port SRAM cell, thereby reducing the load capacitance of the word lines.

[0216] In addition, the same effects as those of the layout structure in FIG. 11 can be obtained.

[0217] In the above-described embodiments and modified examples, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0218] In addition, in each of the above-described embodiments, the cross-sectional shape of the nanosheet is rectangular, but this is not limited thereto, and may be, for example, a square, a circle, an ellipse, or the like. [Industrial Applicability]

[0219] In the present disclosure, in a layout structure of a one-port SRAM cell using a fork sheet transistor, it is possible to increase the speed and improve the write characteristics of a semiconductor memory device while suppressing an increase in the area of ​​the semiconductor memory device. [Explanation of symbols]

[0220] 11~16 Power wiring 21-26, 21a-21c, 23a-23c, 24a-24c, 26a-26c Nanosheets 31~36, 31a, 31b, 33a, 33b, 34a, 34b, 36a, 36b Gate wiring 40~49,40a~46a,40b~46b,40c~46c Pads 51~58 Local wiring 61,62 Shared Contact 71~77,91~93 Wiring PU1, PU2 load transistor PD1, PD2 drive transistor PG1, PG2 access transistor PG11~PG13, PG21~PG23, PD11~PD13, PD21~PD23 Transistor BL,BLB bit lines WL Word Line

Claims

1. A semiconductor memory device including a 1-port SRAM cell, The one-port SRAM cell comprises: a first transistor having one node connected to a first power supply supplying a first voltage, another node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, another node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node, another node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; a fourth transistor having one node connected to the second node, another node connected to the second power supply, and a gate connected to the first node; a fifth transistor having one node connected to the first bit line, another node connected to the first node, and a gate connected to the word line; a sixth transistor having one node connected to a second bit line forming a complementary bit line pair with the first bit line, another node connected to the second node, and a gate connected to the word line; Equipped with The first to sixth transistors are First to sixth nanosheets extending in a first direction; first to sixth gate wirings respectively surrounding the first to sixth nanosheets in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions; Each of them has The first, third and sixth nanosheets are formed in the second direction in the order of the sixth, first and third nanosheets, The second, fourth, and fifth nanosheets are formed in the second direction in the order of the fourth, second, and fifth nanosheets, the first to sixth nanosheets have surfaces on either side in the second direction exposed from the first to sixth gate wirings, respectively; a first power supply wiring is formed below the first to sixth transistors, the first power supply wiring extending in the first direction between the first nanosheet and the second nanosheet in a plan view and supplying the first voltage; the first nanosheet has a second side surface, which is opposite to a first side surface on which the first power supply wiring is formed, exposed from the first gate wiring in the second direction; The second nanosheet has a first side surface, which is opposite to the second side on which the first power supply wiring is formed, exposed from the second gate wiring in the second direction. A semiconductor memory device comprising:

2. 2. The semiconductor memory device according to claim 1, The one-port SRAM cell comprises: a first wiring extending in the first direction and serving as the first bit line; a second wiring extending in the first direction and serving as the second bit line; Further equipped with the first and second wirings are formed in a first wiring layer that is above the first to sixth transistors; At least one of the first and second wirings has a width in the second direction that is wider than a wiring that has a minimum width in the second direction among the wirings formed in the first wiring layer. A semiconductor memory device comprising:

3. 2. The semiconductor memory device according to claim 1, The one-port SRAM cell comprises: a third wiring extending in the second direction and supplying the second voltage; a fourth wiring extending in the second direction and supplying the second voltage; a fifth wiring extending in the second direction and serving as the word line; Further equipped with the third to fifth wirings are formed in a second wiring layer above the first to sixth transistors, The fifth wiring is formed between the third wiring and the fourth wiring in a plan view. A semiconductor memory device comprising:

4. 2. The semiconductor memory device according to claim 1, The one-port SRAM cell comprises: a second power supply wiring extending in the first direction on the first side of the fourth nanosheet in a plan view below the first to sixth transistors and supplying the second voltage; a third power supply wiring that is in a layer below the first to sixth transistors, extends in the first direction on the second side of the third nanosheet in a plan view, and supplies the second voltage; Further equipped with the third nanosheet has a surface on the first side exposed from the third gate wiring, The fourth nanosheet has a surface on the second side exposed from the fourth gate wiring. A semiconductor memory device comprising:

5. 5. The semiconductor memory device according to claim 4, the second power supply wiring is formed on a cell boundary on the first side of the 1-port SRAM cell in a plan view; the third power supply wiring is formed on a cell boundary on the second side of the 1-port SRAM cell in a plan view; the fourth and sixth nanosheets are formed adjacent to a cell boundary of the one-port SRAM cell on the first side; The third and fifth nanosheets are formed adjacent to a cell boundary of the one-port SRAM cell on the second side, the fifth nanosheet has a surface on the first side exposed from the fifth gate wiring, The sixth nanosheet has a surface on the second side exposed from the sixth gate wiring. A semiconductor memory device comprising:

6. 6. The semiconductor memory device according to claim 5, the one-port SRAM cell includes a local interconnection extending in the second direction and connected to a node of any one of the first to sixth transistors; The local wiring has an end in the second direction located between both ends of the node to which it is connected. A semiconductor memory device comprising:

7. 5. The semiconductor memory device according to claim 4, The third to sixth transistors further include seventh to tenth nanosheets extending in the first direction, respectively; the third to sixth gate wirings surround the seventh to tenth nanosheets in the second direction and the third direction, respectively; The first, third, sixth, seventh and tenth nanosheets are arranged in the second direction in the order of the tenth, sixth, first, third and seventh nanosheets, The second, fourth, fifth, eighth and ninth nanosheets are arranged in the second direction. The 8th, 4th, 2nd, 5th, and 9th nanosheets are arranged in this order, the second power supply wiring is formed between the sixth nanosheet and the tenth nanosheet and between the fourth nanosheet and the eighth nanosheet in a plan view, the third power supply wiring is formed between the third nanosheet and the seventh nanosheet and between the fifth nanosheet and the ninth nanosheet in a plan view; the fifth, eighth and tenth nanosheets have the first side surfaces exposed from the fifth, fourth and sixth gate wirings, respectively; The sixth, seventh and ninth nanosheets have the second side surfaces exposed from the sixth, third and fifth gate wirings, respectively. A semiconductor memory device comprising:

8. 8. The semiconductor memory device according to claim 7, The one-port SRAM cell comprises: a fourth power supply wiring extending in the first direction at a cell boundary on the first side of the one-port SRAM cell in a layer below the first to sixth transistors and supplying the second voltage; a fifth power supply wiring extending in the first direction at a cell boundary on the second side of the one-port SRAM cell in a layer below the first to sixth transistors and supplying the second voltage; Further equipped with The third to sixth transistors further include eleventh to fourteenth nanosheets extending in the first direction, respectively; the third to sixth gate wirings surround the eleventh to fourteenth nanosheets in the second direction and the third direction, respectively; The first, third, sixth, seventh, tenth, eleventh and fourteenth nanosheets are formed in the second direction in the order of the fourteenth, tenth, sixth, first, third, seventh and eleventh nanosheets, The second, fourth, fifth, eighth, ninth, twelfth and thirteenth nanosheets are arranged in the second direction in the order of the twelfth, eighth, fourth, second, fifth, ninth and thirteenth nanosheets, the twelfth and fourteenth nanosheets are formed adjacent to a cell boundary on the first side of the one-port SRAM cell, and the second side surfaces are exposed from the fourth and sixth gate wirings, respectively; The eleventh and thirteenth nanosheets are formed in the vicinity of the cell boundary on the second side of the one-port SRAM cell, and the surfaces on the first side are exposed from the third and fifth gate wirings, respectively. A semiconductor memory device comprising:

9. 5. The semiconductor memory device according to claim 4, the third transistor further comprises seventh and eighth nanosheets extending in the first direction; the fourth transistor further comprises ninth and tenth nanosheets extending in the first direction; The fifth transistor further includes an eleventh nanosheet extending in the first direction, The sixth transistor further comprises a twelfth nanosheet extending in the first direction, the third gate wiring surrounds the seventh and eighth nanosheets in the second and third directions, the fourth gate wiring surrounds the ninth and tenth nanosheets in the second and third directions, the fifth gate wiring surrounds the eleventh nanosheet in the second direction and the third direction, the sixth gate wiring surrounds the twelfth nanosheet in the second direction and the third direction, The first, third, sixth, seventh, eighth and twelfth nanosheets are arranged in the second direction in the order of the twelfth, sixth, first, third, seventh and eighth nanosheets, The second, fourth, fifth, ninth, tenth and eleventh nanosheets are arranged in the second direction in the order of the tenth, ninth, fourth, second, fifth and eleventh nanosheets, The second power supply wiring is formed between the fourth nanosheet and the ninth nanosheet in a plan view, the third power supply wiring is formed between the third nanosheet and the seventh nanosheet in a plan view, The tenth and twelfth nanosheets are formed adjacent to a cell boundary of the one-port SRAM cell on the first side, The eighth and eleventh nanosheets are formed adjacent to a cell boundary of the one-port SRAM cell on the second side, a fourth power supply wiring is formed below the first to sixth transistors, the fourth power supply wiring extending in the first direction at a cell boundary on the first side of the one-port SRAM cell and supplying the second voltage; a fifth power supply wiring is formed below the first to sixth transistors, the fifth power supply wiring extending in the first direction at a cell boundary on the second side of the one-port SRAM cell and supplying the second voltage; the sixth, eighth, ninth and eleventh nanosheets have surfaces on the first side exposed from the sixth, third, fourth and fifth gate wirings, respectively; The fifth, seventh, tenth and twelfth nanosheets have the second side surfaces exposed from the fifth, third, fourth and sixth gate wirings, respectively. A semiconductor memory device comprising:

10. 10. The semiconductor memory device according to claim 9, The sixth and ninth nanosheets are formed at the same position in the second direction, The fifth and seventh nanosheets are formed at the same position in the second direction, The eighth and eleventh nanosheets are formed at the same position in the second direction, A semiconductor memory device, characterized in that the tenth and twelfth nanosheets are formed at the same position in the second direction.

11. A semiconductor memory device including a 1-port SRAM cell, The one-port SRAM cell comprises: a first transistor having one node connected to a first power supply supplying a first voltage, another node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, another node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node, another node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; a fourth transistor having one node connected to the second node, another node connected to the second power supply, and a gate connected to the first node; a fifth transistor having one node connected to the first bit line, another node connected to the first node, and a gate connected to the word line; a sixth transistor having one node connected to a second bit line forming a complementary bit line pair with the first bit line, another node connected to the second node, and a gate connected to the word line; Equipped with The first to sixth transistors are First to sixth nanosheets extending in a first direction; first to sixth gate wirings respectively surrounding the first to sixth nanosheets in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions; Each of them has The first, third and sixth nanosheets are formed in the second direction in the order of the sixth, first and third nanosheets, The second, fourth, and fifth nanosheets are formed in the second direction in the order of the fourth, second, and fifth nanosheets, the first to sixth nanosheets have surfaces on either side in the second direction exposed from the first to sixth gate wirings, respectively; a first surface of the first nanosheet facing the second nanosheet in the second direction is exposed from the first gate wiring; a second surface of the second nanosheet facing the first nanosheet in the second direction is exposed from the second gate wiring; a first power supply wiring is formed below the first to sixth transistors, the first power supply wiring extending in the first direction on the second side of the first nanosheet in a plan view and supplying the first voltage or the second voltage; A second power supply wiring is formed below the first to sixth transistors, the second power supply wiring extending in the first direction on the first side of the second nanosheet in a plan view and supplying the first voltage or the second voltage. A semiconductor memory device comprising:

12. 12. The semiconductor memory device according to claim 11, The one-port SRAM cell comprises: a first wiring extending in the first direction and serving as the first bit line; a second wiring extending in the first direction and serving as the second bit line; Further equipped with the first and second wirings are formed in a first wiring layer that is above the first to sixth transistors; At least one of the first and second wirings has a width in the second direction that is wider than a wiring that has a minimum width in the second direction among the wirings formed in the first wiring layer. A semiconductor memory device comprising:

13. 12. The semiconductor memory device according to claim 11, The one-port SRAM cell comprises: a third wiring extending in the second direction and supplying the second voltage; a fourth wiring extending in the second direction and supplying the second voltage; a fifth wiring extending in the second direction and serving as the word line; Further equipped with the third to fifth wirings are formed in a second wiring layer above the first to sixth transistors, The semiconductor memory device according to claim 1, wherein the fifth wiring is formed between the third wiring and the fourth wiring in a plan view.

14. 12. The semiconductor memory device according to claim 11, the fourth nanosheet has a surface on the first side exposed from the fourth gate wiring, the third nanosheet has a surface on the second side exposed from the third gate wiring, the first power supply wiring is formed between the first nanosheet and the third nanosheet in a plan view, The second power supply wiring is formed between the second nanosheet and the fourth nanosheet in a plan view. A semiconductor memory device comprising:

15. 15. The semiconductor memory device according to claim 14, The third to sixth transistors further include seventh to tenth nanosheets extending in the first direction, respectively; the third to sixth gate wirings surround the seventh to tenth nanosheets in the second direction and the third direction, respectively; The first, third, sixth, seventh and tenth nanosheets are arranged in the second direction in the order of the tenth, sixth, first, third and seventh nanosheets, The second, fourth, fifth, eighth and ninth nanosheets are arranged in the second direction in the order of the eighth, fourth, second, fifth and ninth nanosheets, a third power supply wiring is formed below the first to sixth transistors, extending in the first direction on the first side of the eighth and tenth nanosheets in a plan view and supplying the second voltage; a fourth power supply wiring is formed below the first to sixth transistors, extending in the first direction on the second side of the seventh and ninth nanosheets in a plan view and supplying the second voltage; the sixth, seventh and ninth nanosheets have surfaces on the first side exposed from the sixth, third and fifth gate wirings, respectively; The fifth, eighth and tenth nanosheets have the second side surfaces exposed from the fifth, fourth and sixth gate wirings, respectively. A semiconductor memory device comprising:

16. 16. The semiconductor memory device according to claim 15, the eighth and tenth nanosheets are formed adjacent to a cell boundary of the one-port SRAM cell on the first side; the seventh and ninth nanosheets are formed adjacent to a cell boundary of the one-port SRAM cell on the second side; the third power supply wiring is formed on a cell boundary on the first side of the 1-port SRAM cell in a plan view; The fourth power supply wiring is formed on the cell boundary on the second side of the one-port SRAM cell in a plan view. A semiconductor memory device comprising:

17. 16. The semiconductor memory device according to claim 15, The third to sixth transistors further include eleventh to fourteenth nanosheets extending in the first direction, respectively; the third to sixth gate wirings surround the eleventh to fourteenth nanosheets in the second direction and the third direction, respectively; The first, third, sixth, seventh, tenth, eleventh and fourteenth nanosheets are formed in the second direction in the order of the fourteenth, tenth, sixth, first, third, seventh and eleventh nanosheets, The second, fourth, fifth, eighth, ninth, twelfth and thirteenth nanosheets are arranged in the second direction in the order of the twelfth, eighth, fourth, second, fifth, ninth and thirteenth nanosheets, the third power supply wiring is formed between the eighth nanosheet and the twelfth nanosheet and between the tenth nanosheet and the fourteenth nanosheet in a plan view, the fourth power supply wiring is formed between the seventh nanosheet and the eleventh nanosheet and between the ninth nanosheet and the thirteenth nanosheet in a plan view, the twelfth and fourteenth nanosheets have the first side surfaces exposed from the fourth and sixth gate wirings, respectively; The eleventh and thirteenth nanosheets have the second side surfaces exposed from the third and fifth gate wirings, respectively. A semiconductor memory device comprising:

18. 15. The semiconductor memory device according to claim 14, the third transistor further comprises seventh and eighth nanosheets extending in the first direction; the fourth transistor further comprises ninth and tenth nanosheets extending in the first direction; The fifth transistor further includes an eleventh nanosheet extending in the first direction, The sixth transistor further comprises a twelfth nanosheet extending in the first direction, the third gate wiring surrounds the seventh and eighth nanosheets in the second and third directions, the fourth gate wiring surrounds the ninth and tenth nanosheets in the second and third directions, the fifth gate wiring surrounds the eleventh nanosheet in the second direction and the third direction, the sixth gate wiring surrounds the twelfth nanosheet in the second direction and the third direction, The first, third, sixth, seventh, eighth and twelfth nanosheets are arranged in the second direction in the order of the twelfth, sixth, first, third, seventh and eighth nanosheets, The second, fourth, fifth, ninth, tenth and eleventh nanosheets are arranged in the second direction in the order of the tenth, ninth, fourth, second, fifth and eleventh nanosheets, a third power supply wiring is formed below the first to sixth transistors, extending in the first direction between the sixth nanosheet and the twelfth nanosheet and between the ninth nanosheet and the tenth nanosheet, and supplying the second voltage; a fourth power supply wiring is formed below the first to sixth transistors, between the fifth nanosheet and the eleventh nanosheet and between the seventh nanosheet and the eighth nanosheet, extending in the first direction and supplying the second voltage; the fifth, seventh, tenth and twelfth nanosheets have surfaces on the first side exposed from the fifth, third, fourth and sixth gate wirings, respectively; The sixth, eighth, ninth and eleventh nanosheets have the second side surfaces exposed from the sixth, third, fourth and fifth gate wirings, respectively. A semiconductor memory device comprising:

19. A semiconductor memory device including a 1-port SRAM cell, The one-port SRAM cell comprises: a first transistor having one node connected to a first power supply supplying a first voltage, another node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, another node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node, another node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; a fourth transistor having one node connected to the second node, another node connected to the second power supply, and a gate connected to the first node; a fifth transistor having one node connected to the first bit line, another node connected to the first node, and a gate connected to the word line; a sixth transistor having one node connected to a second bit line forming a complementary bit line pair with the first bit line, another node connected to the second node, and a gate connected to the word line; Equipped with The first and second transistors are First and second nanosheets extending in a first direction; a first gate wiring and a second gate wiring that respectively surround the first nanosheet and the second nanosheet in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions; Each of them has The third to sixth transistors are A plurality of third to sixth nanosheets extending in the first direction; third to sixth gate wirings surrounding the third to sixth nanosheets in the second and third directions, respectively; Each of them has The first nanosheet, the plurality of third nanosheets, and the plurality of sixth nanosheets are formed in the second direction in the order of the plurality of sixth nanosheets, the first nanosheets, and the plurality of third nanosheets; The second nanosheet, the plurality of fourth nanosheets, and the plurality of fifth nanosheets are formed in the second direction in the order of the plurality of fourth nanosheets, the second nanosheets, and the plurality of fifth nanosheets; the first and second nanosheets have surfaces on either side in the second direction exposed from the first and second gate wirings, respectively; each of the third nanosheets has a surface on one side in the second direction exposed from the third gate wiring; each of the plurality of fourth nanosheets has a surface on one side in the second direction exposed from the fourth gate wiring; each of the plurality of fifth nanosheets has a surface on one side in the second direction exposed from the fifth gate wiring; each of the sixth nanosheets has a surface on one side in the second direction exposed from the sixth gate wiring; a plurality of power supply wirings are formed in a layer below the first to sixth transistors, the power supply wirings extending in the first direction and supplying the second voltage; the third nanosheets include a third nanosheet on which at least one of the power supply wirings is formed on a side opposite to a side exposed from the third gate wiring in the second direction in a plan view, the plurality of fourth nanosheets include a fourth nanosheet on which at least one of the plurality of power supply wirings is formed on a side opposite to a side exposed from the fourth gate wiring in the second direction in a plan view, The plurality of fifth nanosheets include a fifth nanosheet on which at least one of the plurality of power supply wirings is formed on a side opposite to a side exposed from the fifth gate wiring in the second direction in a plan view, The sixth nanosheets include a sixth nanosheet on which at least one of the power supply wirings is formed on a side opposite to a side exposed from the sixth gate wiring in the second direction in a plan view. A semiconductor memory device comprising:

20. 20. The semiconductor memory device according to claim 19, A semiconductor memory device characterized in that the first and second nanosheets, and the multiple third to sixth nanosheets, have the same width in the second direction.

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