System and method for built-in self-test of electronic circuits - Patents.com

Abstract

SOLUTION: In described examples of a device (305) with built-in-self-test, a multiplexer (315) has at least first and second input terminals and is coupled to receive a first input signal (A) at the first input terminal, a second input signal (B) at the second input terminal, and selection signals (S1, S2). Also, the multiplexer (315) is coupled to output: the first input signal (A) in response to a first combination of the selection signals; the second input signal (B) in response to a second combination of the selection signals; and an analog summation of the first and second input signals (A, B) in response to a third combination of the selection signals (S1, S2).SELECTED DRAWING: Figure 3A

Description

[Technical field]

[0001] This application relates generally to electronic circuits, and more particularly to built-in self-testing of electronic circuits. [Background technology]

[0002] Integrated circuits (ICs) can be designed and built with additional hardware and software configured to perform self-tests. Built-in self-test (BIST) systems allow an integrated circuit to test its own functionality and operation. In some cases, an integrated circuit does not require external automated self-test equipment to verify its functionality. Typically, a BIST system generates test signal patterns to run across the IC's internal circuits and then collects responses from various internal components to determine whether the responses match predetermined expected responses. High data rate ICs can particularly benefit from careful characterization, production testing, and in-system debug capabilities. Such constraints limit the ability to use commercially available, low-cost automated test equipment (ATE) where specialized and expensive (e.g., typically costing more than $100k) bit error ratio testers and oscilloscopes are required.

[0003] In many digital data communication applications, communication is bidirectional, and ICs containing a combination of transmitter and receiver are used at both ends of the communication link. This combination is also known as a transceiver. In the transceiver, a "loopback" test function provides functional "at device speed" testing. BIST can generate test patterns to the transmitter that can be looped back to the receiver. This allows testing of the receiver functionality at device speed in the transceiver IC. In other digital communication applications using integrated circuits, communication is unidirectional, with an upstream transmitter communicating to a downstream receiver. One common example is a video interface for a display device, which is a "receive only" device with no transmission capabilities. Other devices include processors, video controllers, field programmable gate arrays (FPGAs), or application specific integrated circuits (ASICs), which send data to the display device.

[0004] In transceiver systems, loopback BIST functions provide only pass / fail indications and do not provide device margin measurements. In loopback functions, the "loop" is completed within the device, so direct measurements of the signal the receiver actually receives are not practical. The closest measurements can typically be made external to the pads / pins of the device. These pads / pins can be probed, but additional signal impairments (e.g., reflections caused by plating stubs, bond wires, and / or non-ideal terminations) are not measured. Standalone receivers present challenges in testing receiver functionality at device speeds because the tests are done with external connections that can introduce noise and other interference that skew the test results. In high-speed communication systems, signal integrity of the electrical signal is important for an error-free, robust link.

[0005] FIG. 1 shows an example "data eye" diagram, useful for evaluating the performance of a communications link. In a data eye diagram measurement, timing and voltage margins can be measured directly. This is typically done with a high-speed oscilloscope connected to the external boundary or test connections (e.g., pins, balls, or pads) of a packaged IC. The more "open" the eye is vertically, the more voltage margin (measured as the eye amplitude) is available to the receiver. Similarly, the more open the "eye" is horizontally, the more timing margin (measured as the eye width) is available to the receiver.

[0006] This measurement has several disadvantages. One is that it uses expensive oscilloscopes that may not be available in a test environment, and similarly may not be available in a completed or assembled system. Another disadvantage is that by measuring the external boundary of a packaged IC, the data eye diagram does not provide a complete picture of the internal functioning of the device.

[0007] 2 shows an example circuit 200 with a conventional method of testing and measurement. The circuit 200 includes a receiver circuit 205 configured to receive only data (e.g., a display unit). The circuit 200 further includes a transmitter 210. The transmitter 210 can be any circuit configured to transmit data downstream to the receiver 205. The data from the transmitter 210 travels through a transmission line 220 (e.g., a circuit path on a circuit board). The data is received by the receiver 205 at an entrance point 230 of the receiver 205 circuit package. The entrance point 230 can be any circuit connection, such as a pin grid array (PGA), a land grid array (LGA), and other similar IC package connections. The IC package introduces parasitic inductance and capacitance 235 in the signal path. The signal further travels through an internal trace 240 of the receiver 205, which can introduce further signal anomalies due to various factors, such as bond wire inductance 250. The signal is finally received at the IC at termination point 260. Termination point 260 may also introduce parasitic capacitance to the input signal due to electrostatic discharge (ESD) protection circuitry, IC bond pads, and IC active circuit elements at the receiver.

[0008] In conventional test methods, signals are tested at the transmitter exit points and receiver entry points without measuring the voltage and timing margins inside the receiver 205 at the termination point 260. For example, if the signal is initially tested at the output of the transmitter 210, it may illustrate an ideal data eye diagram 270. However, if measurements are made at the entry point 230 and the termination point 260, the data eye diagram may be represented as shown in eye diagrams 280 and 290, respectively. This is due to additional signal losses, reflections, filtering, and equalization caused by non-idealities and electrical behavior of the IC package and / or IC die. The data eye diagram provides different margins for voltage and time at each signal point. As shown, conventional test methods cannot provide data on the receiver's voltage and timing margins. Summary of the Invention

[0009] In a described example of a device with built-in self-test, a multiplexer has at least first and second input terminals, is coupled to receive a first input signal at the first input terminal, a second input signal at the second input terminal, and receives a selection signal, and is coupled to output the first input signal in response to a first combination of the selection signals, the second input signal in response to a second combination of the selection signals, and an analog sum of the first and second input signals in response to a third combination of the selection signals. [Brief description of the drawings]

[0010] [Figure 1] 1 (PRIOR ART) is an example "data eye" diagram.

[0011] [Diagram 2] 1 (PRIOR ART) illustrates an example circuit with a conventional method of test and measurement;

[0012] [Figure 3A] FIG. 1 is a block diagram of an example built-in self-test system according to one embodiment.

[0013] [Figure 3B] FIG. 3B is a block diagram of an example of a receiver circuit for the system of FIG. 3A.

[0014] [Figure 4A] 1 is an example data eye diagram of a receiver's built-in self-test feature in accordance with one embodiment.

[0015] [Figure 4B] 4B is a graph of timing and voltage scales for the example data eye diagram of FIG. 4A.

[0016] [Diagram 5] 4 is a flow chart of an example process for measuring voltage and timing margins of a device using a built-in self-test system according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] To measure signal integrity inside the IC package (where the receiver senses the actual signal), the illustrative embodiment measures voltage and timing margins inside the IC package even if the IC package's high speed data rate exceeds the capabilities of the external test hardware.

[0018] In a described example of a system and method for testing an integrated circuit, the system includes a transmitter configured to provide an internal programmable input with the ability to modify the amplitude and clock phase of the input test signal to identify errors and accurately determine the voltage and timing margins of the device.

[0019] 3A illustrates an example built-in self-test system 300 according to one embodiment. BIST 300 includes a receiver 305 and a control unit 310. Control unit 310 may be any computing device configured to test various functions of receiver 305 and provide data regarding functionality, voltage, and timing margins, and various other aspects of receiver 305 as described herein. In this example, the various components of receiver 305 are formed on a single integrated circuit die.

[0020] The receiver 305 includes a special purpose multiplexer 315. In this example, the multiplexer 315 has (a) two input terminals A and B for receiving first and second input signals, respectively, and (b) an output terminal C for outputting an output signal in response to the input signals. The multiplexer 315 also has two selection terminals S1 and S2 for receiving two selection signals from the control unit 310, in this example.

[0021] In a first example, the first and second input signals (at input terminals A and B, respectively) are digital signals. In a second example, the first and second input signals (at input terminals A and B, respectively) are analog signals. As shown in the example of FIG. 3A , (a) the first input signal (at input terminal A) is received from control unit 310, which is a source external to the integrated circuit die of receiver 305, and (b) the second input signal (at input terminal B) is received from dummy transmitter 350, which is a source within (within) the integrated circuit die of receiver 305.

[0022] Multiplexer 315 provides an output signal (at terminal C) in response to a selection signal (at terminals S1 and S2) as shown in Table 1 below. JPEG0007678459000001.jpg5595

[0023] Thus, in response to a selection signal (at terminals S1 and S2) having a binary value of "11," multiplexer 315 (a) performs an analog summation of the input signals (from terminals A and B) and (b) outputs the analog summation as an output signal at terminal C, so that even though the input signals (from terminals A and B) are digital signals, the output signal at terminal C (which is the analog summation of those input signals) is a continuous analog signal. Unlike multiplexer 315, a conventional multiplexer may output only one of its input signals in response to its selection signal.

[0024] In response to a selection signal (at terminals S1 and S2) having a binary value of "00," multiplexer 315 manipulates terminal C to have an "X value" as shown in Table 1. The "X value" is an "invalid" state, such as a floating value (e.g., high impedance), a grounded zero value, a pulled high value, or other value, according to the needs of a particular implementation.

[0025] Further, in response to a selection signal (at terminals S1 and S2) having a binary value of "01" as shown in Table 1, multiplexer 315 operates terminal C to have the same value as the input signal from terminal A. Similarly, in response to a selection signal (at terminals S1 and S2) having a binary value of "10" as shown in Table 1, multiplexer 315 operates terminal C to have the same value as the input signal from terminal B.

[0026] Although particular values ​​of the selection signals (at terminals S1 and S2) are shown by example in Table 1, multiplexer 315 may be configured to generate the desired output C in response to different values ​​of those selection signals in other examples. For example, (a) in a first alternative embodiment, in response to a selection signal (at terminals S1 and S2) having a binary value of “00”, multiplexer 315 operates terminal C to have the same value as the input signal from terminal A, instead of having an “X value”, (b) in a second alternative embodiment, in response to a selection signal (at terminals S1 and S2) having a binary value of “00”, multiplexer 315 operates terminal C to have the same value as the input signal from terminal B, instead of having an “X value”, (c) in a third alternative embodiment, in response to a selection signal (at terminals S1 and S2) having a binary value of “00”, multiplexer 315 operates terminal C to have the same value as the input signal from a third terminal D (not shown in FIG. 3A ) of multiplexer 315, instead of having an “X value”.

[0027] Also, in this third alternative embodiment, in response to a selection signal (at terminals S1 and S2) having a binary value of “11”, multiplexer 315 (a) performs an analog summation of the input signals (from terminals A, B, and D) and (b) outputs the analog summation as an output signal at terminal C, so that even though the input signals (from terminals A, B, and D) are digital signals, the output signal at terminal C (which is the analog summation of those input signals) is a continuous analog signal.

[0028] Receiver 305 further includes an input buffer / driver 320 coupled to drive an output signal from terminal C to other signal receiver circuitry 330. Error detector 340 is coupled to receive the output of circuitry 330, compare the output to a predefined input signal (e.g., a test signal from control unit 310), and provide the result of the comparison to control unit 310 (and optionally to other units within or external to the integrated circuit die of receiver 305). For example, in at least one embodiment, error detector 340 (a) receives a predefined pattern of expected output signals from control unit 310, (b) compares the predefined pattern to the output of circuitry 330, and (c) provides the result of the comparison to control unit 310 (and optionally to other units within or external to the integrated circuit die of receiver 305). In a first example, the output of error detector 340 is a binary pass / fail indication of the comparison (and optionally to other units within or external to the integrated circuit die of receiver 305). In the second example, the output of the error detector 340 is a detailed report of the comparison.

[0029] A clock generator 360 is coupled to provide clock signals for receiver 305 operation. For clarity, FIG. 3A shows clock generator 360 connected only to circuitry 330 and dummy transmitter 350 in receiver 305, but clock generator 360 is further coupled to other components in receiver 305. As shown in FIG. 3A, clock generator 360 includes an integrated phase rotator (shifter) 362. In another example, the phase shifter is external to clock generator 360. Clock generator 360 generates clock frequencies for receiver 305 to operate at a desired speed. Control unit 310 is coupled to provide various control signals to clock generator 360 via control signal line 365, such as control signals to freeze the internal clock at a desired frequency (e.g., center frequency of the data eye diagram), change / rotate the phase of the internal clock signal to determine the timing margin of receiver 305, and others as described herein. If the phase shifter is external to the clock generator 360, the control unit 310 is configured to provide the appropriate phase shift control signals to the external phase shifter. are combined.

[0030] The dummy transmitter 350 is configurable (e.g., programmable) to generate predetermined test signal patterns. As shown in FIG. 3A, the dummy transmitter 350 is coupled to output those predetermined test signal patterns to the receiver circuit 330 via the multiplexer 315 and the buffer / driver 320. More specifically, the dummy transmitter 350 outputs those predetermined test signal patterns via a signal line 355 that is connected to an input terminal B of the multiplexer 315. The predetermined test signal patterns may be any form of pseudo-random binary sequence ("PRBS") pattern, such as a series of logic "1's" (e.g., positive voltages), logic "0's" (e.g., negative voltages), or other predetermined signal patterns configured to test the functionality of the receiver 305 under various conditions. The amplitude of the test signal pattern is continuously variable (adjustable) by the dummy transmitter 350 in accordance with its configuration (e.g., programming) and in response to appropriate control signals it receives from the control unit 310, thereby advantageously allowing fine tuning of the receiver 305 operation. Thus, as described herein above, the control unit 310 monitors the comparison results output from the error detector 340. In response to those comparison results (and optionally other factors), the control unit 310 outputs appropriate control signals to the dummy transmitter 350 which in response adjusts (continuously increases / decreases) the amplitude of the test signal pattern, thereby determining a voltage margin to allow the receiver 305 to function within its optimal capacity.

[0031] The timing margin of the receiver 305 can be determined by adjusting the phase of its internal clock from the clock generator 360. For example, the control unit 310 may initially cause the clock generator 360 to freeze the phase of the internal clock at a particular frequency (e.g., the center of an ideal data eye diagram) and then output appropriate control signals to rotate / change the internal clock phase, so that the control unit 310 determines the impact of those phase rotations / changes by monitoring the comparison results output from the error detector 340, thereby measuring the timing margin of the receiver 305. If the phase shifter is external to the clock generator 360 (as mentioned in another example above), the control unit 310 outputs appropriate control signals to cause the external phase shifter to generate an arbitrary clock phase for the receiver circuit 330 and then adjust the phase in various directions (e.g., advanced or delayed) to determine the timing margin of the receiver 305.

[0032] The control unit 310 is further coupled to directly output configurable (e.g., programmable) test signal patterns via input terminal A of the multiplexer 315. Those test signal patterns (via input terminal A from the control unit 310) can be combined with other test signal patterns (via input terminal B from the dummy transmitter 350) by the control unit 310 appropriately controlling terminals S1 and S2 of the multiplexer 315 to have a binary value of "11" as described herein above. By appropriately combining those test signal patterns in this manner, the control unit 310 adjusts the amplitudes of the other test signal patterns (via input terminal B from the dummy transmitter 350) according to its configuration (e.g., programming), so that the control unit 310 determines the impact of those amplitude adjustments by monitoring the comparison results output from the error detector 340.

[0033] Furthermore, as described herein above, the control unit 310 is configured to output appropriate control signals to (a) cause the dummy transmitter 350 to adjust the amplitude of the test signal pattern at the input terminal B of the multiplexer 315, and (b) cause the clock generator 360 to change / rotate the phase of the internal clock signal of the receiver 305. Thus, by operating the receiver 305 under various combinations of test signal patterns, amplitudes, and clock phases, the control unit 310 determines a more complete functional profile of the receiver 305. For example, by monitoring the comparison results output from the error detector 340 during such testing, the control unit 305 may generate data eye diagrams (e.g., voltage and timing) to determine the functional margin of the receiver 305.

[0034] FIG. 3B illustrates an example of a receiver circuit 330 (FIG. 3A). In this example, receiver circuit 330 includes an internal clock circuit 331 coupled to provide a local clock signal (to various internal functional units) in response to a signal from buffer / driver 320. A clock data recovery unit 332 is coupled to recover data and clock signals from the output of circuit 331. A demultiplexer 333 is coupled to provide a receiver circuit 330 output signal to error detector 340 by demultiplexing the output of unit 332. For clarity, FIG. 3B illustrates a single signal line between its components, but the components may be connected by multiple signal lines based on the number of bit lines used in receiver 305. Additionally, receiver circuit 330 and receiver 305 may include many other internal elements (not shown).

[0035] FIG. 4A illustrates an example data eye diagram 410 of a BIST function of a receiver, such as receiver 305, according to one embodiment. The "opening" of the eye in data eye diagram 410 may be measured with various offsets to the clock phase and amplitude of the test signal pattern. For example, (a) when the amplitude of the test pattern is changed, the eye may expand / retract vertically, and (b) when the phase of the clock is changed, the eye may expand / retract horizontally. As shown in FIG. 4A, the center portion of the eye may provide an acceptable operating range for the receiver (e.g., receiver 305). As the clock phase and test amplitude are pushed toward the ends of the eye, the error rate may increase to provide a detailed picture of the receiver's functional margin (voltage and timing).

[0036] An error detector in the receiver (e.g., error detector 340) may compare the expected received data pattern against the actual received data pattern. If the input to the receiver is the same pattern as expected by the error detector, the error detector outputs a no error indication. Eventually, as the level of offset introduced by the dummy transmitter 350 increases, the offset becomes larger than the input signal, the receiver sensitivity is impaired, and errors are detected by the error detector. By monitoring the output of the error detector and adjusting the amplitude of the test pattern, the sensitivity of the receiver can be determined.

[0037] As shown in Figure 4A, in the "middle" of the eye, the receiver sensitivity and available signal are sufficient to overcome any offset introduced by the dummy transmitter 350. Initially, a small number of errors are detected by the error detector as the end of the signal amplitude approaches. As the amplitude of the introduced offset increases, a larger number of errors are produced. With this adjustment, the receiver sensitivity can be fully determined and characterized.

[0038] FIG. 4B shows a timing and voltage scale 420 for an example data eye diagram 410 (FIG. 4A). At a data rate of 3.2 Gbps, 64 timing unit steps (of approximately 4.88 ps each) are useful for margin testing across a bit unit interval (UI) of 312.5 ps. Similarly, 32 amplitude steps (of 15 mV each) are useful for voltage margin testing across a total voltage range of + / - 240 mV. By operating the receiver 305 under various combinations of these offsets, the control unit 310 measures multiple timing and voltage offset points (within the data eye of the received signal) to determine whether error-free data is received by the error detector 340. For example, the control unit 310 uses these measurements to evaluate the functionality of the clock data recovery unit 332 (FIG. 3B). The frequency and voltage steps or "slices" are useful for sensitivity measurements in both the timing and voltage domains, thereby allowing the control unit 310 to generate an "eye" profile for the data eye diagram. By appropriately programming the phase of the clock and adding a vertical sensitivity measurement (provided by dummy transmitter 350), control unit 310 maps the entire profile of the "eye." To generate a given profile for receiver 305, this example uses 15mV and 4.88ps, but any number and size of steps can be used based on the voltage and clock rating of a given device.

[0039] FIG. 5 illustrates an example process 500 for measuring voltage and timing margins of a device (e.g., receiver 305) using BIST according to one embodiment. Initially, at 510, control unit 310 applies a predefined test pattern to receiver 305. As described herein above with respect to FIG. 3A, the predefined pattern may include applying a pseudo-random binary sequence from dummy transmitter 350, applying a test pattern from control unit 310, and / or a combination thereof. At 520, control unit 310 measures the output of receiver circuit 330 (either directly or via error detector 340) to determine whether the output matches a predefined pattern of expected output signals. In at least one example, error detector 340 receives the predefined pattern from control unit 310 and determines whether the output of receiver circuit 330 matches the predefined pattern. At 530, control unit 310 determines whether the output of receiver circuit 330 contains an error (e.g., by receiving the results of error detector 340 comparison).

[0040] If the control unit 310 determines (at 530) that the output of the receiver circuit 330 does not include any errors, the control unit 310 selectively adjusts (at 540) the amplitude and / or clock phase of the test signal using predefined steps (e.g., timing unit steps and amplitude steps as described herein above in connection with FIGS. 4A and 4B). As described herein above, the control unit 310 may selectively adjust the amplitude and / or clock phase of the test signal, individually or in combination and / or optionally with other offsets, based on the measurement model to be used for the receiver 305. After adjusting the amplitude and / or phase in this manner (at 540), the control unit 310 applies (at 510) the test pattern with such adjusted amplitude and / or phase (and optionally with such other offsets) to the receiver 305 for the next measurement.

[0041] If the control unit 310 determines (at 530) that the output of the receiver circuit 330 contains errors, the control unit 310 determines (at 550) whether the number of errors exceeds a predetermined limit. The predetermined limit may be based on the "structure" of the data eye diagram. For example, if the applied offset stretches the "eye" to its outer limits (horizontal and / or vertical), the number of errors may increase.

[0042] The predetermined limit may also be based on the device (e.g., receiver 305) rating and the signal error tolerance limit. For example, if the device is used for a certain precision-based application, even a small number of errors may be unacceptable, so the predetermined error limit may be set to a conservatively small number. Alternatively, if the device is used for a certain high error tolerance application, the predetermined error limit may be set to a generously large number.

[0043] If the control unit 310 determines (at 550) that the number of errors does not exceed the predetermined limit, the control unit 310 (a) selectively adjusts (at 540) the amplitude and / or clock phase of the test signal using a predetermined step, and (b) applies (at 510) the test pattern with such adjusted amplitude and / or phase (and optionally with such other offsets) to the receiver 305 for the next measurement. Alternatively, if the control unit 310 determines (at 550) that the number of errors does exceed the predetermined limit, such number may indicate an outer boundary of the receiver 305 range, and therefore the control unit 310 generates (at 560) a report. In at least one example, the report includes the measured data eye diagram and associated parameters including (a) the shape and form of the data eye diagram at various stages of the test pattern, and (b) the values ​​of the signal amplitude and / or clock phase at those stages.

[0044] Modifications may be made to the exemplary embodiments described, and other embodiments are possible, within the scope of the present invention, For example, operations do not necessarily have to be performed in the particular order described herein, and some operations are not necessarily required in some embodiments.

Claims

1. A device, comprising: A multiplexer having at least first and second input terminals, receiving a first input signal at the first input terminal; receiving a second input signal at the second input terminal; Receive a selection signal; outputting the first input signal in response to a first combination of the selection signals; outputting the second input signal in response to a second combination of the selection signals; and outputting an analog sum of the first and second input signals in response to a third combination of the selection signals. the multiplexer coupled as follows: a transmitter coupled to provide the second input signal to the multiplexer, the transmitter configured to produce a predetermined test signal pattern for the device as the second input signal in response to a first control signal; a phase shifter coupled to selectively vary the phase of a clock signal to the transmitter in response to a second control signal; Including, A device wherein the phase of said second input signal is selectively adjustable by selectively varying the phase of said clock signal.

2. 2. The device of claim 1, at least one receiver circuit coupled to provide at least one local signal in response to an output of the multiplexer; an error detector coupled to generate at least one comparison signal to indicate whether the at least one local signal matches an expected output of the at least one receiver circuit; The device further comprises:

3. 3. The device of claim 2, The device, wherein the first and second control signals are provided by a control unit in response to at least one comparison signal from the error detector.

4. 2. The device of claim 1, The device, wherein the predetermined test signal pattern is a pseudo-random binary sequence pattern.

5. 3. The device of claim 2, an input buffer coupled to an output of the multiplexer; the at least one receiver circuit comprising: at least one internal clock circuit coupled to an output of the input buffer, the at least one internal clock circuit configured to generate a local clock signal in response to the output of the input buffer; a clock data recovery unit coupled to at least one output of the at least one internal clock circuit, the clock data recovery unit configured to recover data and clock signals of the first input signal, the second input signal, or an analog sum of the first and second input signals from the local clock signal; a demultiplexer coupled to an output of the clock data recovery unit, the demultiplexer configured to demultiplex the recovered data and a clock signal; Including, The device, wherein an output of the demultiplexer is the at least one local signal.

6. 1. A method for built-in self-test of a device, comprising: receiving a first signal by a first input terminal of a multiplexer; receiving a predetermined test signal pattern as a second signal by a second input terminal of the multiplexer for testing a receiver circuit; generating a third signal as an analog sum of the first and second signals in response to receiving a selection signal by the multiplexer; providing the third signal to the receiver circuit by the multiplexer; measuring an output signal of the receiver circuit with an error detector; determining whether an output signal of the receiver circuit has at least one error; adjusting at least one of an amplitude of the predetermined test signal pattern generated by a transmitter and a phase of a clock signal from a phase shifter to the transmitter in response to determining that the output signal of the receiver circuit does not have at least one error; said measuring step comprising: A method comprising:

7. 7. The method of claim 6, determining whether an output signal of the receiver circuit has at least one error; determining whether an output signal of the receiver circuit matches the predetermined test signal pattern with the error detector; determining that the output signal of the receiver circuit does not have at least one error in response to determining that the output signal of the receiver circuit matches the predetermined test signal pattern; A method comprising:

8. 7. The method of claim 6, The method of claim 1, wherein the predetermined test signal pattern is a pseudo-random binary sequence pattern.

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