Semiconductor device and method for manufacturing the same

Abstract

To allow easy formation of semiconductor regions with a uniform ion concentration without executing precise control in forming a plurality of semiconductor regions of conductivity types different from each other by ion injection.SOLUTION: A semiconductor device has: a semiconductor substrate that is formed of single crystal semiconductor and has a first conductivity type; a groove part that extends in a thickness direction from one principal surface of the semiconductor substrate; an insulator layer that covers an inner surface of the groove part; a first site that is formed to fill the groove part inside the insulator layer and is formed of an electric conductor; a second site that is adjacent to the first site with the insulator layer therebetween, extends in the thickness direction from one principal surface of the semiconductor substrate, and has a second conductivity type; and a third site that is adjacent to the second site, extends in the thickness direction from one principal surface of the semiconductor substrate, and has a third conductivity type.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device that can be used as a variable capacitance element, and a method for manufacturing the semiconductor device. [Background technology]

[0002] For example, a MOS diode is a semiconductor device having a MOS (Metal-Oxide-Semiconductor) structure, and is also called a MOS capacitor. Among these MOS diodes, a variable capacitance element (varicap) whose capacitance can be controlled by voltage is known. The capacitance of a variable capacitance element changes when a bias voltage is applied to change the width of the depletion layer. Variable capacitance elements are used as circuit components in, for example, VCOs (Voltage Controlled Oscillators), phase locked loops, and frequency synthesizers.

[0003] As a conventional MOS-type variable capacitance element, for example, Patent Document 1 discloses a method for manufacturing a varicap in which a groove is formed in the thickness direction from the surface of a semiconductor substrate, a semiconductor region of a first conductivity type is formed on the inner wall of the groove, and a semiconductor material of a second conductivity type is embedded inside the groove, thereby forming an abrupt junction with a steep carrier density distribution at the boundary between the embedded semiconductor material and the inner wall of the groove. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2005-183813 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, the varicap with the structure disclosed in Patent Document 1 has a problem in that it is difficult to form the side and bottom of the groove formed in the semiconductor substrate so that they have the same concentration profile when forming an abrupt junction. That is, when ions are implanted from the narrow groove opening in the depth direction of the groove, the ion implantation angle and ion acceleration energy must be precisely controlled to make the side and bottom of the groove have the same ion concentration, which makes it difficult to efficiently manufacture the varicap.

[0006] The present invention has been made in consideration of the above circumstances, and has an object to provide a semiconductor device and a method for manufacturing the semiconductor device that are capable of easily forming semiconductor regions of uniform ion concentration without precise control when forming a plurality of semiconductor regions of different conductivity types by ion implantation. [Means for solving the problem]

[0007] In order to solve the above problems, the present invention proposes the following means. That is, the semiconductor device of the present invention comprises a semiconductor substrate of a first conductivity type made of a single crystal semiconductor, a groove extending in a thickness direction from one main surface of the semiconductor substrate, an insulating layer covering an inner surface of the groove, a first portion made of a conductor formed inside the insulating layer so as to fill the groove, a second portion of a second conductivity type adjacent to the first portion via the insulating layer and extending in a thickness direction from one main surface of the semiconductor substrate, and a third portion of a third conductivity type adjacent to the second portion and extending in a thickness direction from one main surface of the semiconductor substrate. The semiconductor substrate is a P-type semiconductor, the second portion is a P+ type semiconductor, and the third portion is a P type semiconductor. It is characterized by:

[0008] According to the semiconductor device of the present invention, the first portion made of a conductor, the insulator layer, the second portion 15 of the second conductivity type, and the third portion of the third conductivity type are arranged along the surface spreading direction at a predetermined depth from one main surface of the semiconductor substrate, which eliminates the need to implant ions at a uniform concentration into the inner side and bottom surfaces of the grooves formed in the semiconductor substrate as in the conventional method. This makes it possible to easily control the maximum value of the capacitance by simply controlling the thickness of the insulator layer, and to form a profile that does not depend on an abrupt junction.

[0009] In the semiconductor device of the present invention, the semiconductor substrate may be made of a silicon single crystal substrate, and the insulating layer may be made of silicon dioxide.

[0011] In the semiconductor device of the present invention, the semiconductor device may be a variable capacitance element, and may include a ground electrode electrically connected to the semiconductor substrate and a gate electrode electrically connected to the first portion.

[0012] A method for manufacturing a semiconductor device according to the present invention includes a groove forming step of forming a groove extending in a thickness direction from one main surface of a semiconductor substrate of a first conductivity type made of a single crystal semiconductor; an insulator layer forming step of forming an insulator layer covering an inner surface of the groove; a first portion forming step of forming a first portion made of a conductor so as to fill the groove inside the insulator layer; a second portion forming step of ion-implanting an impurity in a thickness direction from one main surface of the semiconductor substrate toward a region adjacent to the first portion through the insulator layer to form a second portion of a second conductivity type adjacent to the first portion and extending in a thickness direction from one main surface of the semiconductor substrate through the insulator layer; and a third portion forming step of ion-implanting an impurity in a thickness direction from one main surface of the semiconductor substrate toward a region adjacent to the second portion to form a third portion of a third conductivity type adjacent to the second portion and extending in a thickness direction from the one main surface of the semiconductor substrate. The semiconductor substrate is a P-type semiconductor, the second portion is a P+ type semiconductor, and the third portion is a P type semiconductor. It is characterized by:

[0013] According to the method for manufacturing a semiconductor device of the present invention, it is possible to easily manufacture a semiconductor device having a plurality of semiconductor regions of different conductivity types sandwiching an oxide film by simply uniformly implanting ions from the main surface of the semiconductor substrate in the thickness direction, without performing a complex and difficult process of adjusting the ion implantation angle so that the side and bottom surfaces of a trench formed in the semiconductor substrate have the same concentration profile in order to form a step junction. Furthermore, by simply forming a mask layer when ion implanting impurities into each semiconductor region, the concentration profiles of the plurality of semiconductor regions of different conductivity types can be easily controlled. Effect of the Invention

[0014] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing a semiconductor device in which, when forming a plurality of semiconductor regions of mutually different conductivity types by ion implantation, semiconductor regions of uniform ion concentration can be easily formed without precise control. [Brief description of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view showing a variable capacitance element according to an embodiment of the present invention, which is an example of a semiconductor device according to the present invention. [Diagram 2] 2 is a plan view of the variable capacitor of FIG. 1 as viewed from above, excluding the interlayer insulating film. [Diagram 3] 1A to 1C are cross-sectional views showing a stepwise method of manufacturing a variable capacitance element according to an embodiment of the present invention, which is an example of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views showing a stepwise method of manufacturing a variable capacitance element according to an embodiment of the present invention, which is an example of a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, a semiconductor device according to an embodiment of the present invention and a method for manufacturing the semiconductor device will be described with reference to the drawings. Note that the following embodiment is specifically described to better understand the gist of the invention, and does not limit the present invention unless otherwise specified. Also, the drawings used in the following description may show essential parts in an enlarged scale for the sake of convenience in order to make the features of the present invention easier to understand, and the dimensional ratios of each component may not necessarily be the same as the actual ones.

[0017] (Semiconductor Device) As one embodiment of the present invention, a MOS type variable capacitance element (varicap) which is an example of a semiconductor device will be described. In the following description, the boron (B) concentration of p+ type is a concentration corresponding to a resistivity of 8mΩcm to 10mΩcm, the p type is a concentration corresponding to a resistivity of 0.1 to 0.01Ωcm, and the p- type is a concentration corresponding to a resistivity of 0.1Ωcm to 100Ωcm. Also, the phosphorus (P) concentration of n+ type is a concentration corresponding to a resistivity of 8mΩcm to 10mΩcm, the n type is a concentration corresponding to a resistivity of 0.1 to 100Ωcm, and the n- type is a concentration corresponding to a resistivity of 0.1Ωcm to 0.01Ωcm.

[0018] Fig. 1 is a cross-sectional view showing a variable capacitance element according to one embodiment of a semiconductor device of the present invention, and Fig. 2 is a plan view of the variable capacitance element shown in Fig. 1, seen from above, excluding an interlayer insulating film. The variable capacitance element (semiconductor device) 10 has a semiconductor substrate 11 of a first conductivity type, a groove 12 extending from one main surface 11a of the semiconductor substrate 11 in a thickness direction t, an insulating layer 13 covering the inner surface of the groove 12, and a first portion 14 made of a conductor formed inside the insulating layer 13 so as to fill the groove 12.

[0019] The variable capacitance element 10 also has a second portion 15 of a second conductivity type adjacent to the first portion 14 via the insulating layer 13 and extending from one main surface 11a of the semiconductor substrate 11 in the thickness direction t, and a third portion 16 of a third conductivity type adjacent to the second portion 15 and extending from one main surface 11a of the semiconductor substrate 11 in the thickness direction t.

[0020] Furthermore, the variable capacitance element 10 has an interlayer insulating film 17 covering one main surface 11a of the semiconductor substrate 11, a ground electrode 18 penetrating the interlayer insulating film 17 and conducting to the semiconductor substrate 11, and a gate electrode 19 penetrating the interlayer insulating film 17 and conducting to the first portion 14.

[0021] The semiconductor substrate 11 has a boron concentration of, for example, 5.5×10 14 ~14×10 14 atoms / cm 3 , the interstitial oxygen concentration is 6.5×10 17 ~13.5×10 17 atoms / cm 3 A p-type silicon single crystal wafer is sliced ​​from a p-type (first conductivity type) ingot pulled to have a resistivity of 0.1 Ωcm to 100 Ωcm.

[0022] The groove portion 12 is, for example, a groove (trench) having a rectangular cross section that extends from one main surface 11a ((100) plane) of the semiconductor substrate 11 in the thickness direction t. The groove portion 12 can be formed, for example, by forming a mask layer on one main surface 11a of the semiconductor substrate 11 and locally etching the mask layer. The depth of the groove portion 12 may be, for example, about 0.1 μm to 0.2 μm from the one main surface 11a.

[0023] The insulating layer 13 is made of silicon oxide (SiO 2 The insulating layer 13 can be formed by annealing the surface of the semiconductor substrate 11 in the presence of oxygen, and then removing the oxide film on one main surface 11a of the semiconductor substrate 11.

[0024] The insulating layer 13 is preferably formed so that the thickness thereof is the same on the side and bottom surfaces of the groove 12, and is formed to be, for example, about 0.003 μm to 0.1 μm. Depending on the thickness of the insulating layer 13, the capacitance (C 0 ) is determined.

[0025] The first portion 14 is formed so as to fill the groove 12 inside the insulating layer 13 of the groove 12, and its upper end is flush with one main surface 11a of the semiconductor substrate 11. The first portion 14 is made of n+ type (fourth conductivity type) polysilicon (polycrystalline silicon) into which phosphorus (P) has been ion-implanted, for example. The first portion 14 can be formed, for example, by filling the inside of the insulating layer 13 with polysilicon, and then ion-implanting phosphorus (P) to make it into an n+ type semiconductor.

[0026] The second portion 15 is formed in a region adjacent to the first portion 14 via the insulating layer 13 in the surface spreading direction w of one main surface 11a of the semiconductor substrate 11 so as to spread in a rectangular shape from one main surface 11a of the semiconductor substrate 11 in the thickness direction t. That is, the second portion 15 is connected to the first portion 14 via the insulating layer 13. The second portion 15 is formed by, for example, doping the p-type semiconductor substrate 11 with boron (B) at a concentration of, for example, 1×10 20 atoms / cm 3 It is made of p+ type (second conductivity type) single crystal silicon with a high concentration of ion implantation.

[0027] The second portion 15 can be formed by forming a mask layer around a portion of one main surface 11a of the semiconductor substrate 11 where the second portion 15 is to be formed, and ion-implanting boron (B) in the thickness direction t. The depth of the second portion 15 may be the same as the depth of the groove portion 12, and may be, for example, about 0.1 μm to 0.2 μm from the one main surface 11a. If the depth of the second portion 15 is up to 0.2 μm, the concentration of boron (B) can be made almost uniform.

[0028] The third portion 16 is formed in a region adjacent to the second portion 15 in the surface spreading direction w of one main surface 11a of the semiconductor substrate 11 so as to spread in a rectangular shape from one main surface 11a of the semiconductor substrate 11 in the thickness direction t. That is, the third portion 16 is adjacent to and connected to the second portion 15. The third portion 16 is formed, for example, by ion-implanting boron (B) at a medium concentration into the p-type semiconductor substrate 11, so that the boron concentration is, for example, 5×10 16 ~1×10 18 atoms / cm 3 It is sufficient for the semiconductor device to be made of p-type (third conductivity type) single crystal silicon implanted with a medium concentration of ions.

[0029] Such third portion 16 can be formed by forming a mask layer around a portion of one main surface 11a of semiconductor substrate 11 where third portion 16 is to be formed, and ion-implanting boron (B) in thickness direction t. The depth of third portion 16 may be the same as the depth of groove 12 and second portion 15, and may be, for example, about 0.1 μm to 0.2 μm from one main surface 11a. If the depth of third portion 16 is up to 0.2 μm, the concentration of boron (B) can be made almost uniform.

[0030] The interlayer insulating film 17 is a film made of an insulator and formed so as to cover one main surface 11a of the semiconductor substrate 11 except for the portions where the ground electrode 18 and the gate electrode 19 are formed. The interlayer insulating film 17 is made of, for example, silicon oxide (SiO 2 ) layer.

[0031] The ground electrode 18 and the gate electrode 19 are extraction electrodes that are electrically connected to the semiconductor substrate 11 and the first portion 14, respectively, and may be made of a conductive metal such as gold, silver, copper, or aluminum.

[0032] In the variable capacitance element (semiconductor device) 10 of this embodiment configured as described above, a depletion layer is formed by applying a reverse bias voltage between the ground electrode 18 and the gate electrode 19. The area of ​​the depletion layer changes depending on the voltage value, and the capacitance (C 0) also changes. Due to these characteristics, the variable capacitance element 10 can be used, for example, in a voltage controlled oscillator (VCO) in a mobile communication device or the like.

[0033] According to the variable capacitance element (semiconductor device) 10 of this embodiment, the n+ type first portion 14, the insulating layer 13, the p+ type second portion 15, and the p-type third portion 16 are arranged at a predetermined depth from one main surface 11a of the semiconductor substrate 11 along the surface spreading direction w, and therefore, unlike the conventional method, it is not necessary to implant ions at a uniform concentration into the inside (side and bottom surfaces) of the grooves formed in the semiconductor substrate. As a result, the capacitance (C 0 ) can be controlled, making it possible to form a profile that is not dependent on the abrupt junction.

[0034] In the above-described embodiment, the semiconductor substrate 11 of the first conductivity type is formed as p- type, the first portion 14 of the fourth conductivity type is formed as n+ type, the second portion 15 of the second conductivity type is formed as p+ type, and the third portion 16 of the third conductivity type is formed as p type, but the conductivity types are not limited to this. For example, the second conductive type second portion 15 can be an n+ type formed by high concentration ion implantation of phosphorus (P), and the third conductive type third portion 16 can be an n type formed by medium concentration ion implantation of phosphorus (P).

[0035] (Method of manufacturing a semiconductor device) Next, an example of a method for manufacturing a variable capacitance element (semiconductor device) having the above-mentioned configuration will be described. 3 and 4 are cross-sectional views showing a stepwise method of manufacturing a variable capacitance element according to one embodiment, which is an example of a semiconductor device of the present invention. When manufacturing the variable capacitance element (semiconductor device) 10 of this embodiment, first, a p-type (first conductivity type) semiconductor substrate 11 is prepared.

[0036] The semiconductor substrate 11 has a boron concentration of, for example, 5.5×10 14 ~14×10 14 atoms / cm 3 , the interstitial oxygen concentration is 6.5×10 17~13.5×10 17 atoms / cm 3 In this case, a p-type silicon single crystal wafer sliced ​​from a p-type (first conductivity type) ingot pulled to have a resistivity of 0.1 Ωcm to 0.01 Ωcm can be used.

[0037] 3(a), a mask layer 21 is formed on one main surface 11a of the semiconductor substrate 11. For example, a photoresist can be used as the mask layer 21. The mask layer 21 may have a thickness of, for example, about 1 μm to 1.5 μm, and may be patterned to surround the position where the groove portion 12 is to be formed.

[0038] 3(b), one main surface 11a side of the semiconductor substrate 11 is etched to form grooves 12 extending in the thickness direction t (groove forming step). The grooves 12 may be formed so that the depth from the one main surface 11a in the thickness direction t is, for example, about 0.1 μm to 0.2 μm.

[0039] Next, the semiconductor substrate 11 is annealed (thermal oxidation treatment) in the presence of oxygen to form silicon oxide (SiO 2 ) is formed, and then only the oxide film on one main surface 11a of the semiconductor substrate 11 is removed by etching to form an insulating layer 13 covering the inner surfaces (side and bottom surfaces) of the groove 12, as shown in FIG. 3(c) (insulating layer forming process).

[0040] The annealing treatment of the semiconductor substrate 11 can be performed, for example, by heating the semiconductor substrate 11 to 800° C. to 1100° C. in an oxidation type heat treatment furnace. In the insulating layer forming process, the capacitance (C 0 ) can be easily controlled.

[0041] Next, as shown in FIG. 4(a), inside the insulating layer 13 formed on the inner surface of the groove 12, a first portion 14 made of a conductor is formed so as to fill the groove 12 (first portion forming step).

[0042] In the first portion forming step, for example, a low-pressure chemical vapor deposition (LPCVD) device is used to form a polysilicon film inside the groove portion 12 from one main surface 11a of the semiconductor substrate 11, thereby forming the first portion 14. Note that, after the formation of the first portion 14, it is also preferable to perform a step of planarizing the exposed surface on the one main surface 11a side of the formed first portion 14.

[0043] Then, phosphorus (P) as an impurity is ion-implanted from one main surface 11a of semiconductor substrate 11 toward thickness direction t into the formation region of first portion 14. This forms first portion 14 of n+ type (fourth conductivity type) filling groove portion 12 inside insulating layer 13. When phosphorus (P) is implanted into the formation region of first portion 14, a mask layer may be formed to surround first portion 14, and this mask layer may be removed after the implantation.

[0044] 4(b), a mask layer 22 is formed on one main surface 11a of the semiconductor substrate 11. For example, a photoresist may be used as the mask layer 22. The mask layer 22 may be patterned to surround a position where the second portion 15 is to be formed.

[0045] Then, using mask layer 22 as an ion implantation mask, boron (B) as an impurity is ion-implanted at a high concentration from one main surface 11a of semiconductor substrate 11 toward thickness direction t in a region adjacent to first portion 14 via insulator layer 13 (sidewall), which is a planned position for forming second portion 15. This forms second portion 15 of p+ type (second conductivity type) adjacent to first portion 14 via insulator layer 13 and extending from one main surface 11a of semiconductor substrate 11 in thickness direction t (second portion forming step).

[0046] When forming the second portion 15, the ion implantation depth for implanting boron (B) from one main surface 11a of the semiconductor substrate 11 in the thickness direction t is suitably set to, for example, about 0.1 μm to 0.2 μm. If the ion implantation depth is shallower than 0.1 μm, there is a concern that the function as a p+ type region will be limited. Also, if the ion implantation depth is deeper than 0.2 μm, there is a concern that a concentration gradient of boron (B) will occur in the thickness direction t.

[0047] Next, after removing the mask layer 22 used to form the second portion 15, a mask layer 23 is formed on one main surface 11a of the semiconductor substrate 11 as shown in Fig. 4(c). For example, a photoresist may be used as the mask layer 23. For example, the mask layer 23 may be patterned so as to surround the intended position for forming the third portion 16.

[0048] Then, using mask layer 23 as an ion implantation mask, boron (B) as an impurity is ion-implanted at a medium concentration from one main surface 11a of semiconductor substrate 11 toward thickness direction t into a region adjacent to second portion 15, which is a position where third portion 16 is to be formed. This forms third portion 16 of p-type (third conductivity type) adjacent to second portion 15 and extending from one main surface 11a of semiconductor substrate 11 in thickness direction t (third portion forming step).

[0049] When forming the third portion 16, the ion implantation depth for implanting boron (B) from one main surface 11a of the semiconductor substrate 11 in the thickness direction t is suitably set to, for example, about 0.1 μm to 0.2 μm. If the ion implantation depth is shallower than 0.1 μm, there is a concern that the function as a p-type region will be limited. Also, if the ion implantation depth is deeper than 0.2 μm, there is a concern that a concentration gradient of boron (B) will occur in the thickness direction t.

[0050] Thereafter, the mask layer 23 used in forming the third portion 16 is removed, an interlayer insulating film 17 is formed so as to cover one main surface 11a of the semiconductor substrate 11, openings are formed in the interlayer insulating film 17 for forming the ground electrode 18 and the gate electrode 19, and the ground electrode 18 and the gate electrode 19 are formed from a conductive metal, thereby completing the formation of the variable capacitance element (semiconductor device) 10 of this embodiment shown in Figures 1 and 2.

[0051] According to the manufacturing method of the semiconductor device of the present embodiment as described above, it is possible to easily manufacture a semiconductor device having a plurality of semiconductor regions of different conductivity types sandwiched between oxide films by simply uniformly implanting ions from the main surface of the semiconductor substrate in the thickness direction, without performing a complex and difficult process of implanting ions while adjusting the ion implantation angle so that the side and bottom surfaces of a trench formed in the semiconductor substrate have the same concentration profile in order to form a step junction.

[0052] In the method for manufacturing a semiconductor device according to the present embodiment, the concentration profile of a plurality of semiconductor regions of mutually different conductivity types can be controlled simply by forming a mask layer, thereby realizing a method for manufacturing a semiconductor device that can easily form a plurality of semiconductor regions of mutually different conductivity types by ion implantation without precise control of semiconductor regions having a uniform ion concentration.

[0053] In this embodiment, an example has been given of forming an insulating layer and first, second, and third semiconductor regions of different conductivity types on a semiconductor substrate, but a semiconductor region of a different conductivity type can also be formed adjacent to each of these semiconductor regions. Furthermore, although a variable capacitance element has been shown as an example of a semiconductor device, the present invention is not limited to this and can be widely applied to MOS type semiconductor devices.

[0054] Although one embodiment of the present invention has been described above, this embodiment is presented as an example and is not intended to limit the scope of the invention. Such an embodiment can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and gist of the invention. [Explanation of symbols]

[0055] 10...Variable capacitance element (semiconductor device) 11...Semiconductor substrate 11a...One main surface 12...Groove 13...Insulating layer 14…First part 15…Second part 16...Third part 17...Interlayer insulating film 18...Ground electrode 19...Gate electrode

Claims

1. a semiconductor substrate made of a single crystal semiconductor and having a first conductivity type; a groove extending in a thickness direction from one main surface of the semiconductor substrate; an insulating layer covering an inner surface of the groove; a first portion made of a conductor formed inside the insulating layer so as to fill the groove; a second portion of a second conductivity type adjacent to the first portion via the insulating layer and extending in a thickness direction from the one main surface of the semiconductor substrate; and a third portion of a third conductivity type adjacent to the second portion and extending in a thickness direction from the one main surface of the semiconductor substrate, The semiconductor device is characterized in that the semiconductor substrate is a P- type semiconductor, the second portion is a P+ type semiconductor, and the third portion is a P type semiconductor.

2. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a variable capacitance element, and further comprises a ground electrode electrically connected to the semiconductor substrate and a gate electrode electrically connected to the first portion.

3. a groove forming step of forming a groove extending in a thickness direction from one main surface of a semiconductor substrate of a first conductivity type made of a single crystal semiconductor; an insulating layer forming step of forming an insulating layer covering an inner surface of the groove; a first portion forming step of forming a first portion made of a conductor so as to fill the groove inside the insulating layer; a second portion forming step of ion-implanting impurities from one main surface of the semiconductor substrate in a thickness direction toward a region adjacent to the first portion through the insulating layer, to form a second portion of a second conductivity type adjacent to the first portion through the insulating layer and extending in a thickness direction from the one main surface of the semiconductor substrate; a third portion forming step of ion-implanting an impurity from one main surface of the semiconductor substrate in a thickness direction toward a region adjacent to the second portion to form a third portion of a third conductivity type adjacent to the second portion and extending from the one main surface of the semiconductor substrate in a thickness direction, The semiconductor device manufacturing method according to the present invention is characterized in that the semiconductor substrate is a P- type semiconductor, the second portion is a P+ type semiconductor, and the third portion is a P type semiconductor.

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