Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device capable of securing an insulation distance between a semiconductor element and wiring while preventing damage to the semiconductor element.SOLUTION: A semiconductor device includes a first semiconductor element 1, a second semiconductor element, first wiring 11, and second wiring 7. The first semiconductor element 1 has a first main surface 1a and a second main surface 1b. An electrode 1c is formed on the first main surface 1a. The second semiconductor element is disposed at a position different from a position of the first semiconductor element 1 in a thickness direction from the first main surface 1a toward the second main surface 1b. The first wiring 11 includes an end 11a connected to the electrode 1c. The end 11a includes an upper surface 11aa and a cut surface 11ab. The cut surface 11ab is located in a direction different from the upper surface 11aa. A diameter D2 of the second wiring 7 is smaller than a diameter D1 of the first wiring. The second wiring 7 includes a first end 7a and a second end 7b. The first end 7a is directly connected to the upper surface 11aa at the end 11a of the first wiring 11.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Conventionally, there has been known a semiconductor device in which a base (bump) is formed on an electrode of a semiconductor element and wiring is bonded onto the base for the purpose of ensuring an insulating distance between the semiconductor element and wiring bonded to the electrode of the semiconductor element (see, for example, Japanese Patent Application Laid-Open No. 2004-247672). Japanese Patent Application Laid-Open No. 2004-247672 discloses a semiconductor device in which metal wiring is bonded multiple times onto an electrode of a semiconductor element to form a multi-stage bump as a base, and wiring is connected onto the multi-stage bump. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2004-247672 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described above, in order to form a base for connecting wiring to the electrodes, bonding operations are performed multiple times on the electrodes of the semiconductor element. In this case, the semiconductor element is subjected to impacts from the bonding operations multiple times, which may damage the semiconductor element.

[0005] In view of the above, an object of the present disclosure is to provide a semiconductor device capable of ensuring an insulation distance between a semiconductor element and wiring while suppressing damage to the semiconductor element. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a first semiconductor element, a second semiconductor element, a first wiring, and a second wiring. The first semiconductor element has a first main surface and a second main surface. The second main surface is located on the opposite side to the first main surface. An electrode is formed on the first main surface. The second semiconductor element is located at a position different from the first semiconductor element in a thickness direction from the first main surface to the second main surface. The first wiring is connected to the electrode. The first wiring includes an end portion connected to the electrode. The end portion includes an upper surface and a cut surface. The cut surface is located in a direction different from the upper surface. The second wiring electrically connects the first semiconductor element and the second semiconductor element. The diameter of the second wiring is smaller than the diameter of the first wiring. The second wiring includes a first end and a second end. The second end is located on the opposite side to the first end. The first end is directly connected to the upper surface at the end portion of the first wiring. The second end is connected to the second semiconductor element.

[0007] A semiconductor device according to the present disclosure includes a first semiconductor element, a second semiconductor element, a first wiring, and a second wiring. The first semiconductor element has a first main surface and a second main surface. The second main surface is located on the opposite side to the first main surface. An electrode is formed on the first main surface. The second semiconductor element is located at a position different from the first semiconductor element in a thickness direction from the first main surface to the second main surface. The first wiring is connected to the electrode. The first wiring has a ribbon-like shape and includes an end connected to the electrode. The end includes an upper surface. The second wiring electrically connects the first semiconductor element and the second semiconductor element. The diameter of the second wiring is smaller than the width in a direction intersecting the extension direction of the first wiring. The second wiring includes a first end and a second end. The second end is located on the opposite side to the first end. The first end is directly connected to the upper surface at the end of the first wiring. The second end is connected to the second semiconductor element.

[0008] A method for manufacturing a semiconductor device according to the present disclosure includes a step of preparing a first semiconductor element and a second semiconductor element. The first semiconductor element has a first main surface and a second main surface. The second main surface is located on the opposite side to the first main surface. An electrode is formed on the first main surface. The second semiconductor element is located at a position different from that of the first semiconductor element in a thickness direction from the first main surface to the second main surface. The method for manufacturing a semiconductor device further includes a step of connecting an end of a first wiring to the electrode, and a step of electrically connecting the first semiconductor element and the second semiconductor element by the second wiring. The end includes an upper surface and a cut surface. The cut surface is located in a direction different from that of the upper surface. The diameter of the second wiring is smaller than that of the first wiring. The second wiring includes a first end and a second end. The second end is located on the opposite side to the first end. In the step of electrically connecting by the second wiring, the first end is directly connected to the upper surface at the end of the first wiring. The second end is connected to the second semiconductor element.

[0009] A method for manufacturing a semiconductor device according to the present disclosure includes a step of preparing a first semiconductor element and a second semiconductor element. The first semiconductor element has a first main surface and a second main surface. The second main surface is located on the opposite side to the first main surface. An electrode is formed on the first main surface. The second semiconductor element is located at a position different from the first semiconductor element in a thickness direction from the first main surface to the second main surface. The method for manufacturing a semiconductor device further includes a step of connecting an end of a first wiring to the electrode, and a step of electrically connecting the first semiconductor element and the second semiconductor element by the second wiring. The first wiring has a ribbon-like shape. The end includes an upper surface. The diameter of the second wiring is smaller than the width in a direction intersecting the extension direction of the first wiring. The second wiring includes a first end and a second end. The second end is located on the opposite side to the first end. In the step of electrically connecting by the second wiring, the first end is directly connected to the upper surface at the end of the first wiring. The second end is connected to the second semiconductor element. Effect of the Invention

[0010] According to the above, a semiconductor device can be obtained that can ensure an insulation distance between a semiconductor element and wiring while suppressing damage to the semiconductor element. [Brief description of the drawings]

[0011] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a partial schematic cross-sectional view of the semiconductor device shown in FIG. [Diagram 3] 2 is a partial schematic plan view of the semiconductor device shown in FIG. 1. [Figure 4] 2 is a flowchart for explaining a method for manufacturing the semiconductor device shown in FIG. [Diagram 5] 2A to 2C are schematic diagrams for explaining a method for manufacturing the semiconductor device shown in FIG. [Figure 6] FIG. 11 is a partial schematic plan view of a semiconductor device according to a second embodiment. [Figure 7] 7 is a partial schematic cross-sectional view showing a modification of the semiconductor device shown in FIG. 6. [Figure 8] FIG. 11 is a partial schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 9] FIG. 11 is a partial schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 10] FIG. 13 is a partial schematic cross-sectional view of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments of the present disclosure will be described. Note that the same reference numerals are used to refer to the same components, and the description thereof will not be repeated.

[0013] Embodiment 1 <Configuration of Semiconductor Device> Fig. 1 is a schematic cross-sectional view of a semiconductor device according to embodiment 1. Fig. 2 is a partial schematic cross-sectional view of the semiconductor device shown in Fig. 1. Fig. 3 is a partial schematic plan view of the semiconductor device shown in Fig. 1. Fig. 2 is a cross-sectional view taken along a cross section passing through second wiring 7 and first wiring 11 of the portion shown in Fig. 3.

[0014] The semiconductor device according to the present disclosure mainly comprises lead frames 2a, 2b, a first semiconductor element 1, a second semiconductor element 8, a third semiconductor element 3, a first wiring 11, a second wiring 7, and a molding resin 4.

[0015] The lead frame 2a is disposed at a distance from the upper surface of the lead frame 2b. An IC terminal 6 is formed at an end of the lead frame 2a. A power terminal 5 is formed at an end of the lead frame 2b. The IC terminal 6 and the power terminal 5 are terminals for electrically connecting the semiconductor device to the outside. The lead frames 2a and 2b are made of, for example, copper or a copper alloy. The lead frames 2a and 2b have steps formed therein by bending. The lead frame 2a is disposed at a height position of a frame (not shown). The thickness of the lead frames 2a and 2b is set according to the current value flowing through the IC terminal 6 and the power terminal 5 during actual use of the semiconductor device in order to stably manufacture the lead frames 2a and 2b by pressing. The thickness of the lead frames 2a and 2b is, for example, 0.1 mm or more and 1 mm or less.

[0016] A second semiconductor element 8 is connected to the upper surface of the lead frame 2a via a bonding layer 10. The bonding layer 10 is a conductive bonding layer formed, for example, by hardening a silver (Ag) paste. A first semiconductor element 1 and a third semiconductor element 3 are arranged at a distance from each other on the upper surface of the lead frame 2b. The first semiconductor element 1 and the third semiconductor element 3 are each connected to the upper surface of the lead frame 2b via solder 9.

[0017] Second wiring 7 is arranged so as to connect between the first semiconductor element 1 and the second semiconductor element 8, and between the second semiconductor element 8 and the lead frame 2a. First wiring 11 is arranged so as to connect between the first semiconductor element 1 and the third semiconductor element 3, and between the third semiconductor element 3 and the lead frame 2b.

[0018] The first wiring 11 is connected to the first semiconductor element 1, which is a power semiconductor element such as an IGBT, and is a wiring through which a large current flows. For this reason, inexpensive aluminum (Al) is generally used as the material for the first wiring 11, although its electrical conductivity is not as high as that of silver (Ag). The diameter D1 of the first wiring 11, which is the aluminum wiring 16, is, for example, 0.1 mm or more and 0.5 mm or less.

[0019] The material of the second wiring 7 is selected from metals having relatively high electrical conductivity, such as gold (Au), silver (Ag), copper (Cu), etc. The diameter D2 of the second wiring 7 is, for example, 0.05 mm or less.

[0020] The mold resin 4 is formed so as to hold therein parts of the lead frames 2a and 2b, the first semiconductor element 1, the second semiconductor element 8, the third semiconductor element 3, the first wiring 11, and the second wiring 7. The mold resin 4 is made of, for example, a thermosetting epoxy resin. The mold resin 4 may contain a filler. For example, a filler made of silicon dioxide may be used as the filler. Such a mold resin 4 can have a thermal expansion coefficient close to that of the copper constituting the lead frames 2a and 2b.

[0021] The IC terminal 6 formed at the end of the lead frame 2a protrudes outside the molded resin 4. The power terminal 5 formed at the end of the lead frame 2b protrudes outside the molded resin 4. The power terminal 5 protrudes from a first side surface of the molded resin 4. The IC terminal 6 protrudes from a second side surface of the molded resin 4 located on the opposite side to the first side surface. The power terminal 5 is formed so as to extend in a direction (upward) intersecting with the upper surface of the lead frame 2b to which the first semiconductor element 1 is connected. The IC terminal 6 is formed so as to extend in a direction (upward) intersecting with the upper surface of the lead frame 2a to which the second semiconductor element 8 is connected. As shown in FIG. 1, the second semiconductor element 8 is disposed at a position different from the first semiconductor element 1 in the thickness direction from the first main surface 1a toward the second main surface 1b, that is, in the direction indicated by the arrow 30 in FIG. 1.

[0022] The first semiconductor element 1 is, for example, an insulated gate bipolar transistor (IGBT). The first semiconductor element 1 may be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). The second semiconductor element 8 is, for example, an integrated circuit (IC). The third semiconductor element 3 is a diode element. ,Ta For example, it may be a SBD (Schottky Barrier Diode). The material constituting the first semiconductor element 1 and the third semiconductor element 3 may be, for example, silicon, but may also be other materials such as silicon carbide.

[0023] As shown in FIG. 2, the first semiconductor element 1 has a first main surface 1a and a second main surface 1b. The second main surface 1b is located on the opposite side to the first main surface 1a. An electrode 1c is formed on the first main surface 1a. The second main surface 1b faces the lead frame 2b. The first wiring 11 is connected to the electrode 1c. The first wiring 11 includes an end 11a connected to the electrode 1c. The first wiring 11 is connected to the electrode 1c by wedge bonding. Therefore, the end 11a includes an upper surface 11aa and a cut surface 11ab. The cut surface 11ab is a sheared surface of the first wiring 11 and is located in a different direction from the upper surface 11aa. The cut surface 11ab is a side end surface at the end 11a of the first wiring 11.

[0024] The second wiring 7 electrically connects the first semiconductor element 1 and the second semiconductor element 8. As shown in FIG. 2, the diameter D2 of the second wiring 7 is smaller than the diameter D1 of the first wiring. The second wiring 7 includes a first end 7a and a second end 7b. The second end 7b is located on the opposite side to the first end 7a. The first end 7a is directly connected to the upper surface 11aa of the end 11a of the first wiring 11. As shown in FIG. 1, the second end 7b is connected to the second semiconductor element 8.

[0025] 3, two first wirings 11 are connected to the electrode 1c of the first semiconductor element 1. The number of first wirings 11 connected to the electrode 1c may be three or more. The second wirings 7 are connected to each of the multiple first wirings 11 connected to the electrode 1c.

[0026] The second wiring 7 is connected to the first semiconductor element 1 and the second semiconductor element 8 by ball bonding. At either the first end 7a or the second end 7b of the second wiring 7, the planar shape of the portion connected to the upper surface 11aa at the end 11a of the first wiring 11 or the electrode (not shown) of the second semiconductor element 8 is, for example, circular or semicircular. At least a part of the planar shape of the portion is curved. In other words, unlike the end 11a of the first wiring 11, either the first end 7a or the second end 7b of the second wiring 7 does not have a cut surface.

[0027] In the above-mentioned semiconductor device, the power terminal 5 and IC terminal 6 protruding from the mold resin 4 and the region (die bond region) to which the first semiconductor element 1, the second semiconductor element 8, and the third semiconductor element 3 are connected are formed by the same lead frame 2a, 2b, but the die bond region may be formed by an insulating substrate. As the insulating substrate, for example, an insulating substrate having a laminated structure in which a first metal layer is formed on the upper surface of an insulating layer and a second metal layer is formed on the lower surface thereof may be used. The first metal layer and the second metal layer are electrically insulated by the insulating layer. In this case, the first semiconductor element 1, the second semiconductor element 8, or the third semiconductor element 3 is mounted on the first metal layer. The power terminal 5 and IC terminal 6 may be connected to the first metal layer by a bonding material such as solder, or may be directly connected to the first metal layer by ultrasonic bonding or the like. Alternatively, the power terminal 5 and IC terminal 6 may be connected to the first metal layer via a connection wiring.

[0028] <Method of Manufacturing Semiconductor Device> Fig. 4 is a flow chart for explaining a method for manufacturing the semiconductor device shown in Fig. 1. Fig. 5 is a schematic view for explaining a method for manufacturing the semiconductor device shown in Fig. 1.

[0029] As shown in FIG. 4, in the manufacturing method of the semiconductor device, a preparation step (S10) is first performed. In this step (S10), lead frames 2a and 2b, a first semiconductor element 1, a second semiconductor element 8, and a third semiconductor element 3 are prepared. Furthermore, the first semiconductor element 1, the second semiconductor element 8, and the third semiconductor element 3 are bonded to the lead frames 2a and 2b. The first semiconductor element 1 has a first main surface 1a and a second main surface 1b as shown in FIG. 2. The second main surface 1b is located on the opposite side to the first main surface 1a. An electrode 1c is formed on the first main surface 1a. The second semiconductor element 8 is bonded to the lead frame 2a located above the lead frame 2b to which the first semiconductor element 1 is bonded. Specifically, a silver paste is placed on the upper surface of the lead frame 2a, and the second semiconductor element 8 is mounted on the silver paste. The silver paste is hardened by heating in an oven to form a bonding layer 10 (see FIG. 1). The second semiconductor element 8 is joined to the lead frame 2a by the bonding layer 10. The first semiconductor element 1 and the third semiconductor element 3 are each joined to the lead frame 2b by solder 9 (see FIG. 1). The second semiconductor element 8 is disposed above the first semiconductor element 1 at a different position from the first semiconductor element 1 in the thickness direction from the first main surface 1a to the second main surface 1b.

[0030] Next, the first wiring step (S20) is performed. In this step, the end 11a of the first wiring 11 is connected to the electrode 1c. Specifically, the electrode 1c (see FIG. 2) of the first semiconductor element 1 and the electrode of the third semiconductor element 3 are connected by the first wiring 11. Also, the electrode of the third semiconductor element 3 and a pad (not shown) formed on the lead frame 2b are connected by the first wiring 11. The first wiring 11 is connected by wedge bonding using an ultrasonic bonding device. In wedge bonding, for example, at the end 11a bonded to the electrode 1c, an indentation caused by pressing with a tool remains on the upper surface 11aa. Also, at the side end of the end 11a, a cut surface 11ab is formed by cutting the first wiring 11 during wedge bonding.

[0031] Next, a second wiring step (S30) is performed. In this step (S30), the first semiconductor element 1 and the second semiconductor element 8 are electrically connected by the second wiring 7. Also, the second semiconductor element 8 and the pad of the lead frame 2a are electrically connected by the second wiring 7. On the electrode 1c of the first semiconductor element 1, the first end 7a of the second wiring 7 is directly connected to the upper surface 11aa at the end 11a of the first wiring 11. The second end 7b is connected to the second semiconductor element 8. Also, the second semiconductor element 8 and the pad (not shown) formed on the lead frame 2a are connected by the second wiring 7. The second wiring 7 is connected by ball bonding.

[0032] Here, ball bonding will be briefly described. In ball bonding of the second wiring 7, as shown in FIG. 5, the second wiring 7 is held in a state where the end of the second wiring 7 protrudes from the tip of the capillary 13 attached to the tip of the horn 12 in the ultrasonic bonding device. The capillary 13 is a cylindrical bonding tool. The second wiring 7 is inserted inside the capillary 13 and partially protrudes from the tip of the capillary 13 as described above. The spark rod 15 is arranged so as to face the second wiring 7 protruding from the tip of the capillary 13. By applying a voltage to the spark rod 15, a discharge is generated between the spark rod 15 and the tip of the second wiring 7. The tip of the second wiring 7 is melted by the discharge, and a FAB (Free Air Ball) 14 is formed. After the FAB 14 is formed, the horn 12 and the capillary 13 are moved, and the FAB 14 of the second wiring 7 is pressed against an electrode (not shown) formed on the upper surface of the second semiconductor element 8, which is the part to be bonded. In this state, ultrasonic waves are applied to the second wiring 7 to bond the FAB 14 of the second wiring 7 to the electrode of the second semiconductor element 8.

[0033] Then, the horn 12 and the capillary 13 are moved while the second wiring 7 is paid out from the tip of the capillary 13 so that the second wiring 7 forms a loop. After the capillary 13 moves onto the upper surface 11aa (see FIG. 2) of the end 11a of the first wiring 11, a part of the second wiring 7 located at the tip of the capillary 13 is pressed against the upper surface 11aa (see FIG. 2) of the end 11a of the first wiring 11. By applying ultrasonic waves to the second wiring 7 in this state, the second wiring 7 is joined to the end 11a of the first wiring 11. Then, the capillary 13 rises while holding a part of the second wiring 7 so as to move away from the end 11a of the first wiring 11. As a result, a tensile stress is applied to a part of the second wiring 7 located between the part (fixed part) of the second wiring 7 joined to the end 11a of the first wiring 11 and the capillary 13, and the part is broken. In this manner, the first semiconductor element 1 and the second semiconductor element 8 are electrically connected by the second wiring 7. The second wiring 7 connected to the first semiconductor element 1 is a wiring on the source side.

[0034] In this way, the second wiring 7 having a relatively small diameter D2 is connected by ball bonding to the first wiring 11 (so-called wedge-bonded wiring) having a diameter D1 larger than the diameter D2 of the second wiring 7 and having a cut surface 11ab at the end 11a which is the connection portion with the electrode 1c. In this way, since the second wiring 7 is connected onto the end 11a of the first wiring 11, the distance L1 between the surface of the electrode 1c of the first semiconductor element 1 and the second wiring 7 can be made sufficiently large as shown in FIG. 2. In addition, since the second wiring 7 is not directly ball-bonded to the surface of the electrode 1c of the first semiconductor element 1, the possibility of the first semiconductor element 1 being damaged by the impact caused by the bonding operation can be reduced.

[0035] The bonding method of the second wiring 7 that connects the second semiconductor element 8 and the pad of the lead frame 2a is basically the same as the above-mentioned method. Specifically, after the FAB is formed at the tip of the second wiring 7, the horn 12 and the capillary 13 are moved to press the FAB 14 of the second wiring 7 against an electrode (not shown) formed on the upper surface of the second semiconductor element 8. In this state, ultrasonic waves are applied to the second wiring 7 to bond the FAB 14 of the second wiring 7 to the electrode of the second semiconductor element 8. Next, the horn 12 and the capillary 13 are moved while the second wiring 7 is paid out from the tip of the capillary 13 so that the second wiring 7 forms a loop. After the capillary 13 moves onto the pad of the lead frame 2a, a part of the second wiring 7 located at the tip of the capillary 13 is pressed against the pad. In this state, ultrasonic waves are applied to the second wiring 7 to bond the second wiring 7 to the pad of the lead frame 2a. Thereafter, the capillary 13 rises away from the lead frame 2a while holding a portion of the second wiring 7. As a result, a tensile stress is applied to a portion of the second wiring 7 located between the capillary 13 and a portion (fixed portion) of the second wiring 7 joined to the pad of the lead frame 2a, causing the portion to break. In this manner, the second semiconductor element 8 and the pad of the lead frame 2a are electrically connected by the second wiring 7.

[0036] Next, a post-processing step (S40) is performed. In this step (S40), a part of the lead frames 2a, 2b, the first semiconductor element 1, the second semiconductor element 8, the third semiconductor element 3, the first wiring 11, and the second wiring 7 are sealed with a molding resin 4. The molding resin 4 is molded using, for example, a transfer molding device. In this manner, the semiconductor device shown in FIGS. 1 to 3 is manufactured.

[0037] <effect> The semiconductor device according to the present disclosure includes a first semiconductor element 1, a second semiconductor element 8, a first wiring 11, and a second wiring 7. The first semiconductor element 1 has a first main surface 1a and a second main surface 1b. The second main surface 1b is located on the opposite side to the first main surface 1a. An electrode 1c is formed on the first main surface 1a. The second semiconductor element 8 is located at a position different from that of the first semiconductor element 1 in the thickness direction from the first main surface 1a to the second main surface 1b. The first wiring 11 is connected to the electrode 1c. The first wiring 11 includes an end 11a connected to the electrode 1c. The end 11a includes an upper surface 11aa and a cut surface 11ab. The cut surface 11ab is located in a direction different from that of the upper surface 11aa. The second wiring 7 electrically connects the first semiconductor element 1 and the second semiconductor element 8. The diameter D2 of the second wiring 7 is smaller than the diameter D1 of the first wiring. The second wiring 7 includes a first end 7a and a second end 7b. The second end 7b is located on the opposite side to the first end 7a. The first end 7a is directly connected to an upper surface 11aa of the end 11a of the first wiring 11. The second end 7b is connected to the second semiconductor element 8.

[0038] In this case, since the second wiring 7 is connected to the upper surface 11aa at the end 11a of the first wiring 11, the distance L1 between the second wiring 7 and the first semiconductor element 1 can be sufficiently ensured by the first wiring 11. Also, since the end 11a serving as the base of the second wiring 7 is connected to the electrode 1c, shocks due to multiple bonding operations to form a base on the first semiconductor element 1 are not applied, as in the conventional case of forming a multi-stage bump as a base. Therefore, the possibility of the first semiconductor element 1 being damaged due to such shocks can be reduced.

[0039] For example, when the first semiconductor element 1 and the second semiconductor element 8 arranged at different positions in the thickness direction of the first semiconductor element 1 are connected by the second wiring 7 to be ball-bonded, the head portion of the capillary 13 (see FIG. 5) of the ultrasonic bonding device used for ball bonding will be inclined at different angles on the first semiconductor element 1 and on the second semiconductor element 8. If the inclination of the head portion differs in this way, the stress applied to the second wiring 7 during bonding will change compared to the normal state (when the head portion is in a position almost perpendicular to the first semiconductor element 1, etc.). Therefore, it is possible that a stress different from the normal state will be applied to the first semiconductor element 1 during bonding, causing the first semiconductor element 1 to be damaged. However, in the above-mentioned semiconductor device, the second wiring 7 is connected to the end 11a of the first wiring 11 and does not directly contact the first semiconductor element 1. Therefore, the occurrence of the above-mentioned problem can be suppressed.

[0040] The method for manufacturing a semiconductor device according to the present disclosure includes a step (S10) of preparing a first semiconductor element 1 and a second semiconductor element 8. The first semiconductor element 1 has a first main surface 1a and a second main surface 1b. The second main surface 1b is located on the opposite side to the first main surface 1a. An electrode 1c is formed on the first main surface 1a. The second semiconductor element 8 is located at a position different from the first semiconductor element 1 in the thickness direction from the first main surface 1a to the second main surface 1b. The method for manufacturing a semiconductor device further includes a step (S20) of connecting an end 11a of a first wiring 11 to the electrode 1c, and a step (S30) of electrically connecting the first semiconductor element 1 and the second semiconductor element 8 by a second wiring 7. The end 11a includes an upper surface 11aa and a cut surface 11ab. The cut surface 11ab is located in a direction different from the upper surface 11aa. The diameter D2 of the second wiring 7 is smaller than the diameter D1 of the first wiring 11. The second wiring 7 includes a first end 7a and a second end 7b. The second end 7b is located on the opposite side to the first end 7a. In the step (S30) of electrically connecting through the second wiring 7, the first end 7a is directly connected to the upper surface 11aa of the end 11a of the first wiring 11. The second end 7b is connected to the second semiconductor element 8.

[0041] In this manner, the semiconductor device shown in FIGS. 1 to 3 can be obtained.

[0042] In the method for manufacturing a semiconductor device described above, in the step (S20) of connecting the end 11a of the first wiring 11, the end 11a may be connected to the electrode 1c by wedge bonding. In the step (S30) of electrically connecting via the second wiring 7, the second wiring 7 may be connected to the first semiconductor element 1 and the second semiconductor element 8 by ball bonding.

[0043] In this case, the upper surface 11aa of the end 11a of the first wiring is pressed by the processing tool during wedge bonding, and therefore becomes a relatively flat surface suitable for joining the first end 7a of the second wiring 7. Therefore, the first end 7a of the second wiring 7 can be easily joined to the end 11a of the first wiring 11.

[0044] Embodiment 2 <Configuration of Semiconductor Device> Fig. 6 is a partial schematic plan view of a semiconductor device according to embodiment 2. The semiconductor device shown in Fig. 6 basically has the same configuration as the semiconductor device shown in Fig. 1 to Fig. 3 and can obtain the same effects, but differs from the semiconductor device shown in Fig. 1 to Fig. 3 in that the first wiring 11 is a ribbon wire 19 having a ribbon-like shape.

[0045] The ribbon wire 19 includes an end 11a connected to the electrode 1c. The ribbon wire 19 has a rectangular cross-sectional shape in a width direction intersecting with the extension direction. The end 11a includes an upper surface 11aa. The second wiring 7 electrically connects the first semiconductor element 1 and the second semiconductor element 8 (see FIG. 1). The diameter D2 of the second wiring 7 is smaller than the width W of the ribbon wire 19 as the first wiring 11 in a direction intersecting with the extension direction. The second wiring 7 includes a first end 7a and a second end 7b (see FIG. 1). The second end 7b is located on the opposite side to the first end 7a. The second end 7b is connected to the second semiconductor element 8 as shown in FIG. 1. The first end 7a is directly connected to the upper surface 11aa of the end 11a of the first wiring 11.

[0046] The material of the ribbon wire 19 can be, for example, aluminum. In this case, when the second wiring 7 is bonded to the ribbon wire 19, the impact generated during the bonding (for example, the impact generated when ultrasonic bonding is performed) can be absorbed to some extent by the ribbon wire 19. This reduces the possibility that the first semiconductor element 1 will be damaged by the impact.

[0047] <Method of Manufacturing Semiconductor Device> The manufacturing method of the semiconductor device shown in FIG. 6 has a basically similar configuration to the manufacturing method of the semiconductor device shown in FIG. 4, but the content of the first wiring step (S20) shown in FIG. 4 is partially different. In this step (S20), the end 11a of the ribbon wire 19 as the first wiring 11 is connected to the electrode 1c. Specifically, the electrode 1c (see FIG. 2) of the first semiconductor element 1 and the electrode of the third semiconductor element 3 are connected by the ribbon wire 19. Also, the electrode of the third semiconductor element 3 and a pad (not shown) formed on the lead frame 2b are connected by the ribbon wire 19 or a normal conductive wire. The ribbon wire 19 is connected by wedge bonding using an ultrasonic bonding device. In wedge bonding, for example, at the end 11a to be bonded to the electrode 1c, an indentation caused by pressing with a tool remains on the upper surface 11aa.

[0048] Other than the above step (S20), steps (S10), (S30) and (S40) are the same as those in the method for manufacturing a semiconductor device shown in FIG.

[0049] <Modification> Fig. 7 is a partial cross-sectional schematic diagram showing a modified example of the semiconductor device shown in Fig. 6. The semiconductor device shown in Fig. 7 basically has the same configuration as the semiconductor device shown in Fig. 6 and can obtain the same effect, but the configuration of the joint between the ribbon wire 19 as the first wiring 11 and the electrode 1c is different from that of the semiconductor device shown in Fig. 6. In the semiconductor device shown in Fig. 7, the ribbon wire 19 is joined to the electrode 1c via the solder 31. The thickness of the solder 31 is smaller than the thickness T of the ribbon wire 19 as the first wiring 11.

[0050] <effect> As shown in FIG. 1, FIG. 6, and FIG. 7, the semiconductor device according to the present disclosure includes a first semiconductor element 1, a second semiconductor element 8, a ribbon wire 19 as a first wiring 11, and a second wiring 7. The first semiconductor element 1 has a first main surface 1a and a second main surface 1b. The second main surface 1b is located on the opposite side to the first main surface 1a. An electrode 1c is formed on the first main surface 1a. The second semiconductor element 8 is located at a position different from that of the first semiconductor element 1 in the thickness direction from the first main surface 1a to the second main surface 1b. The ribbon wire 19 as the first wiring 11 is connected to the electrode 1c. The ribbon wire 19 as the first wiring 11 has a ribbon-like shape and includes an end 11a connected to the electrode 1c. The end 11a includes an upper surface 11aa. The second wiring 7 electrically connects the first semiconductor element 1 and the second semiconductor element 8. The diameter D2 of the second wiring 7 is smaller than the width W in a direction intersecting the extension direction of the first wiring 11. The diameter D2 of the second wiring 7 is smaller than the thickness T of the ribbon wire 19 serving as the first wiring 11. The second wiring 7 includes a first end 7a and a second end 7b. The second end 7b is located on the opposite side to the first end 7a. The first end 7a is directly connected to the upper surface 11aa of the end 11a of the ribbon wire 19 serving as the first wiring 11. The second end 7b is connected to the second semiconductor element 8.

[0051] In this case, the second wiring 7 is connected to the upper surface 11aa at the end 11a of the ribbon wire 19, which is the ribbon-shaped first wiring 11, so that the distance L1 between the second wiring 7 and the first semiconductor element 1 can be sufficiently secured by the ribbon wire 19. Also, since the end 11a serving as the base of the second wiring 7 is connected to the electrode 1c, shocks due to multiple bonding operations to form a base on the first semiconductor element 1 are not applied, unlike in the conventional case where a multi-stage bump is formed as a base. Therefore, the possibility of the first semiconductor element 1 being damaged due to the shocks can be reduced.

[0052] In addition, since ribbon wire 19 is used as first wiring 11, the area of ​​upper surface 11aa of end 11a can be made larger than when first wiring 11 is a linear wiring. This increases the degree of freedom in selecting the connection position of second wiring 7 to upper surface 11aa. In addition, multiple second wirings 7 can be easily connected to end 11a.

[0053] The method for manufacturing a semiconductor device according to the present disclosure includes a step (S10) of preparing a first semiconductor element 1 and a second semiconductor element 8. The first semiconductor element 1 has a first main surface 1a and a second main surface 1b. The second main surface 1b is located on the opposite side to the first main surface 1a. An electrode 1c is formed on the first main surface 1a. The second semiconductor element 8 is located at a position different from the first semiconductor element 1 in the thickness direction from the first main surface 1a to the second main surface 1b. Furthermore, the method for manufacturing a semiconductor device includes a step (S20) of connecting an end 11a of a ribbon wire 19 as a first wiring 11 to the electrode 1c, and a step (S30) of electrically connecting the first semiconductor element 1 and the second semiconductor element 8 by the second wiring 7. The first wiring 11 is a ribbon wire 19 having a ribbon-like shape. The end 11a includes an upper surface 11aa. A diameter D2 of the second wiring 7 is smaller than a width W in a direction intersecting the extending direction of the ribbon wire 19 serving as the first wiring 11. The second wiring 7 includes a first end 7a and a second end 7b. The second end 7b is located on the opposite side to the first end 7a. In the step (S30) of electrically connecting by the second wiring 7, the first end 7a is directly connected to an upper surface 11aa of the end 11a of the ribbon wire 19 serving as the first wiring 11. The second end 7b is connected to the second semiconductor element 8.

[0054] In this way, the semiconductor device shown in FIG. 6 can be obtained.

[0055] Embodiment 3 <Configuration of Semiconductor Device> FIG. 8 is a partial cross-sectional schematic diagram of a semiconductor device according to a third embodiment. The semiconductor device shown in FIG. 8 basically has the same configuration as the semiconductor device shown in FIG. 6 and can obtain the same effect, but the configuration of the joint between the ribbon wire 19 as the first wiring 11 and the electrode 1c is different from that of the semiconductor device shown in FIG. 6. Specifically, in the semiconductor device shown in FIG. 8, the first wiring 11 is folded and stacked at the end 11a of the ribbon wire 19 as the first wiring 11. In FIG. 8, the ribbon wire 19 is folded twice at the end 11a to form a stacked structure 20 with three stacked layers. At the end 11a, the upper surface 11aa is the top surface of the stacked ribbon wire 19. The first end 7a of the second wiring 7 is connected to the top surface of the stacked ribbon wire 19. The direction in which the ribbon wire 19 extends from the end 11a and the direction in which the second wiring 7 extends away from the upper surface 11aa of the end 11a are opposite in the horizontal direction.

[0056] <Method of Manufacturing Semiconductor Device> The manufacturing method of the semiconductor device shown in FIG. 8 has a basically similar configuration to the manufacturing method of the semiconductor device shown in FIG. 6, but the content of the first wiring step (S20) shown in FIG. 4 is partially different. In this step (S20), the ribbon wire 19 as the first wiring 11 is bent and laminated on the electrode 1c. Specifically, the tip of the ribbon wire 19 as the first wiring 11 is connected to the electrode 1c, and the tip of the ribbon wire 19 is bent to form a laminated structure 20. In the step (S20), the electrode 1c (see FIG. 2) of the first semiconductor element 1 and the electrode of the third semiconductor element 3 are connected by the ribbon wire 19. In addition, the electrode of the third semiconductor element 3 and a pad (not shown) formed on the lead frame 2b are connected by the ribbon wire 19 or a normal conductive wire. The ribbon wire 19 is connected by wedge bonding using an ultrasonic bonding device. When connecting the ribbon wire 19 to the electrode 1c of the first semiconductor element 1, first, the tip of the ribbon wire 19 is joined to the electrode 1c by wedge bonding, as shown in Fig. 8. Then, the ribbon wire 19 is pressed in a state where it is folded multiple times on the tip by operating a bonding tool. As a result, as shown in Fig. 8, an end 11a is obtained, which is a laminated structure 20 in which the ribbon wire 19 is folded multiple times and laminated.

[0057] Other than the above step (S20), steps (S10), (S30) and (S40) are the same as those in the method for manufacturing a semiconductor device shown in FIG.

[0058] <effect> In the above-described semiconductor device, the ribbon wire 19 as the first wiring 11 may be folded and stacked at the end 11a of the ribbon wire 19 as the first wiring 11. At the end 11a, the upper surface 11aa may be the top surface of the ribbon wire 19 as the stacked first wiring 11.

[0059] In this case, even if the thickness T of the first wiring is not sufficiently thick, the ribbon wire 19 is folded and laminated at the end 11a, so that the height from the electrode 1c to the upper surface 11aa of the end 11a (the height of the end 11a) can be made sufficiently large. Therefore, as in the semiconductor device shown in FIG. 1 to FIG. 3, the distance L1 between the second wiring 7 and the first semiconductor element 1 can be made sufficiently large. In addition, since the height of the end 11a can be controlled by changing the number of layers of the ribbon wire 19, it is not necessary to use a special ribbon wire 19 with a thicker thickness T as the first wiring 11, and a general ribbon wire 19 can be used. Therefore, the increase in the manufacturing cost of the semiconductor device can be suppressed.

[0060] In the above-described method for manufacturing a semiconductor device, in the step (S20) of connecting end 11a of first wiring 11, first wiring 11 may be bent at end 11a and stacked on electrode 1c. In the step (S30) of electrically connecting via second wiring 7, upper surface 11aa at end 11a may be the top surface of stacked first wiring 11.

[0061] In this case, the semiconductor device shown in FIG. 8 can be obtained.

[0062] Embodiment 4 <Configuration of Semiconductor Device> FIG. 9 is a partial cross-sectional schematic diagram of a semiconductor device according to a fourth embodiment. The semiconductor device shown in FIG. 9 basically has the same configuration as the semiconductor device shown in FIG. 6 and can obtain the same effect, but the configuration of the joint between the ribbon wire 19 as the first wiring 11 and the electrode 1c is different from that of the semiconductor device shown in FIG. 6. Specifically, in the semiconductor device shown in FIG. 9, the end 11a of the ribbon wire 19 as the first wiring 11 includes a fixed portion 11ac and a loop portion 11ad. The fixed portion 11ac is directly connected to the electrode 1c. The loop portion 11ad is continuous with the fixed portion 11ac and is convex in a direction away from the electrode 1c in the thickness direction of the fixed portion 11ac (a direction toward the second semiconductor element 8 or an upward direction). The end of the loop portion 11ad opposite to the side connected to the fixed portion 11ac extends to above the third semiconductor element 3 (see FIG. 1) in the ribbon wire 19. In the end 11a, the upper surface 11aa is the upper surface of the loop portion 11ad. The second wiring 7 is connected to the upper surface 11aa of the loop portion 11ad.

[0063] A part of the loop portion 11ad is located on the fixed portion 11ac. In a plan view seen from a direction perpendicular to the surface of the electrode 1c, a part of the loop portion 11ad overlaps with the fixed portion 11ac. The first end 7a of the second wiring 7 may be connected to the loop portion 11ad at a position overlapping with the fixed portion 11ac in a plan view. Alternatively, the first end 7a of the second wiring 7 may be connected to the loop portion 11ad at a position not overlapping with the fixed portion 11ac in a plan view. The direction in which the ribbon wire 19 extends from the end portion 11a and the direction in which the second wiring 7 extends away from the upper surface 11aa of the end portion 11a are opposite to each other in the horizontal direction.

[0064] <Method of Manufacturing Semiconductor Device> The manufacturing method of the semiconductor device shown in FIG. 9 has a basically similar configuration to the manufacturing method of the semiconductor device shown in FIG. 6, but the content of the first wiring step (S20) shown in FIG. 4 is partially different. In this step (S20), when the ribbon wire 19 is connected to the electrode 1c of the first semiconductor element 1, the end 11a consisting of the fixed portion 11ac and the loop portion 11ad is formed by the ribbon wire 19 as the first wiring 11. Specifically, as shown in FIG. 9, the tip of the ribbon wire 19 is bonded to the electrode 1c by wedge bonding to form the fixed portion 11ac. Thereafter, the ribbon wire 19 is bent so that the ribbon wire 19 forms the loop portion 11ad on the fixed portion 11ac by operating the bonding tool. As a result, as shown in FIG. 9, the end 11a of the ribbon wire 19 has the fixed portion 11ac directly connected to the electrode 1c and the loop portion 11ad that is connected to the fixed portion 11ac and is convex from the electrode 1c to the second semiconductor element 8 side in the thickness direction of the ribbon wire 19.

[0065] Other than the above step (S20), steps (S10), (S30), and (S40) are the same as those in the method for manufacturing a semiconductor device shown in Fig. 4. In step (S30), the second wiring 7 is connected to the upper surface of the loop portion 11ad, which serves as the upper surface 11aa, at the end portion 11a.

[0066] <effect> In the above semiconductor device, the end 11a of the ribbon wire 19 serving as the first wiring 11 includes a fixed portion 11ac and a loop portion 11ad. The fixed portion 11ac is directly connected to the electrode 1c. The loop portion 11ad is continuous with the fixed portion 11ac and protrudes from the electrode 1c toward the second semiconductor element 8 in the thickness direction. In the end 11a, the upper surface 11aa may be the upper surface of the loop portion 11ad.

[0067] In this case, in the loop portion 11ad to which the first end 7a of the second wiring 7 is connected, a space is formed under the region to which the first end 7a is connected. Therefore, even if a tool (such as a capillary) for connecting the second wiring 7 comes into contact with the end 11a of the ribbon wire 19 when connecting the first end 7a of the second wiring 7 to the ribbon wire 19, the loop portion 11ad can be easily displaced, so that it is possible to prevent excessive force from being applied to the tool. Therefore, it is possible to reduce the possibility that the tool will be damaged or that a defect will occur in the process of connecting the end 11a of the second wiring 7.

[0068] In the above-described method for manufacturing a semiconductor device, in the step (S20) of connecting end 11a of first wiring 11, end 11a of first wiring 11 may be formed with fixed portion 11ac directly connected to electrode 1c, and loop portion 11ad continuing to fixed portion 11ac and protruding from electrode 1c toward second semiconductor element 8 in the thickness direction. In the step (S30) of electrically connecting through second wiring 7, upper surface 11aa of end 11a may be the upper surface of loop portion 11ad.

[0069] In this case, the semiconductor device shown in FIG. 9 can be obtained.

[0070] Embodiment 5. <Configuration of Semiconductor Device> FIG. 10 is a partial cross-sectional schematic diagram of a semiconductor device according to a fifth embodiment. The semiconductor device shown in FIG. 10 basically has the same configuration as the semiconductor device shown in FIG. 8 and can obtain the same effect, but the configuration of the joint between the ribbon wire 19 as the first wiring 11 and the electrode 1c is different from that of the semiconductor device shown in FIG. 8. Specifically, in the semiconductor device shown in FIG. 10, the end 11a of the ribbon wire 19 as the first wiring 11 includes a closed loop-shaped loop portion 11ad and a laminated fixing portion 11ae. The laminated fixing portion 11ae is a laminated structure portion including a bottom layer directly connected to the electrode 1c and an upper layer laminated on the bottom layer. The loop portion 11ad is connected to the laminated fixing portion 11ae and is convex from the electrode 1c in the thickness direction of the laminated fixing portion 11ae in the direction away from the electrode 1c (the direction toward the second semiconductor element 8 or the upward direction). Both ends of the loop portion 11ad are connected to the upper layer laminated on the laminated fixing portion 11ae. Therefore, the loop portion 11ad is a closed loop. A part of the loop portion 11ad is located outside the laminated fixing portion 11ae in a plan view. At the end portion 11a, the upper surface 11aa is the upper surface of the loop portion 11ad. The second wiring 7 is connected to the upper surface 11aa of the loop portion 11ad.

[0071] A part of the loop portion 11ad is located on the bottom layer of the laminated structure. In a plan view seen from a direction perpendicular to the surface of the electrode 1c, a part of the loop portion 11ad overlaps with the bottom layer. The first end 7a of the second wiring 7 may be connected to the loop portion 11ad at a position overlapping with the bottom layer in a plan view. Alternatively, the first end 7a of the second wiring 7 may be connected to the loop portion 11ad at a position not overlapping with the bottom layer in a plan view. The direction in which the ribbon wire 19 extends from the end portion 11a and the direction in which the second wiring 7 extends away from the upper surface 11aa of the end portion 11a are opposite in the horizontal direction.

[0072] <Method of Manufacturing Semiconductor Device> The manufacturing method of the semiconductor device shown in FIG. 10 has a basically similar configuration to the manufacturing method of the semiconductor device shown in FIG. 8, but the content of the first wiring step (S20) shown in FIG. 4 is partially different. In this step (S20), the ribbon wire 19 is folded and laminated at the end 11a of the ribbon wire 19 as the first wiring 11, and a closed loop portion 11ad is formed by the ribbon wire 19. Specifically, as shown in FIG. 10, the tip of the ribbon wire 19 is bonded to the electrode 1c by wedge bonding to form the bottom layer of the laminated fixing portion 11ae. Thereafter, the ribbon wire 19 is folded so that the ribbon wire 19 forms the loop portion 11ad on the bottom layer by operating the bonding tool. Thereafter, the laminated ribbon wire 19 is pressed to form the laminated fixing portion 11ae. As a result, as shown in Figure 10, at the end 11a of the ribbon wire 19, a laminated fixing portion 11ae is formed which includes the bottom layer directly connected to the electrode 1c, and a closed loop portion 11ad which is connected to the laminated fixing portion 11ae and which is convex from the electrode 1c toward the second semiconductor element 8 in the thickness direction of the ribbon wire 19.

[0073] Other than the above step (S20), steps (S10), (S30), and (S40) are the same as those in the method for manufacturing a semiconductor device shown in Fig. 4. In step (S30), the second wiring 7 is connected to the upper surface of the loop portion 11ad, which serves as the upper surface 11aa, at the end portion 11a.

[0074] <effect> In the above-described semiconductor device, at the end 11a of the ribbon wire 19 as the first wiring 11, the ribbon wire 19 may be bent and stacked, and a loop portion 11ad having a closed loop shape may be formed by the ribbon wire 19. At the end 11a, the upper surface 11aa may be the upper surface of the loop portion 11ad.

[0075] In the above-described method for manufacturing a semiconductor device, in the step (S20) of connecting the end 11a of the first wiring 11, the ribbon wire 19 as the first wiring 11 may be folded and laminated at the end 11a of the ribbon wire 19 as the first wiring 11, and a loop portion 11ad in a closed loop shape may be formed by the ribbon wire 19. In the step (S30) of electrically connecting by the second wiring 7, the upper surface 11aa of the end 11a may be the upper surface of the loop portion 11ad.

[0076] In this case, in the loop portion 11ad to which the first end 7a of the second wiring 7 is connected, a space is formed under the region to which the first end 7a is connected. Therefore, even if a tool (such as a capillary) for connecting the second wiring 7 comes into contact with the end 11a of the ribbon wire 19 when connecting the first end 7a of the second wiring 7 to the ribbon wire 19 as the first wiring 11, the loop portion 11ad can be easily displaced, so that it is possible to suppress the application of excessive force to the tool. Therefore, it is possible to reduce the possibility that the tool will be damaged or that a defect will occur in the process of connecting the end 11a of the second wiring 7.

[0077] In addition, since the loop portion 11ad is in a closed loop shape, the shape retention performance of the loop portion 11ad can be improved. Therefore, even if the loop portion 11ad is displaced to a certain extent, it can return to its original shape. Therefore, the distance between the first semiconductor element 1 and the second wiring 7 can be sufficiently maintained.

[0078] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. Unless inconsistent, at least two of the embodiments disclosed herein may be combined. The basic scope of the present disclosure is indicated by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0079] 1 first semiconductor element, 1a first main surface, 1b second main surface, 1c electrode, 2a, 2b lead frame, 3 third semiconductor element, 4 molding resin, 5 power terminal, 6 IC terminal, 7 second wiring, 7a first end, 7b second end, 8 second semiconductor element, 9, 31 solder, 10 bonding layer, 11 first wiring, 11a end, 11aa top surface, 11ab cut surface, 11ad loop portion, 11ae laminated fixing portion, 12 horn, 13 capillary, 15 spark rod, 16 aluminum wiring, 19 ribbon wire, 20 laminated structure, 30 arrow, D1, D2 diameter, L1 distance, T thickness, W width.

Claims

1. A first semiconductor element having a first main surface and a second main surface located opposite the first main surface, an electrode being formed on the first main surface, and further comprising: a second semiconductor element disposed at a position different from that of the first semiconductor element in a thickness direction from the first main surface toward the second main surface; a first wiring connected to the electrode, the first wiring has a ribbon-like shape and includes an end portion connected to the electrode, The end portion includes a top surface, and further includes: a second wiring electrically connecting the first semiconductor element and the second semiconductor element; a diameter of the second wiring is smaller than a width of the first wiring in a direction intersecting an extension direction of the first wiring; the second wiring includes a first end and a second end located opposite to the first end, the first end is directly connected to the top surface at the end of the first wiring, the second end is connected to the second semiconductor element; the end portion of the first wiring is folded and laminated, At the end portion, the upper surface is a top surface of the stacked first wiring.

2. A first semiconductor element having a first main surface and a second main surface located opposite the first main surface, an electrode being formed on the first main surface, and further comprising: a second semiconductor element disposed at a position different from that of the first semiconductor element in a thickness direction from the first main surface toward the second main surface; a first wiring connected to the electrode, the first wiring has a ribbon-like shape and includes an end portion connected to the electrode, The end portion includes a top surface, and further includes: a second wiring electrically connecting the first semiconductor element and the second semiconductor element; a diameter of the second wiring is smaller than a width of the first wiring in a direction intersecting an extension direction of the first wiring; the second wiring includes a first end and a second end located opposite to the first end, the first end is directly connected to the top surface at the end of the first wiring, the second end is connected to the second semiconductor element; the end of the first wiring includes a fixed portion directly connected to the electrode and a loop portion connected to the fixed portion and protruding from the electrode toward the second semiconductor element in the thickness direction, At the end portion, the top surface is the top surface of the loop portion.

3. A first semiconductor element having a first main surface and a second main surface located opposite the first main surface, an electrode being formed on the first main surface, and further comprising: a second semiconductor element disposed at a position different from that of the first semiconductor element in a thickness direction from the first main surface toward the second main surface; a first wiring connected to the electrode, the first wiring has a ribbon-like shape and includes an end portion connected to the electrode, The end portion includes a top surface, and further includes: a second wiring electrically connecting the first semiconductor element and the second semiconductor element; a diameter of the second wiring is smaller than a width of the first wiring in a direction intersecting an extension direction of the first wiring; the second wiring includes a first end and a second end located opposite to the first end, the first end is directly connected to the top surface at the end of the first wiring, the second end is connected to the second semiconductor element; the first wiring is folded and laminated at the end portion of the first wiring, and a loop portion having a closed loop shape is formed by the first wiring; At the end portion, the top surface is the top surface of the loop portion.

4. A method comprising the steps of preparing a first semiconductor element and a second semiconductor element, the first semiconductor element has a first main surface and a second main surface located opposite the first main surface; An electrode is formed on the first main surface, The second semiconductor element is disposed at a position different from that of the first semiconductor element in a thickness direction from the first main surface to the second main surface, and connecting an end of a first wiring to the electrode; and electrically connecting the first semiconductor element and the second semiconductor element by a second wiring. The first wiring has a ribbon shape, the end portion includes a top surface; a diameter of the second wiring is smaller than a width of the first wiring in a direction intersecting an extension direction of the first wiring; the second wiring includes a first end and a second end located opposite to the first end, In the step of electrically connecting by the second wiring, the first end is directly connected to the top surface at the end of the first wiring, the second end is connected to the second semiconductor element; In the step of connecting the end of the first wiring, the end of the first wiring is bent and laminated on the electrode, A method for manufacturing a semiconductor device, wherein in the step of electrically connecting by the second wiring, at the end portion, the upper surface is a top surface of the stacked first wiring.

5. A method comprising the steps of preparing a first semiconductor element and a second semiconductor element, the first semiconductor element has a first main surface and a second main surface located opposite the first main surface; An electrode is formed on the first main surface, The second semiconductor element is disposed at a position different from that of the first semiconductor element in a thickness direction from the first main surface to the second main surface, and connecting an end of a first wiring to the electrode; and electrically connecting the first semiconductor element and the second semiconductor element by a second wiring. The first wiring has a ribbon shape, the end portion includes a top surface; a diameter of the second wiring is smaller than a width of the first wiring in a direction intersecting an extension direction of the first wiring; the second wiring includes a first end and a second end located opposite to the first end, In the step of electrically connecting by the second wiring, the first end is directly connected to the top surface at the end of the first wiring, the second end is connected to the second semiconductor element; In the step of connecting the end of the first wiring, a fixed portion directly connected to the electrode and a loop portion connected to the fixed portion and protruding from the electrode toward the second semiconductor element in the thickness direction are formed at the end of the first wiring, A method for manufacturing a semiconductor device, wherein in the step of electrically connecting by the second wiring, the top surface at the end portion is a top surface of the loop portion.

6. A method comprising the steps of preparing a first semiconductor element and a second semiconductor element, the first semiconductor element has a first main surface and a second main surface located opposite the first main surface; An electrode is formed on the first main surface, The second semiconductor element is disposed at a position different from that of the first semiconductor element in a thickness direction from the first main surface to the second main surface, and connecting an end of a first wiring to the electrode; and electrically connecting the first semiconductor element and the second semiconductor element by a second wiring. The first wiring has a ribbon shape, the end portion includes a top surface; a diameter of the second wiring is smaller than a width of the first wiring in a direction intersecting an extension direction of the first wiring; the second wiring includes a first end and a second end located opposite to the first end, In the step of electrically connecting by the second wiring, the first end is directly connected to the top surface at the end of the first wiring, the second end is connected to the second semiconductor element; In the step of connecting the ends of the first wiring, the first wiring is folded and laminated at the ends of the first wiring, and a loop portion having a closed loop shape is formed by the first wiring; A method for manufacturing a semiconductor device, wherein in the step of electrically connecting by the second wiring, the top surface at the end portion is a top surface of the loop portion.

7. In the step of connecting the end of the first wiring, the end is connected to the electrode by wedge bonding; 7. The method for manufacturing a semiconductor device according to claim 4, wherein in the step of electrically connecting by the second wiring, the second wiring is connected to the first semiconductor element and the second semiconductor element by ball bonding.

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