Silicon-on-insulator wafer and its manufacturing method, semiconductor device

Abstract

A silicon-on-insulator wafer and a method for manufacturing the same and a semiconductor device are disclosed, the silicon-on-insulator wafer including a first substrate and an upper silicon layer, the first substrate including a first surface, where the first substrate has a maximum dimension D along a first direction. max and the first surface has a second dimension D2 along the first direction, and 100 μm≦D max -D2≦500 μm, and the top silicon layer is disposed on the first surface. The silicon-on-insulator wafer provided herein provides a suitable position for manufacturing the top silicon layer by optimizing edge sizes of the first substrate and the first surface, which helps to obtain a silicon-on-insulator wafer with a narrow step width. The present application further provides a method for manufacturing the silicon-on-insulator wafer, and a semiconductor device including the silicon-on-insulator wafer.

Description

[Technical Field]

[0001] This application claims priority from a Chinese patent application filed with the China Patent Office on December 27, 2022, bearing application number 202211652519.9 and entitled "Silicon-on-insulator wafer and manufacturing method thereof, and semiconductor device," the entire contents of which are incorporated herein by reference.

[0002] This application relates to the field of semiconductor wafer technology, and more particularly to silicon-on-insulator wafers and their manufacturing methods, and semiconductor devices. [Background technology]

[0003] Current silicon-on-insulator wafer manufacturing techniques mainly include oxygen injection separation, intelligent stripping, and bonded thinning. Bonded thinning, which involves bonding a support substrate to a device layer substrate to thin the device layer substrate, has attracted attention due to its simplicity and low cost. However, due to the thinning process conditions, the unbonded portions at the edges of the device layer substrate must be removed by additional grinding or etching processes. This makes it difficult to precisely control the size and uniformity of the device layer substrate, which directly affects the performance of the silicon-on-insulator wafer. Summary of the Invention [Problem to be solved by the invention]

[0004] The present application provides a silicon-on-insulator wafer, a manufacturing method thereof, and a semiconductor device, in which the edge size of the first substrate is optimized so that the unbonded area at the edge of the device layer substrate is automatically removed during the thinning process, thereby obtaining a silicon-on-insulator wafer with a narrow step width. [Means for solving the problem]

[0005] According to a first aspect, the present silicon-on-insulator wafer comprises a first substrate and an upper silicon layer, the first substrate comprising a first surface, wherein the first substrate has a maximum dimension D along a first direction. max the first surface has a second dimension D2 along a first direction, and 100 μm≦D max -D2≦500 μm is satisfied, and the upper silicon layer is disposed on the first surface.

[0006] In some embodiments, the maximum dimension D max and the second dimension D2 is 100 μm≦D max -D2≦160μm is satisfied. In some embodiments, the top silicon layer has a first dimension D1 along a first direction, D max -D1≦2mm. In some embodiments, the top silicon layer is formed by chemical mechanical polishing on a bonding region, the bonding region having an eighth dimension D0 along a first direction, and the top silicon layer having a first dimension D1 along the first direction, where D1-D0≦0.1 mm.

[0007] In some embodiments, the top silicon layer has a first dimension D1 along a first direction, and the first dimension D1, the second dimension D2, and a maximum dimension D max teeth, 0.1≦(D max -D2) / (D max -D1)≦1.

[0008] In some embodiments, the first substrate further includes a second surface spaced apart from the first surface along a second direction, the second surface having a third dimension D3 along the first direction; The relationship 1≦D2 / D3≦1.5 is satisfied.

[0009] In some embodiments, a first arcuate second surface is provided from an edge of the first surface toward an edge of the first substrate, and a second arcuate second surface is provided from the edge of the second surface toward an edge of the first substrate, the first arcuate second surface having a fifth dimension L5 in the first direction, and the second arcuate second surface having a sixth dimension L6 in the first direction; The relationship 0.01≦L5 / L6≦1 is satisfied.

[0010] In some embodiments, the silicon-on-insulator wafer further comprises: 50 μm≦L5≦80 μm, and / or The distance L6 satisfies 220 μm≦L6≦450 μm.

[0011] In some embodiments, the semiconductor device further includes a first oxide layer and a second oxide layer, the first oxide layer being located between the first substrate and the top silicon layer, the first oxide layer contacting the first surface, and the second oxide layer being located on a side of the first substrate away from the top silicon layer, the second oxide layer contacting the second surface.

[0012] In some embodiments, the upper silicon layer has a thickness along a second direction, the second direction being perpendicular to the first direction, the thickness of the upper silicon layer in the second direction being 3 to 20 μm, and / or the distance between the first surface and the second surface being 400 to 1000 μm, and / or the thickness of the first oxide layer in the second direction being 0.1 to 2 μm, and / or the thickness of the second oxide layer in the second direction being 0.1 to 2 μm.

[0013] According to a second aspect, the present application further provides a method for manufacturing a silicon-on-insulator wafer, comprising the steps of: providing a first substrate, said first substrate comprising a first surface, wherein said first substrate has a maximum dimension D along a first direction; max the first surface having a second dimension D2 along a first direction; 100μm≦D max -D2≦500μm is satisfied, a second substrate is provided, the second substrate including a third surface, the second substrate is bonded to the first substrate and annealed with the third surface in contact with the first surface such that the second substrate includes a bonding region and a separation region, the separation region is disposed to surround the bonding region and connects to an edge of the bonding region, the side of the second substrate away from the third surface is thinned so that the separation region is removed, a step is formed where the separation region is removed, the step surrounds the bonding region, and the bonding region forms an upper silicon layer on the first substrate.

[0014] In some embodiments, the maximum dimension D max and the second dimension D2 is 100μm≦D max -D2≦160μm is satisfied. the top silicon layer has a first dimension D1 along a first direction; D max -D1≦2mm.

[0015] In some embodiments, after thinning the side of the second substrate away from the third surface, the side of the second substrate away from the third surface includes a stress damage layer, and the step of forming a top silicon layer on the first substrate at the bonding region includes performing chemical mechanical polishing on the side of the second substrate away from the third surface to first remove the stress damage layer, and then continuing polishing to a target thickness and a surface roughness level similar to that of a conventionally polished silicon wafer, and the top silicon layer is formed after the bonding region is chemical mechanical polished.

[0016] In some embodiments, the bonding region has an eighth dimension D0 along a first direction, and the top silicon layer has a first dimension D1 along the first direction, where D1-D0≦0.1 mm. In some embodiments, the top silicon layer has a first dimension D1 along the first direction, and 0.1≦(D max -D2) / (Dmax -D1)≦1.

[0017] In some embodiments, the first substrate further comprises a second surface disposed away from the first surface along a second direction, and the second substrate further comprises a fourth surface disposed away from the third surface along the second direction, wherein the second surface has a third dimension D3 along the first direction, and the fourth surface has a fourth dimension D4 along the first direction; 1≦D2 / D3≦1.5, and / or The relationship 1≦D2 / D4≦1.5 is satisfied.

[0018] In some embodiments, a second surface of a first arcuate surface is provided from an edge of the first surface toward an edge of the first substrate, and a second surface of a second arcuate surface is provided from the edge of the second surface toward the edge of the first substrate, the second surface of the first arcuate surface having a fifth dimension L5 in the first direction, and the second surface of the second arcuate surface having a sixth dimension L6 in the first direction, satisfying 0.01≦L5 / L6≦1.

[0019] In some embodiments, a third arcuate surface is provided from an edge of the third surface toward an edge of the second substrate, and a fourth arcuate surface is provided from an edge of the fourth surface toward an edge of the second substrate, the third arcuate surface being connected to the fourth arcuate surface, the third arcuate surface having a seventh dimension L7 in the first direction, and the fourth arcuate surface having a seventh dimension L8 in the first direction. 2 inches It has modulus L8, 0.01≦L7 / L8≦1, and / or The relationship 0.01≦L7 / L5≦1 is satisfied.

[0020] In some embodiments, after the first substrate is provided, the method further includes performing an oxidation process on the first substrate to form a first oxide layer on the first surface and / or a second oxide layer on the second surface.

[0021] In some embodiments, the annealing refers to raising the temperature to 900-1200°C at a rate of 2-5°C / min in a nitrogen or oxygen atmosphere and holding the temperature for 4-6 hours. In some embodiments, thinning the second substrate on the side away from the third surface is performed by mechanical grinding. In some embodiments, the removal amount by chemical mechanical polishing is 4-5 μm.

[0022] According to a third aspect, the present application further provides a semiconductor device, the semiconductor device including the silicon-on-insulator wafer described above, or the semiconductor device including a silicon-on-insulator wafer obtained by the manufacturing method described above. [Effects of the Invention]

[0023] In comparison with the prior art, the silicon-on-insulator wafer of the present application comprises a first substrate and an upper silicon layer, the first substrate comprising a first surface, wherein the first substrate has a maximum dimension D along a first direction. max and the first surface has a second dimension D2 along the first direction, and 100 μm≦D max The silicon-on-insulator wafer provided herein optimizes the edge size of the first substrate, thereby providing a suitable position for fabricating the top silicon layer and helping to obtain a silicon-on-insulator wafer with a narrow step width.

[0024] The present invention provides a method for fabricating a silicon-on-insulator wafer, comprising the steps of: providing a first substrate, the first substrate including a first surface, the first substrate having a maximum dimension D along a first direction; max and the first surface has a second dimension D2 along the first direction, and 100 μm≦D maxA second substrate is provided, the third surface of which meets the requirement of -D2≦500 μm. The second substrate includes a third surface, and the third surface is brought into contact with the first surface. The second substrate is bonded to the first substrate and annealed, so that the second substrate includes a bonding region and a separation region. The separation region is disposed to surround the bonding region and connect to the edge of the bonding region. The second substrate is thinned on a side away from the third surface so that the separation region is removed, forming a step where the separation region is removed, the step surrounding the bonding region, and the bonding region forms an upper silicon layer on the first substrate. The manufacturing method of the present application optimizes the annealing process of the first and second substrates to increase the bonding strength of the edge region by 1 to 3 mm. The grinding process during the mechanical thinning process is optimized so that the unbonded edge region is automatically removed during the thinning process, with the width of the automatically removed region not exceeding 1 mm, resulting in a width non-uniformity of the upper silicon layer of ≦5%. In this way, the edge step width can be minimized by optimizing the substrate shape and bonding / thinning process without requiring special chamfer grinding or chamfer etching processes, which not only reduces process costs but also enables the production of silicon-on-insulator wafers with narrow step widths. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a schematic diagram of the structure of a silicon-on-insulator wafer provided in an embodiment of the present application. [Figure 2] 1 is a schematic diagram of a partial structure of a silicon-on-insulator wafer provided in an embodiment of the present application. [Figure 3] FIG. 2 is a structural schematic diagram of a first substrate provided in an embodiment of the present application. [Figure 4] FIG. 2 is a structural schematic diagram of a second substrate provided in an embodiment of the present application. [Figure 5] FIG. 2 is a structural schematic diagram of the first substrate and the second substrate after bonding provided in an embodiment of the present application. [Figure 6] FIG. 2 is a structural schematic diagram of the thinning of the second substrate provided in the embodiment of the present application. [Figure 7]FIG. 1 is a schematic diagram of the automatic shedding of the separation region provided in the examples of the present application. [Figure 8] 1 is a comparison of step width uniformity between Example 1 of the present invention and Comparative Example 4. DETAILED DESCRIPTION OF THE INVENTION

[0026] The present application provides a silicon-on-insulator wafer, a manufacturing method thereof, and a semiconductor device. In order to clarify the objectives, technical solutions, and advantages of the present application, the present application will be described in more detail below with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application and are not used to limit the present application.

[0027] Silicon-on-insulator wafers, thanks to their unique structure, achieve true physical isolation vertically through a buried oxide layer (BOX) and lateral isolation laterally through deep trench isolation (DTI). This allows components to be placed on separate isolation islands, reducing or eliminating the leakage and latch-up effects commonly found in bulk silicon power devices and improving circuit integration density. At the same time, silicon-on-insulator wafer technology has lower leakage current than bulk silicon components, allowing them to operate at higher voltages and temperatures. While leveraging the advantages of bulk silicon integrated circuits, silicon-on-insulator wafers completely eliminate latch-up effects and parasitic capacitance, and completely block leakage channels to the substrate. This technology offers superior speed and low power consumption, making it the preferred choice for manufacturing highly integrated, high-speed, low-power, and highly reliable semiconductor integrated circuit devices.

[0028] Currently, the manufacturing technologies for silicon-on-insulator substrate materials mainly include oxygen implantation isolation, intelligent stripping, and bond thinning. While the top silicon thickness and buried oxide layer thickness of wafers manufactured using oxygen implantation isolation are highly uniform, due to limitations of the oxygen ion implantation process, the device silicon layer thickness cannot exceed 300 nm, and the buried oxide layer thickness cannot exceed 240 nm. Furthermore, discontinuous silicon island defects are often found in the buried oxide layer, resulting in a breakdown voltage much lower than that of conventional thermal oxidation, limiting the product applications and technological development of oxygen implantation isolation. Intelligent stripping, characterized by its mature process, good device layer uniformity, and low process cost, has become the mainstream manufacturing technology for 8-inch power insulator silicon substrate materials. Bond thinning technology features simple processing and low cost. The wafer-on-insulator manufactured using this technology has a crystal defect density and surface quality comparable to that of bulk silicon wafers, and is widely adjustable. However, due to the thinning process, it is difficult to precisely control the thickness uniformity of the silicon layer of the device, and the non-uniformity is generally ±0.5 μm. Therefore, it is mainly used in the fields of high-voltage power devices and MEMS devices, and most of them are concentrated in the 4-6 inch range.

[0029] The silicon-on-insulator wafers manufactured using these three technologies retain the original edge shape of the substrate wafer, i.e., there is no edge step. The silicon-on-insulator wafers manufactured using the intelligent stripping and bonding thinning technologies have a circular step at the edge of the upper device silicon layer after bonding and thinning. This is formed by removing the edge portion of the device silicon layer to relieve edge stress. The width of the step varies depending on the process. For example, in the case of intelligent stripping, the edge step width of the final silicon-on-insulator wafer ranges from 1mm to 2.8mm. If the step width is too wide, the effective silicon layer area of ​​the device will be reduced, reducing chip yield and making it more susceptible to edge defects in subsequent processes, which will affect product quality and electrical performance parameters.

[0030] The bond thinning process includes edge chamfering and alkaline etching processes to remove the edge of the silicon layer of the device. However, the addition of these processes significantly increases the processing cost of silicon-on-insulator wafers, and the alkaline etching process is prone to corrosion defects. Therefore, achieving a narrow and uniform step width and reducing process costs are crucial for improving the quality of silicon-on-insulator wafers.

[0031] 1 , the present application provides a silicon-on-insulator wafer, comprising a first substrate 1 and a top silicon layer 2, the first substrate 1 comprising a first surface 11, and the top silicon layer 2 disposed on the first surface 11. Here, the first substrate 1 has a maximum dimension D along a first direction X. max and the first surface 11 has a second dimension D2 along the first direction X, and 100 μm≦D max -D2≦500μm is satisfied.

[0032] In some embodiments, optimizing the edge size of the first substrate 1 and the first surface 11 provides an appropriate position for fabricating the upper silicon layer 2, which helps to obtain a silicon-on-insulator wafer with a narrow step width. The first direction X is the direction of the horizontal arrow in FIG. 1 , and the second direction Y is the direction of the vertical arrow in FIG. 1 . The first direction and the second direction are shown schematically to represent the positional relationship and size between the first substrate 1 and the upper silicon layer 2. The first direction and the second direction are not limited to the directions shown in the drawings, but intersect in space, preferably perpendicular to each other. The first direction and the second direction in this embodiment refer to the arrangement in FIG. 1 .

[0033] In some embodiments, the maximum dimension D max and the second dimension D2 is 100 μm≦D max Preferably, -D2≦160 μm. In some embodiments, the upper silicon layer 2 has a first dimension D1 along the first direction X, and D max -D1≦2mm is satisfied. max By satisfying -D1≦2 mm, the quality of the upper silicon layer 2 is ensured and a narrow and uniform step width is obtained. In some embodiments, the upper silicon layer 2 is formed by chemical mechanical polishing on the bonding region 501. The bonding region 501 has an eighth dimension D0 along the first direction X, and the upper silicon layer 2 has a first dimension D1 along the first direction, and D1-D0≦0.1 mm is satisfied. Here, D0 <D1。である。

[0034] In some embodiments, the chemical mechanical polishing process is controlled so that the first dimension D1 and the eighth dimension D0 satisfy D1-D0≦50 μm. In some embodiments, the chemical mechanical polishing process is controlled so that the first dimension D1 and the eighth dimension D0 are equal, i.e., D0=D1. In some embodiments, the top silicon layer 2 has a first dimension D1 along the first direction X, and the first dimension D1, the second dimension D2, and the maximum dimension D max teeth, 0.1≦(D max -D2) / (D max -D1)≦1.

[0035] In some embodiments, (D max -D2) / (D max If the value of (D -D1) is less than 0.1, the step width of the upper silicon layer 2 increases, and the edge of the support substrate may be chipped. max -D2) / (D max If (D -D1) is greater than 1, the edge of the upper device layer cannot be automatically shed during the thinning process, and chipping of the silicon edge of the upper device layer may occur. max -D2) / (D max If (D -D1)≦1 is satisfied, it is guaranteed that a silicon-on-insulator wafer with a narrow step width and free from the influence of edge chipping can be obtained. max -D2) / (D max -D1) range is 0.1≦(D max -D2) / (D max -D1)≦0.5, and more preferably, (D max -D2) / (D max -D1) range is 0.1≦(D max -D2) / (D max -D1)≦0.3.

[0036] In some embodiments, to ensure the integrity of the first substrate 1, the first substrate 1 further includes a second surface 12 disposed along the second direction away from the first surface 11, the second surface 12 having a third dimension D3 along the first direction, where 1≦D2 / D3≦1.5 is satisfied. The second surface 12 may have the same area as the first surface 11 or a different area.

[0037] In some embodiments, both the first surface 11 and the second surface 12 of the first substrate 1 may be chamfered to facilitate processing. After the chamfering, an arcuate surface is formed on the edge of the first substrate 1. Referring to FIG. 2 , a first arcuate surface 13 extends from the edge of the first surface 11 toward the edge of the first substrate 1, and a second arcuate surface 14 extends from the edge of the second surface 12 toward the edge of the first substrate 1. The first arcuate surface 13 has a fifth dimension L5 in the first direction, and the second arcuate surface 14 has a sixth dimension L6 in the first direction, where 0.01≦L5 / L6≦1 is satisfied. When the value of L5 / L6 is 1, the chamfers of the first surface 11 and the second surface 12 of the first substrate 1 are vertically symmetrical. When the value of L5 / L6 is less than 1, the chamfers of the first surface 11 and the second surface 12 of the first substrate 1 are asymmetrical.

[0038] In some embodiments, the silicon-on-insulator wafer further satisfies the ranges 50 μm≦L5≦80 μm and 220 μm≦L6≦450 μm. More preferred ranges are 60 μm≦L5≦70 μm and 300 μm≦L6≦400 μm. In some embodiments, referring to FIG. 2 , the silicon-on-insulator wafer further includes a first oxide layer 3 and a second oxide layer 4, where the first oxide layer 3 is located between the first substrate 1 and the top silicon layer 2, and the first oxide layer 3 contacts the first surface 11. The second oxide layer 4 is located on a side of the first substrate 1 away from the top silicon layer 2, and the second oxide layer 4 contacts the second surface 12.

[0039] In some embodiments, the upper silicon layer 2 has a thickness along the second direction Y, the second direction Y being perpendicular to the first direction X, the thickness of the upper silicon layer 2 in the second direction Y being 3 to 20 μm, the distance between the first surface 11 and the second surface 12 being 400 to 1000 μm, the thickness of the first oxide layer 3 in the second direction Y being 0.1 to 2 μm, and the thickness of the second oxide layer 4 in the second direction Y being 0.1 to 2 μm. More preferably, the thickness of the upper silicon layer 2 in the second direction Y is 5 to 10 μm, the distance between the first surface 11 and the second surface 12 being 600 to 800 μm, the thickness of the first oxide layer 3 in the second direction Y being 0.5 to 1 μm, and the thickness of the second oxide layer 4 in the second direction Y being 0.5 to 1 μm.

[0040] In some embodiments, the present application further provides a method for manufacturing a silicon-on-insulator wafer, the method comprising the steps of: Referring to Figures 1 and 3, a first substrate 1 is provided, the first substrate 1 comprising a first surface 11, wherein the first substrate 1 has a maximum dimension D along a first direction X; max and the first surface 11 has a second dimension D2 along the first direction X, and 100 μm≦D max -D2≦500 μm. Referring to FIG. 4, a second substrate 5 is provided, and the second substrate 5 includes a third surface 51. Referring to FIGS. 5, 6, and 7, the third surface 51 is brought into contact with the first surface 11, and the second substrate 5 is bonded to the first substrate 1 and annealed such that the second substrate 5 includes a bonding region 501 and an isolation region 502. The isolation region 502 is disposed to surround the bonding region 501 and connects to the edge of the bonding region 501. The side of the second substrate 5 away from the third surface 51 is thinned so that the isolation region 502 is removed. The bonding region 501 forms an upper silicon layer 2 on the first substrate 1.

[0041] In some embodiments, the annealing process for the first substrate 1 and the second substrate 5 can be optimized to increase the bonding strength of the edge region of 1 to 3 mm, and the grinding process during the mechanical thinning process can be optimized to automatically remove the unbonded edge region 501 during the thinning process, with the width of the automatically removed region not exceeding 1 mm, resulting in a width non-uniformity of ≦5% for the upper silicon layer 2. In this way, the edge step width can be minimized by optimizing the substrate shape and the bonding and thinning process, without requiring special chamfer grinding or chamfer etching processes.

[0042] In some embodiments, the upper silicon layer 2 has a step structure relative to the first substrate 1, and the distance between the edge of the upper silicon layer 2 and the edge of the first substrate 1 is the width of the step structure, and the width is (D max -D1) / 2, where the width size determines the overall size of the upper silicon layer 2. Since part of the isolation region 502 may automatically fall off during the thinning process, a smaller width ensures that the thickness of the upper silicon layer 2 at the edge portion is constant in any direction, thereby achieving uniformity in the width of the upper silicon layer 2.

[0043] In some embodiments, the first substrate 1 refers to a conventionally polished silicon wafer or a thermally oxidized wafer with a silicon dioxide film formed on its surface by dry or wet oxygen oxidation. One side of the first substrate 1 is polished, and the doping type and resistivity are not limited, and the edge shape can be symmetrically or asymmetrically chamfered. The second substrate 5 can be a conventionally polished silicon wafer or a silicon epitaxial wafer. One side of the second substrate 5 is polished, and the doping type and resistivity are not limited, and the edge shape can be symmetrically or asymmetrically chamfered.

[0044] 7 and 1 , in some embodiments, the side of the second substrate 5 away from the third surface 51 is thinned to remove the separation region 502, and the thinning causes the side of the second substrate 5 away from the third surface 51 to include a stress damage layer. The step of forming the upper silicon layer 2 on the first substrate 1 with the bonding region 501 includes performing chemical mechanical polishing on the side of the second substrate 5 away from the third surface 51 to first remove the stress damage layer, and then forming the upper silicon layer 2 after the bonding region 501 is chemical mechanical polished.

[0045] 7, the bonding region 501 has an eighth dimension D0 along the first direction, and the top silicon layer 2 has a first dimension D1 along the first direction X, where D1-D0≦0.1 mm. In some embodiments, referring to FIG. 4, the second substrate 5 further includes a fourth surface 52 disposed along the second direction Y and spaced apart from the third surface 51, where the fourth surface 52 has a fourth dimension D4 along the first direction, where 1≦D2 / D4≦1.5.

[0046] 4, a third arcuate surface 53 is provided from the edge of the third surface 51 toward the edge of the second substrate 5, and a fourth arcuate surface 54 is provided from the edge of the fourth surface 52 toward the edge of the second substrate 5, and the third arcuate surface 53 is connected to the fourth arcuate surface 54. The third arcuate surface 53 has a seventh dimension L7 in the first direction X, and the fourth arcuate surface 54 has a seventh dimension L8 in the first direction X. 2 inchesThe formula L8 satisfies 0.01≦L7 / L8≦1 and 0.01≦L7 / L5≦1. When the value of L7 / L8 is 1, the chamfers on the third surface 51 and the fourth surface 52 of the second substrate 5 are vertically symmetrical. When the value of L7 / L8 is less than 1, the chamfers on the third surface 51 and the fourth surface 52 of the second substrate 5 are asymmetrical. Furthermore, by further specifying the range of L7 / L5, it is possible to prevent the quality of the upper silicon layer 2 from being affected by the chamfer dimensions on the third surface 51 of the second substrate 5 being too large or too small relative to the chamfer dimensions on the first surface 11 of the first substrate 1. This is because if the chamfered area is too large, it will be difficult for the chamfered area to automatically fall off during the thinning process after bonding. However, if the chamfered area is too small, the width of the step in the upper silicon layer 2 will be too large, which will affect the performance of the subsequently manufactured device.

[0047] In some embodiments, referring to FIG. 3 , after the first substrate 1 is provided, the method further includes performing an oxidation process on the first substrate 1 to form a first oxide layer 3 on the first surface 11 and a second oxide layer 4 on the second surface 12.

[0048] In some embodiments, the bonding and annealing of the second substrate 5 and the first substrate 1 refers to bonding the first surface 11 of the first substrate 1 to the third surface 51 of the second substrate 5. The annealing refers to heating the substrate in a nitrogen or oxygen atmosphere to 900-1200°C at a rate of 2-5°C / min and maintaining the temperature for 4-6 hours. In some embodiments, annealing can be performed by passing H2 / O2 through the substrate and using water vapor formed by ignition of hydrogen and oxygen. In some embodiments, the bonding and annealing process is as follows: The bonded first substrate 1 and second substrate 5 are transferred together to a vertical or horizontal furnace, and annealed at a temperature exceeding 1000°C, with the heating rate controlled to not exceed 6°C / min. Nitrogen or oxygen can be introduced during the annealing process, and the annealing time is 2 hours or longer. The preferred annealing temperature is 1150°C, the heating rate is 3°C / min, the annealing time is 5 hours, and the introduced gas is oxygen.

[0049] In some embodiments, referring to Figures 6 and 7, in thinning the side of the second substrate 5 away from the third surface 51, the thinning is performed by mechanical grinding, and during the mechanical grinding process, the unbonded parts of the edge are automatically and uniformly removed due to the strong contact of the grinding wheel, i.e., the separation region 502 is automatically removed.

[0050] In some embodiments, thinning is performed by mechanical grinding, which refers to mechanically grinding the fourth surface 52 of the second substrate 5 on a single-chip thinning device using a grinding wheel driven by a high-speed rotating spindle. The coarse grinding wheel is used to remove most of the substrate silicon, and then a fine grinding wheel is used to remove a smaller amount. The fine grinding removal rate and feed / discharge speed are controlled to achieve a target silicon thickness of no more than 40 μm for the final device layer. During the thinning process, the unbonded portions of the silicon edge of the device are automatically and uniformly removed, ultimately forming an edge step with a step width of ≦1 mm and a uniform width.

[0051] In some embodiments, during thinning and removal, a coarse grinding wheel is used for coarse grinding and a fine grinding wheel is used for fine grinding. The mesh number of the coarse grinding wheel is ≦500 mesh, and the mesh number of the fine grinding wheel is ≧3000 mesh. The feed / discharge rate of the fine grinding process is controlled to not exceed 5 μm / s to grind to the target thickness. A preferred coarse grinding wheel is 300-400 mesh, and a preferred fine grinding wheel is 5000-8000 mesh. The preferred feed / discharge rate of the fine grinding process is 3-4 μm / s. In some embodiments, the removal amount by mechanical grinding is ≧600 μm.

[0052] In some embodiments, the bonding region 501 is chemically mechanically polished to form the upper silicon layer 2, with a removal volume of 4-5 μm. The preferred polishing method is chemical mechanical polishing (CMP), which refers to the use of single-tip polishing to remove surface stress damage caused by mechanical grinding during the previous thinning process while improving the surface roughness to the level of that of a conventional polishing sheet. Because the edge bonding force is sufficiently large, the edge step width does not change significantly after CMP, i.e., D1-D0≦0.1 mm, maintaining a narrow step width and excellent width uniformity. Chemically polishing the ground bonded substrate completely removes the grinding-induced stress damage layer, fully meeting the surface roughness requirements, while controlling the removal volume to mitigate the degradation effects of uneven thickness of the device silicon layer. The preferred removal volume is 4-5 μm. The polishing process does not affect the edge width of the device layer, with a width change of ≦0.1 mm before and after, maintaining edge width regularity.

[0053] In some embodiments, the present application further provides a semiconductor device, which includes the above-described silicon-on-insulator wafer. According to the above-described manufacturing method, several groups of silicon-on-insulator wafers, specifically including Examples 1 to 16 and Comparative Examples 1 to 3, were manufactured, and the resulting width data are shown in Table 1. In the table, ΔD is (D max -D2) / (D max -D1), and the range of ΔD in Comparative Examples 1 to 3 is outside the range set in this example.

[0054] [Table 1]

[0055] As can be seen from Table 1, D of Examples 1 to 16 max -D2 meets the requirements of 100~500μm, (D max -D2) / (D max-D1) satisfies the limit range of 0.1 to 1, which allows the width of the upper silicon layer 2 from the edge to be reliably controlled within a narrower range, thereby obtaining a silicon-on-insulator wafer with a narrow step width. In Comparative Examples 1 to 3, (D max -D2) / (D max If −D1) is less than 0.1, the width of the upper silicon layer 2 from the edge increases, which impairs the uniformity of the width of the upper silicon layer 2 and also affects the performance of the subsequent device.

[0056] Comparative Example 4 Silicon-on-insulator wafers are fabricated using Smart-cut technology, in which hydrogen ions are implanted into a bonded wafer and then bonded to another silicon wafer at a specific temperature. When the bonding heat treatment temperature is approximately 500°C, continuous cavities are formed at the hydrogen ion implantation sites, which then automatically delaminate to form the silicon-on-insulator wafer. Comparing the silicon-on-insulator wafers of Comparative Example 4 and Example 1 of the present application, as shown in Figure 8, Example 1 of the present application has equal edge step widths in all four directions, demonstrating excellent width uniformity. However, Comparative Example 4 exhibits different edge step widths in all four directions due to Smart-cut technology. Therefore, the present fabrication method optimizes the grinding process so that the unbonded edge region, i.e., the separation region 502, automatically falls off during the thinning process. The width of the automatically fallen region does not exceed 1 mm, and the width non-uniformity of the upper silicon layer 2 is also small. Thus, the edge step width can be minimized by optimizing the substrate shape and the bonding and thinning process, without requiring special chamfer grinding or chamfer etching processes.

[0057] The above is a detailed introduction to the silicon-on-insulator wafer and its manufacturing method, and semiconductor device provided in the examples of the present application, and specific examples are used in the present application to explain the principles and embodiments of the present application. The description of the above examples is only used to understand the technical solutions and core ideas of the present application, and it should be understood that those skilled in the art can modify the technical solutions recorded in the above examples or make equivalent substitutions for some technical features, and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the examples of the present application. [Explanation of symbols]

[0058] 1 First board 2. Top silicon layer 3 First oxide layer 4 Second oxide layer 5 Second board 11 First Surface 12 Second Surface 13 First arc surface 14 Second arc surface 51 The Third Surface 52 The Fourth Surface 53 Third arc surface 54 Fourth Arc Surface 501 Combined area 502 Separation area

Claims

1. A silicon-on-insulator wafer comprising a first substrate (1) and a top silicon layer (2); The first substrate (1) comprises a first surface (11), wherein the first substrate (1) has a maximum dimension D along a first direction. ｍａｘ and the first surface (11) has a second dimension D along a first direction. ２ and 100 μm≦D ｍａｘ -D ２ ≦500 μm, The upper silicon layer (2) is disposed on the first surface (11); The upper silicon layer (2) has a first dimension D along a first direction. １ and the first dimension D １ , the second dimension D ２ , and the maximum dimension D ｍａｘ 0.1≦(D ｍａｘ -D ２ ) / (D ｍａｘ -D １ )≦0.

3.

2. The maximum dimension D ｍａｘ and the second dimension D ２ 100 μm≦D ｍａｘ -D ２ 2. The silicon-on-insulator wafer of claim 1, wherein the thickness satisfies ≦160 μm.

3. D ｍａｘ -D １ 2. The silicon-on-insulator wafer of claim 1, wherein the thickness of the silicon-on-insulator wafer satisfies ≦2 mm.

4. the silicon-on-insulator wafer further comprises a second substrate (5), the second substrate (5) comprising a third surface (51), wherein the third surface (51) is brought into contact with the first surface (11) to bond the second substrate (5) to the first substrate (1) to form a bonding region (501); The upper silicon layer (2) is formed by chemical mechanical polishing to the bonding region (501), the bonding region (501) having an eighth dimension D along a first direction. ０ and the upper silicon layer (2) has a first dimension D along a first direction. １ D １ -D ０ 2. The silicon-on-insulator wafer of claim 1, wherein the thickness satisfies ≦0.1 mm.

5. The first substrate (1) further includes a second surface (12) disposed away from the first surface (11) along a second direction, the second surface (12) having a third dimension D along the first direction. ３ and 1≦D ２ / D ３ 2. The silicon-on-insulator wafer of claim 1, wherein the silicon-on-insulator wafer satisfies ≦1.

5.

6. A first arcuate surface (13) is provided from an edge of the first surface (11) toward an edge of the first substrate (1), and a second arcuate surface (14) is provided from an edge of the second surface (12) toward an edge of the first substrate (1), and the first arcuate surface (13) has a fifth dimension L in the first direction. ５ and the second arcuate surface (14) has a sixth dimension L in the first direction. ６ and 0.01≦L ５ / L ６ 6. The silicon-on-insulator wafer of claim 5, wherein: ≦1 is satisfied.

7. The silicon-on-insulator wafer further comprises: ５ ≦80 μm, 220 μm≦L ６ 7. The silicon-on-insulator wafer of claim 6, wherein the thickness satisfies ≦450 μm.

8. Further comprising a first oxide layer (3) and a second oxide layer (4), the first oxide layer (3) is located between the first substrate (1) and the upper silicon layer (2), the first oxide layer (3) being in contact with the first surface (11); 8. The silicon-on-insulator wafer according to claim 5, wherein the second oxide layer (4) is located on a side of the first substrate (1) facing away from the upper silicon layer (2), the second oxide layer (4) being in contact with the second surface (12).

9. The silicon-on-insulator wafer of any one of claims 1 to 7, characterized in that the upper silicon layer (2) has a thickness along a second direction, the second direction being perpendicular to the first direction, and the thickness of the upper silicon layer (2) in the second direction is 3 to 20 μm.

10. A silicon-on-insulator wafer according to any one of claims 5 to 7, characterized in that the distance between the first surface (11) and the second surface (12) is between 400 and 1000 μm.

11. 9. The silicon-on-insulator wafer of claim 8, wherein the first oxide layer (3) has a thickness in the second direction of 0.1 to 2 μm, and the second oxide layer (4) has a thickness in the second direction of 0.1 to 2 μm.

12. A method for manufacturing a silicon-on-insulator wafer, comprising the steps of: Providing a first substrate (1), said first substrate (1) comprising a first surface (11), wherein said first substrate (1) has a maximum dimension D along a first direction. ｍａｘ and the first surface (11) has a second dimension D along a first direction. ２ and 100 μm≦D ｍａｘ -D ２ ≦500 μm; providing a second substrate (5), said second substrate (5) comprising a third surface (51); bonding and annealing the second substrate (5) to the first substrate (1) by contacting the third surface (51) with the first surface (11) such that the second substrate (5) comprises a bonding region (501) and a separation region (502), the separation region (502) being disposed around the bonding region (501) and connecting to an edge of the bonding region (501); thinning the side of the second substrate (5) facing away from the third surface (51) such that the separation regions (502) fall off; The bonding region (501) comprises forming an upper silicon layer (2) on the first substrate (1), the upper silicon layer (2) being disposed on the first surface (11), the upper silicon layer (2) having a first dimension D along a first direction. １ and the first dimension D １ , the second dimension D ２ , and the maximum dimension D ｍａｘ 0.1≦(D ｍａｘ -D ２ ) / (D ｍａｘ -D １ )≦0.3; and 1. A method for producing a silicon-on-insulator wafer, comprising:

13. The maximum dimension D ｍａｘ and the second dimension D ２ 100 μm≦D ｍａｘ -D ２ The method for producing a silicon-on-insulator wafer according to claim 12, characterized in that the thickness satisfies ≦160 μm.

14. The upper silicon layer (2) has a first dimension D along a first direction. １ D ｍａｘ -D １ The method for producing a silicon-on-insulator wafer according to claim 12, characterized in that the thickness satisfies ≦2 mm.

15. 13. The method of claim 12, wherein after the step of thinning the side of the second substrate (5) away from the third surface (51), the side of the second substrate (5) away from the third surface (51) contains a stress damage layer and the bonding region (501) is formed on the first substrate (1), the step of forming a top silicon layer (2) on the first substrate (1) comprises the steps of performing chemical mechanical polishing on the side of the second substrate (5) away from the third surface (51) to first remove the stress damage layer and to form the top silicon layer (2) after the bonding region (501) has been chemical mechanical polished.

16. The bonding area (501) has an eighth dimension D along a first direction. ０ and the upper silicon layer (2) has a first dimension D along a first direction. １ D １ -D ０ The method for producing a silicon-on-insulator wafer according to claim 12, characterized in that the thickness satisfies ≦0.1 mm.

17. the first substrate (1) further comprises a second surface (12) disposed away from the first surface (11) along a second direction, and the second substrate (5) further comprises a fourth surface (52) disposed away from the third surface (51) along a second direction; wherein the second surface (12) has a third dimension D along the first direction ３ and the fourth surface (52) has a fourth dimension D along the first direction. ４ and 1≦D ２ / D ３ ≦1.5, 1≦D ２ / D ４ 13. The method for producing a silicon-on-insulator wafer according to claim 12, wherein the ratio satisfies ≦1.

5.

18. A first arcuate surface (13) is provided from an edge of the first surface (11) toward an edge of the first substrate (1), and a second arcuate surface (14) is provided from an edge of the second surface (12) toward an edge of the first substrate (1), and the first arcuate surface (13) has a fifth dimension L in the first direction. ５ and the second arcuate surface (14) has a sixth dimension L in the first direction. ６ and 0.01≦L ５ / L ６ 18. The method for producing a silicon-on-insulator wafer according to claim 17, wherein the following is satisfied: ≦1.

19. A third arcuate surface (53) is provided from an edge of the third surface (51) toward an edge of the second substrate (5), and a fourth arcuate surface (54) is provided from an edge of the fourth surface (52) toward an edge of the second substrate (5), the third arcuate surface (53) is connected to the fourth arcuate surface (54), and the third arcuate surface (53) has a seventh dimension L in the first direction. ７ and the fourth arcuate surface (54) has a dimension L ８ and 0.01≦L ７ / L ８ ≦1, 0.01≦L ７ / L ５ 18. The method for producing a silicon-on-insulator wafer according to claim 17, wherein the following is satisfied: ≦1.

20. After the step of providing the first substrate (1), 20. The method for producing a silicon-on-insulator wafer according to any one of claims 17 to 19, further comprising the step of performing an oxidation process on the first substrate (1) to form a first oxide layer (3) on the first surface (11) and / or a second oxide layer (4) on the second surface (12).

21. 20. The method for producing a silicon-on-insulator wafer according to claim 12, wherein the annealing comprises increasing the temperature to 900 to 1200° C. at a rate of 2 to 5° C. / min in a nitrogen or oxygen atmosphere and holding the temperature for 4 to 6 hours.

22. 20. The method for producing a silicon-on-insulator wafer according to any one of claims 12 to 19, characterized in that the step of thinning the side of the second substrate (5) facing away from the third surface (51) is performed by mechanical grinding.

23. 16. The method for producing a silicon-on-insulator wafer according to claim 15, wherein the removal amount by the chemical mechanical polishing is 4 to 5 μm.

24. A semiconductor device comprising the silicon-on-insulator wafer according to any one of claims 1 to 7.

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