Semiconductor device and its manufacturing method

Abstract

To provide a technique that can suppress the decrease in performance of a semiconductor device and secure the reliability of the semiconductor device.SOLUTION: A semiconductor device includes a plurality of unit cells UC. Each of the unit cells UC includes a pair of column regions PC, a pair of trenches TR formed between the pair of column regions PC in an X direction, and a pair of gate electrodes GE formed in the pair of trenches TR through an insulating film (GF). The two unit cells UC that are adjacent in the X direction are disposed so that one of the pair of column regions PC is folded back in common. In the X direction, among the trenches TR of the two adjacent unit cells UC, the distance between the two trenches TR that are adjacent through one column region PC is different from the distance between the pair of trenches TR of one unit cell UC.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a column region below a body region and a method for manufacturing the same.

Background Art

[0002] In a semiconductor element such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), there is a PN junction structure called a super junction structure (SJ structure) as a structure for improving breakdown voltage. In the case of an n-type MOSFET, by two-dimensionally arranging p-type column regions in the n-type drift region, the periphery of the p-type column regions can be depleted, and the breakdown voltage can be improved.

[0003] For example, Patent Document 1 proposes a multi-trench SJ structure in which a pair of trench gates is provided in one unit cell. In this multi-trench SJ structure, a plurality of column regions are formed at the boundaries of each unit cell at the same pitch. Also, a plurality of trench gates are formed in each unit cell at the same pitch. In Patent Document 1, by not providing a column region between a pair of trench gates, an increase in manufacturing variations is suppressed while reducing the normalized on-resistance (Rsp).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When considering promoting further miniaturization in Patent Document 1, the dimensions of the unit cell will be reduced while maintaining the existing structure. However, simply reducing each dimension will make manufacturing variations and the like more prominent, so there is a risk that the performance and reliability of the semiconductor device will deteriorate due to the effects of various ion implantations.

[0006] The main object of the present application is to suppress these problems, and to provide a technique that can suppress a decrease in the performance of a semiconductor device and ensure the reliability of the semiconductor device. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] Among the embodiments disclosed in the present application, the outline of a representative one will be briefly described as follows.

[0008] A semiconductor device according to an embodiment includes a plurality of unit cells. Each of the plurality of unit cells includes a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type, a body region of a second conductivity type formed on the surface of the drift region and opposite to the first conductivity type, a source region of the first conductivity type formed on the surface of the body region, a pair of column regions of the second conductivity type formed in the drift region so as to be located below the body region and adjacent to each other with a distance therebetween in a first direction in a plan view, a pair of trenches formed in the drift region so that their bottoms reach a position deeper than the body region and formed between the pair of column regions in the first direction, and a pair of gate electrodes formed in the pair of trenches via a gate insulating film, respectively. Here, two adjacent unit cells in the first direction are arranged so as to share and fold back one of the pair of column regions, and in the first direction, the distance between two trenches adjacent to each other via the one column region among the trenches of two adjacent unit cells is different from the distance between the pair of trenches of one unit cell.

[0009] A method for manufacturing a semiconductor device including a plurality of unit cells according to an embodiment includes: (a) preparing a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type; (b) forming a pair of trenches in the drift region; (c) forming a pair of column regions of a second conductivity type opposite to the first conductivity type in the drift region so as to be adjacent to each other and separated from each other in a first direction in a plan view; (d) forming a pair of gate electrodes in the pair of trenches via a gate insulating film, respectively; (e) forming a body region of the second conductivity type on the surface of the drift region; and (f) forming a source region of the first conductivity type on the surface of the body region. Here, the pair of trenches are formed between the pair of column regions in the first direction, the bottom of each of the pair of trenches reaches a position deeper than the body region, each of the plurality of unit cells includes the semiconductor substrate, the drift region, the pair of trenches, the pair of column regions, the gate insulating film, the pair of gate electrodes, the body region, and the source region, two adjacent unit cells in the first direction are arranged so as to share and fold back one of the pair of column regions, and in the first direction, the distance between two trenches adjacent to each other via the one column region among the trenches of two adjacent unit cells is different from the distance between the pair of trenches of one unit cell.

Advantages of the Invention

[0010] According to an embodiment, it is possible to suppress a decrease in the performance of the semiconductor device and ensure the reliability of the semiconductor device.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

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Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

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Figure 14

Figure 15

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. Further, in the following embodiments, the description of the same or similar parts is not repeated in principle unless particularly necessary.

[0013] In addition, the X direction, Y direction, and Z direction described in the present application intersect and are orthogonal to each other. In the present application, the Z direction is described as the vertical direction, height direction, or thickness direction of a certain structure. Further, expressions such as "plan view" or "plan view" used in the present application mean that the plane formed by the X direction and the Y direction is the "plane", and this "plane" is viewed from the Z direction.

[0014] (Embodiment 1) FIG. 1 is a plan view of a semiconductor chip which is the semiconductor device 100. As shown in FIG. 1, most of the semiconductor device 100 is covered with the source wiring SW, and a gate wiring GW is formed on the outer periphery of the source wiring SW. Although not shown here, the source wiring SW and the gate wiring GW are covered with a protective film PIQ. An opening is provided in a part of the protective film PIQ, and the source wiring SW and the gate wiring GW exposed at the opening become a source pad and a gate pad. By connecting external connection terminals such as wire bonding or a clip (copper plate) on the source pad and the gate pad, the semiconductor device 100 is electrically connected to other chips or a wiring board. The cell region 1A shown in FIG. 1 is a region where main transistors such as a power MOSFET are formed.

[0015] <Matters Studied by the Inventors of the Present Application> Hereinafter, with reference to FIGS. 14 and 15, a semiconductor device of an examination example studied by the inventors of the present application and its problems will be described. FIG. 14 is a partial plan view showing an enlarged view of the cell region 1A shown in FIG. 1, and FIG. 15 is a cross-sectional view taken along line B-B shown in FIG. 14.

[0016] As shown in FIG. 14, the semiconductor device of the examination example includes a plurality of unit cells UC in the cell region 1A. Further, each unit cell UC has a multi-trench SJ structure including a pair of trenches TR and a pair of gate electrodes GE.

[0017] As shown in FIG. 15, the unit cell UC includes a semiconductor substrate SUB having an n-type drift region NV, a p-type body region PB formed on the surface of the drift region NV, an n-type source region formed on the surface of the body region PB, a pair of p-type column regions PC formed in the drift region NV so as to be located below the body region PB, a pair of trenches TR formed in the drift region NV, and a pair of gate electrodes GE formed in the pair of trenches TR via gate insulating films GF, respectively. Further, an n-type drain region ND and a drain electrode DE are formed on the back surface of the semiconductor substrate SUB.

[0018] In the unit cell UC, an interlayer insulating film IL is formed on the semiconductor substrate SUB, and a pair of holes CH1 and a hole CH3 are formed in the interlayer insulating film IL. A source wiring SW is formed on the interlayer insulating film IL so as to fill the pair of holes CH1 and the hole CH3. Further, at the bottom of each of the pair of holes CH1 and the hole CH3, a high-concentration region PR having an impurity concentration higher than that of the body region PB is formed in the body region PB.

[0019] In such a multi-trench SJ structure, a plurality of p-type column regions PC are formed at the boundaries of each unit cell UC at the same pitch (distance L1) in the X direction. Also, the pitch of adjacent trenches TR in the X direction is the same distance L2. Further, in the X direction, the widths of the hole CH1 and the hole CH3 are the same width L3.

[0020] Also, the distance between the trench TR and the hole CH1 is the same as the distance between the trench TR and the hole CH3, and is the distance L4. However, the distance L4 is a numerical value at the time of design, and when forming the holes CH1 and CH3, the positions of the holes CH1 and CH3 may shift in the X direction due to misalignment of the mask. Considering such a case, the distance L4 of the present application can also be defined as follows. The distance L4 is the average value of the distance between one of the pair of trenches TR and the hole CH3 and the distance between the other of the pair of trenches TR and the hole CH3 within one unit cell UC. Also, the distance L4 is the average value of the distance between the trench TR and the hole CH1 in one unit cell UC and the distance between the trench TR and the hole CH1 in the other unit cell UC in two adjacent unit cells UC in the X direction.

[0021] Note that, similar to Patent Document 1 described above, in order to reduce the normalized on-resistance (Rsp), a column region PC is not provided between the pair of trenches TR.

[0022] Here, according to the study by the inventors of the present application, in order to promote the miniaturization of the semiconductor device, it has been found that simply reducing each dimension causes a problem that the high-concentration region PR approaches the trench TR and an increase in the threshold voltage occurs. Also, it has been found that damage may occur in the vicinity of the corner of the trench TR (the region where the gate insulating film GF is formed) due to ion implantation for forming the column region PC. That is, it has been found that if an attempt is made to promote miniaturization, the performance of the semiconductor device may deteriorate and the reliability of the semiconductor device may also deteriorate.

[0023] <Structure of the semiconductor device in Embodiment 1> The inventors of the present application devised the semiconductor device 100 in Embodiment 1 in consideration of the problems of the above-described study example. Hereinafter, the semiconductor device 100 in Embodiment 1 will be described with reference to FIGS. 2 and 3. FIG. 2 is a partial plan view enlarging the cell region 1A shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line A-A shown in FIG. 2.

[0024] As shown in FIG. 2, the semiconductor device 100 of Embodiment 1 includes a plurality of unit cells UC in the cell region 1A, and each unit cell UC has a multi-trench SJ structure, similar to the study example.

[0025] FIG. 3 shows a cross-sectional structure of one unit cell UC of the semiconductor device 100. The semiconductor substrate SUB is made of, for example, n-type silicon and has a drift region NV made of an n-type semiconductor layer. A p-type body region is formed on the surface of the drift region NV. An n-type source region NS is formed on the surface of the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0026] In the drift region NV, a pair of column regions PC are formed so as to be located below the body region PB. The pair of column regions PC extend in the Y direction, are adjacent to each other while being separated in the X direction, and are physically separated from the body region PB in the Z direction. Note that the pair of column regions PC have a higher impurity concentration than the body region PB.

[0027] In the drift region NV, a pair of trenches TR are formed such that their bottoms reach a position deeper than the body region PB. The pair of trenches TR extend in the Y direction and are formed between the pair of column regions PC in the X direction. In each of the pair of trenches TR, a pair of gate electrodes GE are formed via a gate insulating film GF. The gate insulating film GF is, for example, a silicon oxide film, and the gate electrode GE is, for example, an n-type polycrystalline silicon film.

[0028] Also, an n-type drain region ND and a drain electrode DE are formed on the back surface of the semiconductor substrate SUB. The n-type drain region ND has a higher impurity concentration than the drift region NV. The drain electrode DE is made of, for example, a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a laminated film obtained by appropriately laminating these metal films.

[0029] On a semiconductor substrate SUB, an interlayer insulating film IL is formed so as to cover a pair of gate electrodes GE. In the interlayer insulating film IL, a pair of holes CH1 and a hole CH2 are formed. The pair of holes CH1 and the hole CH2 penetrate through the interlayer insulating film IL and the source region NS such that their bottoms are located within the body region PB. The pair of holes CH1 are provided at positions overlapping a pair of column regions PC in plan view and extend in the Y direction. The hole CH2 is formed between the pair of gate electrodes GE in the X direction, and a plurality of holes CH2 are formed in the interlayer insulating film IL so as to be adjacent to each other while being separated from each other in the Y direction. Also, at the bottom of each of the pair of holes CH1 and the hole CH2, a high-concentration region PR having an impurity concentration higher than that of the body region PB is formed within the body region PB.

[0030] On the interlayer insulating film IL, a source wiring SW is formed so as to fill the inside of the pair of holes CH1 and the hole CH2. The source wiring SW is electrically connected to the source region NS, the body region PB, and the high-concentration region PR, and supplies a source potential thereto. On the source wiring SW, a protective film PIQ such as a polyimide film is formed. Although not shown here, a gate wiring GW electrically connected to the gate electrode GE is also formed on the interlayer insulating film IL. Further, the source wiring SW and the gate wiring GW are composed of, for example, a barrier metal film such as a titanium nitride film and a main conductive film such as an aluminum film.

[0031] The semiconductor device 100 can be applied to, for example, the high-side MOSFET and the low-side MOSFET included in a DC / DC converter. Further, when the DC / DC converter is used as a motor drive circuit, the low-side MOSFET may be used as a diode by short-circuiting the gate electrode GE to the source wiring SW. Here, due to the electromotive force generated from the motor (inductance), a voltage Vds is applied between the source and the drain of the MOSFET for the diode, the output capacitance changes, and a reverse recovery current is generated. If the dependency of the output capacitance on the voltage Vds is high, the reverse recovery current is generated abruptly, and this appears as noise. To reduce this noise, a method of mounting a snubber circuit (MIM capacitance) or the like can be considered, but there is a problem that the high-speed operation of the MOSFET is restricted when the snubber circuit is provided.

[0032] Here, the column region PC of the first embodiment is physically separated from the body region PB. Therefore, the source potential is not applied to the pair of column regions PC, and the pair of column regions PC has a floating structure. In the case of the floating structure, at the time of thermal equilibrium state (voltage Vds = 0V), the depletion layers generated from the column region PC and the body region PB are separated. Therefore, compared with the case where the column region PC is physically connected to the body region PB, a sudden change in the output capacitance can be mitigated at the time of positive bias (voltage Vds>0V). Thus, noise can be reduced without mounting a snubber circuit.

[0033] <Main features of the first embodiment> Hereinafter, the main features of the first embodiment (FIGS. 2 and 3) will be described while comparing with the above-described study examples (FIGS. 14 and 15).

[0034] In the first embodiment as well as in the study example, a plurality of p-type column regions PC are formed at the boundaries of each unit cell UC at the same pitch (distance L1) in the X direction. That is, two adjacent unit cells UC in the X direction are arranged so as to share and fold back one of the pair of column regions PC.

[0035] In the study example, the pitch of each trench TR adjacent in the X direction was the same distance L2. In contrast, in Embodiment 1, the pitch (distance L5b) of a pair of trenches TR in one unit cell UC is different from the pitch (distance L6b) of each trench TR in different unit cells UC and is smaller than the distance L6b. That is, the distance L5a between a pair of trenches TR in one unit cell UC is different from the distance L6a between each trench TR in different unit cells UC. In other words, in the X direction, among the trenches of two adjacent unit cells UC, the distance L6a between two trenches TR adjacent via one column region PC is different from the distance L5a between a pair of trenches TR in one unit cell UC and is larger than the distance L5a.

[0036] In the study example, there were problems such as damage occurring near the corners of the trenches TR due to ion implantation in the column region PC, and an increase in the threshold voltage occurring due to the high-concentration region PR approaching the trenches TR. In contrast, in Embodiment 1, each trench TR moves away from the column region PC and also moves away from the high-concentration region PR located above the column region PC. Therefore, the above problems can be suppressed.

[0037] Incidentally, in other words, the above feature means making the distance L8 between the trench TR and the hole CH1 larger than the distance L4 in the study example. Therefore, in Embodiment 1, in the X direction, the distance L8 between the trench TR and the hole CH1 is larger than the distance L9 between the trench TR and the hole CH2. That is, in the X direction, the distance L8 between one trench TR located near one column region PC of a pair of trenches TR and one hole CH1 of a pair of holes CH1 that overlaps the one column region PC in plan view is larger than the distance L9 between the one trench TR and the hole CH2.

[0038] Note that, as will be described later, the high-concentration region PR is formed by performing ion implantation on the body region PB located at the bottoms of a pair of holes CH1 and CH2 after forming these holes. Therefore, the fact that the distance between the trench TR and the hole CH1 approaches, or the distance between the trench TR and the hole CH2 approaches, means that the high-concentration region PR approaches the trench TR, and an increase in the threshold voltage is likely to occur.

[0039] By setting the distance L8 as described above, the distance L9 between one trench TR and the hole CH2 is smaller than the distance L4 in the study example. Then, on the hole CH2 side, there is a risk that an increase in the threshold voltage will occur because the high-concentration region PR approaches the trench TR.

[0040] Therefore, in Embodiment 1, the hole CH2 is not formed in a stripe shape like the hole CH1, but is formed as a plurality of dot patterns. That is, the plurality of holes CH2 are formed so as to be adjacent to each other with a separation in the Y direction. By providing such a plurality of holes CH2, on the hole CH2 side, the area where the high-concentration region PR faces the trench TR can be three-dimensionally reduced. Therefore, an increase in the threshold voltage can also be suppressed on the hole CH2 side.

[0041] Furthermore, in the study example, in the X direction, the widths of the pair of holes CH1 and the hole CH3 were the same width L3, but in Embodiment 1, in the X direction, the width L7 of the hole CH2 is smaller than each width L3 of the pair of holes CH1. Specifically, the width of the hole CH2 is the minimum processing dimension in manufacturing the semiconductor device 100. Therefore, the trench TR can be kept as far as possible from the high-concentration region PR, and an increase in the threshold voltage can be further suppressed.

[0042] On the other hand, the hole CH1 is stripe-shaped as in the study example, and the width of the hole CH1 is the width L3.

[0043] In the semiconductor device 100, an operation (UIS operation) of forcibly turning off the device while a large current is flowing is performed. At this time, avalanche breakdown occurs and electron-hole pairs are generated. Here, the electrons are discharged to the drain electrode DE side, but for the holes, it is necessary to efficiently discharge them to the source wiring SW side through the holes CH1 and CH2. Since avalanche breakdown mainly occurs in the vicinity of the column region PC, it is efficient to secure a hole discharge path on the CH1 side rather than on the CH2 side. Therefore, by extending the hole CH1 in the Y direction to form a stripe shape and making the width of the hole CH1 larger than the width L7 of the hole CH2, efficient discharge of the holes can be achieved.

[0044] As described above, in the first embodiment, while the pitch (distance L1) of each unit cell UC is equivalent to that of the study example, various problems that occurred in the study example can be suppressed. Therefore, the performance of the semiconductor device 100 can be improved, and the reliability of the semiconductor device 100 can be improved. In addition, since the problems of the study example become more prominent as miniaturization progresses, the technology disclosed in the first embodiment is also effective for promoting miniaturization.

[0045] <Method for manufacturing a semiconductor device> Hereinafter, with reference to FIGS. 4 to 11, a method for manufacturing the semiconductor device 100 in the first embodiment will be described. FIGS. 4 to 11 are cross-sectional views taken along the line A-A of FIG. 2, similar to FIG. 3, and show the steps of manufacturing one unit cell UC.

[0046] First, as shown in FIG. 4, a semiconductor substrate SUB having a drift region NV made of an n-type semiconductor layer is prepared. The drift region NV can be formed, for example, by growing a silicon layer while introducing phosphorus (P) by epitaxial growth on an n-type silicon substrate.

[0047] As shown in FIG. 5, a pair of trenches TR are formed in the drift region NV. First, an insulating film IF1 made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, the CVD method. Next, a resist pattern RP1 having an opening is formed on the insulating film IF1 by photolithography. Next, a dry etching process is performed on the insulating film IF1 and the drift region NV exposed from the above opening using the resist pattern RP1 as a mask, thereby forming a pair of trenches TR in the drift region NV. Thereafter, the resist pattern RP1 is removed by ashing, and the insulating film IF1 is removed by wet etching using, for example, hydrofluoric acid.

[0048] As shown in FIG. 6, a pair of p-type column regions PC are formed in the drift region NV. First, an insulating film IF2 made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, the CVD method so as to fill the inside of the pair of trenches TR. Next, the insulating film IF2 located outside the pair of trenches TR is removed by, for example, the CMP method or dry etching.

[0049] Next, an insulating film IF3, an insulating film IF4, and an insulating film IF5 are sequentially formed on the semiconductor substrate SUB by, for example, the CVD method. The insulating film IF3 and the insulating film IF5 are, for example, silicon oxide films, and the insulating film IF4 is, for example, a silicon nitride film. Note that the thickness of the insulating film IF5 is adjusted to a thickness such that ion implantation in the next step does not reach the semiconductor substrate SUB, and is thicker than the thicknesses of each of the insulating film IF3 and the insulating film IF4.

[0050] Next, the insulating film IF5 is selectively patterned using photolithography and dry etching, thereby forming an opening reaching the insulating film IF4 in the insulating film IF5. Next, using the insulating film IF5 as a mask, for example, boron (B) or the like is ion-implanted with the insulating film IF3 and the insulating film IF4 as protective films for protecting the surface of the semiconductor substrate SUB. Thereby, a pair of p-type column regions PC are formed in the drift region NV located below the opening of the insulating film IF5.

[0051] As shown in FIG. 7, the insulating film IF5, insulating film IF4, insulating film IF3, and insulating film IF2 are sequentially removed by wet etching. First, the insulating film IF5 is removed by wet etching using, for example, hydrofluoric acid. Next, the insulating film IF4 is removed by wet etching using, for example, phosphoric acid. Next, the insulating film IF3 and insulating film IF2 are removed by wet etching using, for example, hydrofluoric acid. As a result, the surface of the semiconductor substrate SUB including the inside of the trench TR is exposed.

[0052] As shown in FIG. 8, a pair of gate electrodes GE are formed in a pair of trenches TR via gate insulating films GF, respectively. First, a gate insulating film GF made of a silicon oxide film is formed on the semiconductor substrate SUB including the inside of the pair of trenches TR by, for example, thermal oxidation. Next, a polycrystalline silicon film into which, for example, n-type impurities are introduced is formed on the semiconductor substrate SUB so as to fill the inside of the pair of trenches TR via the gate insulating film GF by, for example, CVD. Next, the polycrystalline silicon film located outside the pair of trenches TR is removed by, for example, CMP or dry etching.

[0053] As shown in FIG. 9, a p-type body region PB is formed on the surface of the drift region NV, and an n-type source region NS is formed on the surface of the body region PB. First, the p-type body region PB is formed by introducing boron (B) or the like onto the surface of the drift region NV by photolithography and ion implantation. Next, the n-type source region NS is formed by introducing arsenic (As) or the like onto the surface of the body region PB by photolithography and ion implantation.

[0054] As shown in FIG. 10, an interlayer insulating film IL is formed on a semiconductor substrate SUB, a pair of holes CH1 and CH2 are formed in the interlayer insulating film IL, and a high-concentration region PR is formed in the body region PB. First, an interlayer insulating film IL made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, CVD method so as to cover a pair of gate electrodes GE. Next, a pair of holes CH1 and CH2 that penetrate the interlayer insulating film IL and the source region NS are formed by photolithography and dry etching processes. The bottom of each of the pair of holes CH1 and CH2 is located within the body region PB. Next, at the bottom of each of the pair of holes CH1 and CH2, boron (B) or the like is ion-implanted into the body region PB to form a p-type high-concentration region PR having an impurity concentration higher than that of the body region PB.

[0055] As shown in FIG. 11, a source wiring SW is formed on the interlayer insulating film IL, and a protective film PIQ is formed on the source wiring SW. First, the source wiring SW is formed on the interlayer insulating film IL by sputtering or CVD method so as to fill the inside of a pair of holes CH1 and CH2. Although not shown here, a gate wiring GW is also formed on the interlayer insulating film IL by the same process as the process of forming the source wiring SW. Next, a protective film PIQ made of, for example, a polyimide film is formed on the source wiring SW and the gate wiring GW by, for example, a coating method. Although not shown, thereafter, a part of the protective film PIQ is opened to expose regions that will become source pads and gate pads on the source wiring SW and the gate wiring GW.

[0056] After FIG. 11, first, the back surface of the semiconductor substrate SUB is polished as necessary. Next, an n-type drain region ND is formed by introducing, for example, arsenic (As) or the like into the back surface of the semiconductor substrate SUB by ion implantation. Next, a drain electrode DE is formed on the drain region ND by sputtering.

[0057] Through the above steps, the semiconductor device 100 shown in FIG. 3 is manufactured.

[0058] (Embodiment 2) The semiconductor device 100 in Embodiment 2 will be described below with reference to FIGS. 12 and 13. In the following description, the differences from Embodiment 1 will be mainly described, and the description of the points overlapping with Embodiment 1 will be omitted. FIG. 13 is a cross-sectional view taken along the C-C line shown in FIG. 12. The cross-sectional view taken along the A-A line shown in FIG. 12 is the same as FIG. 3 of Embodiment 1.

[0059] As shown in FIGS. 12 and 13, in Embodiment 2, a p-type connection region PCa is formed in the drift region NV, and the p-type connection region PCa is provided in the middle of the column region PC extending in the Y direction. The p-type connection region PCa is provided at a position shallower than the column region PC and deeper than the body region PB. A part of the pair of column regions PC is connected to the body region PB by the connection region PCa. The impurity concentration of the connection region PCa is equivalent to that of the column region PC and higher than that of the body region PB.

[0060] As described above, since avalanche breakdown mainly occurs in the vicinity of the column region PC, it is efficient to secure a discharge path for holes on the hole CH1 side. Here, at the location where the column region PC is connected to the body region PB, the discharge efficiency of holes can be increased. By providing such a location in a part of the column region PC by the connection region PCa, the discharge efficiency of holes can be increased compared to the case where the entire column region PC has a floating structure.

[0061] Such a connection region PCa can be formed as follows. First, from the state of FIG. 6, a resist pattern is formed to cover a part of the opening of the insulating film IF5. Next, using the resist pattern and the insulating film IF5 as masks, for example, boron (B) or the like is ion-implanted to form the connection region PCa in the drift region NV. Then, the resist pattern is removed by an ashing process. The connection region PCa may be formed after the column region PC or before the column region PC.

[0062] As described above, the present invention has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist thereof.

Explanation of Reference Numerals

[0063] 100 Semiconductor device 1A Cell region CH1~CH3 Holes DE Drain electrode GE Gate electrode GF Gate insulating film GW Gate wiring IF1~IF5 Insulating films IL Interlayer insulating film ND Drain region NS Source region NV Drift region PB Body region PC Column region PCa Connection region PIQ Protective film PR High-concentration region RP1 Resist pattern SUB Semiconductor substrate SW Source wiring TR Trench UC Unit cell

Claims

1. A semiconductor device including a plurality of unit cells, Each of the plurality of unit cells comprises: a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type; a body region of a second conductivity type opposite to the first conductivity type, the body region being formed on a surface of the drift region; a source region of the first conductivity type formed on a surface of the body region; a pair of column regions of the second conductivity type formed in the drift region so as to be located below the body region and spaced apart from each other in a first direction in a plan view; a pair of trenches formed in the drift region such that their bottoms reach a position deeper than the body region, and formed between the pair of column regions in the first direction; a pair of gate electrodes formed in the pair of trenches with gate insulating films interposed therebetween; an interlayer insulating film formed on the semiconductor substrate so as to cover the pair of gate electrodes; a pair of first holes penetrating the interlayer insulating film and the source region so that bottoms of the first holes are located within the body region and provided at positions overlapping the pair of column regions in a plan view; a second hole penetrating the interlayer insulating film and the source region and formed between the pair of gate electrodes in the first direction so that a bottom portion of the second hole is located within the body region; a source wiring formed on the interlayer insulating film so as to fill the pair of first holes and the second hole; Equipped with two unit cells adjacent to each other in the first direction are arranged so as to share one of the pair of column regions and to be folded back; in the first direction, a distance between two of the trenches adjacent to each other across the one column region is greater than a distance between the pair of trenches of one of the unit cells; a distance in the first direction between one of the pair of trenches located near the one column region and one of the pair of first holes overlapping with the one column region in a plan view is larger than a distance between the one trench and the second hole, the pair of column regions, the pair of trenches, and the pair of first holes each extend in a second direction intersecting the first direction in a plan view, The second holes are formed in a plurality of locations in the interlayer insulating film so as to be spaced apart from each other in the second direction.

2. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the width of the second hole in the first direction is smaller than the width of each of the pair of first holes.

3. 3. The semiconductor device according to claim 2, A semiconductor device, wherein a high concentration region of the second conductivity type having a higher impurity concentration than the body region is formed in the body region at the bottom of each of the pair of first holes and the second hole.

4. 2. The semiconductor device according to claim 1, The pair of column regions are physically separated from the body region.

5. 5. The semiconductor device according to claim 4, a connection region of the second conductivity type is formed in the drift region; the pair of column regions extend in a second direction intersecting the first direction in a plan view, a portion of the pair of column regions being connected to the body region by the connection region;

6. A method for manufacturing a semiconductor device including a plurality of unit cells, comprising the steps of: (a) preparing a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type; (b) forming a pair of trenches in the drift region; (c) forming a pair of column regions of a second conductivity type opposite to the first conductivity type in the drift region so as to be spaced apart from each other in a first direction in a plan view; (d) forming a pair of gate electrodes in the pair of trenches via gate insulating films; (e) forming a body region of the second conductivity type on a surface of the drift region; (f) forming a source region of the first conductivity type on a surface of the body region; (g) forming an interlayer insulating film on the semiconductor substrate so as to cover the pair of gate electrodes; (h) forming a pair of first and second holes penetrating the interlayer insulating film and the source region such that bottoms of the first and second holes are located within the body region; (i) forming a source wiring on the interlayer insulating film so as to fill the pair of first holes and the second hole; Equipped with the pair of trenches are formed between the pair of column regions in the first direction; a bottom of each of the pair of trenches reaches a position deeper than the body region; each of the plurality of unit cells includes the semiconductor substrate, the drift region, the pair of trenches, the pair of column regions, the gate insulating film, the pair of gate electrodes, the body region, the source region, the interlayer insulating film, the pair of first holes, the second hole, and the source wiring; two unit cells adjacent to each other in the first direction are arranged so as to share one of the pair of column regions and to be folded back; in the first direction, a distance between two of the trenches adjacent to each other across the one column region is greater than a distance between the pair of trenches of one of the unit cells; the pair of first holes are provided at positions overlapping the pair of column regions in a plan view, the second hole is formed between the pair of gate electrodes in the first direction, a distance in the first direction between one of the pair of trenches located near the one column region and one of the pair of first holes overlapping with the one column region in a plan view is larger than a distance between the one trench and the second hole, the pair of column regions, the pair of trenches, and the pair of first holes each extend in a second direction intersecting the first direction in a plan view, a second hole formed in the interlayer insulating film so as to be spaced apart from each other in the second direction in the step (h).

7. 7. The method of manufacturing a semiconductor device according to claim 6, a width of the second hole in the first direction is smaller than a width of each of the pair of first holes.

8. 8. The method for manufacturing a semiconductor device according to claim 7, (j) between the step (h) and the step (i), forming a high concentration region of the second conductivity type having a higher impurity concentration than the body region in the bottom of each of the pair of first holes and the second hole within the body region; The method for manufacturing a semiconductor device further comprises:

9. 7. The method of manufacturing a semiconductor device according to claim 6, The method for manufacturing a semiconductor device, wherein the pair of column regions are physically separated from the body region.

10. 10. The method of manufacturing a semiconductor device according to claim 9, (k) forming a connection region of the second conductivity type in the drift region; Further comprising: the pair of column regions extend in a second direction intersecting the first direction in a plan view, A method for manufacturing a semiconductor device, wherein a portion of the pair of column regions is connected to the body region by the connection region.

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