Semiconductor device and its manufacturing method

Abstract

To provide a technique that can secure the reliability of a semiconductor device.SOLUTION: A semiconductor device includes a cell region CR where a plurality of unit cells UC are formed, and an outer peripheral region OR surrounding the cell region CR in a plan view. Each of the unit cells UC includes a semiconductor substrate SUB including a drift region NV, a body region PB, a source region NS, a pair of column regions PC1, and a gate electrode GE formed in a trench TR through a gate insulating film GF. On a surface of the drift region NV in the outer peripheral region OR, a well region PW is formed. In the drift region NV below the well region PW, a column region PC2 extending in a Y direction and an X direction is formed so as to surround the cell region CR. The well region PW is connected to the body region PB and the column region PC2 is connected to the well region PW.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a column region below a body region and a method for manufacturing the same.

Background Art

[0002] In a semiconductor element such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), there is a PN junction structure called a super junction structure (SJ structure) as a structure for improving breakdown voltage. In the case of an n-type MOSFET, by two-dimensionally arranging p-type column regions in the n-type drift region, the periphery of the p-type column regions can be depleted, and the breakdown voltage can be improved.

[0003] For example, Patent Document 1 proposes a multi-trench SJ structure in which a pair of trench gates are provided in one unit cell. In this multi-trench SJ structure, a plurality of column regions are formed at the boundaries of each unit cell at the same pitch. However, Patent Document 1 does not disclose anything regarding the arrangement of the column regions in the outer peripheral region surrounding each unit cell.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a semiconductor device equipped with a power MOSFET, in the outer peripheral region surrounding each unit cell, various impurity regions and the like are formed to ensure breakdown voltage. Even in the case of a power MOSFET having an SJ structure, a device for ensuring breakdown voltage in the outer peripheral region is required, but Patent Document 1 does not disclose anything about such a device.

[0006] The main object of the present application is to ensure breakdown voltage in the outer peripheral region, thereby ensuring the reliability of the semiconductor device. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] Among the embodiments disclosed in the present application, the outline of a representative one will be briefly described as follows.

[0008] A semiconductor device according to an embodiment includes a cell region in which a plurality of unit cells are formed, and an outer peripheral region surrounding the cell region in a plan view. Each of the plurality of unit cells includes a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type, a body region of a second conductivity type formed on a surface of the drift region in the cell region and opposite to the first conductivity type, a source region of the first conductivity type formed on a surface of the body region, a pair of first columnar regions of the second conductivity type formed in the drift region below the body region so as to be physically separated from the body region and adjacent to each other with a distance therebetween in a first direction in a plan view, a trench formed in the drift region such that a bottom portion thereof reaches a position deeper than the body region and formed between the pair of first columnar regions in the first direction, and a gate electrode formed in the trench via a gate insulating film. Here, a first impurity region of the second conductivity type is formed on a surface of the drift region in the outer peripheral region, a second columnar region of the second conductivity type extending in the first direction and in a second direction intersecting the first direction in a plan view so as to surround the cell region is formed in the drift region below the first impurity region, the first impurity region is connected to the body region, and the second columnar region is connected to the first impurity region.

[0009] A method for manufacturing a semiconductor device including a cell region in which a plurality of unit cells according to an embodiment are formed and an outer peripheral region surrounding the cell region in plan view includes: (a) preparing a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type; (b) forming a trench in the drift region of the cell region; (c) forming a pair of first column regions of a second conductivity type opposite to the first conductivity type in the drift region of the cell region so as to be adjacent to each other and separated from each other in a first direction in plan view; (d) forming a second column region of the second conductivity type extending in the first direction and a second direction intersecting the first direction in plan view in the drift region of the outer peripheral region so as to surround the cell region; (e) forming a gate electrode in the trench via a gate insulating film; (f) forming a body region of the second conductivity type on the surface of the drift region of the cell region; (g) forming a source region of the first conductivity type on the surface of the body region; (h) forming a first impurity region of the second conductivity type on the surface of the drift region of the outer peripheral region. Here, the trench is formed between the pair of first column regions in the first direction, the bottom of the trench reaches a position deeper than the body region, each of the plurality of unit cells includes the semiconductor substrate, the drift region, the trench, the pair of first column regions, the gate insulating film, the gate electrode, the body region, and the source region, the pair of first column regions are formed in the drift region below the body region so as to be physically separated from the body region, the first impurity region is connected to the body region, the second column region is formed in the drift region below the first impurity region and is connected to the first impurity region. A method for manufacturing a semiconductor device.

Effects of the Invention

[0010] According to an embodiment, the reliability of the semiconductor device can be ensured.

Brief Description of the Drawings

[0011]

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Embodiments for Carrying Out the Invention

[0012] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. In the following embodiments, explanations of the same or similar parts are not repeated in principle unless particularly necessary.

[0013] In addition, the X direction, Y direction, and Z direction described in the present application intersect each other and are orthogonal to each other. In the present application, the Z direction is described as the vertical direction, height direction, or thickness direction of a certain structure. Further, expressions such as "plan view" or "plan view" used in the present application mean that the plane composed of the X direction and the Y direction is the "plane", and this "plane" is viewed from the Z direction.

[0014] (Embodiment 1) FIGS. 1 and 2 are plan views of a semiconductor chip which is a semiconductor device 100. FIG. 1 mainly shows the wiring formed on the semiconductor substrate SUB, and FIG. 2 shows the structure below the above wiring and shows the structure formed near the surface of the semiconductor substrate SUB.

[0015] As shown in FIG. 1, most of the semiconductor device 100 is covered with a source wiring SW, and a gate wiring GW is formed on the outer periphery of the source wiring SW. Although not shown here, the source wiring SW and the gate wiring GW are covered with a protective film PIQ. An opening is provided in a part of the protective film PIQ, and the source wiring SW and the gate wiring GW exposed at the opening serve as a source pad and a gate pad. By connecting external connection terminals such as wire bonding or a clip (copper plate) on the source pad and the gate pad, the semiconductor device 100 is electrically connected to other chips or a wiring board.

[0016] Further, the semiconductor device 100 includes a cell region CR and an outer peripheral region OR surrounding the cell region CR in a plan view. The cell region CR is a region where main transistors such as a power MOSFET having an SJ structure are formed as unit cells UC.

[0017] As shown in FIG. 2, in the cell region CR, a plurality of gate electrodes GE extend in the X direction. A gate lead-out portion for connecting the plurality of gate electrodes GE is formed near the boundary between the outer peripheral region OR and the cell region CR. A hole CH2 is provided above the gate lead-out portion, and a part of the gate wiring GW is embedded in the hole CH2, so that the gate wiring GW and the plurality of gate electrodes GE are electrically connected.

[0018] Also, in the cell region CR, a plurality of p-type column regions PC1 extending in the X direction are formed between the plurality of gate electrodes GE. In the outer peripheral region OR, p-type column regions PC2 extending in the X direction and the Y direction are formed so as to surround the cell region CR. A plurality of column regions PC2 are formed in the outer peripheral region OR. Here, a case where the cell region CR is surrounded by a double column region PC2 is exemplified. However, the number of column regions PC2 is not limited to two and may be three or more.

[0019] <Matters studied by the inventors of the present application> The semiconductor device of an examination example studied by the inventors of the present application and its problems will be described below with reference to FIG. 23. FIG. 23 is a cross-sectional view corresponding to the enlarged region 1A shown in FIGS. 1 and 2.

[0020] As shown in FIG. 23, the semiconductor device of the examination example includes a plurality of unit cells UC in a cell region CR. Each unit cell UC includes a semiconductor substrate SUB having an n-type drift region NV, a p-type body region PB formed on the surface of the drift region NV, an n-type source region formed on the surface of the body region PB, a pair of p-type column regions PC1 formed in the drift region NV so as to be located below the body region PB, a trench TR formed in the drift region NV, and a gate electrode GE formed in the trench TR via a gate insulating film GF. Further, an n-type drain region ND and a drain electrode DE are formed on the back surface of the semiconductor substrate SUB.

[0021] Also, in each unit cell UC, an interlayer insulating film IL is formed on the semiconductor substrate SUB, and a hole CH1 is formed in the interlayer insulating film IL. A source wiring SW is formed on the interlayer insulating film IL so as to fill the hole CH1. Further, at the bottom of the hole CH1, a high-concentration region PR having an impurity concentration higher than that of the body region PB is formed in the body region PB.

[0022] In the cell region CR, a plurality of column regions PC1 are formed at the boundaries of each unit cell UC at the same pitch in the X direction. Also, in the outer peripheral region OR, column regions PC1 equivalent to the column regions PC1 of the cell region CR are formed at the same pitch. Note that in the outer peripheral region OR, in order to distinguish from the column regions PC1 of the cell region CR, the column regions PC1 are described as column regions PC2.

[0023] In addition, a p-type well region PW is formed in the outer peripheral region OR. The p-type well region PW and the column region PC2 are provided to ensure the breakdown voltage of the semiconductor device. When the unit cell UC is turned on, the depletion layer 50 spreads as shown by the broken line in FIG. 23. In the cell region CR, since a plurality of column regions PC1 are arranged at equal intervals, the spread of the depletion layer 50 is sufficient. However, in the outer peripheral region OR, since the column region PC2 is physically separated from the well region PW, there is a problem that the depletion layer 50 does not spread sufficiently. Specifically, there is a problem that the spread of the depletion layer 50 in the X direction is not sufficient. That is, it has been found that in the study example, the reliability of the semiconductor device may decrease.

[0024] <Structure of the semiconductor device in Embodiment 1> In consideration of the problems of the above-described study example, the inventors of the present application devised a semiconductor device 100 in Embodiment 1. Hereinafter, the semiconductor device 100 in Embodiment 1 will be described with reference to FIG. 3. FIG. 3 is a cross-sectional view corresponding to the enlarged region 1A shown in FIGS. 1 and 2.

[0025] As shown in FIG. 3, the semiconductor device 100 of Embodiment 1 includes a plurality of unit cells UC in the cell region CR, similar to the study example, and each unit cell UC has an SJ structure. First, the structure of each unit cell UC in the cell region CR will be described.

[0026] The semiconductor substrate SUB is made of, for example, n-type silicon and has a drift region NV made of an n-type semiconductor layer. A p-type body region is formed on the surface of the drift region NV. An n-type source region NS is formed on the surface of the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0027] In the drift region NV, a pair of column regions PC1 are formed so as to be located below the body region PB. The pair of column regions PC1 extend in the X direction, are adjacent to each other with a separation in the Y direction, and are physically separated from the body region PB in the Z direction. Note that the pair of column regions PC1 have an impurity concentration higher than that of the body region PB.

[0028] In the drift region NV, trenches TR are formed such that their bottoms reach a position deeper than the body region PB. The trenches TR extend in the X direction and are formed between the pair of column regions PC1 in the Y direction. Gate electrodes GE are formed in the trenches TR via gate insulating films GF respectively. The gate insulating films GF are, for example, silicon oxide films, and the gate electrodes GE are, for example, n-type polycrystalline silicon films.

[0029] Also, an n-type drain region ND and a drain electrode DE are formed on the back surface of the semiconductor substrate SUB. The n-type drain region ND has an impurity concentration higher than that of the drift region NV. The drain electrode DE is composed of, for example, a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film or a silver film, or a laminated film formed by appropriately laminating these metal films.

[0030] An interlayer insulating film IL is formed on the semiconductor substrate SUB so as to cover the gate electrode GE. The interlayer insulating film IL is, for example, a silicon oxide film. A plurality of holes CH1 are formed in the interlayer insulating film IL. The plurality of holes CH1 penetrate the interlayer insulating film IL and the source region NS such that their bottoms are located in the body region PB. The plurality of holes CH1 are provided at positions overlapping the pair of column regions PC1 in a plan view and extend in the X direction. Also, at the bottom of each of the plurality of holes CH1, a high-concentration region PR having an impurity concentration higher than that of the body region PB is formed in the body region PB. Note that although not shown here, a plurality of holes CH2 are also formed in the interlayer insulating film IL.

[0031] On the interlayer insulating film IL, a source wiring SW is formed so as to fill a plurality of holes CH1. The source wiring SW is electrically connected to a source region NS, a body region PB, and a high-concentration region PR, and supplies a source potential thereto. A protective film PIQ such as a polyimide film is formed on the source wiring SW. Note that a gate wiring GW is also formed on the interlayer insulating film IL. Although not shown here, the gate wiring GW is embedded in the hole CH2 and is electrically connected to the gate electrode GE. A gate potential is applied to the gate electrode GE from the gate wiring GW. The source wiring SW and the gate wiring GW are each composed of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium nitride film, and the conductive film is, for example, an aluminum film.

[0032] Note that the source wiring SW and the gate wiring GW may be composed of a plug layer that fills the inside of the hole CH1 or the hole CH2, and the barrier metal film and the conductive film formed on the interlayer insulating film IL. In that case, the plug layer is composed of a barrier metal film such as a titanium nitride film and a conductive film such as a tungsten film.

[0033] The semiconductor device 100 can be applied to, for example, a high-side MOSFET and a low-side MOSFET included in a DC / DC converter. Also, when the DC / DC converter is used as a motor drive circuit, the low-side MOSFET may be used as a diode by short-circuiting the gate electrode GE to the source wiring SW. Here, a voltage Vds is applied between the source and the drain of the MOSFET for the diode by the electromotive force generated from the motor (inductance), the output capacitance changes, and a reverse recovery current is generated. If the dependency of the output capacitance on the voltage Vds is high, the reverse recovery current is generated abruptly, which appears as noise. To reduce this noise, a method of mounting a snubber circuit (MIM capacitor) or the like can be considered, but there is a problem that the high-speed operation of the MOSFET is restricted when the snubber circuit is provided.

[0034] Here, the column region PC1 of Embodiment 1 is physically separated from the body region PB. Therefore, no source potential is applied to the pair of column regions PC1, and the pair of column regions PC1 has a floating structure. In the case of a floating structure, at the thermal equilibrium state (voltage Vds = 0V), the depletion layers generated from the column region PC1 and the body region PB are separated. Therefore, compared with the case where the column region PC1 is physically connected to the body region PB, a rapid change in the output capacitance during positive bias (voltage Vds > 0V) can be mitigated. Thus, noise can be reduced without mounting a snubber circuit.

[0035] On the surface of the drift region NV in the outer peripheral region OR, a p-type well region (impurity region) PW is formed. The well region PW is connected to the body region PB. Also, a plurality of column regions PC2 are formed in the drift region NV below the well region PW. Note that the impurity concentration of the well region PW is lower than that of the body region PB, and the impurity concentration of each of the column regions PC1 and the column region PC2 is higher than the impurity concentration of each of the well region PW and the body region PB.

[0036] Similar to the study example in Embodiment 1, the plurality of column regions PC1 and the plurality of column regions PC2 are arranged at equal intervals. However, in the study example, the thickness of the column region PC2 was the same as the thickness of the column region PC1, but in Embodiment 1, the thickness of the column region PC2 is thicker than the thickness of the column region PC1. Therefore, the plurality of column regions PC2 are connected to the well region PW. That is, the plurality of column regions PC2 are electrically connected to the source wiring SW via the body region PB and the well region PW. Therefore, a source potential is applied to the plurality of column regions PC2 from the source wiring SW via the body region PB and the well region PW.

[0037] During the on-operation of the unit cell UC, the depletion layer 50 spreads sufficiently as shown by the broken line in FIG. 3. Therefore, breakdown voltage can be ensured in the outer peripheral region OR, and the reliability of the semiconductor device 100 can be ensured.

[0038] Note that not all of the plurality of column regions PC2 need to be thicker than the thickness of the column region PC1, nor do they need to be connected to the well region PW. However, the outermost column region PC2 among the plurality of column regions PC2 needs to be formed to be thicker than the thickness of the column region PC1 and connected to the well region PW. Note that the outermost column region PC2 is the column region PC2 located farthest from the cell region CR and is the column region PC2 closest to the end of the semiconductor device 100 (the end of the semiconductor chip).

[0039] <Method for manufacturing a semiconductor device> Hereinafter, with reference to FIGS. 4 to 12, a method for manufacturing the semiconductor device 100 in Embodiment 1 will be described. FIGS. 4 to 12 are cross-sectional views corresponding to the enlarged region 1A shown in FIGS. 1 and 2, similar to FIG. 3.

[0040] First, as shown in FIG. 4, a semiconductor substrate SUB having a drift region NV made of an n-type semiconductor layer is prepared. The drift region NV can be formed, for example, by growing a silicon layer while introducing phosphorus (P) by an epitaxial growth method on an n-type silicon substrate.

[0041] As shown in FIG. 5, a trench TR is formed in the drift region NV of the cell region CR. First, an insulating film IF1 made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, a CVD method. Next, a resist pattern RP1 having an opening is formed on the insulating film IF1 by a photolithography method. Next, a dry etching process is performed on the insulating film IF1 and the drift region NV exposed from the opening using the resist pattern RP1 as a mask, thereby forming a trench TR in the drift region NV. Thereafter, the resist pattern RP1 is removed by an ashing process, and the insulating film IF1 is removed by a wet etching process using, for example, hydrofluoric acid.

[0042] As shown in FIG. 6, a p-type column region PC1 is formed in the drift regions NV of the cell region CR and the outer peripheral region OR. First, an insulating film IF2 made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, the CVD method so as to fill the trench TR. Next, the insulating film IF2 located outside the pair of trenches TR is removed by, for example, the CMP method or dry etching treatment.

[0043] Next, an insulating film IF3, an insulating film IF4, and an insulating film IF5 are sequentially formed on the semiconductor substrate SUB by, for example, the CVD method. The insulating film IF3 and the insulating film IF5 are, for example, silicon oxide films, and the insulating film IF4 is, for example, a silicon nitride film. Note that the thickness of the insulating film IF5 is greater than the thickness of each of the insulating film IF3 and the insulating film IF4.

[0044] Next, a resist pattern RP2 is formed on the insulating film IF5, and the insulating film IF5 is selectively patterned by performing a dry etching treatment using the resist pattern RP2 as a mask, and an opening reaching the insulating film IF4 is formed in the insulating film IF5. Next, using the resist pattern RP2 and the insulating film IF5 as masks, ions such as boron (B) are implanted to use the insulating film IF3 and the insulating film IF4 as protective films for protecting the surface of the semiconductor substrate SUB. As a result, a p-type column region PC1 is formed in the drift region NV located below the opening of the insulating film IF5.

[0045] Note that the column region PC1 formed in the drift region NV of the outer peripheral region OR is formed as a part of the column region PC2. Thereafter, the resist pattern RP2 is removed by an ashing treatment.

[0046] As shown in FIG. 7, a p-type column region PC2 is formed in the drift region NV of the outer peripheral region OR. First, a resist pattern RP3 having a pattern that covers the opening of the insulating film IF5 in the cell region CR and exposes the opening of the insulating film IF5 in the outer peripheral region OR is formed on the insulating film IF5. Next, using the resist pattern RP3 and the insulating film IF5 as masks, for example, boron (B) or the like is selectively ion-implanted into the outer peripheral region OR. As a result, the other part of the column region PC2 is formed in the drift region NV above a part (column region PC1) of the column region PC2.

[0047] Note that the ion implantation in FIG. 7 is performed in multiple times with an implantation energy lower than that of the ion implantation in FIG. 6. By appropriately adjusting the implantation energy, a column region PC2 having a thickness that contacts the well region PW in a later process can be formed. Thereafter, the resist pattern RP3 is removed by an ashing process.

[0048] As shown in FIG. 8, the insulating film IF5, the insulating film IF4, the insulating film IF3, and the insulating film IF2 are sequentially removed by a wet etching process. First, the insulating film IF5 is removed by a wet etching process using, for example, hydrofluoric acid. Next, the insulating film IF4 is removed by a wet etching process using, for example, phosphoric acid. Next, the insulating film IF3 and the insulating film IF2 are removed by a wet etching process using, for example, hydrofluoric acid. As a result, the surface of the semiconductor substrate SUB including the inside of the trench TR is exposed.

[0049] As shown in FIG. 9, a gate electrode GE is formed in the trench TR via a gate insulating film GF, respectively. First, a gate insulating film GF made of a silicon oxide film is formed on the semiconductor substrate SUB including the inside of the trench TR by, for example, a thermal oxidation method. Next, a polycrystalline silicon film into which, for example, an n-type impurity is introduced is formed on the semiconductor substrate SUB so as to fill the inside of the trench TR via the gate insulating film GF by, for example, a CVD method. Next, the polycrystalline silicon film located outside the trench TR is removed by, for example, a CMP method or a dry etching process.

[0050] As shown in FIG. 10, first, by introducing boron (B) or the like onto the surface of the drift region NV of the outer peripheral region OR by photolithography and ion implantation, a p-type well region PW is formed. Next, by introducing boron (B) or the like onto the surface of the drift region NV of the cell region CR by photolithography and ion implantation, a p-type body region PB is formed. Next, by introducing arsenic (As) or the like onto the surface of the body region PB by photolithography and ion implantation, an n-type source region NS is formed.

[0051] As shown in FIG. 11, an interlayer insulating film IL is formed on the semiconductor substrate SUB, a hole CH1 is formed in the interlayer insulating film IL of the cell region CR, and a high-concentration region PR is formed in the body region PB. First, an interlayer insulating film IL made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, CVD so as to cover the gate electrode GE. Next, a hole CH1 that penetrates the interlayer insulating film IL and the source region NS is formed by photolithography and dry etching. The bottom of the hole CH1 is located within the body region PB. Next, at the bottom of the hole CH1, boron (B) or the like is ion-implanted into the body region PB to form a p-type high-concentration region PR having an impurity concentration higher than that of the body region PB.

[0052] Thereafter, although not shown, a hole CH2 is formed by photolithography and dry etching in a part of the interlayer insulating film IL located on a part of the gate electrode GE set in the gate lead-out portion.

[0053] As shown in FIG. 12, a source wiring SW is formed on an interlayer insulating film IL, and a protective film PIQ is formed on the source wiring SW. First, on the interlayer insulating film IL, a laminated film of a barrier metal film made of, for example, a titanium nitride film and a conductive film made of, for example, an aluminum film is formed by a sputtering method or a CVD method so as to fill the inside of a hole CH1. Next, the source wiring SW is formed by patterning the laminated film. Although not shown here, a gate wiring GW is also formed on the interlayer insulating film IL so as to fill the inside of a hole CH2 by the same process as the process of forming the source wiring SW. Next, a protective film PIQ made of, for example, a polyimide film is formed on the source wiring SW and the gate wiring GW by, for example, a coating method. Thereafter, although not shown, a part of the protective film PIQ is opened to expose regions that will become source pads and gate pads on the source wiring SW and the gate wiring GW.

[0054] After FIG. 12, first, the back surface of the semiconductor substrate SUB is polished as necessary. Next, an n-type drain region ND is formed by introducing, for example, arsenic (As) or the like into the back surface of the semiconductor substrate SUB by an ion implantation method. Next, a drain electrode DE is formed on the drain region ND by a sputtering method.

[0055] Through the above steps, the semiconductor device 100 shown in FIG. 3 is manufactured.

[0056] (Modification example) Hereinafter, with reference to FIGS. 13 to 17, a method for manufacturing a semiconductor device in a modification example will be described. In the following description, the differences from Embodiment 1 will be mainly described, and the description of the points overlapping with Embodiment 1 will be omitted.

[0057] In the modification example, the order of manufacturing each component such as the column region PC1 is different from that in Embodiment 1, but the process of manufacturing each component itself is substantially the same as that in Embodiment 1. Therefore, hereinafter, the order of each component will be mainly described, and the detailed description of the process itself will be omitted.

[0058] The manufacturing method of the semiconductor device in the modified example is the same as that of the first embodiment up to FIG. 5. After the process of FIG. 5, as shown in FIG. 13, a well region PW is formed on the surface of the drift region NV in the outer peripheral region OR. Next, a trench TR is formed in the drift region NV of the cell region CR.

[0059] Next, as shown in FIG. 14, gate electrodes GE are formed in the trenches TR via gate insulating films GF respectively. Next, as shown in FIG. 15, a body region PB is formed on the surface of the drift region NV of the cell region CR, and a source region NS is formed on the surface of the body region PB.

[0060] Next, as shown in FIG. 16, an insulating film IF3, an insulating film IF4, and an insulating film IF5 are sequentially formed on the gate insulating film GF on the semiconductor substrate SUB, for example, by CVD method. Next, a resist pattern RP2 is formed on the insulating film IF5, and a dry etching process is performed using the resist pattern RP2 as a mask, thereby selectively patterning the insulating film IF5 to form an opening in the insulating film IF5 that reaches the insulating film IF4.

[0061] Next, using the resist pattern RP2 and the insulating film IF5 as masks, for example, boron (B) or the like is ion-implanted. Thereby, a p-type column region PC1 is formed in the drift region NV located below the opening of the insulating film IF5. Note that, similar to the first embodiment, the column region PC1 formed in the drift region NV of the outer peripheral region OR is formed as a part of the column region PC2. Thereafter, the resist pattern RP2 is removed by ashing treatment.

[0062] Next, as shown in FIG. 17, a resist pattern RP3 similar to that of the first embodiment is formed on the insulating film IF5. Next, using the resist pattern RP3 and the insulating film IF5 as masks, for example, boron (B) or the like is selectively ion-implanted into the outer peripheral region OR. Thereby, the other part of the column region PC2 is formed in the drift region NV above a part (column region PC1) of the column region PC2.

[0063] Thereafter, the resist pattern RP3 is removed by an ashing process, and the insulating film IF5, the insulating film IF4, and the insulating film IF3 are sequentially removed by a wet etching process. Here, the gate insulating film GF on the semiconductor substrate SUB may be removed together with the insulating film IF3, or may be left. Also, the insulating film IF3 may be left without being removed.

[0064] Thereafter, the processes after FIG. 11 described in Embodiment 1 are performed. Thus, even in the method of manufacturing a semiconductor device in the modification, the semiconductor device 100 in FIG. 3 can be manufactured.

[0065] (Embodiment 2) Hereinafter, the semiconductor device 100 in Embodiment 2 will be described with reference to FIG. 18. In the following description, the differences from Embodiment 1 will be mainly described, and the description of the points overlapping with Embodiment 1 will be omitted.

[0066] As shown in FIG. 18, the column region PC2 in Embodiment 2 has the same configuration as the column region PC1 and is formed by the same ion implantation as the column region PC1. Therefore, the thickness of the column region PC2 is the same as the thickness of the column region PC1 in the cell region CR. Instead, in Embodiment 2, the thickness of the well region PW is thicker than the thickness of the body region PB. For this reason, also in Embodiment 2, the column region PC2 is connected to the well region PW. Therefore, since the depletion layer 50 spreads sufficiently, breakdown voltage can be ensured in the outer peripheral region OR, and the reliability of the semiconductor device 100 can be ensured.

[0067] Note that the well region PW in Embodiment 2 can be formed by performing ion implantation for the well region PW in a plurality of times so that each implantation energy is different. Since the well region PW is formed in this way, in Embodiment 2, it is not necessary to newly add a mask for forming the well region PW.

[0068] In addition, since the column region PC2 is formed by the same ion implantation as the column region PC1 using the resist pattern RP2 shown in FIG. 6, the ion implantation performed using the resist pattern RP3 shown in FIG. 7 can be omitted. Therefore, in the second embodiment, compared with the first embodiment, the manufacturing process can be simplified.

[0069] (Embodiment 3) Hereinafter, the semiconductor device 100 in the third embodiment will be described with reference to FIGS. 19 to 21. In the following description, the differences from the first embodiment will be mainly described, and the description of the points overlapping with the first embodiment will be omitted.

[0070] As shown in FIG. 19, in the third embodiment, the thickness of the column region PC2 is substantially the same as the thickness of the column region PC1 in the cell region CR, but the position of the bottom of the column region PC2 is shallower than the position of the bottom of the column region PC1. Also in the third embodiment, the column region PC2 is connected to the well region PW. Therefore, since the depletion layer 50 spreads sufficiently, the breakdown voltage can be ensured in the outer peripheral region OR, and the reliability of the semiconductor device 100 can be ensured.

[0071] The column region PC2 in the third embodiment is formed by the same ion implantation as the column region PC1. This ion implantation is performed in a state where a stacked film of the insulating film IF3 and the insulating film IF4 formed on the drift region NV is formed. However, in the third embodiment, the thickness of the stacked film in the outer peripheral region OR is different from the thickness of the stacked film in the cell region CR, and is thicker than the thickness of the stacked film in the cell region CR. For this reason, when the same ion implantation is performed on the outer peripheral region OR and the cell region CR, the position of the bottom of the column region PC2 in the outer peripheral region OR becomes shallower than the position of the bottom of the column region PC1 in the cell region CR.

[0072] Such ion implantation is performed in a state as shown in FIG. 20 or FIG. 21 instead of FIGS. 6 and 7 of the first embodiment.

[0073] In FIG. 20, the thickness of the insulating film IF4 in the outer peripheral region OR is greater than the thickness of the insulating film IF4 in the cell region CR. To achieve such a state, after forming the insulating film IF4 with a thickness greater than that in the first embodiment, the thickness of the insulating film IF4 in the cell region CR may be selectively reduced by photolithography and dry etching processes. Thereafter, similar to the first embodiment, the insulating film IF5 and the resist pattern RP2 are formed. After forming an opening in the insulating film IF5, ion implantation is performed.

[0074] In FIG. 21, the thickness of the insulating film IF3 in the outer peripheral region OR is greater than the thickness of the insulating film IF3 in the cell region CR. To achieve such a state, after forming the insulating film IF3 with a thickness greater than that in the first embodiment, the thickness of the insulating film IF3 in the cell region CR may be selectively reduced by photolithography and dry etching processes. Thereafter, similar to the first embodiment, the insulating film IF4, the insulating film IF5, and the resist pattern RP2 are formed. After forming an opening in the insulating film IF5, ion implantation is performed.

[0075] When applying such ion implantation to the manufacturing method of the modification, instead of FIGS. 16 and 17 of the modification, the technical concept of FIG. 20 or FIG. 21 may be applied.

[0076] (Embodiment 4) Hereinafter, the semiconductor device 100 in Embodiment 4 will be described with reference to FIG. 22. In the following description, the differences from Embodiment 1 will be mainly described, and the description of the points overlapping with Embodiment 1 will be omitted.

[0077] Each unit cell UC of Embodiment 4 has a multi-trench SJ structure provided with a pair of trenches TR and a pair of gate electrodes GE. In the Y direction, the pair of trenches TR is located between the pair of column regions PC1, but no column region PC1 is provided between the pair of trenches TR. By applying such a unit cell UC to the cell region CR, it is possible to reduce the normalized on-resistance (Rsp) (see Patent Document 1). Also, in Embodiment 4, it is possible to ensure breakdown voltage in the outer peripheral region OR and ensure the reliability of the semiconductor device 100.

[0078] Note that the unit cell UC having the multi-trench SJ structure disclosed in Embodiment 4 can also be applied to Embodiment 2 or Embodiment 3.

[0079] As described above, the present invention has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Explanation of Reference Numerals

[0080] 50 depletion layer 100 semiconductor device 1A enlarged region CH1, CH2 holes CR cell region DE drain electrode GE gate electrode GF gate insulating film GW gate wiring IF1~IF5 insulating films IL interlayer insulating film ND drain region NS source region NV drift region OR outer peripheral region PB body region PC1, PC2 column regions PIQ protective film PR high-concentration region RP1~RP3 resist patterns PW well region (impurity region) SUB Semiconductor substrate SW Source wiring TR Trench UC Unit cell

Claims

1. 1. A semiconductor device including a cell region in which a plurality of unit cells are formed, and a peripheral region surrounding the cell region in a plan view, Each of the plurality of unit cells comprises: a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type; a body region of a second conductivity type opposite to the first conductivity type, the body region being formed on a surface of the drift region of the cell region; a source region of the first conductivity type formed on a surface of the body region; a pair of first column regions of the second conductivity type formed in the drift region below the body region so as to be physically separated from the body region and spaced apart from each other in a first direction in a plan view; a trench formed in the drift region such that a bottom portion of the trench reaches a position deeper than the body region and is formed between the pair of first column regions in the first direction; a gate electrode formed in the trench via a gate insulating film; Equipped with a first impurity region of the second conductivity type is formed on a surface of the drift region of the peripheral region, a second column region of the second conductivity type extending in the first direction and in a second direction intersecting the first direction in a plan view is formed in the drift region below the first impurity region so as to surround the cell region; the first impurity region is connected to the body region; the second column region is connected to the first impurity region, an impurity concentration of the first impurity region is lower than an impurity concentration of the body region; an impurity concentration of each of the second column region and the pair of first column regions is higher than an impurity concentration of each of the first impurity region and the body region.

2. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the second column region is thicker than the pair of first column regions.

3. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the first impurity region is thicker than the body region.

4. 2. The semiconductor device according to claim 1, a bottom position of the second column region is shallower than a bottom position of the pair of first column regions.

5. 2. The semiconductor device according to claim 1, Each of the plurality of unit cells further comprises: an interlayer insulating film formed on the semiconductor substrate so as to cover the gate electrode; a pair of first holes penetrating the interlayer insulating film and the source region so that bottoms of the first holes are located within the body region and provided at positions overlapping the pair of first column regions in a plan view; a source wiring formed on the interlayer insulating film so as to fill the pair of first holes; Equipped with a source potential is applied to the second column region from the source wiring via the body region and the first impurity region.

6. 2. The semiconductor device according to claim 1, the first conductivity type is n-type, The second conductivity type is a p-type.

7. A semiconductor device including a cell region in which a plurality of unit cells are formed, and a peripheral region surrounding the cell region in a plan view, Each of the plurality of unit cells comprises: a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type; a body region of a second conductivity type opposite to the first conductivity type, the body region being formed on a surface of the drift region of the cell region; a source region of the first conductivity type formed on a surface of the body region; a pair of first column regions of the second conductivity type formed in the drift region below the body region so as to be physically separated from the body region and spaced apart from each other in a first direction in a plan view; a trench formed in the drift region such that a bottom portion of the trench reaches a position deeper than the body region and is formed between the pair of first column regions in the first direction; a gate electrode formed in the trench via a gate insulating film; Equipped with a first impurity region of the second conductivity type is formed on a surface of the drift region of the peripheral region, a second column region of the second conductivity type extending in the first direction and in a second direction intersecting the first direction in a plan view is formed in the drift region below the first impurity region so as to surround the cell region; the first impurity region is connected to the body region; the second column region is connected to the first impurity region, A semiconductor device, wherein the second column region is thicker than the pair of first column regions.

8. 1. A method for manufacturing a semiconductor device including a cell region in which a plurality of unit cells are formed, and a peripheral region surrounding the cell region in a plan view, comprising: (a) preparing a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type; (b) forming a trench in the drift region of the cell area; (c) forming a pair of first column regions of a second conductivity type opposite to the first conductivity type in the drift region of the cell region so as to be spaced apart from each other in a first direction in a plan view; (d) forming a second column region of the second conductivity type in the drift region of the outer periphery region, the second column region extending in the first direction and in a second direction intersecting the first direction in a plan view, so as to surround the cell region; (e) forming a gate electrode in the trench via a gate insulating film; (f) forming a body region of the second conductivity type on a surface of the drift region in the cell region; (g) forming a source region of the first conductivity type on a surface of the body region; (h) forming a first impurity region of the second conductivity type on a surface of the drift region in the peripheral region; Equipped with the trench is formed between the pair of first column regions in the first direction; The bottom of the trench reaches a position deeper than the body region, each of the plurality of unit cells includes the semiconductor substrate, the drift region, the trench, the pair of first column regions, the gate insulating film, the gate electrode, the body region, and the source region; the pair of first column regions are formed in the drift region below the body region so as to be physically separated from the body region; the first impurity region is connected to the body region; the second column region is formed in the drift region below the first impurity region and is connected to the first impurity region; an impurity concentration of the first impurity region is lower than an impurity concentration of the body region; a first column region and a second column region having a first impurity region and a body region, the first column region and a second column region having a first impurity region and a body region, the second column region and a second column region having a first impurity region and a body region,

9. 9. The method for manufacturing a semiconductor device according to claim 8, The step (c) is carried out by ion implantation, In the step (c), the first column region is also formed in the drift region of the outer circumferential region as a part of the second column region, a second column region formed in the drift region above the second column region by selectively implanting ions into the outer circumferential region in the step (d).

10. 9. The method for manufacturing a semiconductor device according to claim 8, the steps (c) and (d) are performed by the same ion implantation; a thickness of the first impurity region formed in the step (h) is greater than a thickness of the body region formed in the step (f).

11. 9. The method for manufacturing a semiconductor device according to claim 8, the step (c) and the step (d) are performed by the same ion implantation in a state in which a stacked film of a first insulating film and a second insulating film is formed on the drift region in each of the cell region and the peripheral region; A method for manufacturing a semiconductor device, wherein a thickness of the laminated film in the outer periphery region is greater than a thickness of the laminated film in the cell region.

12. 9. The method for manufacturing a semiconductor device according to claim 8, (i) forming an interlayer insulating film on the semiconductor substrate so as to cover the gate electrode; (j) forming a pair of first holes penetrating the interlayer insulating film and the source region such that bottoms of the first holes are located within the body region; (k) forming a source wiring on the interlayer insulating film so as to fill the pair of first holes; Further comprising: the pair of first holes are provided at positions overlapping the pair of first column regions in a plan view, each of the plurality of unit cells further includes the interlayer insulating film, the pair of first holes, and the source wiring; the second column region is electrically connected to the source wiring via the body region and the first impurity region.

13. 9. The method for manufacturing a semiconductor device according to claim 8, the first conductivity type is n-type, The second conductivity type is a p-type.

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