Semiconductor Device

Abstract

To miniaturize a semiconductor device, and to reduce an area of a drive circuit of a semiconductor device having a memory cell.SOLUTION: A semiconductor device comprises: an element formation layer having at least a first semiconductor element; first wiring provided on the element formation layer; an interlayer film provided on the first wiring; and second wiring superposed with the first wiring via the interlayer film. The first wiring, the interlayer film, and the second wiring configure a second semiconductor element. The first wiring and the second wiring are supplied with the same potential.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed invention relates to a semiconductor device utilizing a semiconductor element. [Background technology]

[0002] EEPROM and flash memory are devices that allow you to repeatedly write and erase data. Semiconductor devices such as non-volatile memory devices that can store data are highly convenient and resistant to physical shocks. Therefore, the main devices used are portable storage media such as USB memory and memory cards, and wireless information RFID (Radio Frequency Identification) They are used in RF tags, which are a medium for photoelectron ion (PES), and are widely available on the market. The device has a transistor functioning as a memory element in each memory cell. A transistor has an electrode called a floating gate, which is connected to a gate electrode and a semiconductor active layer. The floating gate has a gap between the semiconductor membrane and the gate, and data is stored by accumulating charges on the floating gate. This can be done.

[0003] The following Patent Documents 1 and 2 disclose floating gates formed on a glass substrate. A thin film transistor having [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 6-021478 [Patent Document 2] JP 2005-322899 A Summary of the Invention [Problem to be solved by the invention]

[0005] By the way, when forming a circuit having a plurality of signal lines in a driver circuit of a semiconductor device, In order to reduce the area of ​​the driver circuit, the number of wiring layers is increased and signal lines are formed on each layer. However, simply increasing the number of wiring layers does not necessarily mean increasing the number of wiring masks. Increasing the number of sheets is not preferable because it increases costs.

[0006] In particular, a semiconductor device such as a memory device includes a memory cell and a drive circuit for driving the memory cell. The size of the semiconductor device is limited by the area of ​​the driver circuit. Even if the cell area is reduced, if the driving circuit area cannot be reduced, the semiconductor Therefore, it is not possible to reduce the area of ​​the driving circuit. This is important in miniaturizing semiconductor devices.

[0007] In view of the above, an object of one embodiment of the present invention is to miniaturize a semiconductor device.

[0008] Another embodiment of the present invention is to reduce the area of ​​a driver circuit of a semiconductor device having memory cells. One of the challenges we face is to: [Means for solving the problem]

[0009] One embodiment of the disclosed invention is a semiconductor device including an element formation layer having at least a first semiconductor element; A first wiring provided on the formation layer, an interlayer film provided on the first wiring, and a and a second wiring layer overlapping the first wiring layer. , constitute a second semiconductor element, and the first wiring and the second wiring are supplied with the same potential. The semiconductor device is an interconnect.

[0010] Another embodiment of the disclosed invention is a method for forming an element having at least a first semiconductor element. a first wiring provided on the element formation layer; an interlayer film provided on the first wiring; and a second wiring layer overlapping the first wiring layer via an interlayer film. The second wiring constitutes a second semiconductor element, and the first wiring and the second wiring are in-phase. This is a semiconductor device in which signals are supplied via wiring.

[0011] Another embodiment of the disclosed invention is a semiconductor memory device including a memory cell and a driver circuit for the memory cell. A semiconductor device, comprising: a memory cell including a first channel forming region, a first gate electrode, a first a first transistor including a first source electrode and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode; a second transistor and a capacitance element, and the second transistor is at least partially connected to the first transistor. The driving circuit section is provided so as to overlap with the second source electrode or the second drain electrode. A first wiring formed in the same process as the electrode is overlapped with the first wiring via an interlayer film, and and a second wiring formed in the same process as the gate electrode of the first gate electrode. The wiring and the second wiring are wirings to which the same potential is supplied in the semiconductor device.

[0012] Another embodiment of the disclosed invention is a semiconductor memory device including a memory cell and a driver circuit for the memory cell. A semiconductor device, comprising: a memory cell including a first channel forming region, a first gate electrode, a first a first transistor including a first source electrode and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode; a second transistor and a capacitance element, and the second transistor is at least partially connected to the first transistor. The driving circuit section is provided so as to overlap with the second source electrode or the second drain electrode. A first wiring formed in the same process as the electrode is overlapped with the first wiring via an interlayer film, and and a second wiring formed in the same process as the gate electrode of the first gate electrode. The wiring and the second wiring are wirings to which signals of the same phase are supplied in the semiconductor device.

[0013] In the semiconductor device, the semiconductor element may be a level shifter. The thickness is preferably 10 nm or more and 100 nm or less.

[0014] In addition, the terms "above" and "below" in this specification and the like refer to the positional relationship of components "directly above" or "below." For example, "gate electrode on a gate insulating film" is not limited to "directly under". ", it excludes those that include other components between the gate insulating film and the gate electrode. do not have.

[0015] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wire." In addition, the term "electrode" or "wiring" may be used to refer to the plural "electrodes" or "wirings". This also includes cases where the "line" is formed as an integral part.

[0016] In addition, the functions of the "source" and "drain" may differ depending on whether transistors of different polarities are used or not. However, they may be swapped when the direction of the current changes during circuit operation. In this specification, the terms "source" and "drain" can be used interchangeably. It is possible.

[0017] In addition, in this specification, "electrically connected" means "something that has some electrical effect" " includes cases where the device is connected via "anything that has some electrical effect." " is not subject to any particular restriction as long as it enables the transmission and reception of electrical signals between the connection objects. For example, "things that have some kind of electrical function" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as

[0018] In addition, in this specification, the term "same potential" includes "approximately the same potential." The technical idea is to form a thin insulating film between conductive layers (first wiring and The object of the present invention is to make each of the first wiring (the first wiring and the second wiring) function as a wiring and to suppress parasitic capacitance. Therefore, a first potential (for example, VDD) is supplied to the first wiring, and a second potential (for example, VDD) is supplied to the second wiring. In comparison with the case where a second potential (e.g. GND) is supplied from a power line different from the first potential, This includes "approximately the same potential" such as a potential that can sufficiently reduce the parasitic capacitance (to one percent or less). In addition, for example, the difference in the degree of potential deviation caused by wiring resistance etc. is fully tolerated. The "in-phase" potential includes the "approximately in-phase" potential. Effect of the Invention

[0019] By using one embodiment of the present invention, a miniaturized semiconductor device can be provided. .

[0020] In addition, by using one embodiment of the present invention, a memory cell having a reduced area for a driver circuit can be provided. It is possible to provide a semiconductor device having the above structure. [Brief description of the drawings]

[0021] [Figure 1] 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device. [Diagram 2] FIG. 1 is a circuit diagram of a semiconductor device. [Diagram 3] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 4] FIG. [Diagram 5] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 6] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 7] FIG. [Figure 8] FIG. [Figure 9] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 10] FIG. [Figure 11] FIG. [Figure 12] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 13] FIG. [Figure 14] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 15] 1A and 1B are a cross-sectional view and a plan view of a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 18] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 19] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 20] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 21] Examples of electronic devices. [Figure 22] FIG. [Figure 23] 1A to 1C are cross-sectional views relating to a manufacturing process of a semiconductor device. [Figure 24] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Diagram 25] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 26] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 27] FIG. 13 is a graph for explaining the gate voltage dependence of mobility obtained by calculation. [Figure 28] FIG. 2 is a graph showing the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 29] FIG. 2 is a graph showing the gate voltage dependence of drain current and mobility obtained by calculation. [Diagram 30] FIG. 2 is a graph showing the gate voltage dependence of drain current and mobility obtained by calculation. [Diagram 31] 1A and 1B are diagrams illustrating cross-sectional structures of transistors used in calculation. [Diagram 32] 13A to 13C show characteristics of a transistor including an oxide semiconductor film. [Diagram 33] FIG. 13 shows Vg-Id characteristics of the transistor of Sample 1 after a BT test. [Diagram 34] FIG. 13 shows Vg-Id characteristics of the transistor of Sample 2 after a BT test. [Diagram 35] FIG. 2 shows XRD spectra of sample A and sample B. [Diagram 36] 13 is a graph showing the relationship between the off-state current of a transistor and the substrate temperature during measurement. [Figure 37] FIG. 1 shows the Vg dependence of Id and field-effect mobility. [Figure 38] 1A and 1B are graphs showing the relationship between the substrate temperature and the threshold voltage, and the relationship between the substrate temperature and the field effect mobility. [Figure 39] 1A and 1B are a top view and a cross-sectional view of a semiconductor device. [Diagram 40] 1A and 1B are a top view and a cross-sectional view of a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] An embodiment of the present invention will be described below with reference to the drawings. The present invention is not limited to the above description, and may be modified in various forms and without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the embodiment shown in the accompanying drawings.

[0023] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as in the actual embodiment, for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The present invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0024] In this specification, ordinal numbers such as "first," "second," and "third" are used to refer to the mixture of elements. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0025] (Embodiment 1) In this embodiment, a basic structure of a semiconductor device according to one embodiment of the disclosed invention will be described with reference to FIG. The description will be given with reference to the surface.

[0026] FIG. 1 illustrates a configuration of a semiconductor device according to one embodiment of the present invention. 1(A) and 1(B) are schematic diagrams showing the cross-sectional structure and the circuit configuration, respectively.

[0027] FIG. 1A shows a layer on a substrate 300 on which semiconductor elements such as transistors are formed (hereinafter, referred to as "element"). A first wiring 302, a first interlayer film 305, a second wiring 303, a second The structure of the semiconductor device having an interlayer film 306 and a third wiring 304 stacked thereon is shown. 301 is a semiconductor element that can be formed with not only transistors but also capacitors, resistors, and other semiconductor elements. In FIG. 1, the thickness of the first interlayer film 305 is greater than the thickness of the second interlayer film 306. The first wiring 302, the second wiring 303 and the third wiring 304 are Each of the first interlayer film 305 and the second interlayer film 306 is formed of a single layer or a multilayer conductive layer. Each of the second interlayer films 306 is formed of a single layer or a multilayer insulating layer.

[0028] FIG. 1B shows the circuit configuration and wiring arrangement of the circuit 100. 100 includes a wiring 303a arranged across the circuit 100 and a wiring 303b branching from the wiring 303a. The wiring 303a and the wiring 302a are overlapped with each other. The wiring 303a receives an input signal, and the wiring 303b receives an input signal. 3a, and is connected to the gate electrode of the transistor 101 through the wiring 302a that is electrically connected to the The wiring 303a is formed using the second wiring 303 in FIG. 2a is formed using the first wiring 302 in FIG.

[0029] In general, a semiconductor device having a cross-sectional structure as shown in FIG. 1A has the following problems: Since the first wiring 302 and the second wiring 303 are separated by the thin first interlayer film 305, Therefore, a large parasitic capacitance is generated in the area where the first wiring 302 and the second wiring 303 overlap each other. As a result, the signal provided to the first wiring 302 and the second wiring 303 This can cause delay times to increase, slowing down circuit operation or even causing it to stop working. In order to avoid this effect, only one of the first wiring 302 and the second wiring 303 is However, the number of available wires is reduced by one, resulting in a larger circuit area. There is a challenge to grow.

[0030] In contrast, in the configuration shown in FIG. 1B, the wiring 303a and the wiring 302a overlap each other. Although a large parasitic capacitance is formed in the region 102 arranged in such a manner, This is because the wiring 303a and the wiring 302a are conductors, and the influence on the delay time can be suppressed. Therefore, the two terminals on which the parasitic capacitance is formed are substantially at the same potential, and the charging This is because almost no discharge occurs.

[0031] As a result, the first interlayer film 305 in FIG. 1(A) separates the first interlayer film 305 from the first interlayer film 306. It is possible to configure a circuit using the area where the first wiring and the second wiring are arranged overlapping each other. This allows for a smaller circuit area than when only the first or second wiring is used. As a result, a small-sized semiconductor device can be realized.

[0032] By using the circuit configuration and wiring arrangement shown in FIG. 1B, the first No matter how thin the interlayer film 305 is, the first wiring 302 and the second wiring 303 Since the overlapping area can be used as part of the circuit, it is effective in reducing the circuit area. On the other hand, in the semiconductor device, the first interlayer film 305 acts as a dielectric material for the capacitance element or a transistor. When used as a gate insulating film for a transistor, the first interlayer film 305 has a thickness of 10 nm or more and 300 nm or less, preferably 10 nm or more and 100 nm or less, and more preferably 1 It is preferable that the thickness is 0 nm or more and 30 nm or less.

[0033] In the configuration shown in FIG. 1B, the thickness of the wiring 302a is larger than that of the wiring 303a. In such a case, the sheet resistance of the wiring 302a is The sheet resistance of the wiring 302a becomes larger than that of the wiring 303a, and the wiring 302a has a large wiring resistance. However, there is a concern that the long wiring that is arranged across the circuit 100 may cause a problem. By using the wiring 303a, the wiring 302a can be used only for short wiring. Therefore, the wiring resistance of the wiring 302a can be reduced. This makes it possible to suppress the effect of resistance on circuit operation.

[0034] On the other hand, in the manufacturing process of the semiconductor device, by making the film thickness of the wiring 302a thin, The step caused by the wiring 302a arranged in the lower layer is reduced, and the wiring 303a is prevented from being broken or This is preferable because it is possible to prevent a short circuit between the wiring 302a and the wiring 303a. The thickness of the wiring 302a is preferably 50 nm or more and 150 nm or less. By setting the value to a value as large as possible within a range where the influence of the wiring resistance of the wiring 302a on the circuit operation can be suppressed. The semiconductor device has a large sheet resistance and is free from steps caused by the wiring 302a during the manufacturing process. The impact can be reduced.

[0035] In FIG. 1B, the wiring 302a and the gate electrode of the transistor 101 in the circuit 100 Although the case where the and are electrically connected is shown as a representative example, the present embodiment is not limited to this. The wiring 302a may be connected to the gate electrodes of multiple transistors. The line 302a is connected to the source of the transistor, except when it is connected to the gate electrode of the transistor. The gate electrode may be connected to a gate electrode or a drain electrode, or may be connected to a semiconductor element such as a capacitance element or a resistance element. This may be continued.

[0036] As a semiconductor device different from the example shown in FIG. 1B, a semiconductor device having a circuit configuration and wiring arrangement shown in FIG. The semiconductor device having the above-mentioned positional relationship will be described. The cross-sectional structure of the semiconductor device is shown in FIG. ) is applied.

[0037] FIG. 2 shows a circuit configuration and wiring arrangement of the circuit 200. The wiring 303b and the wiring 302b are connected to the transistors 201 and 202. The wiring 303b has a region 203 where the wiring 303b overlaps with the circuit 200. A signal to be input to the transistor 201 is given to the transistor 202 and is electrically connected to the gate electrode of the transistor 201. A signal output from the circuit 200 is supplied to the wiring 302b, and the transistor 2 The wiring 30 is electrically connected to one of the source electrode and the drain electrode of the wiring 30. 3b is formed using the second wiring 303 in FIG. 1A, and the wiring 302b is formed using the first wiring 303 in FIG. It is formed using one wiring 302.

[0038] Moreover, signals of the same phase are applied to the wiring 303b and the wiring 302b. In digital signals, High and Low are signals that have the same phase. The ow (low) period is the same for all signals. The degree of agreement is determined by whether the rise or fall times of the signals are at least partially It is preferable that the rise and fall times overlap. In this case, the rise and fall times of each line are longer than when they are not overlapped. Since charging and discharging of the parasitic capacitance of the is suppressed, the signal delay time is reduced. .

[0039] As described above, a semiconductor device having a cross-sectional structure as shown in FIG. 1A is generally manufactured as follows. The first wiring 302 and the second wiring 303 are separated by the thin first interlayer film 305. Since the first wiring 302 and the second wiring 303 are separated by the As a result, a large parasitic capacitance is formed between the first wiring 302 and the second wiring 303. The delay time of the signal given to the input becomes large, and the circuit operation becomes slow or does not work at all. In order to avoid this effect, the first wiring 302 and the second wiring 3 It is possible to use only one of the 03, but this reduces the number of available wires by one. Therefore, there is a problem that the circuit area becomes large.

[0040] In contrast, in the configuration shown in FIG. 2, the wiring 303b and the wiring 302b are arranged to overlap each other. Although a large parasitic capacitance is formed in the region 203 where the This is because the wiring 303b and the wiring 302b have the same phase. Since a signal is applied, the potential difference between the two terminals where the parasitic capacitance is formed is kept small. This is because charging and discharging to the terminals is suppressed.

[0041] As a result, the wirings separated by a thin interlayer film (the first interlayer film 305 in FIG. 1(A)) are The area 203 where the line 302b and the wiring 303b are arranged overlapping is applied as a part of the circuit. This makes it possible to reduce the wiring distance compared to when only one of the wiring 302b and the wiring 303b is used. As a result, a small circuit area can be realized. It becomes Noh.

[0042] As shown in FIG. 1A, the first interlayer film 305 has a thickness smaller than that of the second interlayer film 306. The structure having the first wiring 302 and the second wiring 303 can be used in various semiconductor devices. The second wiring 303 is a part of a semiconductor element other than the semiconductor element formed in the element formation layer 301. Specifically, the first wiring 302 and the second wiring The wiring 303 may be used as an electrode of a capacitor. The thinner the thickness, the larger the capacitance value, so it is preferable that the first interlayer film 305 is thin. The first wiring 302 is used as a gate electrode of a transistor, and the second wiring 303 is used as a When used as a source electrode or a drain electrode of a transistor, the first interlayer film 305 Since the first wiring 3 is used as a gate insulating film, it may be formed thin. 02 is used as a source electrode or a drain electrode, and the second wiring 303 is used as a gate electrode. As the transistor, a transistor using amorphous silicon in the semiconductor active region may be used. and transistors using an oxide semiconductor in a semiconductor active region. Moreover, the first wiring 302 and the second wiring 303 are used as a part of a resistor element or a memory element. This may also be the case.

[0043] By using the circuit configuration and wiring arrangement shown in FIG. 2, the first interlayer film shown in FIG. No matter how thin the thickness of 305 is, the first wiring 302 and the second wiring 303 overlap each other. Since the overlapping area can be used as part of the circuit, it is effective in reducing the circuit area. On the other hand, in the semiconductor device, the first interlayer film 305 serves as a dielectric of a capacitance element or a transistor. When used as a gate insulating film for a photoresist, the first interlayer film 305 has a thickness of 10 nm. More preferably, the thickness is 10 nm or more and 300 nm or less, more preferably, the thickness is 10 nm or more and 100 nm or less, and even more preferably, the thickness is 10 nm or more and 300 nm or less. It is preferable that m is greater than or equal to 30 nm.

[0044] In FIG. 2, the wiring 303b and the gate electrode of the transistor 201 are electrically connected to each other in the circuit 200. The wiring 302b and the source electrode or drain electrode of the transistor 202 are electrically connected to each other. Although the case where one side is electrically connected to the other side has been shown as a representative example, this embodiment is not limited to this. The wiring 303b is connected to one of the source electrode or the drain electrode of the transistor. The wiring 302b may be connected to a gate electrode of a transistor. In addition, the wiring 302b and the wiring 303b are connected to gate electrodes or sources of a plurality of transistors. The gate electrode may be connected to a drain electrode, or may be connected to a capacitance means, a resistance means, a semiconductor means such as a diode, etc. It may be connected to a conductive element.

[0045] In this embodiment, the wiring 303b is formed using the second wiring 303 in FIG. The wiring 302b is formed using the first wiring 302 in FIG. The line 302b is formed using the second wiring 303 in FIG. 1(A), and the wiring 303b is formed using the second wiring 303 in FIG. ) may be used as the first wiring 302.

[0046] In FIG. 2, a signal to be input to the circuit 200 is supplied to the wiring 303b. However, the present embodiment is not limited to this. In FIG. 2, the wiring 302b may be provided with a In the embodiment, a signal is applied to the wiring 302b. However, the present embodiment is not limited to this. One of the internal signals of the circuit 200 may be provided.

[0047] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0048] (Embodiment 2) In this embodiment mode, the circuit configuration shown in Embodiment Mode 1 is applied to a driver circuit of a semiconductor device. In this embodiment, a semiconductor device will be described with reference to the drawings. Here is an example of application.

[0049] <Memory cell configuration and operation> First, the configuration and operation of the memory cell 502 included in the memory device will be described. A circuit diagram of the cell 502 is shown in FIG. 3. The memory cell 502 shown in FIG. The second transistor 1201, the second transistor 1202, and the capacitor element 1203. The gate electrode of the second transistor 1202 is electrically connected to the second signal line S2. Either the source electrode or the drain electrode of the transistor 1202 is electrically connected to the first signal line S1. The other of the source electrode and the drain electrode of the second transistor 1202 is The gate electrode of the first transistor 1201 and one electrode of the capacitor 1203 are connected to each other. The source electrode of the first transistor 1201 is electrically connected to the source line (SL). The drain electrode of the first transistor 1201 is electrically connected to the bit line (BL). The other electrode of the capacitor 1203 is electrically connected to the word line (WL). .

[0050] Here, the second transistor 1202 is preferably a transistor including an oxide semiconductor. Since the off-state current of a transistor using an oxide semiconductor is extremely small, By applying a resistor to a memory cell, it is possible to retain stored information for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation can be performed in a short time. Since it is possible to extremely reduce the frequency of the above-mentioned problems, it is possible to realize a semiconductor device including a memory cell. The power consumption of the device can be sufficiently reduced. It is possible to retain stored contents for a long period of time. As the transistor 1, a transistor using a semiconductor material other than an oxide semiconductor is used. Examples of the semiconductor material used for the first transistor include silicon, germanium, and silicon. Silicon germanium, silicon carbide, or gallium arsenide can be used, and single crystal It is preferable to use a semiconductor. The first transistor using such a semiconductor material is sufficiently Since it is capable of high-speed operation, it is possible to read out stored information at high speed. .

[0051] A schematic diagram showing a cross section of memory cell 502 is shown in FIG. 4. As shown in FIG. 2 is a first transistor 1301 and at least a part of the first transistor 1301 and a second transistor 1302 overlapping the second transistor 1301. 02 is formed above the first transistor 1301, The gate electrode and one of the source electrode and the drain electrode of the second transistor 1302 are electrically connected to The first transistor 1301 in FIG. 4 is connected to the first transistor 120 in FIG. First, the second transistor 1302 in FIG. 4 corresponds to the second transistor 1202 in FIG. do.

[0052] In the semiconductor device shown in FIG. 3, the potential of the gate electrode of the first transistor 1201 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: It is.

[0053] First, the writing and holding of information will be described. The potential is set to a potential at which the second transistor 1202 is turned on, 202 is turned on. This causes the potential of the first signal line (S1) to The voltage is applied to the gate electrode of the first transistor 1201 and the capacitance element 1203. A predetermined potential is applied to the gate electrode of the transistor 1201 and the capacitance element 1203 (see FIG. Here, we will use two different charges that give different potentials (hereinafter, the charge that gives the lower potential is called the charge QL, the charge that gives the high potential is called charge QH) is given through S1. It is also possible to apply charges with three or more different potentials to increase the memory capacity. It is okay to raise it.

[0054] After that, the potential of the second signal line (S2) is changed so that the second transistor 1202 is turned off. By applying a potential to the second transistor 1202 to turn it off, the first transistor The charge applied to the gate electrode of the second transistor 1201 is held (retained). Since the off-current of the transistor 1202 is extremely small, the gate electrode of the first transistor 1201 The potential will be maintained for a long period of time.

[0055] Next, the reading of information will be described. A predetermined potential (constant potential) is applied to the source line (SL). When an appropriate potential (read potential) is applied to the word line (WL) while the first transistor Depending on the amount of charge held in the gate electrode of the transistor 1201, the bit line (BL) will have different voltages. In general, if the first transistor 1201 is an N-channel type, The apparent threshold voltage Vth when QH is applied to the gate electrode of transistor 1201 -H is the apparent current when QL is applied to the gate electrode of the first transistor 1201. This is because the apparent threshold voltage Vth-L is lower than the threshold voltage Vth-L of the The word line (WL) voltage required to turn the first transistor 1201 “on” is This refers to pressure.

[0056] Therefore, the potential of the word line (WL) is set to a potential VO between Vth-H and Vth-L. This makes it possible to determine the charge applied to the gate electrode of the first transistor 1201 . For example, when QH is given in a write operation, the potential of the word line (WL) is set to V When Vth-H is set to 0, VO is higher than Vth-H, so the first transistor 1201 is in the ON state. On the other hand, when QL is given in a write operation, the potential of the word line (WL) If V is VO, then V is lower than Vth-L, so the first transistor 1201 is in the off state. Therefore, by determining the potential of the bit line (BL), The information can be read out.

[0057] When memory cells are arranged in an array, only the information of a desired memory cell is read. In this way, it is necessary to read the information of a specific memory cell and When the information of the memory cells other than the target memory cell is not read, the word of the memory cell that is not the target memory cell is erased. The first transistor 1201 is turned on regardless of the state of the gate electrode with respect to the gate line (WL). Specifically, the state of the gate electrode is To turn on the first transistor 1201 regardless of the state of the word line (WL), If a potential higher than th-L is applied, the first transistor To turn off the transistor 1201, a voltage smaller than Vth-H is applied to the word line (WL). That's good.

[0058] A first transistor 1201 is connected to the word line (WL) of a memory cell that is not the object of reading. A potential is applied so that the first transistor 1201 is turned on or the first transistor 1202 is turned off. The application of such a potential depends on the connection relationship of the memory cells 502 (for example, the memory cells are connected in series). The number of terminals can be determined appropriately depending on the number of terminals (e.g., whether the terminals are connected in series or in parallel).

[0059] Next, the rewriting of information will be described. The rewriting of information includes the above-mentioned writing of information and That is, the potential of the second signal line (S2) is set to the potential of the second transistor (S3). The second transistor 1202 is turned on by applying a potential to the first transistor 1202. As a result, the potential of the wiring of the first signal line (S1) (potential related to new information) becomes The voltage Vcc is applied to the gate electrode of the transistor 1201 and the capacitor element 1203. The potential of the second signal line (S2) is set to a potential at which the second transistor 1202 is turned off. By turning off the second transistor 1202, the first transistor 12 The gate electrode of 01 is in a state where a charge related to new information is held.

[0060] In this way, the semiconductor device according to the disclosed invention can directly read data by rewriting the data. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need to extract charge from the floating gate using high voltages, and the erase operation In other words, it is possible to suppress the decrease in the operating speed caused by the above-mentioned problem. In this case, the problem pointed out in the conventional floating gate type transistor is There is no problem of deterioration of the gate insulating film (tunnel insulating film) that is used in conventional The problem was the deterioration of the gate insulating film when electrons were injected into the floating gate. This is because there is no theoretical limit to the number of times data can be written. This means:

[0061] The source electrode or drain electrode of the second transistor 1202 is the same as that of the first transistor 1202. By electrically connecting the gate electrode of the transistor 1201, the transistor is used as a non-volatile memory element. The floating gate of the floating gate type transistor can be used For this reason, in the figure, the source electrode or drain electrode of the second transistor 1202 is A portion to which the gate electrode of the first transistor 1201 is electrically connected is called a node C. When the second transistor 1202 is off, the node C can be considered to be buried in an insulator. Thus, charge is stored in the node C. The off-state current of 02 is less than 1 / 100,000 of that of transistors made of silicon semiconductors, etc. Therefore, the charge stored at node C due to the leakage current of the second transistor 1202 is That is, the second transistor 1202 can dissipate the power. It is possible to realize a non-volatile memory device that can retain information even without power supply. It is Noh.

[0062] For example, when the off-state current of the second transistor 1202 at room temperature (25° C.) is 10 zA (1 zA (Zeptoampere) is 1 x 10 -21 A) or less, and the capacitance value of the capacitance element 1203 is 10 If the temperature is around fF, it should be at least 10 4 It is possible to hold data for more than 10 seconds. Needless to say, the retention time varies depending on the transistor characteristics and capacitance value.

[0063] <Configuration of Semiconductor Device> An example of a circuit diagram of a semiconductor device is shown in FIG. 5. The circuit shown in FIG. 5 includes the above-mentioned memory cell 502, The driving circuit shown in FIG. 00, a row driver 501, and a memory cell 502. A plurality of recells 502 are arranged in an array.

[0064] The row driver 501 includes a NAND gate unit 504, a first level shifter 505, a first buffer 506, a second NAND gate 507, a second level shifter 508, a second buffer The NAND gate section 504 includes a first NAND gate 503.

[0065] <Drive circuit configuration and operation> The operation of the driving circuit shown in FIG. The output line of the row decoder 500 is connected to the first NAND gate. One of the inputs of the first NAND gate 503 and one of the inputs of the second NAND gate 507 are electrically connected to On the other hand, the other input of the first NAND gate 503 is connected to the write enable WE is electrically connected to the input of the second NAND gate 507. The read enable signal line (RE) is electrically connected to the write enable signal line. In the case of a logic-only operation, i.e., when WE is active, the output of the first NAND gate 503 is When RE is active, the second NA The output of the ND gate 507 becomes active.

[0066] The output of the first NAND gate 503 is input to a first level shifter 505, which outputs a second NAND The output of the ND gate 507 is input to a second level shifter 508. A write voltage (VW) is applied to the power supply line of the second level shifter 505, and The read voltage (VR) is applied as the power supply line. When the output of the first level shifter 503 is active, the row decoder 5 The output of 00 is amplified to the write voltage, and the output of the second NAND gate 507 is active. If so, the first level shifter 508 amplifies the signal to a read voltage. The output of the lid 505 passes through a first buffer 506 and is sent to the memory cell as a second signal line (S2). 502, and the output of the second level shifter 508 passes through a second buffer 509 and The data is input to the memory cell 502 as a bit line (WL). The line (BL) and the first signal line (S1) are connected.

[0067] As shown in FIG. 3, the memory cell 502 includes a first transistor 1201 and a and a second transistor 1202 overlapping the transistor 1201. 4, the layer 1300 including the first transistor 1301 in FIG. This corresponds to the element formation layer 301. In this embodiment, the second transistor 120 The wiring for the driving circuit part, which is fabricated in the same process as the source electrode or drain electrode of 2, is shown in Figure 1( A) corresponds to the first wiring 302, and the gate insulating film of the second transistor 1202 The interlayer film formed in the same process corresponds to the first interlayer film 305 in FIG. The wiring of the driver circuit part, which is manufactured in the same process as the gate electrode of the transistor 1202 in FIG. This corresponds to the second wiring 303 in (A). In this case, the configuration of the first embodiment is applied. As a result, in the driver circuit portion, the second transistor 1202 included in the memory cell 502 The wiring is fabricated in the same process as the source electrode or drain electrode of the transistor, and the gate of the transistor is The electrodes and wiring, which are fabricated in the same process, can be used together as part of the circuit. Therefore, the area of ​​the drive circuit portion can be reduced.

[0068] More specifically, a NAND gate unit 504, a first level shifter 505, a second level shifter The circuit configuration described in the first embodiment is applied to the lid 508. 504 includes the circuit configuration shown in FIG. 1B, a first level shifter 505 and a second level The circuit configuration shown in FIG. 2 is applied to the shifter 508.

[0069] First, the application of the circuit configuration shown in FIG. 1B to the NAND gate unit 504 will be described with reference to the drawings. 6 is a circuit diagram of the NAND gate unit 504.

[0070] The circuit shown in FIG. 6 includes N-type transistors 601 and 602, P-type transistors 603 and 604, It has a signal line 605 and a signal line 606 .

[0071] Signal line 605 is connected to a plurality of NAND gates (NAND gate 503 and NAND gate Signal line 606 is a common signal line that drives the output terminal 507. The gate electrode of the N-type transistor 601 and the gate of the P-type transistor 603 are connected to each other. It is electrically connected to the electrode.

[0072] 6, a signal line 606 corresponds to the first wiring 302 shown in FIG. 1, and a signal line 605 corresponds to the first wiring 302 shown in FIG. More specifically, the signal line 606 is connected to the memory cell 5 The same process as the source electrode or drain electrode of the second transistor 1202 included in 02 The signal line 605 is fabricated in the same process as the gate electrode of the transistor. Therefore, the gate insulation of the second transistor 1202 included in the memory cell 502 The film and the interlayer film between the signal line 606 and the signal line 605 are fabricated in the same process. It is possible to make the thickness of the interlayer film thinner. The thickness of the interlayer film is 10 nm to 300 nm. , preferably 10 nm or more and 100 nm or less, and more preferably 10 nm or more and 30 nm or less. It can be said that:

[0073] In FIG. 6, the signal line 606 and the signal line 605 have an overlapping region 607. A large parasitic capacitance is formed in a region 607 where the signal lines 605 and 606 overlap. Even though the delay time is increased, the effect on the signal delay time can be suppressed. Since the signal line 605 and the signal line 606 are electrically connected, the two terminals where the parasitic capacitance is formed are This is because the two terminals are substantially at the same potential, and charging and discharging to and from the two terminals hardly occurs.

[0074] The signal line 605 is connected to a source electrode or a drain electrode of the second transistor 1202. The signal line 606 is fabricated in the same process as the gate electrode of the transistor. It is also possible to form wiring in the same process as the source electrode or drain electrode. A wiring film with a thickness of 100 nm to 150 nm, which is produced in the same process as the gate electrode. The reason for making the wiring thinner compared to the thickness is to prevent disconnection due to a step in the lower wiring (first wiring). This is preferable because it can be prevented.

[0075] FIG. 7 is a diagram showing a part of a cross section of the NAND gate unit 504. The cross section shown in FIG. The signal line 700 includes a NAND gate 702 and a signal line 704. The NAND gate 702 is a transistor. In FIG. 7, the transistors 703a and 703b are The first transistor 1201 included in the memory cell 502 is manufactured in the same process. 6. Also, the signal line 704 in FIG. 7 corresponds to the signal line 606 in FIG. 6. In FIG. 7, the signal line 700 corresponds to the signal line 605. 6. A region 705 where the signal line 704 overlaps with the signal line 705 corresponds to the region 607 in FIG.

[0076] In FIG. 7, signal line 700 is electrically connected to signal line 704, which is a NAN. The gate electrode of the transistor 703a in the D gate 702 and the gate The gate electrode is electrically connected to the gate electrode.

[0077] 8 is a top view of the NAND gate unit 504 shown in FIGS. The dashed line A-A' in FIG. 8 corresponds to the A-A' in the cross-sectional view shown in FIG.

[0078] The NAND gate 802 shown in FIG. 8 corresponds to the NAND gate 702 shown in FIG. 7. Signal line 800 corresponds to signal line 700 shown in FIG. 7, and signal line 804 corresponds to signal line 704 shown in FIG. 7. Accordingly, an area 805 where the signal line 800 and the signal line 804 overlap corresponds to the area 705 shown in FIG. The transistor 803a in the NAND gate 802 is the transistor 70 shown in FIG. 3a, and transistor 803b corresponds to transistor 703b shown in FIG.

[0079] The transistor 703a constituting the NAND gate 702 is the N-type transistor 601 shown in FIG. 6. The signal line 700 is The signal line 704 is in the same wiring layer as the gate electrode of the second transistor 1302 in FIG. The source electrode or drain electrode of the second transistor 1302 in FIG. Therefore, it is preferable that the thickness of the signal line 700 is 200 nm or more. The thickness of the film is preferably 100 nm or more and 150 nm or less.

[0080] In the region 705, the signal line 700 and the signal line 704 are laminated with an interlayer film 706 interposed therebetween. The thickness of the interlayer film 706 is 10 nm or more and 300 nm or less, preferably 10 nm or less. The thickness of the interlayer film 706 is set to 100 nm or more, and more preferably 10 nm or more and 30 nm or less. 4 , the source electrode or drain electrode of the second transistor 1302 and the gate electrode This film is formed in the same process as the film that separates the semiconductor device and the gate insulating film.

[0081] The signal line 700 and the signal line 704 are only separated by the thin interlayer film 706 as described above. However, by applying the circuit configuration shown in FIG. 6, the signal line 700 and the signal line 704 can be connected to the same Since signals are input, even if the thickness of the interlayer insulating film between the two is thin, the signals will not be affected by each other. Therefore, there is no overlapping region 705 between the signal line 700 and the signal line 704. Even in this case, the signal lines 700 and 704 can function as wiring. do.

[0082] Next, the first level shifter 505 and the second level shifter 506 in the semiconductor device of FIG. An example of applying the circuit configuration shown in FIG. 2 to 508 will be described with reference to FIG. 9. 2 is a circuit diagram of a first level shifter 505 and a second level shifter 508. FIG.

[0083] The level shifter shown in FIG. 9 includes N-type transistors 901 and 902, and a P-type transistor 903. , 904, 905, 906.

[0084] In the level shifter shown in FIG. 9, the potential of the input signal line and the inverted signal input line is the power supply potential when the line is high. When the signal is low, it is at ground potential. When the signal is high, the potential of the output signal line and the inverted signal output line is When the first level shifter 505 is turned on, the high potential power supply VDDH is turned on, and when the second level shifter 505 is turned on, the ground potential is turned on. In the case of the first level shifter 508, VW is used as the high potential power supply, and in the case of the second level shifter 508, VR is used as the high potential power supply. Applies.

[0085] In FIG. 9, one of the input signal line 910 and the output signal line 912 is connected to the The first wiring 302 is the first wiring 302, and the other is the second wiring 303 shown in FIG. Specifically, one of the input signal line 910 or the output signal line 912 is connected to a The source electrode or drain electrode of the second transistor 1202 is formed in the same process as that of the second transistor 1202. The other is to be fabricated in the same process as the gate electrode of the transistor.

[0086] 9, either the inverted signal input line 911 or the inverted signal output line 913 may be connected to 1(A) as the first wiring 302, and the other as the second wiring 303 shown in FIG. More specifically, the inverted signal input line 911 or the inverted signal output line 913 may be One of the electrodes is connected to the source electrode or drain electrode of the second transistor 1202 included in the memory cell 502. The other electrode is fabricated in the same process as the gate electrode of the transistor. This shall be the case.

[0087] This allows the interlayer film between the input signal line 910 and the output signal line 912, or the inverted signal input The interlayer film between the force line 911 and the inverted signal output line 913, or both of them, are Since the gate insulating film of the second transistor 1202 included in The thickness of the interlayer film can be reduced. or less, preferably 10 nm to 100 nm, and more preferably 10 nm to 30 nm It can be as follows:

[0088] The input signal line 910 is a wiring for inputting the input signal IN, and the inverted signal input line 911 is a wiring for inputting an inverted signal INB of the input signal. The inverted signal output line 913 is a wiring that outputs the inverted signal OUT This is the wiring that outputs B.

[0089] The second transistor 1302 included in the memory cell 502 is a top-gate transistor. In the case of using the second transistor 130 as the first transistor, the first wiring 302 shown in FIG. The second wiring 303 is a wiring formed in the same process as the source electrode or drain electrode of It is preferable that the gate electrode of the second transistor 1302 is formed in the same process as the gate electrode of the second transistor 1302. In the second transistor 1302, the source electrode or the drain electrode is Since the first wiring has a thickness thinner than that of the electrode, the first wiring becomes stepped, which can cause the second wiring to break. This is because the first wiring (the source of the second transistor 1302) can be prevented from The thickness of the source electrode or drain electrode is preferably 100 nm or more and 150 nm or less. stomach.

[0090] Note that Figure 9 shows a level shifter that converts a high signal from the power supply potential to a high potential power supply. However, the same applies to level shifters that convert low signals from ground potential to a low-potential power supply. Applicability is possible.

[0091] FIG. 10 is a diagram showing a part of a cross section of the level shifter shown in FIG. 10, the transistor 1000, the wiring 1001, and the wiring 1002. The transistor 1000 is fabricated in the same process as the first transistor 1201 included in the memory cell 502. The level shifter shown in FIG. 10 is fabricated by overlapping wiring 1001 and wiring 1002. The wiring 1001 is connected to the source of the transistor 1000. The source electrode or the drain electrode is electrically connected to the wiring 10. 02 is electrically connected to the gate electrode of a transistor different from the transistor 1000. .

[0092] Transistor 1000 shown in FIG. 10 corresponds to the transistor in inverter 900 of FIG. 9. The wiring 1001 corresponds to the inverted signal input line 911 in FIG. 9, and the wiring 1002 corresponds to the inverted signal input line 911 in FIG. 9. The wiring 1001 corresponds to the signal output line 913 of FIG. 9. The wiring 1002 corresponds to the output signal line 912 in FIG.

[0093] 11 is a top view of the level shifter shown in FIGS. The dashed line B-B' corresponds to the line B-B' in the cross-sectional view shown in FIG.

[0094] The transistor 1100 shown in FIG. 11 corresponds to the transistor 1000 shown in FIG. The line 1101 corresponds to the wiring 1001 shown in FIG. 10, and the wiring 1102 corresponds to the wiring 1001 shown in FIG. 02, and the area 1103 where the wiring 1101 and the wiring 1102 overlap is the area shown in FIG. Corresponds to 1003.

[0095] In FIG. 10, the wiring 1001 is the same as the gate electrode of the second transistor 1302 in FIG. The wiring 1002 is a wiring formed in the process of FIG. The wiring is fabricated in the same process as the source electrode or drain electrode. The thickness of the wiring 1002 is preferably 100 nm or more. It is preferable that the thickness is 150 nm or less.

[0096] In the region 1003, the wiring 1001 and the wiring 1002 are arranged in a laminated manner with an interlayer film 1006 interposed therebetween. The thickness of the interlayer film 1006 is 10 nm or more and 300 nm or less, and preferably 1 The thickness is preferably 0 nm or more and 100 nm or less, and more preferably 10 nm or more and 30 nm or less. 1006 is a source electrode or drain electrode of the second transistor 1302 in FIG. This film is formed in the same process as the film that separates the gate electrodes (that is, the gate insulating film).

[0097] In the level shifter to which the circuit configuration of FIG. 2 is applied, the wiring 1001 and the wiring 1002 are as described above. Although they are only separated by a thin interlayer film, the wiring 1001 and the wiring 1002 have the same phase signal. Since the signal is input, the effect of parasitic capacitance can be suppressed even if the film thickness between the two layers is thin. Therefore, as shown in the area 1003, the wiring 1001 and the wiring 1002 overlap each other. Even if the wiring 1001 and the wiring 1002 have a region 1003, This can be used to make it function.

[0098] In addition, the first level shifter 505 and the second level shifter 506 in the semiconductor device of FIG. The example of applying the circuit configuration shown in FIG. 2 to 508 is not limited to the configurations shown in FIGS. For example, a level shifter having a configuration as shown in FIG. 12 and FIG. 13 may be used. FIG. 12 is a circuit diagram of the first level shifter 505 and the second level shifter 508. FIG. 13 is a diagram showing a part of a cross section of the level shifter shown in FIG.

[0099] The level shifter shown in FIG. 12 includes an inverter 1400, N-type transistors 1401 and 140 2, P-type transistors 1403, 1404, 1405, and 1406. Inverter 1 400 includes an N-type transistor 1407 and a P-type transistor 1408 .

[0100] The level shifter shown in Figure 12 has a power supply voltage when the potential of the input signal line and the inverted signal input line are high. When the signal is high, the output signal line and the inverted signal output line are at ground potential. When the level is high, it becomes the high potential power supply VDDH, and when it is low, it becomes the ground potential. In the case of 505, VW is used as the high potential power supply, and in the case of the second level shifter 508, VR is applied as the above.

[0101] In FIG. 12, one of the input signal line 1410 and the output signal line 1412 is connected to the The first wiring 302 shown in FIG. 1A is a first wiring 302, and the other is a second wiring 303 shown in FIG. In brief, one of the input signal line 1410 or the output signal line 1412 is connected to the memory cell 5 The same process as the source electrode or drain electrode of the second transistor 1202 included in 02 and the other is fabricated in the same process as the gate electrode of the transistor.

[0102] 12, either the inverted signal input line 1411 or the inverted signal output line 1413 The first wiring 302 shown in FIG. 1A is the first wiring 302, and the other is the second wiring 303 shown in FIG. More specifically, the inverted signal input line 1411 or the inverted signal output line One of the terminals 1413 is connected to the source voltage of the second transistor 1202 included in the memory cell 502. The other electrode is fabricated in the same process as the gate electrode of the transistor. It will be produced in the process.

[0103] This allows the interlayer film between the input signal line 1410 and the output signal line 1412, or the inverted signal line The interlayer film between the signal input line 1411 and the inverted signal output line 1413, or both of them, The gate insulating film of the second transistor 1202 included in the rechargeable cell 502 is fabricated in the same process. Therefore, it is possible to make the thickness of the interlayer thin. 00 nm or less, preferably 10 nm to 100 nm, and more preferably 10 nm or more It can be 30 nm or less.

[0104] The input signal line 1410 is a wiring for inputting the input signal IN, and the inverted signal input line 14 11 is a wiring for inputting an inverted signal INB of the input signal. Also, the output signal line 1412 is 14 is a wiring for outputting the output signal OUT, and the inverted signal output line 1413 is a wiring for outputting the inverted signal of the output signal OUT. This is the wiring that outputs the signal OUTB.

[0105] The second transistor 1302 included in the memory cell 502 is a top-gate transistor. In the case of using a second transistor 1302 as a second transistor, the first wiring 302 shown in FIG. The second wiring 303 is a wiring that is fabricated in the same process as the source electrode or the drain electrode. It is preferable that the gate electrode of the transistor 1302 be formed in the same process as the gate electrode of the transistor 1302 . In the second transistor 1302, the source electrode or the drain electrode is closer to the gate electrode than the Since the first wiring has a smaller thickness than the second wiring, it prevents the second wiring from being broken due to a step in the first wiring. This is because the first wiring (the source electrode of the second transistor 1302) The thickness of the gate electrode (or drain electrode) is preferably 100 nm or more and 150 nm or less.

[0106] In addition, in Figure 12, a level shifter that converts a high signal from the power supply potential to a high potential power supply is used. The same is true for level shifters that convert low signals from ground potential to a low-potential power supply. It is possible to apply

[0107] 13 is a diagram showing a part of a cross section of the level shifter shown in FIG. 13 includes a transistor 1500, a wiring 1501, and a wiring 1502. The transistor 1500 is made of the same process as the second transistor 1202 included in the memory cell 502. The level shifter shown in FIG. The wiring 1501 is connected to the transistor 1500 via a region 1503 that overlaps the transistor 1500. The source electrode or the drain electrode is electrically connected to the wiring 1, which is not shown in the figure. 502 is electrically connected to the gate electrode of a transistor different from the transistor 1500. do.

[0108] The transistor 1500 shown in FIG. 13 is an N-type transistor in the inverter 1400 of FIG. 12. Wiring 1501 corresponds to the inverted signal input line 1411 in FIG. 502 corresponds to the inverted signal output line 1413 in FIG. 12. The wiring 1502 corresponds to the input signal line 1410 in FIG. .

[0109] In FIG. 13, the wiring 1501 is the same as the gate electrode of the second transistor 1302 in FIG. The wiring 1502 is a wiring formed in the process of FIG. The wiring is fabricated in the same process as the source electrode or drain electrode. The thickness of the wiring 1502 is preferably 100 nm or more. It is preferable that the thickness is 150 nm or less.

[0110] In the region 1503, a wiring 1501 and a wiring 1502 are laminated with an interlayer film 1506 interposed therebetween. The thickness of the interlayer film 1506 is 10 nm or more and 300 nm or less, and preferably 1 The thickness is preferably 0 nm or more and 100 nm or less, and more preferably 10 nm or more and 30 nm or less. 1506 is a source electrode or drain electrode of the second transistor 1302 in FIG. This film is formed in the same process as the film that separates the gate electrodes (that is, the gate insulating film).

[0111] In the level shifter to which the circuit configuration of FIG. 2 is applied, the wiring 1501 and the wiring 1502 are as described above. Although they are only separated by a thin interlayer film, the wiring 1501 and the wiring 1502 have the same phase signal. Since the signal is input, the effect of parasitic capacitance can be suppressed even if the film thickness between the two layers is thin. Therefore, as shown in the area 1503, the wiring 1501 and the wiring 1502 overlap each other. Even if the wiring 1501 and the wiring 1502 have a region 1503, This can be used to make it function.

[0112] Next, a circuit having a buffer that can be used in the semiconductor device shown in FIG. An example of applying the configuration shown in FIG. 1(A) will be described with reference to FIG. 14. FIG. 14 shows a semiconductor A common signal line that is input to multiple circuits in the device, and wiring within the circuit that branches off from the signal line 1 is a diagram showing one embodiment of a circuit having a signal line used as a filter.

[0113] The circuit 1601 shown in FIG. 14 includes a buffer 1602 and a circuit 1603. The input electrode of the signal line 1600 is electrically connected to the signal line 1604. The signal line 1600 includes a circuit 1601. The signal line is a common signal line for driving a plurality of circuits including the signal line 1602 and is electrically connected to the signal line 1604. The signal line 1605 is electrically connected to the output terminal of the buffer 1602 and the input terminal of the circuit 1603. To be continued.

[0114] In FIG. 14, the signal line 1604 corresponds to the first wiring 302 shown in FIG. The signal line 1604 corresponds to the second wiring 303 shown in FIG. A source electrode or a drain electrode of a second transistor 1202 included in the memory cell 502 The signal line 1600 is fabricated in the same process as the gate electrode of the transistor. Similarly, the signal line 1605 is assumed to be the first wiring 302 shown in FIG. can be done.

[0115] As a result, the gate insulating film of the second transistor 1202 included in the memory cell 502 , the interlayer film between the signal line 1600 and the signal line 1604, and the signal line 1600 and the signal line 1 Since the interlayer films between 605 and 606 are fabricated in the same process, the thickness of these interlayer films can be reduced. The thickness of the interlayer film is 10 nm or more and 300 nm or less, preferably 10 nm or more. It can be 100 nm or less, and more preferably 10 nm or more and 30 nm or less.

[0116] The second transistor 1202 included in the memory cell 502 is a top-gate transistor. In the case of using a second transistor 1302 as a second transistor, the first wiring 302 shown in FIG. The second wiring 303 is a wiring that is fabricated in the same process as the source electrode or the drain electrode. It is preferable that the gate electrode of the transistor 1302 be formed in the same process as the gate electrode of the transistor 1302 . In the second transistor 1302, the source electrode or the drain electrode is closer to the gate electrode than the Since the first wiring has a smaller thickness than the second wiring, it prevents the second wiring from being broken due to a step in the first wiring. This is because the first wiring (the source electrode of the second transistor 1302) The thickness of the gate electrode (or drain electrode) is preferably 100 nm or more and 150 nm or less.

[0117] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0118] (Embodiment 3) In this embodiment, a structure of a semiconductor device and a manufacturing method thereof according to one embodiment of the disclosed invention will be described. This will be described with reference to Figures 15 to 20. Specifically, The structure of the cell and the method for fabricating it will be described.

[0119] <Cross-sectional and planar configurations of semiconductor device> FIG. 15 shows an example of the configuration of a semiconductor device. FIG. 15(A) shows a cross section of the semiconductor device. 15(B) shows a plan view of the semiconductor device. This corresponds to the cross sections taken along lines A1-A2 and B1-B2 in FIG. 15(A) and FIG. 1(B). The semiconductor device shown in FIG. 5(B) has a transistor 160 using a first semiconductor material in the lower part. The first semiconductor material is a MOS transistor 162, and the second semiconductor material is a MOS transistor 162. It is preferable that the first semiconductor material and the second semiconductor material are different materials. The first semiconductor material is a semiconductor material other than an oxide semiconductor, and the second semiconductor material is an oxide semiconductor. Examples of semiconductor materials other than oxide semiconductors include silicon, germanium, Silicon germanium, silicon carbide, or gallium arsenide can be used. It is preferable to use a crystalline semiconductor. Alternatively, an organic semiconductor material may be used. On the other hand, transistors using oxide semiconductors can operate at high speed. The transistors used have the characteristic of being able to hold charge for a long time. The semiconductor device may be used as a memory cell.

[0120] The technical essence of the disclosed invention is that it uses an off-type semiconductor such as an oxide semiconductor to hold information. The advantage of using a semiconductor material for transistor 162 that can sufficiently reduce the current is that The specific configuration of the semiconductor device, such as the materials used in the semiconductor device and the structure of the semiconductor device, is also described. It is not necessary to be limited to what is shown here.

[0121] The transistor 160 in FIG. 15 is a transistor provided in a semiconductor layer on a semiconductor substrate 400. A channel forming region 134 and impurity regions 1 provided to sandwich the channel forming region 134 32 (also referred to as a source region and a drain region) and a channel forming region 134. A gate insulating film 122a is formed on the gate insulating film 122a, and a channel forming region 134 is formed on the gate insulating film 122a. and a gate electrode 128a arranged to contact the gate electrode 128a. There are cases where the source electrode and the drain electrode are not provided, but for convenience, this is also referred to as the transistor. In this case, in order to explain the connection relationship of the transistor, In addition, the source region and drain region are sometimes referred to as the source electrode and drain electrode. That is, in this specification, the term "source electrode" may include the source region. The term "drain electrode" may include the drain region.

[0122] In addition, the conductive layer 12 is formed in the impurity region 126 provided in the semiconductor layer on the semiconductor substrate 400. Here, the conductive layer 128b is connected to the source electrode of the transistor 160 and It also functions as a drain electrode. An insulating layer 1 is formed on the transistor 160 so as to cover the transistor 160. 36, insulating layer 138, and insulating layer 140 are provided. To achieve this, the transistor 160 has a structure without a sidewall insulating layer as shown in FIG. On the other hand, when the characteristics of the transistor 160 are important, A sidewall insulating layer is provided on the side surface of the electrode 128a, and an impurity having a region with a different impurity concentration is formed. A pure region 132 may also be provided.

[0123] The transistor 162 in FIG. 15 is an oxide semiconductor provided on the insulating layer 140 etc. The oxide semiconductor layer 144 and a source electrode (or a drain electrode) electrically connected to the oxide semiconductor layer 144. a drain electrode (or source electrode) 142a, and a drain electrode (or source electrode) 142b, and an oxide semiconductor a gate insulating film 146 covering the layer 144, the source electrode 142a and the drain electrode 142b; A gate electrode is provided on the gate insulating film 146 so as to overlap with the oxide semiconductor layer 144. 148a.

[0124] Here, impurities such as hydrogen are sufficiently removed from the oxide semiconductor layer 144. It is preferable that the oxygen supply is sufficient to make the oxygen highly purified. Specifically, the hydrogen concentration in the oxide semiconductor layer 144 is, for example, 5×10 19 atoms / cm 3 Less than 5×10 18 atoms / cm 3 Less than or equal to 5×10 17 a toms / cm 3Note that the hydrogen concentration in the oxide semiconductor layer 144 is determined as follows. Secondary Ion Mass Spectrometry (SIMS) In this way, the hydrogen concentration is sufficiently reduced and high purity The defect level in the energy gap caused by oxygen deficiency is eliminated by the supply of sufficient oxygen. In the oxide semiconductor layer 144, the carrier concentration is reduced to 1×10 12 / cm 3 Less than, desired Or 1×10 11 / cm 3 Less than 1.45×10 10 / cm 3 Less than For example, the off-current at room temperature (25°C) (here, per unit channel width (1 μm)) The value of 100zA (1zA (zeptoampere) is 1×10 -21 A) The following is desirable: In this way, the oxide that has become i-type (intrinsic) or substantially i-type is By using a semiconductor, it is possible to obtain a transistor 162 with excellent off-state current characteristics. can.

[0125] In the transistor 162 of FIG. 15, the leakage current occurring between elements due to miniaturization is In order to suppress this, the oxide semiconductor layer 144 is processed into an island shape. In the case where the oxide semiconductor layer is not processed into an island shape, This can prevent contamination of the oxide semiconductor layer 144 due to etching during the etching.

[0126] The capacitance element 164 in FIG. 15 includes a drain electrode 142b, a gate insulating film 146, and That is, the drain electrode 142b is formed of the capacitance element 164. The conductive layer 148b serves as one electrode of the capacitor 164. By adopting such a configuration, it is possible to ensure a sufficient capacity. In addition, when the oxide semiconductor layer 144 and the gate insulating film 146 are laminated, the drain The insulation between the electrode 142b and the conductive layer 148b can be sufficiently ensured. If no capacitance is required, the capacitor 164 may be omitted.

[0127] In this embodiment, the transistor 162 and the capacitor 164 are the same as the transistor 160. The planar layout is such that at least a portion of the two-dimensional image sensor 100 is overlapped with the other. For example, if the minimum processing dimension is F, then The area occupied by the room is 15F 2 ~25F 2 It is possible to make the following:

[0128] An insulating layer 150 is provided over the transistor 162 and the capacitor 164. In addition, a wiring 154 is provided in the opening formed in the gate insulating film 146 and the insulating layer 150. The wiring 154 connects one of the memory cells to another memory cell. The wiring 154 is connected to the impurity region 126 via the source electrode 142a and the conductive layer 128b. This allows the source region or drain region of the transistor 160 to The region and the source electrode 142a of the transistor 162 are connected to different wirings. Compared to the conventional method, the number of wirings can be reduced, improving the integration density of semiconductor devices. It can be done.

[0129] In addition, the conductive layer 128b is provided to connect the impurity region 126 to the source electrode 142a. The position where the source electrode 142a and the wiring 154 are connected to each other is provided so as to overlap with the position where the source electrode 142a and the wiring 154 are connected to each other. By adopting such a planar layout, the noise caused by the contact area can be reduced. In other words, the degree of integration of the semiconductor device can be increased. can.

[0130] Note that in the semiconductor device illustrated in FIG. 15, the layer including the transistor 160 is This corresponds to the element formation layer 301 in the semiconductor memory device shown in FIG. and a drive circuit unit (not shown) for driving the memory cell. The first wiring 302 in FIG. The wiring (same layer) is fabricated in the same process as the source electrode 142a (drain electrode 142b) of 62. The first interlayer film 305 in FIG. 1A corresponds to the wiring in the driver circuit section. This corresponds to an insulating layer formed in the same process as the gate insulating film 146 of the transistor 162. The gate insulating film 146 is not patterned and is used as the first interlayer film 305. In addition, the second wiring 303 in FIG. This corresponds to a wiring formed in the same process as the gate electrode 148a of the transistor 162. In addition, the second interlayer film 306 in FIG. 1A is the same as the insulating layer 150 of the transistor 162. The insulating layer 150 corresponds to the insulating layer fabricated in the same process. It can also be used as the interlayer film 306 of the third wiring 3 in FIG. 04 is manufactured in the same process as the wiring 154 of the transistor 162 in the driver circuit section. It corresponds to wiring.

[0131] <Method for manufacturing SOI substrate> Next, an example of a method for manufacturing an SOI substrate used in manufacturing the semiconductor device will be described with reference to FIG. 16 as follows.

[0132] First, a semiconductor substrate 400 is prepared as a base substrate (see FIG. 16(A)). As the semiconductor substrate 400, semiconductor substrates such as a single crystal silicon substrate and a single crystal germanium substrate can be used . Also, as the semiconductor substrate, a solar cell grade silicon (SOG-Si: Solar Grade Silicon) substrate or the like may be used . Further, a polycrystalline semiconductor substrate may be used . When using solar cell grade silicon or a polycrystalline semiconductor substrate, the manufacturing cost can be suppressed as compared with the case of using a single crystal silicon substrate or the like .

[0133] Note that instead of the semiconductor substrate 400, various glass substrates used in the electronics industry such as aluminosilicate glass, aluminoborosilicate glass, barium borosilicate glass, a quartz substrate , a ceramic substrate, and a sapphire substrate can be mentioned. Also, a ceramic substrate having a coefficient of thermal expansion close to that of silicon and mainly composed of silicon nitride and aluminum oxide may be used . .

[0134] The surface of the semiconductor substrate 400 is preferably cleaned in advance. Specifically, it is preferable to clean the semiconductor substrate 400 using a hydrochloric acid hydrogen peroxide water mixed solution (HPM), a sulfuric acid hydrogen peroxide water mixed solution (SPM), an ammonia hydrogen peroxide water mixed solution (APM), a dilute hydrofluoric acid (DHF), etc . .

[0135] Next, a bond substrate is prepared. Here, a single crystal semiconductor substrate 410 is used as the bond substrate (See FIG. 16(B)). In this case, a single crystal substrate is used as the bond substrate. The crystallinity of the bond substrate does not need to be limited to single crystal.

[0136] The single crystal semiconductor substrate 410 may be, for example, a single crystal silicon substrate or a single crystal germanium-based A single crystal semiconductor substrate made of a group 14 element, such as a single crystal silicon germanium substrate, is used. In addition, by using a compound semiconductor substrate such as gallium arsenide or indium phosphide, Commercially available silicon substrates are 5 inch (125 mm) and 6 inch (125 mm) in diameter. (150mm), 8 inch diameter (200mm), 12 inch diameter (300mm), 1 inch diameter A typical example is a circular substrate with a size of 6 inches (400 mm). The shape of 10 is not limited to a circle, but may be, for example, a rectangle. The crystalline semiconductor substrate 410 is formed by a CZ (Czochralski) method or an FZ (Floating Zone) method. It can be prepared using

[0137] An oxide film 412 is formed on the surface of the single crystal semiconductor substrate 410 (see FIG. 16C). In order to remove contaminants, a mixed solution of hydrochloric acid and hydrogen peroxide (HPM) was used before the formation of the oxide film 412. ), Sulfuric acid hydrogen peroxide solution mixture (SPM), Ammonia hydrogen peroxide solution mixture (APM) , dilute hydrofluoric acid (DHF), FPM (a mixture of hydrofluoric acid, hydrogen peroxide, and pure water), etc. It is preferable to clean the surface of the crystalline semiconductor substrate 410 in advance. It may be discharged and washed.

[0138] The oxide film 412 is, for example, a single layer of a silicon oxide film, a silicon oxynitride film, or the like, or a laminated layer. The oxide film 412 can be formed by a method such as thermal oxidation, CVD, etc. In addition, when the oxide film 412 is formed by the CVD method, In order to achieve good bonding, tetraethoxysilane (abbreviation: TEOS, a chemical Formula Si(OC 2 H 5 ) 4 It is preferable to form a silicon oxide film using an organic silane such as It is nice.

[0139] In this embodiment, the single crystal semiconductor substrate 410 is subjected to thermal oxidation treatment to form an oxide film 412 (Here, SiO x Thermal oxidation is performed by adding halogen to an oxidizing atmosphere. It is preferable to carry out the above steps.

[0140] For example, the single crystal semiconductor substrate 410 is subjected to a thermal oxidation process in an oxidizing atmosphere containing chlorine (Cl). By carrying out the above process, an oxide film 412 that is oxidized with chlorine can be formed. The oxide film 412 becomes a film containing chlorine atoms. Collects pure heavy metals (e.g. Fe, Cr, Ni, Mo, etc.) and forms metal chlorides By removing the etched portion to the outside, contamination of the single crystal semiconductor substrate 410 can be reduced.

[0141] The halogen atoms contained in the oxide film 412 are not limited to chlorine atoms. The surface of the single crystal semiconductor substrate 410 may be oxidized by fluorine. The method is to immerse the material in a HF solution and then perform thermal oxidation in an oxidizing atmosphere. 3 of One method is to add it to an oxidizing atmosphere and perform thermal oxidation treatment.

[0142] Next, ions are accelerated by an electric field and irradiated onto the single crystal semiconductor substrate 410. An embrittled region 414 in which the crystal structure is damaged is formed at a predetermined depth in a crystalline semiconductor substrate 410 (FIG. 1 6(D)).

[0143] The depth of the region where the embrittlement region 414 is formed depends on the kinetic energy of the ions, the mass and potential of the ions. The embrittlement region 414 can be adjusted by adjusting the charge, the angle of incidence of the ions, etc. The depth of the ions is approximately the same as the average penetration depth of the ions. Therefore, the thickness of the single crystal semiconductor layer separated from the single crystal semiconductor substrate 410 can be adjusted. For example, the thickness of the single crystal semiconductor layer is 10 nm or more and 500 nm or less, preferably 50 nm or less. The average penetration depth may be adjusted to be about m or more and 200 nm or less.

[0144] The ion irradiation process can be performed using an ion doping device or an ion implantation device. A typical example of an ion doping device is an ion doping device that uses plasma generated by exciting a process gas. There is a non-mass separation type apparatus in which all the ion species generated are irradiated onto the workpiece. The ion species in the plasma are irradiated onto the workpiece without being mass-separated. An ion implanter is a mass separation type device. In an ion implanter, the ion species in the plasma are The ions are mass-separated, and an ion species having a specific mass is irradiated onto the object to be processed.

[0145] In this embodiment mode, hydrogen is added to the single crystal semiconductor substrate 410 using an ion doping apparatus. A gas containing hydrogen is used as the source gas. For more information, see H 3 + It is better to increase the ratio of H + , H2 + , H 3 + Total H for quantity 3 + The ratio of is 50% or more (more preferably 80% or more). H 3 + By increasing the ratio, the efficiency of ion irradiation can be improved.

[0146] The ions to be added are not limited to hydrogen, and ions such as helium ions may also be added. In addition, the type of ions to be added is not limited to one, and multiple types of ions may be added. For example, when hydrogen and helium are irradiated simultaneously using an ion doping apparatus, different The number of steps can be reduced compared to the case where irradiation is performed in a single step, and the single crystal semiconductor It is possible to suppress surface roughness of the layer.

[0147] When the embrittled region 414 is formed using an ion doping apparatus, heavy metals are also simultaneously However, the ions are irradiated through the oxide film 412 containing halogen atoms. By performing irradiation, contamination of the single crystal semiconductor substrate 410 with these heavy metals can be prevented. can.

[0148] Next, the semiconductor substrate 400 and the single crystal semiconductor substrate 410 are placed opposite to each other with an oxide film 412 interposed therebetween. As a result, the semiconductor substrate 400 and the single crystal semiconductor substrate 410 are bonded together. Note that the semiconductor substrate 410 is bonded to the single crystal semiconductor substrate 410. An oxide film or a nitride film may be formed on the surface of 400 .

[0149] When bonding, 0. 001N / cm2 More than 100N / cm 2 For example, 1N / cm 2 More than 20N / cm 2 It is recommended to apply the following pressure. By applying pressure, the bonding surfaces will come closer and become tightly attached. At the contacted portion, a bond is formed between the semiconductor substrate 400 and the oxide film 412. The spontaneous bonding of the two surfaces occurs over almost the entire surface. This bonding is caused by van der Waals forces and hydrogen The bond is functional and can be carried out at room temperature.

[0150] Before bonding the single crystal semiconductor substrate 410 and the semiconductor substrate 400 together, It is preferable to perform a surface treatment on the surface of the single crystal semiconductor. The bonding strength at the interface between the solid substrate 410 and the semiconductor substrate 400 can be improved.

[0151] Surface treatment can be wet treatment, dry treatment, or a combination of wet and dry treatment. Also, different wet treatments can be used in combination. Alternatively, different dry processes may be used in combination.

[0152] After the bonding, a heat treatment may be performed to increase the bonding strength. The treatment temperature is a temperature at which separation does not occur in the embrittled region 414 (for example, room temperature or higher, 400° C. The semiconductor substrate 400 and the oxide film 412 are heated in this temperature range. The above heat treatment may be performed in a heating furnace such as a diffusion furnace or a resistance heating furnace, or in a RTA (instantaneous thermal annealing) furnace. Thermal annealing, Rapid Thermal Anneal equipment, microwave heating equipment, etc. The above temperature conditions are merely examples and may be used in the present invention. This is not to be construed as limiting the present invention.

[0153] Next, heat treatment is performed to separate the single crystal semiconductor substrate 410 at the embrittlement region. A single crystal semiconductor layer 416 is formed on a semiconductor substrate 400 via an oxide film 412 (FIG. 16). (See (F)).

[0154] It is desirable that the heat treatment temperature during the above separation be as low as possible. This is because the lower the temperature at the time of the treatment, the more the surface roughness of the single crystal semiconductor layer 416 can be suppressed. For example, the heat treatment temperature during the separation may be 300° C. or higher and 600° C. or lower. A temperature between 400°C and 500°C is more effective.

[0155] After the single crystal semiconductor substrate 410 is separated, the single crystal semiconductor layer 416 is Heat treatment is performed at a temperature of 0° C. or higher to reduce the concentration of hydrogen remaining in the single crystal semiconductor layer 416. This may be allowed.

[0156] Next, the surface of the single crystal semiconductor layer 416 is irradiated with laser light to improve the flatness of the surface. A single crystal semiconductor layer 418 having improved thermal conductivity and reduced defects is formed (see FIG. 16G). It should be noted that a heat treatment may be carried out instead of the laser light irradiation treatment.

[0157] In this embodiment mode, immediately after the heat treatment for separating the single crystal semiconductor layer 416, However, one embodiment of the present invention is not limited to this. After the heat treatment for separating the crystalline semiconductor layer 416, an etching treatment is performed to form a single crystalline semiconductor layer. 416 After removing the surface defect area, the laser light irradiation treatment may be performed. Laser irradiation may be performed after improving the flatness of the surface of the single crystal semiconductor layer 416. The above etching process may be wet etching or dry etching. In this embodiment, the laser beam is irradiated as described above. After that, a thinning process may be performed to reduce the thickness of the single crystal semiconductor layer 416. Thinning of layer 416 may be achieved by dry etching or wet etching, or both. can be used.

[0158] Through the above steps, an SOI substrate having a single crystal semiconductor layer 418 with good characteristics can be obtained. This is possible (see Figure 16(G)).

[0159] <Method for manufacturing semiconductor device> Next, a method for manufacturing a semiconductor device using the above-described SOI substrate will be described with reference to FIGS. This will be explained in light of the above.

[0160] <How to make the lower transistor> First, a method for fabricating the lower transistor 160 will be described with reference to FIGS. 17 and 18. 17 and 18 show a part of an SOI substrate produced by the method shown in FIG. 15(B) is a cross-sectional process diagram corresponding to the lower transistor shown in FIG. 15(A).

[0161] First, the single crystal semiconductor layer 418 is processed into an island shape to form the semiconductor layer 120 (FIG. 17(A) )). Before and after this process, in order to control the threshold voltage of the transistor, In addition, impurity elements that give n-type conductivity or p-type conductivity are added to the semiconductor. When the semiconductor is silicon, it can be added as an impurity element to give n-type conductivity. For example, phosphorus or arsenic can be used. The pure element may be, for example, boron, aluminum, or gallium.

[0162] Next, an insulating layer 122 is formed so as to cover the semiconductor layer 120 (see FIG. 17(B)). The layer 122 will later become a gate insulating film. The insulating layer 122 is, for example, 20 It can be formed by surface heat treatment (thermal oxidation treatment, thermal nitridation treatment, etc.). Instead of the plasma treatment, a high-density plasma treatment may be applied. Rare gases such as e, Ar, Kr, and Xe, oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen Of course, the CVD method and sputtering method can also be used. The insulating layer 122 may be formed by a method such as a silicon oxide method or a silicon oxynitride method. Silicon, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide Hafnium, hafnium silicate (HfSixOy(x>0, y>0)), nitrogen doped Hafnium silicate (HfSixOy(x>0, y>0)), nitrogen doped hafnium oxide Single layer or multilayer structure including tungsten aluminate (HfAlxOy (x>0, y>0)) The thickness of the insulating layer 122 is preferably in the range of 1 nm to 100 nm. m or less, preferably 10 nm or more and 50 nm or less. A single insulating layer containing silicon oxide is formed by using a plasma CVD method.

[0163] Next, a mask 124 is formed on the insulating layer 122, and an impurity element that imparts one conductivity is doped to form a semiconductor The layer 120 is doped to form an impurity region 126 (see FIG. 17(C)). After the impurity element is added, the mask 124 is removed.

[0164] Next, a mask is formed on the insulating layer 122, and the insulating layer 122 is etched in a region overlapping the impurity region 126. By removing a part of the region, a gate insulating film 122a is formed (see FIG. 17(D)). The insulating layer 122 can be removed by etching such as wet etching or dry etching. An etching process can be used.

[0165] Next, a gate electrode (including wiring formed in the same layer) is formed on the gate insulating film 122a. A conductive layer for forming the gate electrode 128a and the conductive layer is formed by processing the conductive layer. A layer 128b is formed (see FIG. 17(E)).

[0166] The conductive layer used for the gate electrode 128a and the conductive layer 128b may be aluminum, copper, or It can be formed using a metal material such as titanium, tantalum, or tungsten. A semiconductor material such as crystalline silicon may be used to form the layer containing the conductive material. The method is not particularly limited, and various methods such as deposition, CVD, sputtering, and spin coating can be used. The conductive layer can be processed by etching using a resist mask. This can be done by

[0167] Next, the gate electrode 128a and the conductive layer 128b are used as a mask to form a non-transparent layer having one conductivity type. A pure element is added to the semiconductor layer to form a channel forming region 134, an impurity region 132, and an impurity region 133. A pure region 130 is formed (see FIG. 18(A)). For example, an n-type transistor is formed. To achieve this, impurity elements such as phosphorus (P) and arsenic (As) can be added to p-type transistors. To form a sta, impurity elements such as boron (B) and aluminum (Al) are added. The concentration of the added impurity element can be appropriately set. After the doping of the pure element, a heat treatment is performed for activation. The concentration of the impurity region is The impurity regions 126, 132, and 130 have the highest conductivity in this order.

[0168] Next, an insulating layer is formed to cover the gate insulating film 122a, the gate electrode 128a, and the conductive layer 128b. Layer 136, insulating layer 138 and insulating layer 140 are formed (see FIG. 18(B)).

[0169] The insulating layers 136, 138, and 140 may be made of silicon oxide, silicon oxynitride, or nitride. The material used is an inorganic insulating material such as silicon oxide, silicon nitride, or aluminum oxide. In particular, the insulating layers 136, 138, and 140 may be made of a material having a low dielectric constant. By using low-k materials, the capacitance caused by the overlap of various electrodes and wiring is sufficiently low. In addition, the insulating layer 136, the insulating layer 138, and the insulating layer 14 are preferably A porous insulating layer using these materials may be applied to the 0. The dielectric constant is reduced compared to dense insulating layers, further reducing the capacitance caused by electrodes and wiring. In addition, the insulating layer 136, the insulating layer 138, and the insulating layer 140 are made of a poly It is also possible to form the insulating film by using an organic insulating material such as imide or acrylic. The insulating layer 136 is silicon oxynitride, the insulating layer 138 is silicon oxynitride, and the insulating layer 139 is silicon oxynitride. The case where silicon oxide is used as the insulating layer 140 will be described. 36, the insulating layer 138 and the insulating layer 140 are stacked. The number of layers is not limited to this. It may be one or two layers, or may be a laminated structure of four or more layers. stomach.

[0170] Next, the insulating layer 138 and the insulating layer 140 are subjected to a CMP (Chemical Mechanical Polishing) process and an etching process. By performing the process, the insulating layer 138 and the insulating layer 140 are planarized (see FIG. 18(C)). Here, the CMP process is performed until a part of the insulating layer 138 is exposed. When silicon oxynitride is used and silicon oxide is used for the insulating layer 140, the insulating layer 138 becomes ethylene. It functions as an etching stopper.

[0171] Next, the insulating layer 138 and the insulating layer 140 are subjected to CMP processing and etching processing. , the top surfaces of the gate electrode 128a and the conductive layer 128b are exposed (see FIG. 18D). Here, etching is performed until the gate electrode 128a and the conductive layer 128b are partially exposed. The etching process is preferably performed by dry etching. A wet etching process may be used to expose a portion of the gate electrode 128a and the conductive layer 128b. In the step of exposing the semiconductor layer, in order to improve the characteristics of the transistor 162 to be formed later, It is preferable that the surfaces of the insulating layers 136, 138, and 140 are as flat as possible. I wish.

[0172] Through the above steps, the lower transistor 160 can be formed (see FIG. 18(D)). see).

[0173] Before and after each of the above steps, further processes for forming electrodes, wiring, semiconductor layers, insulating layers, etc. may be performed. For example, the wiring structure may be a laminated structure of an insulating layer and a conductive layer. It is also possible to realize a highly integrated semiconductor device by adopting a multi-layer wiring structure.

[0174] <How to make the upper transistor> Next, a method for manufacturing the upper transistor 162 will be described with reference to FIGS. 19 and 20. Reveal.

[0175] First, the gate electrode 128a, the conductive layer 128b, the insulating layer 136, the insulating layer 138, and the insulating layer 14 0, etc., and processing the oxide semiconductor layer to form an oxide semiconductor layer Note that before the oxide semiconductor layer is formed, an insulating layer 144 is formed. An insulating layer that functions as a base may be provided on the insulating layer 136, the insulating layer 138, and the insulating layer 140. The insulating layer is formed by a method such as PVD, sputtering, or plasma CVD. It can be formed by using a VD method or the like.

[0176] The oxide semiconductor used contains at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of the transistors added to them, In addition, it is preferable to use gallium (Ga) as a stabilizer. It is preferable that the stabilizer contains hafnium (Hf). It is preferable that the stabilizer contains aluminum (Al). stomach.

[0177] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0178] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. There can be.

[0179] In this case, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than a and Zn may be present.

[0180] In addition, InMO 3 (ZnO) m (m>0 and m is not an integer) In addition, M may be selected from Ga, Fe, Mn, and Co. The metal element is one or more metal elements. In 3 SnO 5 (ZnO) n A material expressed as (n>0, and n is an integer) may be used.

[0181] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Alternatively, In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In--Sn--Zn-based oxide having an atomic ratio or an oxide having a composition close to that.

[0182] However, the present invention is not limited to these, and can be applied to any semiconductor characteristics (mobility, threshold, variation, etc.) required. In order to obtain the required semiconductor characteristics, the appropriate composition should be used. Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the above appropriate.

[0183] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0184] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with the atomic ratio of In:Ga:Zn=A:B:C (A+B+C = 1), a, b, and c are in the vicinity of the oxide composition (a-A) 2 +(b-B) 2 + (c-C) 2 ≦r 2 The above condition is satisfied, and r can be set to, for example, 0.05. The same is true for compounds.

[0185] The oxide semiconductor may be single-crystalline or non-single-crystalline. In the latter case, it may be amorphous or polycrystalline. In addition, the structure may include a portion having crystallinity in the amorphous state, or a non-amorphous structure. That's fine too.

[0186] Since it is relatively easy to obtain a flat surface for an amorphous oxide semiconductor, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high quality. Therefore, high mobility can be obtained.

[0187] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility equal to or higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form the surface on a thickness of 0.1 nm or less.

[0188] In addition, Ra is the center line average roughness defined in JIS B0601 that can be applied to the surface. This is a three-dimensional extension of the method, which is based on the principle of averaging the absolute value of the deviation from the reference surface to the specified surface. This can be expressed as the "value obtained by dividing the total number of bits by the number of bits" and is defined by the following formula:

[0189]

number

[0190] In the above, S 0 is the measurement surface (coordinate (x 1 ,y 1 )(x 1 ,y 2 )(x 2 ,y 1 )(x 2 ,y 2 ) is the rectangular area enclosed by the four points represented by Z 0 teeth It refers to the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). It can be evaluated using a microscope.

[0191] In this embodiment, the c-axis is oriented and has a triangular or triangular shape when viewed from the ab plane, surface, or interface direction. The atomic arrangement is hexagonal or hexagonal, and the metal atoms are arranged in layers or in a combination of metal atoms and oxygen atoms along the c axis. The molecules are arranged in layers, and the a-axis and b-axis directions are different in the ab plane (the c-axis is the center). C-Axis Aligned Crystal (CAAC) This article will explain oxides containing .

[0192] In a broad sense, oxides containing CAAC are non-single crystals that are not crystalline when viewed from a direction perpendicular to the ab plane. The atomic arrangement is a triangle, a hexagon, an equilateral triangle, or an equilateral hexagon, and is perpendicular to the c-axis direction. From the viewpoint of the direction, it is an acid containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to a monster.

[0193] CAAC is not a single crystal, but it is not composed of only amorphous matter. AC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is not clearly defined. Sometimes it is not possible to determine with certainty.

[0194] When oxygen is contained in CAAC, a part of the oxygen may be replaced with nitrogen. The c-axes of the individual crystals that make up the CAAC are aligned in a certain direction (e.g., the substrate surface supporting the CAAC, C The CAAC may be aligned in a direction perpendicular to the surface of the AAC. The normal to the ab plane of the crystal part of the CAAC is in a certain direction (for example, the substrate plane supporting the CAAC, The direction may be perpendicular to the surface of the substrate.

[0195] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Also, depending on the composition, it may be transparent or opaque to visible light. To do.

[0196] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from the direction, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, When the metal atoms are mixed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Crystals may also be mentioned.

[0197] An example of a crystal structure contained in CAAC will be described in detail with reference to FIGS. 24 to 26, the upward direction is the c-axis direction, and the The plane that is the boundary between the two is called the ab plane. The upper half and the lower half.

[0198] In Figure 24(A), one hexacoordinate In atom and six tetracoordinate oxygen atoms (hereafter referred to as 4) adjacent to the In atom are shown. The structure shown here has one metal atom and one nearby oxygen atom. The structure shown in Fig. 24(A) is an octahedral structure, but it is easy to For simplicity, the structure is shown in a plan view. There are three O atoms in each group with four coordinates. The small group shown in Figure 24(A) has a zero charge.

[0199] In Figure 24(B), one pentagonal Ga atom and three trigonal oxygen atoms (hereafter referred to as 3) adjacent to the Ga atom are shown. The structure shows a structure having a 4-coordinated O atom and two 4-coordinated O atoms adjacent to Ga. The 3-coordinated O atom is Both exist on the ab plane. There are four of them, one each in the upper and lower halves of Figure 24(B). In addition, since In also has a 5-coordinate structure, the structure shown in Figure 24(B) can be formed. The small group shown in FIG. 24(B) has a charge of 0.

[0200] FIG. 24(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 24(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. Or, in the upper half of Figure 24(C), there are three 4-coordinate Os, and in the lower half, there is one There may be 4-coordinated O. The small group shown in Figure 24(C) has a zero charge.

[0201] FIG. 24(D) shows a structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. The upper half of Figure 24(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 24(D) has a charge of +1.

[0202] Figure 24(E) shows a small group containing two Zn atoms. The upper half of Figure 24(E) shows one Zn atom. The small group shown in Figure 24(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0203] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a These are called large groups (also called unit cells).

[0204] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the 6-coordinate In have three adjacent In atoms downward, and the lower half Each of the three O atoms has three adjacent In atoms in the upward direction. Each O has one adjacent Ga in the downward direction, and each O in the lower half has one adjacent Ga in the upward direction. The upper half of the 4-coordinated Zn has one O atom adjacent to it downwards, and the lower half has Each of the three O atoms has three adjacent Zn atoms in the upward direction. The number of O atoms in the tetrahedral coordination is equal to the number of adjacent metal atoms below the O atoms. The number of 4-coordinated O atoms below the O is equal to the number of adjacent metal atoms above the O. Since this is a coordination, the sum of the number of adjacent metal atoms below and the number of adjacent metal atoms above is 4. Therefore, the number of 4-coordinated O atoms above a metal atom and the number of O atoms below another metal atom When the sum of the number of tetracoordinated O in the For example, a 6-coordinate metal atom (In or Sn) can be bonded to the lower half of a 4-coordinate When bonding through O, there are three 4-coordinate O atoms, so the 5-coordinate metal atom (Ga or In, or a four-coordinate metal atom (Zn).

[0205] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinate oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0206] Figure 25(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 25(B) shows a large group consisting of three medium groups. FIG. 25C shows the atomic arrangement when the layer structure of FIG. 25B is observed from the c-axis direction.

[0207] In FIG. 25(A), for simplicity, the tricoordinate O is omitted, and only the number of the tetracoordinate O is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate O atoms, as shown in the circle. Similarly, in FIG. 25(A), the upper and lower halves of In are Each has one 4-coordinate O, which is shown as 1 in a circle. In (A), there is one tetracoordinate O in the lower half and three tetracoordinate O in the upper half. Zn with one tetrahedral O atom in the upper half and three tetrahedral O atoms in the lower half. This shows that:

[0208] In FIG. 25(A), the middle group, which is composed of an In-Sn-Zn-O system layer structure, is Sn has three tetracoordinate O atoms in the upper half and three in the lower half, and one tetracoordinate O atom in the upper half. The In is bonded to the In in the upper and lower halves of the Z atom, which has three tetracoordinate O atoms in the upper half. n, and three tetracoordinate O atoms are bonded to the upper half of the Zn via one tetracoordinate O atom in the lower half of the Zn. and In in the lower half, which is bonded to Zn2 with one 4-coordinated O in the upper half. It bonds to a small group of 4-coordinate O atoms in the lower half of this small group. The structure has three O atoms bonded to Sn atoms in the upper and lower halves. Multiple loops are combined to form large groups.

[0209] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6, respectively. 67, -0.5. For example, In (6 or 5 coordinates), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, a layer structure containing Sn is formed. To do this, a charge of -1 is required to cancel out the charge of +1. As shown in Figure 4(E), a small group of Zn-containing cations is included. For example, Sn-containing cations are If there is one small group with two Zn atoms per small group, the charges are cancelled out. Therefore, the total charge of the layer structure can be set to zero.

[0210] Specifically, the large group shown in FIG. 25(B) is repeated to form In-Sn-Zn -O system crystals (In 2 SnZn 3 O 8 ) can be obtained. The layer structure of the -Zn-O system is In 2 SnZn 2 O 7 (ZnO) m (m is 0 or a natural number.) This can be expressed by the composition formula:

[0211] In addition, there are oxides of four-component metals, such as In-Sn-Ga-Zn oxides and trimetallic oxides. In-Ga-Zn oxide (also written as IGZO), which is an oxide of the elemental metal, In- Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-A l-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-C e-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm -Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb- Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Z n-type oxides, In-Tm-Zn-type oxides, In-Yb-Zn-type oxides, In-Lu-Zn In-Zn oxides, Sn-Zn oxides, and Al oxides are binary metal oxides. -Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and I The same applies when n-Ga-based oxides are used.

[0212] For example, Figure 26(A) shows a model of the middle group consisting of an In-Ga-Zn-O layer structure. A diagram of the rule is shown.

[0213] In FIG. 26(A), the middle group, which is made up of an In-Ga-Zn-O-based layer structure, is In the upper half and lower half, there are three tetracoordinate O atoms, and in the lower half, there is one tetracoordinate O atom. It bonds to Zn at the bottom of the Zn atom, and one tetracoordinate O atom is bonded to the Zn atom via the three tetracoordinate O atoms in the bottom half of the Zn atom. It bonds to Ga in the upper and lower halves, respectively, and is bonded to one tetracoordinate O in the lower half of the Ga. The structure is such that three 4-coordinate O atoms are bonded to In atoms in the upper and lower halves. These medium groups combine to form large groups.

[0214] Figure 26(B) shows a large group consisting of three medium groups. 26(B) shows the atomic arrangement when the layer structure of FIG. 26(B) is observed from the c-axis direction.

[0215] Here, the charges of In (6 or 5 coordinates), Zn (4 coordinates), and Ga (5 coordinates) are Since the valence numbers are +3, +2, and +3, respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge will always be zero.

[0216] The middle group, which is made up of an In-Ga-Zn-O-based layer structure, is shown in FIG. Not limited to the middle group, large-scale combination of middle groups with different arrangements of In, Ga, and Zn Groups are also possible.

[0217] In-Sn-Zn oxide can be called ITZO, and the composition of the target used is The composition ratio of In:Sn:Zn is 1:2:2, 2:1:3, 1:1:1, or Use an oxide target with a ratio of 20:45:35, etc.

[0218] In addition, when using an In-Zn-O-based material as an oxide semiconductor, the composition of the target used The composition ratio, in atomic ratio, is In:Zn=50:1 to 1:2 (converted to molar ratio, In 2 O 3 In:ZnO=25:1 to 1:4, preferably In:Zn=20:1 to 1:1 (molar ratio) This translates to In 2 O 3 In:ZnO=10:1 to 1:2), more preferably In:Zn=1 5:1 to 1.5:1 (converted to molar ratio: In 2 O 3 :ZnO=15:2~3:4) For example, the target used for forming an In-Zn-O oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0219] The thickness of the oxide semiconductor layer is preferably 3 nm or more and 30 nm or less. If the conductor layer is made too thick (for example, more than 50 nm), the transistor will become normally-on. This is because there is a risk that the

[0220] The oxide semiconductor layer is formed by a method that is unlikely to be contaminated with impurities such as hydrogen, water, a hydroxyl group, or a hydride. For example, it can be manufactured by using a sputtering method.

[0221] In this embodiment, the oxide semiconductor layer is formed using an In-Ga-Zn-O oxide target. The film is formed by a sputtering method.

[0222] The In-Ga-Zn-O oxide target may have a composition ratio of, for example, In 2 O 3 :Ga 2 O 3 It is possible to use an oxide target with a molar ratio of ZnO=1:1:1. The material and composition of the target do not have to be limited to those described above. For example, In 2 O 3 :Ga 2 O 3 The oxide target had a composition ratio of ZnO=1:1:2 [molar ratio]. It can also be used.

[0223] The filling rate of the oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using an oxide target with a high filling rate, the oxide semiconductor film formed This is because the body layer can be made into a dense membrane.

[0224] The film formation atmosphere is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. In addition, hydrogen, water, or a hydroxyl group may be added to the oxide semiconductor layer. In order to prevent contamination by impurities such as hydrogen, water, hydroxyl groups, and hydrides, It is preferable to use an atmosphere using a high purity gas that has been removed.

[0225] For example, the oxide semiconductor layer can be formed as follows.

[0226] First, the substrate is held in a deposition chamber maintained under reduced pressure, and the substrate temperature is increased to 200° C. for 5 minutes. 00°C or less, preferably more than 300°C and less than 500°C, more preferably 350°C or more and 400°C or less. Heat to below 50°C.

[0227] Next, while removing the remaining moisture in the film formation chamber, impurities such as hydrogen, water, hydroxyl groups, and hydrides are thoroughly removed. A high-purity gas having been removed from the target was introduced into the target chamber, and an oxide semiconductor layer was formed on the substrate using the target. In order to remove the residual moisture in the deposition chamber, a cryopump is used as an exhaust means. Adsorption type vacuum pumps such as ion pumps and titanium sublimation pumps can be used. It is also preferable that the exhaust means is a turbo pump with a cold trap. The deposition chamber evacuated using a cryopump may contain, for example, hydrogen, water, hydroxyl groups, or hydrogen. Impurities such as chlorine and fluorine (and more preferably compounds containing carbon atoms) are removed. Hydrogen, water, a hydroxyl group, hydride, or the like contained in the oxide semiconductor layer formed in the deposition chamber The concentration of impurities can be reduced.

[0228] When the substrate temperature during film formation is low (for example, 100°C or lower), the oxide semiconductor contains hydrogen atoms. It is preferable to heat the substrate to the above-mentioned temperatures, since there is a risk of contamination with substances that may be harmful to the substrate. By heating the substrate to the above-mentioned temperature to form the oxide semiconductor layer, the substrate temperature becomes high. Therefore, the hydrogen bonds are broken by heat, and substances containing hydrogen atoms are incorporated into the oxide semiconductor layer. Therefore, the oxide semiconductor layer is formed in a state where the substrate is heated to the above-mentioned temperature. By performing this, impurities such as hydrogen, water, a hydroxyl group, or hydride contained in the oxide semiconductor layer can be eliminated. It is possible to sufficiently reduce the concentration of substances. It is also possible to reduce damage caused by sputtering. This can be done.

[0229] As an example of the deposition conditions, the distance between the substrate and the target is 60 mm, the pressure is 0.4 Pa, The direct current (DC) power supply was 0.5 kW, the substrate temperature was 400°C, and the deposition atmosphere was oxygen (oxygen flow rate If a pulsed DC power source is used, the powdery material generated during film formation is This is preferable because it can reduce particles (also called dust) and make the film thickness distribution uniform.

[0230] Before the oxide semiconductor layer is formed by a sputtering method, argon gas is introduced. The powder adhering to the surface on which the oxide semiconductor layer is to be formed is removed by performing reverse sputtering to generate plasma. It is preferable to remove the crystalline substances (also called particles or dust). This is a method in which a voltage is applied to the plate, plasma is generated near the substrate, and the surface on the substrate side is modified. Instead of argon, gas such as nitrogen, helium, or oxygen may be used.

[0231] The oxide semiconductor layer is processed by forming a mask of a desired shape on the oxide semiconductor layer and then The above mask can be used as a photoresist. It can be formed by using a method such as lithography. Alternatively, it can be formed by using an inkjet method. Note that the etching of the oxide semiconductor layer may be performed by a dry etching method. Etching or wet etching may be used. Of course, these may be used in combination. good.

[0232] After that, the oxide semiconductor layer 144 may be subjected to heat treatment (first heat treatment). By performing the treatment, the substance including hydrogen atoms contained in the oxide semiconductor layer 144 can be further The heat treatment temperature is 250°C to 700°C in an inert gas atmosphere. The temperature is preferably 450° C. to 600° C. or lower, or lower than the distortion point of the substrate. The atmosphere is mainly composed of nitrogen or rare gas (helium, neon, argon, etc.). It is preferable to use an atmosphere that does not contain water, hydrogen, etc. The purity of nitrogen and rare gases such as helium, neon, and argon introduced into the treatment equipment is 6N (9 9.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurities The concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0233] The heat treatment is carried out, for example, by placing the workpiece in an electric furnace using a resistance heating element, and heating the workpiece in a nitrogen atmosphere. The heat treatment can be performed under conditions of 450° C. and 1 hour. During this time, the oxide semiconductor layer 144 is not exposed to the air. Do not allow leakage or contamination with water or hydrogen.

[0234] The above-mentioned heat treatment has the effect of removing hydrogen and water, so the heat treatment is also called desorption. This heat treatment can also be called hydration treatment or dehydrogenation treatment. It can also be performed before processing the semiconductor layer into islands or after forming the gate insulating film. In addition, such dehydration and dehydrogenation treatments can be carried out not only once but also multiple times. good.

[0235] Next, a source electrode and a drain electrode (the same layer as this) are formed on the oxide semiconductor layer 144 etc. A conductive layer for forming a semiconductor device (including wiring formed by a method using a semiconductor device) is formed, and the conductive layer is processed to form a semiconductor device. A source electrode 142a and a drain electrode 142b are formed (see FIG. 19(B)).

[0236] The conductive layer can be formed by using a PVD method or a CVD method. The materials used are aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten. The selected elements or alloys containing the above elements can be used. Magnesium, zirconium, beryllium, neodymium, or scandium, or A combination of these materials may also be used.

[0237] The conductive layer may have a single layer structure or a laminated structure of two or more layers. A single layer structure of a titanium nitride film or titanium film, a single layer structure of an aluminum film containing silicon, Two-layer structure with titanium film laminated on titanium nitride film, two-layer structure with titanium film laminated on titanium nitride film Examples include a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated. In addition, when the conductive layer has a single-layer structure of a titanium film or a titanium nitride film, the conductive layer has a tapered shape. The advantage is that it is easy to process the source electrode 142a and the drain electrode 142b. There is.

[0238] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), oxide Indium tin oxide alloy (In 2 O 3 -SnO 2 (sometimes abbreviated as ITO), oxide Indium Zinc Oxide Alloy (In 2 O 3 -ZnO), or these metal oxide materials It is possible to use one containing silicon or silicon oxide.

[0239] The etching of the conductive layer is performed to remove the edges of the source electrode 142a and the drain electrode 142b that are to be formed. It is preferable that the cutting is performed so that the portion has a tapered shape. Here, the taper angle is, for example, The angle is preferably 30° or more and 60° or less. The end of b is etched to have a tapered shape, so that the gate This improves the coverage of the insulating film 146 and prevents discontinuities.

[0240] The channel length (L) of the upper transistor is determined by the distance between the source electrode 142a and the drain electrode 142b. It is determined by the distance between the bottom ends of the first and second electrodes 42b. When performing exposure to form a mask used to form a transistor, the It is preferable to use extreme ultraviolet light with a short wavelength. Extreme ultraviolet light exposure has high resolution and a large depth of focus. The channel length (L) of the transistor must be between 10 nm and 1000 nm (1 μm). This makes it possible to increase the operating speed of the circuit. It is also possible to reduce the power consumption of the device.

[0241] Next, the source electrode 142a and the drain electrode 142b are covered with an oxide semiconductor layer 144 A gate insulating film 146 is formed so as to be in contact with a part of the gate insulating film 146 (see FIG. 19C).

[0242] The gate insulating film 146 can be formed by using a CVD method, a sputtering method, or the like. The gate insulating film 146 is made of silicon oxide, silicon nitride, silicon oxynitride, or gallium oxide. Aluminum, aluminum oxide, tantalum oxide, hafnium oxide, yttrium oxide, hafnium Hafnium silicate (HfSixOy(x>0, y>0)), nitrogen-doped hafnium silicate HfSixOyNz(x>0,y>0,z>0) HfAlxOyNz(x>0,y>0,z>0) The gate insulating film 146 may have a single layer structure or may be formed of any of the above materials. The thickness of the laminate may be, but is not limited to, the thickness of the semiconductor device. When miniaturizing a device, it is desirable to make it thinner in order to ensure the operation of the transistor. For example, when silicon oxide is used, the thickness is set to 1 nm or more and 100 nm or less, preferably 10 nm or less. The thickness can be m or more and 50 nm or less.

[0243] As mentioned above, if the gate insulating film is made thin, the gate leakage caused by the tunnel effect etc. To solve the gate leakage problem, the gate insulating film 146 is doped with hafnium oxide. tantalum oxide, yttrium oxide, hafnium silicate (HfSixOy(x>0 , y>0), nitrogen-doped hafnium silicate (HfSixOyNz(x>0, y>0, z>0), nitrogen-doped hafnium aluminate (HfAlxOyNz( It is recommended to use high-k materials such as x>0, y>0, z>0. By using an igh-k material for the gate insulating film 146, the electrical characteristics are ensured while the gate It is possible to increase the film thickness to suppress leakage. and silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, alumina oxide, Alternatively, it may have a laminated structure with a film containing any one of aluminum and the like.

[0244] In addition, the insulating layer in contact with the oxide semiconductor layer 144 (the gate insulating film 1 in this embodiment) 46) may be an insulating material containing a Group 13 element and oxygen. Many of them contain Group 13 elements, and insulating materials containing Group 13 elements are compatible with oxide semiconductors. By using this for the insulating layer in contact with the oxide semiconductor layer, It can be kept in good condition.

[0245] An insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. The insulating material containing a Group 13 element is, for example, gallium oxide, aluminum oxide, etc. gallium oxide, aluminum gallium oxide, and gallium aluminum oxide. Aluminum gallium is a material that has a higher aluminum content (atomic percent) than the gallium content (atomic percent). Gallium aluminum oxide is a material that has a high gallium content (atomic percent). indicates an aluminum content (atomic percent) of 100 or more.

[0246] For example, when a gate insulating film is formed in contact with an oxide semiconductor layer containing gallium, By using a material containing gallium oxide for the gate insulating film, In addition, the oxide semiconductor layer and the insulating layer containing gallium oxide can be formed on the insulating film. By providing the insulating layer in contact with the oxide semiconductor layer, hydrogen pile-up at the interface between the oxide semiconductor layer and the insulating layer can be prevented. Note that when an element in the same group as a component element of the oxide semiconductor is used for the insulating layer, For example, a material containing aluminum oxide can provide a similar effect. It is also effective to form an insulating layer using aluminum oxide. Therefore, the use of this material can prevent water from entering the oxide semiconductor layer. It is also preferable in terms of preventing intrusion.

[0247] The insulating layer in contact with the oxide semiconductor layer 144 is subjected to a heat treatment in an oxygen atmosphere or an oxygen doping treatment. It is preferable to make the insulating material have more oxygen than the stoichiometric composition by, for example, a vacuum. Oxygen doping refers to adding oxygen to the bulk. The term is used to clarify that the acid is added not only to the surface of the thin film but also to the inside of the thin film. The elemental doping includes oxygen plasma doping in which oxygen in the form of plasma is added to the bulk. The oxygen doping may be performed by using an ion implantation method or an ion doping method.

[0248] For example, when gallium oxide is used as an insulating layer in contact with the oxide semiconductor layer 144, By performing heat treatment under atmospheric conditions and oxygen doping, the composition of gallium oxide is changed to Ga 2 O x (X=3+α, 0<α<1). When aluminum oxide is used as the insulating layer, heat treatment in an oxygen atmosphere or oxygen doping By carrying out the above steps, the composition of aluminum oxide is changed to Al 2 O X (X=3+α, 0<α<1) Alternatively, a gallium oxide film can be used as an insulating layer in contact with the oxide semiconductor layer 144. When aluminum (aluminum gallium oxide) is used, heat treatment in an oxygen atmosphere, By doping with oxygen, gallium aluminum oxide (aluminum gallium oxide) The composition of Ga X Al 2-X O 3+α (0 <X<2、0<α<1)とすることができる。

[0249] By performing oxygen doping treatment, etc., an insulating film having a region with more oxygen than the stoichiometric composition ratio is formed. When the insulating layer having such a region is in contact with the oxide semiconductor layer, As a result, excess oxygen in the insulating layer is supplied to the oxide semiconductor layer, and the oxide semiconductor layer is dehydrated. The present invention reduces oxygen deficiency defects in an oxide semiconductor layer or at the interface between the oxide semiconductor layer and an insulating layer. In this case, the oxide semiconductor layer can be made to be an i-type or an oxide semiconductor that is as close to i-type as possible.

[0250] The insulating layer having a region with more oxygen than the stoichiometric composition ratio may be used instead of the gate insulating film 146. In addition, the insulating layer may be formed as a base film for the oxide semiconductor layer 144, and may be used as a gate insulating film. This may be applied to both the insulating film 146 and the underlying insulating film.

[0251] After the gate insulating film 146 is formed, a second thermal treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0 and 350°C. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. In addition, when the gate insulating film 146 contains oxygen, it can be dehydrated. Oxygen is supplied to the oxide semiconductor layer 144 to compensate for oxygen vacancies in the oxide semiconductor layer 144. Alternatively, an oxide semiconductor layer that is an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is extremely close to an i-type can be formed. .

[0252] In this embodiment, the second heat treatment is performed after the gate insulating film 146 is formed. The timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. A heat treatment may be performed. In addition, a second heat treatment may be performed after the first heat treatment, or the first heat treatment may be performed after the first heat treatment. The first heat treatment may also serve as the second heat treatment, or the second heat treatment may also serve as the first heat treatment. This may be allowed.

[0253] Next, a conductive layer is formed to form the gate electrode (including the wiring formed in the same layer). The conductive layer is then processed to form a gate electrode 148a and a conductive layer 148b (FIG. 19(D)).

[0254] The gate electrode 148a and the conductive layer 148b are made of molybdenum, titanium, tantalum, or tungsten. Metallic materials such as zinc, aluminum, copper, neodymium, scandium, etc., or materials containing these as the main components The gate electrode 148a and the conductive layer 148b can be formed using an alloy material having the same properties as the gate electrode 148a and the conductive layer 148b. 48b may have a single layer structure or a laminated structure.

[0255] Next, an insulating layer 148 is formed on the gate insulating film 146, the gate electrode 148a, and the conductive layer 148b. The insulating layer 150 is formed by using a PVD method, a CVD method, or the like. It can also be formed by using silicon oxide, silicon oxynitride, silicon nitride, and halide. It is formed using a material containing an inorganic insulating material such as fluorine, gallium oxide, or aluminum oxide. The insulating layer 150 may be made of a material having a low dielectric constant or a structure having a low dielectric constant (multiple It is preferable to use a porous structure, etc., for the insulating layer 150. This is because it is possible to reduce the capacitance generated between wirings and electrodes, and to increase the speed of operation. In the present embodiment, the insulating layer 150 has a single-layer structure. The embodiment is not limited to this, and a laminated structure of two or more layers may also be used.

[0256] Next, an opening is formed in the gate insulating film 146 and the insulating layer 150, the opening reaching the source electrode 142a. After that, a wiring 154 that contacts the source electrode 142a is formed on the insulating layer 150 ( See FIG. 20(B). The opening is formed by selective etching using a mask or the like. This is carried out by.

[0257] The wiring 154 is formed by forming a conductive layer using a PVD method or a CVD method, and then patterning the conductive layer. The conductive layer is formed by etching. Elements selected from the group consisting of aluminum, copper, tantalum, titanium, molybdenum, and tungsten, and the above-mentioned elements Manganese, magnesium, zirconium, and other alloys containing these elements can be used. Beryllium, neodymium, or scandium, or a combination of these materials may also be used.

[0258] More specifically, for example, a titanium film is thinly formed by PVD in the area including the opening of the insulating layer 150. After forming a titanium film by the PVD method, the opening is filled with the titanium film. A method for forming an aluminum film on the substrate by the PVD method can be applied. The titanium film reduces the oxide film (such as the natural oxide film) on the surface on which it is formed, and In the case of the source electrode 142a, the contact resistance between the source electrode 142a and the aluminum It is possible to prevent hillocks on the film. In addition, the barrier film made of titanium or titanium nitride can be After the formation, a copper film may be formed by plating.

[0259] The opening formed in the insulating layer 150 is preferably formed in a region overlapping with the conductive layer 128b. By forming an opening in such a region, the increase in element area due to the contact region can be prevented. can be suppressed.

[0260] Here, the connection between the impurity region 126 and the source electrode 142a is achieved without using the conductive layer 128b. In this case, the case where the source electrode 142a and the wiring 154 are overlapped will be described. In this case, the insulating layer 136, the insulating layer 138, and the insulating layer 140 formed on the impurity region 126 are An opening (called a bottom contact) is formed in the bottom contact, and a source electrode 142a is connected to the bottom contact. After formation, the gate insulating film 146 and the insulating layer 150 overlap with the lower contact. An opening (called an upper contact) is formed in the corresponding region, and wiring 154 is formed. When forming the upper contact in the area overlapping the lower contact, the upper contact is etched away. This may result in disconnection of the source electrode 142a formed on the lower contact. To avoid this, the lower contact and the upper contact are formed so that they do not overlap. This causes a problem of an increase in element area.

[0261] As shown in this embodiment, the conductive layer 128b is used to form the source electrode 142a. This allows the upper contact to be formed without breaking the wire. Since the contact on the top can be overlapped, the contact area is reduced. In other words, the degree of integration of the semiconductor device can be increased. can.

[0262] Next, an insulating layer 156 is formed so as to cover the wiring 154 (see FIG. 20(C)).

[0263] Through the above steps, the transistor 162 including the purified oxide semiconductor layer 144 and The capacitance element 164 is completed (see FIG. 20C).

[0264] In the transistor 162, the oxide semiconductor layer 144, the source electrode 142a, and the drain electrode A conductive oxide layer serving as a source region and a drain region is provided between the gate electrode 142b and the gate electrode 142c. The oxide conductive layer may be provided as a buffer layer. The transistors 162A and 162B are shown in FIGS.

[0265] The transistors 162A and 162B in FIG. 22A and FIG. 22B include an oxide semiconductor layer 144 and a source Between the source electrode 142a and the drain electrode 142b, a region that functions as a source region and a drain region is formed. The oxide conductive layers 404a and 404b are formed. The shapes of the oxide conductive layers 404a and 404b of the transistors 162A and 162B are different depending on the manufacturing process. This is an example.

[0266] In the transistor 162A in FIG. 22A, a stack of an oxide semiconductor film and an oxide conductive film is formed. The oxide semiconductor film and the oxide conductive film are stacked in the same photolithography process. The oxide semiconductor layer 144 and the oxide conductive film are formed by processing the oxide semiconductor layer 144 into an island shape. After forming a source electrode 142a and a drain electrode 142b on the oxide conductive film, The island-shaped oxide conductive film is etched using the drain electrodes 142a and 142b as masks. Oxide conductive layers 404a and 404b which become source and drain regions are formed.

[0267] In the transistor 162B in FIG. 22B, an oxide conductive film is formed over the oxide semiconductor layer 144. A metal conductive film is formed thereon, and the oxide conductive film and the metal conductive film are formed by the same photolithography. The oxide conductive layer 404 which becomes the source region and the drain region is processed by a roughening process. a, 404b, a source electrode 142a, and a drain electrode 142b are formed.

[0268] Note that, during etching treatment for processing the shape of the oxide conductive layer, the oxide semiconductor layer may be excessively In order to prevent etching, the etching conditions (type, concentration, etc. of etching material) must be carefully considered. Adjust the schedule (time, etc.) as appropriate.

[0269] The oxide conductive layers 404a and 404b are formed by a sputtering method or a vacuum deposition method (electron beam deposition). The coating is then applied to the metal by a variety of methods, including vapor deposition, arc discharge ion plating, and spraying. The materials for the conductive layer are zinc oxide, a compound of silicon oxide and indium tin oxide, and oxide. Zinc aluminum nitride, zinc aluminum oxynitride, zinc gallium oxide, etc. can be applied. The above materials may also contain silicon oxide.

[0270] As a source region and a drain region, an oxide conductive layer is formed between the oxide semiconductor layer 144 and the source electrode 142a and the drain electrode 142b, The resistance can be reduced, and the transistors 162A and 162B can operate at high speed. Cut.

[0271] In addition, the oxide semiconductor layer 144, the oxide conductive layers 404a and 404b, the source electrode 142a, By configuring the drain electrode 142b, the withstand voltage of the transistors 162A and 162B is The pressure can be improved.

[0272] In the transistor 162 described in this embodiment, the oxide semiconductor layer 144 is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below, preferably 5x 10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 below The carrier density of the oxide semiconductor layer 144 is 100 nm, which is lower than that of a typical silicon wafer. The carrier density (1×10 14 / cm 3 A sufficiently small value (e.g., 1 ×10 12 / cm 3 less than 1.45×10 10 / cm 3 (Less than) In addition, the off-state current of the transistor 162 is also sufficiently small. The off-state current (here, the value per unit channel width (1 μm)) is 100 zA (1 zA ( Zeptoampere) is 1 x 10 -21 A) or less, preferably 10zA or less.

[0273] By using the oxide semiconductor layer 144 which has been highly purified and made intrinsic, It is easy to sufficiently reduce the off-state current of such a transistor. By using this method, a semiconductor device capable of retaining memory contents for an extremely long period of time can be obtained. do.

[0274] In addition, in the semiconductor device shown in this embodiment mode, wiring can be shared. It is possible to realize a semiconductor device with a sufficiently high degree of integration.

[0275] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination.

[0276] (Embodiment 4) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 21. In this embodiment, Telephones, mobile phone devices, portable information terminals (including portable game consoles, audio playback devices, etc.) (including digital cameras, digital video cameras, and other cameras, electronic paper, televisions, etc.) The above-mentioned semiconductors are used in electronic devices such as televisions and television receivers. A case where the device is applied will be described.

[0277] FIG. 21A shows a notebook personal computer. The display unit 709 and the keyboard 710 are included. At least one of the semiconductor devices is provided. It has high speed writing and reading of information, long-term memory retention, and low power consumption. This realizes a notebook-type personal computer with a reduced size.

[0278] FIG. 21B shows a personal digital assistant (PDA), and a main body 711 includes a display unit 713 and an external The terminal 715 and the operation button 714 are provided. The main body 711 includes a stylus 712 for operating the terminal. Therefore, writing and reading of information can be performed at high speed. A portable information terminal capable of long-term memory retention and with sufficiently reduced power consumption is realized. .

[0279] FIG. 21C shows an electronic book 720 equipped with electronic paper. The electronic book 720 is made up of a housing 721 and a housing 722. The display device 720 is configured with two housings, namely, housing 721 and housing 723. The housing 721 and housing 723 each include a display unit 7 25 and a display unit 727 are provided. The housing 721 and the housing 723 are connected by a shaft portion 737. The housing 7 is connected to the housing 7 via the shaft portion 737, and can be opened and closed around the shaft portion 737. 21 includes a power source 731, operation keys 733, a speaker 735, etc. At least one of the housings 723 is provided with the semiconductor device described in the above embodiment. This allows for high speed writing and reading of information, long-term storage, and erasability. This allows for the realization of electronic books with significantly reduced power consumption.

[0280] FIG. 21D shows a mobile phone that is composed of two housings, a housing 740 and a housing 741. Furthermore, the housing 740 and the housing 741 slide and unfold as shown in FIG. It can be folded up and folded up, making it possible to make it compact and suitable for carrying. The housing 741 also includes a display panel 742, a speaker 743, a microphone 744, and an operation Key 745, pointing device 746, camera lens 747, external connection terminal 74 The housing 740 also includes a solar cell 749 for charging the mobile phone. , an external memory slot 750, etc. Also, the antenna is built into the housing 741. At least one of the housing 740 and the housing 741 is provided with the semiconductor device shown in the previous embodiment. This allows for high speed writing and reading of information and long-term storage. Thus, a portable telephone that can be held and has sufficiently reduced power consumption is realized.

[0281] FIG. 21E shows a digital camera, which includes a main body 761, a display unit 767, an eyepiece unit 763, and an operation unit. The device is made up of an operation switch 764, a display unit 765, a battery 766, etc. The semiconductor device described in the above embodiment is provided in the inside of 761. High speed writing and reading, long term memory retention, and low power consumption Thus, a digital camera having such a configuration is realized.

[0282] FIG. 21F shows a television device 770, which includes a housing 771, a display unit 773, a stand, and the like. The television device 770 is operated by a switch provided in the housing 771. The housing 771 and the remote control 780 can be used. The semiconductor device described in the above embodiment is mounted on the device 780. It has high speed writing and reading, long-term memory retention, and low power consumption. A reduced television set is realized.

[0283] As described above, the electronic device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This makes it possible to realize electronic devices with reduced power consumption.

[0284] (Embodiment 5) In the above embodiment, an oxide semiconductor that can be used for the semiconductor layer of the transistor 162 One embodiment of the conductor layer will be described with reference to FIG.

[0285] The oxide semiconductor layer of this embodiment is a crystalline oxide semiconductor layer having a first crystalline oxide The semiconductor layer has a stacked structure including a second crystalline oxide semiconductor layer that is thicker than the semiconductor layer.

[0286] An insulating layer 437 is formed on the insulating layer 401. In this embodiment, the insulating layer 437 is made of P An oxide film with a thickness of 50 nm to 600 nm is formed by CVD or sputtering. An insulating layer is formed. For example, a silicon oxide film, a gallium oxide film, an aluminum oxide film, an oxide a silicon oxynitride film, an aluminum oxynitride film, or a silicon oxynitride film; Layers or stacks thereof may be used.

[0287] Next, a first oxide semiconductor film is formed to a thickness of 1 nm to 10 nm over the insulating layer 437. The first oxide semiconductor film is formed by a sputtering method. The substrate temperature during the film formation is set to 200° C. or higher and 400° C. or lower.

[0288] In this embodiment, a target for an oxide semiconductor (for an In-Ga-Zn-O-based oxide semiconductor) is Target (In 2 O 3 :Ga 2 O 3 ZnO = 1:1:2 (molar ratio) The distance between the substrate and the target was 170 mm, the substrate temperature was 250°C, the pressure was 0.4 Pa, and the DC power supply 0.5kW, oxygen only, argon only, or argon and oxygen atmosphere A first oxide semiconductor film is formed to a thickness of 5 nm.

[0289] In addition, when using an In-Zn-O-based material as an oxide semiconductor, the composition of the target used The composition ratio is In:Zn=50:1-1:2 in atomic ratio (In2O3 In:ZnO=25:1 to 1:4, preferably In:Zn=20:1 to 1:1 (molar ratio) In terms of In2O3:ZnO=10:1 to 1:2), more preferably In:Zn=1 5:1 to 1.5:1 (converted to a molar ratio of In2O3:ZnO = 15:2 to 3:4) For example, the target used for forming an In-Zn-O oxide semiconductor has an atomic ratio of When In:Zn:O=X:Y:Z, Z>1.5X+Y.

[0290] In-Sn-Zn oxide can be called ITZO, and the composition of the target used is The composition ratio of In:Sn:Zn is 1:2:2, 2:1:3, 1:1:1, or Use an oxide target with a ratio of 20:45:35, etc.

[0291] Next, the atmosphere in the chamber in which the substrate is placed is changed to nitrogen or dry air, and a first heat treatment is performed. The temperature of the first heat treatment is set to 400° C. or more and 750° C. or less. Thus, a first crystalline oxide semiconductor layer 450a is formed (see FIG. 23A).

[0292] Although it depends on the substrate temperature during film formation and the temperature of the first heat treatment, the first heat treatment Crystallization occurs from the film surface, and crystals grow from the surface toward the inside of the film, forming c-axis oriented crystals. The first heat treatment causes zinc and oxygen to gather on the surface of the film, resulting in a hexagonal top surface. One or more layers of graphene-type two-dimensional crystals made of zinc and oxygen form on the outermost surface. These grow in the film thickness direction and become stacked. When the temperature of the heat treatment is increased, Crystal growth progresses from the inside to the bottom and then from the inside to the bottom.

[0293] The first heat treatment converts oxygen in the insulating layer 437, which is an oxide insulating layer, into a first crystalline oxide. The semiconductor layer 450a is diffused at its interface with the semiconductor layer 450a or in its vicinity (within a range of ±5 nm from the interface). As a result, oxygen vacancies in the first crystalline oxide semiconductor layer are reduced. The insulating layer 437 is insulated from the first crystalline oxide semiconductor layer 450a in the film (bulk). At least an amount of oxygen exceeding the stoichiometric ratio is present at either the interface of the edge layer 437 or the interface of the edge layer 437. It is preferable to do so.

[0294] Next, a second oxide semiconductor layer having a thickness of more than 10 nm is formed on the first crystalline oxide semiconductor layer 450a. The second oxide semiconductor film is formed by a sputtering method. The substrate temperature during film formation is set to 200° C. or higher and 400° C. or lower. By setting the temperature to 400° C. or higher, the first crystalline oxide semiconductor layer is formed in contact with the surface of the first crystalline oxide semiconductor layer. The precursors are aligned in the oxide semiconductor layer, so that the oxide semiconductor layer can have order. .

[0295] In this embodiment, a target for an oxide semiconductor (for an In-Ga-Zn-O-based oxide semiconductor) is Target (In 2 O 3 :Ga 2 O 3 ZnO = 1:1:2 [molar ratio]) The distance between the substrate and the target was 170 mm, the substrate temperature was 400°C, the pressure was 0.4 Pa, and the direct current (DC) Power supply: 0.5 kW, oxygen only, argon only, or argon and oxygen atmosphere A second oxide semiconductor film is formed to a thickness of 25 nm.

[0296] Next, the chamber atmosphere in which the substrate is placed is changed to a nitrogen atmosphere, an oxygen atmosphere, or a nitrogen and oxygen atmosphere. The second heat treatment is performed in an oxygen mixed atmosphere. The temperature of the second heat treatment is 400° C. or higher. The second heat treatment is performed at a temperature of 750° C. or lower. A second crystalline oxide semiconductor layer 450b is formed by the second heat treatment. The second heat treatment is performed in a nitrogen atmosphere, an oxygen atmosphere, or By performing the deposition in a mixed atmosphere of nitrogen and oxygen, the densification and The second heat treatment is performed to reduce the number of defects in the first crystalline oxide semiconductor layer 450a. The crystal growth proceeds in the thickness direction, i.e., from the bottom to the inside, with the nucleus being the second crystalline oxide semiconductor. Layer 450b is formed.

[0297] In addition, the steps from the formation of the insulating layer 437 to the second heat treatment are performed continuously without exposure to the air. The steps from the formation of the insulating layer 437 to the second heat treatment are preferably performed in the following order. In an atmosphere containing almost no moisture (inert atmosphere, reduced pressure atmosphere, dry air atmosphere, etc.) For example, the moisture content is controlled to a dew point of -40°C or less, preferably a dew point of - The atmosphere should be dry nitrogen and below 50℃.

[0298] Next, the first crystalline oxide semiconductor layer 450a and the second crystalline oxide semiconductor layer 450b are The oxide semiconductor layer 45 is formed by processing the oxide semiconductor layer 45. In FIG. 23C, a first crystalline oxide semiconductor layer 450a and a second crystalline oxide semiconductor layer 450b are formed. The interface between the first and second crystalline oxide semiconductor layers 450b and 450c is indicated by a dotted line, and the first and second crystalline oxide semiconductor layers 450b and 450c are described as a stack of oxide semiconductor layers. However, there is no clear interface, and the illustration is given merely for ease of explanation. is doing.

[0299] The oxide semiconductor stack is processed by forming a mask with a desired shape over the oxide semiconductor stack. The above-described mask can be used for etching the oxide semiconductor stack. It can be formed using a method such as photolithography. The mask may be formed using a method such as a photolithography method.

[0300] Note that the etching of the oxide semiconductor stack can be either dry etching or wet etching. Of course, these may be used in combination.

[0301] In addition, the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer obtained by the above manufacturing method The semiconductor layer is characterized in that it has a c-axis orientation. The crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer do not have a single crystal structure but have an amorphous structure. The structure is not a c-axis aligned crystal (C Axis Aligned Crystal The first crystalline oxide semiconductor has an oxide containing tal (also referred to as CAAC). The first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer partially have grain boundaries.

[0302] The oxide semiconductor used contains at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of the transistors added to them, In addition, it is preferable to use gallium (Ga) as a stabilizer. It is preferable that the stabilizer contains hafnium (Hf). It is preferable that the stabilizer contains aluminum (Al). stomach.

[0303] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0304] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. There can be.

[0305] In this case, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than a and Zn may be present.

[0306] In addition, a two-layer structure in which a second crystalline oxide semiconductor layer is formed on a first crystalline oxide semiconductor layer can be used. However, the present invention is not limited to the above, and a third crystalline oxide semiconductor layer may be formed after the second crystalline oxide semiconductor layer is formed. By repeating the process of film formation and heat treatment to form a layer structure of three or more layers, good.

[0307] The oxide semiconductor layer 453 formed by the above-described method is The above-mentioned semiconductor device can be appropriately used as the transistor 162 which can be applied to the semiconductor device disclosed in .

[0308] In addition, in the case of Embodiment 3 in which the oxide semiconductor stack of this embodiment is used as the oxide semiconductor layer, In the transistor, an electric field is applied from one surface of the oxide semiconductor layer to the other surface of the oxide semiconductor layer. In addition, the current does not flow in the thickness direction (from one surface to the other surface) of the oxide semiconductor stack. The current does not flow in the direction of the wire (specifically, in the vertical direction in Fig. 15(A)). Since the transistor structure has a flow through the interface of the oxide semiconductor stack, the transistor is exposed to light. Even if the transistor is subjected to a BT stress, the degradation of the transistor characteristics is suppressed. or reduced.

[0309] A first crystalline oxide semiconductor layer such as the oxide semiconductor layer 453 and a second crystalline oxide semiconductor layer By using a stack of layers in a transistor, it is possible to achieve stable electrical characteristics and high reliability. This makes it possible to realize a high-speed transistor.

[0310] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0311] (Embodiment 6) The field effect mobility of insulated gate transistors, not limited to oxide semiconductors, is actually measured as However, due to various reasons, the mobility becomes lower than it should be. The factors that reduce the mobility are There are defects inside the semiconductor and at the interface between the semiconductor and the insulating film, but the Levinson model Using this method, we can theoretically derive the field effect mobility assuming that there are no defects inside the semiconductor. Can.

[0312] The inherent mobility of semiconductors is μ 0 Let μ be the field effect mobility to be measured, and let μ be the field effect mobility of some porphyrin in the semiconductor. Assuming the existence of potential barriers (such as grain boundaries), this can be expressed by the following equation:

[0313]

number

[0314] where E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. In addition, if we assume that the potential barrier originates from defects, the Levinson model gives , expressed by the following formula:

[0315]

number

[0316] Here, e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the Dielectric constant, n is the number of carriers contained in the channel per unit area, C ox is per unit area Capacity, V g is the gate voltage, and t is the channel thickness. In the case of a semiconductor layer, the thickness of the channel may be the same as the thickness of the semiconductor layer. Drain current I d is expressed as follows:

[0317]

number

[0318] Here, L is the channel length and W is the channel width, where L=W=10 μm. Also, V d is the drain voltage. Dividing both sides of the above equation by Vg and then taking the logarithm of both sides gives us It looks like this:

[0319]

number

[0320] The right hand side of number 5 is Vg As can be seen from this formula, the vertical axis is ln(Id / Vg), The defect density N is calculated from the slope of the line obtained by plotting the measured values ​​on the horizontal axis of 1 / Vg. That is, the I d -V g From the characteristics, the defect density can be evaluated. As an oxide semiconductor, the ratio of indium (In), tin (Sn), and zinc (Zn) is I In the case of n:Sn:Zn=1:1:1, the defect density N is 1×10 12 / cm 2 That's about it.

[0321] Based on the defect density thus obtained, μ 0 =120cm 2 / Vs The mobility measured in the defective In-Sn-Zn oxide system is 35 cm 2 / However, the oxide film without defects in the semiconductor and at the interface between the semiconductor and the insulating film Mobility μ of semiconductor 0 is 120cm 2 It can be expected that / Vs.

[0322] However, even if there are no defects inside the semiconductor, the electrons may be scattered at the interface between the channel and the gate insulating film. The transport properties of the transistor are affected by the distance x from the gate insulating film interface. Mobility μ at the location 1 is expressed by the following formula:

[0323]

number

[0324] Here, D is the electric field in the direction of the gate electrode, and B and G are constants. B and G are the actual measurement results. From the above measurement results, B = 4.75 × 10 7cm / s, G= 10 nm (depth of interface scattering). As D increases (i.e., gate voltage increases), Since the second term of equation 6 increases when 1 It can be seen that decreases.

[0325] Mobility of a transistor using an ideal oxide semiconductor channel with no internal defects μ 2 The calculation results are shown in Figure 27. The calculation was performed using a Synopsys device simulator. Sentaurus Device is a software that can be used to measure the bandgap of oxide semiconductors. The top, electron affinity, dielectric constant, and thickness are 2.8 eV, 4.7 eV, and These values ​​were measured for thin films formed by sputtering. This was obtained by

[0326] In addition, the work functions of the gate electrode, source electrode, and drain electrode are set to 5.5 eV. The gate insulating film thickness was 100 nm. The channel length and width were both 10 μm, and the drain Voltage V d is 0.1V.

[0327] As shown in Figure 27, the mobility is 100 cm at a gate voltage of just over 1 V. 2 Peaks above / Vs However, if the gate voltage is increased further, the interface scattering increases and the mobility decreases. In order to reduce interface scattering, the surface of the semiconductor layer must be flattened at the atomic level (At omic layer flatness is preferred.

[0328] The characteristics of a miniaturized transistor manufactured using an oxide semiconductor having such mobility are as follows: The results of the calculation of the characteristics are shown in Figs. 28 to 30. The structure of the transistor shown in FIG. + Conductivity type of The semiconductor region 2103a and the semiconductor region 2103c are included. The resistivity of the semiconductor region 2103c is 2×10 -3 Let it be Ωcm.

[0329] The transistor shown in FIG. 31A includes a base insulating film 2101 and a A buried insulating material 2102 made of aluminum oxide is formed on the buried insulating material 2102. The transistor is made up of a semiconductor region 2103a, a semiconductor region 2103c, and a semiconductor region 2103b sandwiched therebetween. The semiconductor device has an intrinsic semiconductor region 2103b which becomes a channel forming region and a gate electrode 2105. The width of the gate electrode 2105 is set to 33 nm.

[0330] Between the gate electrode 2105 and the semiconductor region 2103b, a gate insulating film 2104 is provided. In addition, the gate electrode 2105 is provided on both sides with a sidewall insulator 2106a and a sidewall insulator 2106b. In order to prevent a short circuit between the gate electrode 2105 and other wiring, The width of the sidewall insulator is set to 5 nm. 3a and the semiconductor region 2103c, a source electrode 2108a and a drain electrode 2108b are provided. The channel width of this transistor is 40 nm.

[0331] The transistor shown in FIG. 31B is made of a base insulating film 2101 and aluminum oxide. A semiconductor region 2103a and a semiconductor region 2103c are formed on the buried insulator 2102. and an intrinsic semiconductor region 2103b sandwiched therebetween, and a gate electrode 2105 having a width of 33 nm. The gate insulating film 2104, the sidewall insulator 2106a, the sidewall insulator 2106b, and the insulator 2106b. 107 and the source electrode 2108a and the drain electrode 2108b. This is the same as the transistor shown in

[0332] The transistor shown in FIG. 31(A) differs from the transistor shown in FIG. 31(B) in that the sidewall insulation The conductivity type of the semiconductor region under the edge 2106a and the sidewall insulator 2106b. In the transistor shown in A), the sidewall insulators 2106a and 2106b are The semiconductor region is n + The semiconductor regions 2103a and 2103c have the same conductivity type. However, in the transistor shown in FIG. 31(B), the intrinsic semiconductor region is 2103b. That is, in the semiconductor layer shown in FIG. 31(B), the semiconductor region 2103a (semiconductor region 21 03c) and the gate electrode 2105 do not overlap by Loff. This is called the offset region, and its width Loff is called the offset length. As is clear from the figure, The offset length is the same as the width of the sidewall insulator 2106a (sidewall insulator 2106b).

[0333] The other parameters used in the calculation are as described above. We used the Sentaurus Device simulation software. Figure 28 shows the Drain current (Id, solid line) and mobility of a transistor having the structure shown in FIG. 31(A) The graph shows the gate voltage (Vg, the potential difference between the gate electrode and the source electrode) dependence of the gate-side potential (μ, dotted line). The drain current Id is calculated by setting the drain voltage (potential difference between the drain electrode and the source electrode) to +1V. The mobility μ is calculated assuming a drain voltage of +0.1V.

[0334] FIG. 28(A) shows a gate insulating film having a thickness of 15 nm, and FIG. 28(B) shows a gate insulating film having a thickness of 10 nm. m, and FIG. 28(C) is 5 nm. The gate insulating film becomes thinner. As the temperature increases, the drain current Id (off-state current) in the off state drops significantly. There is no noticeable change in the peak value of μ or the drain current Id (on-state current) in the on-state. At a gate voltage of around 1V, the drain current exceeds 10μA, which is required for memory cells, etc. was shown.

[0335] FIG. 29 shows a transistor having the structure shown in FIG. 31(B), with the offset length Loff set to 5n Dependence of drain current Id (solid line) and mobility μ (dotted line) on gate voltage Vg for m The drain current Id is calculated by assuming a drain voltage of +1 V, and the mobility μ is calculated by assuming a drain voltage of +1 V. The calculation was performed with a gate insulating film thickness of 15 nm. FIG. 29(B) shows the result when the thickness is 10 nm, and FIG. 29(C) shows the result when the thickness is 5 nm. This is what was done.

[0336] FIG. 30 shows the offset length Loff Drain current Id (solid line) and mobility μ (dotted line) for a 15 nm gate The drain current Id is the drain voltage of +1 V, and the mobility μ is the drain voltage of The calculation was performed with a voltage of +0.1V. m, FIG. 30(B) is for 10 nm, and FIG. 30(C) is for 5 nm This is what we have decided.

[0337] In both cases, the thinner the gate insulating film, the more significantly the off-state current decreases, while the peak of the mobility μ There is no noticeable change in the on-state current or the on-state voltage.

[0338] In addition, the peak of the mobility μ is 80 cm in FIG. 2 / Vs, but in Figure 29, cm 2 / Vs, 40cm in Figure 30 2 / Vs, the offset length Loff increases. The off-current also has a similar tendency. On the other hand, the on-current also decreases with increasing offset length L It decreases with increasing off, but it is much slower than the decrease in off current. In addition, the gate voltage is about 1V, and the drain current is 1 It was shown to exceed 0 μA. EXAMPLES

[0339] A transistor that uses an oxide semiconductor containing In, Sn, and Zn as its main components for the channel formation region is The oxide semiconductor film is formed by heating the substrate or by forming the oxide semiconductor film. By performing heat treatment after formation, good characteristics can be obtained. This refers to an element that is contained at 5 atomic % or more in a mixture.

[0340] Intentionally heating the substrate after forming an oxide semiconductor film mainly composed of In, Sn, and Zn Therefore, it is possible to improve the field effect mobility of the transistor. It is possible to positively shift the threshold voltage of the transistor and make it normally off.

[0341] For example, Figs. 32(A) to (C) show a semiconductor device with a channel length L of 3 μm, which is mainly composed of In, Sn, and Zn. The oxide semiconductor film has a channel width W of 10 μm and a gate insulating film with a thickness of 100 nm. These are the characteristics of the transistors used. d was set to 10V.

[0342] Figure 32(A) shows a sputtering method in which the main components In, Sn, and Zn were deposited without intentionally heating the substrate. The field-effect mobility (field effect mobility) of the transistor is shown in FIG. Degree is 18.8cm 2 On the other hand, the substrate was intentionally heated to obtain In, S By forming an oxide semiconductor film mainly composed of n and Zn, it is possible to improve the field effect mobility. FIG. 32(B) shows the formation of a GaN film mainly composed of In, Sn, and Zn by heating the substrate to 200°C. The transistor characteristics when an oxide semiconductor film is formed are shown. The field-effect mobility is 32.2 cm 2 / Vsec is obtained.

[0343] The field effect mobility was measured by forming an oxide semiconductor film mainly composed of In, Sn, and Zn and then performing heat treatment. Fig. 32(C) shows the results of the experiment using In, Sn, and Zn. The oxide semiconductor film mainly composed of is formed by sputtering at 200°C, and then heat-treated at 650°C. The transistor characteristics are shown below. In this case, the field effect mobility is 34.5 cm 2 / V sec is obtained.

[0344] By intentionally heating the substrate, moisture is absorbed into the oxide semiconductor film during sputtering. In addition, by performing a heat treatment after the film formation, the effect of reducing the amount of oxidation can be expected. Hydrogen, hydroxyl groups, or moisture can be released and removed from the compound semiconductor film, as described above. Such an improvement in the field effect mobility can be achieved by dehydration. Not only does hydrogenation and dehydrogenation remove impurities, but the interatomic distances become shorter due to the increased density. It is also estimated that crystallization can be promoted by removing impurities from an oxide semiconductor and purifying it. Such a highly purified non-single-crystal oxide semiconductor can be ideally 0cm 2 It is estimated that it will be possible to achieve a field effect mobility of more than 1 / Vsec.

[0345] Oxygen ions are implanted into an oxide semiconductor whose main components are In, Sn, and Zn, and the oxide is then converted into The hydrogen, hydroxyl groups, or moisture contained in the oxide semiconductor is released, and the heat treatment is performed simultaneously or in conjunction with the heat treatment. The oxide semiconductor may be crystallized by subsequent heat treatment. By the crystallization treatment, a non-single-crystal oxide semiconductor with good crystallinity can be obtained.

[0346] The effect of intentionally heating the substrate during film formation and / or heat treatment after film formation is that the electric field This not only improves the effective mobility but also contributes to making the transistor normally off. The oxide semiconductor, which is mainly composed of In, Sn, and Zn, was formed without intentionally heating the substrate. A transistor with a conductive film as the channel formation region has a negative shift in threshold voltage. However, when an oxide semiconductor film is used that is formed by intentionally heating a substrate, In this case, the negative shift of the threshold voltage is eliminated. This tendency is shown in Figure 32(A) and Figure 32(B). ) can also be confirmed by comparing

[0347] The threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. It is possible to obtain a transistor with a composition ratio of In:Sn:Zn=2:1:3. In addition, the composition ratio of the target is In:Sn:Zn By adjusting the ratio of the carbon nanotube diameter to the carbon nanotube diameter, an oxide semiconductor film with high crystallinity can be obtained.

[0348] The intentional substrate heating temperature or heat treatment temperature is 150° C. or higher, preferably 200° C. or higher. More preferably, the temperature is 400° C. or higher. By forming the film or performing heat treatment at a higher temperature, the transistor can be formed. This makes it possible to achieve a normally-off state for the starter.

[0349] In addition, the gate bianode can be formed by intentionally heating the substrate and / or by carrying out heat treatment after the film formation. It can improve the stability against ass-stress. For example, 2MV / cm, 150℃ , and 1 hour application, the drift is less than ±1.5V, preferably 1.0V You can get less than that.

[0350] In fact, Sample 1 was not subjected to heat treatment after the oxide semiconductor film was formed, and Sample 2 was subjected to heat treatment at 650° C. The BT test was performed on the transistor of sample 2 that had been subjected to the above.

[0351] First, the substrate temperature was set to 25°C, Vd was set to 10V, and the Vg-Id characteristics of the transistor were measured. The V d indicates the drain voltage (potential difference between the drain and source). Next, The temperature was set to 150° C., and Vd was set to 0.1 V. Next, the electric field strength applied to the gate insulating film was A voltage of 20 V was applied to Vg so that the capacitance was 2 MV / cm, and the voltage was maintained for 1 hour. g was set to 0 V. Next, the substrate temperature was set to 25° C., Vd was set to 10 V, and the Vg- Id measurement was performed. This is called the Plus BT test.

[0352] Similarly, first, set the substrate temperature to 25°C, Vd to 10V, and measure the Vg-Id characteristics of the transistor. Next, the substrate temperature was set to 150°C and Vd was set to 0.1V. Next, the gate Apply -20V to Vg so that the electric field strength applied to the insulating film is -2MV / cm. The substrate temperature was then set to 25°C and Vd was set to 1 The Vg-Id of the transistor was measured at 0 V. This is called a negative BT test.

[0353] The results of the positive BT test of sample 1 are shown in Figure 33(A), and the results of the negative BT test are shown in Figure 33(B). The results of the positive BT test of sample 2 are shown in FIG. 34(A), and the results of the negative BT test are shown in FIG. The results are shown in Figure 34(B).

[0354] The threshold voltage shifts of sample 1 due to the positive BT test and the negative BT test are 1.80V and -0.42V. In addition, the positive BT test and negative BT test of sample 2 The threshold voltage variations due to the BT test were 0.79 V and 0.76 V, respectively. In both samples 1 and 2, the change in threshold voltage before and after the BT test was small, and the signal It is known to be highly reliable.

[0355] The heat treatment can be carried out in an oxygen atmosphere, but it is first necessary to prepare a nitrogen or inert gas or a reducing gas atmosphere. Alternatively, heat treatment may be performed under pressure and then in an oxygen-containing atmosphere. By adding oxygen to the oxide semiconductor after dehydrogenation, the effect of the heat treatment can be further improved. To add oxygen later, oxygen ions can be accelerated by an electric field to form a A method of injecting the film may also be applied.

[0356] Defects due to oxygen vacancies are generated in the oxide semiconductor and at the interface between the oxide semiconductor and the film. However, when excess oxygen is contained in the oxide semiconductor by such heat treatment, It is possible to compensate for the oxygen deficiency that is constantly generated by excess oxygen. is mainly interstitial oxygen, and its oxygen concentration is 1×10 16 / cm 3 More than 2×10 20 / cm 3 If the following conditions are met, the material can be included in the oxide semiconductor without causing distortion or the like to the crystal. It is possible.

[0357] In addition, by making the oxide semiconductor contain crystals at least in part through heat treatment, For example, when the composition ratio of In:Sn:Zn=1, a more stable oxide semiconductor film can be obtained. The oxide film was sputtered using a 1:1 target without intentionally heating the substrate. The semiconductor film was found to have a halo pattern by X-ray diffraction (XRD). The oxide semiconductor film thus formed is crystallized by heat treatment. The heat treatment temperature can be selected as desired, but for example, by performing heat treatment at 650°C, X-ray A clear diffraction peak can be observed by diffraction.

[0358] In fact, we performed XRD analysis of the In-Sn-Zn-O film. Using the AXS X-ray diffraction device D8 ADVANCE, the out-of-plane method was used. Measured.

[0359] Samples A and B were prepared for XRD analysis. The method for preparing material B will be explained.

[0360] An In-Sn-Zn-O film was formed to a thickness of 100 nm on a dehydrogenated quartz substrate. .

[0361] The In-Sn-Zn-O film was formed by sputtering in an oxygen atmosphere at a power of 100 W ( The target was In:Sn:Zn=1:1:1 [atomic ratio]. An n-Sn-Zn-O target was used. The substrate heating temperature during film formation was 200°C. The sample thus prepared was designated as sample A.

[0362] Next, a sample prepared in the same manner as sample A was subjected to a heat treatment at a temperature of 650°C. The heat treatment is first performed in a nitrogen atmosphere for one hour, and then in an oxygen atmosphere without lowering the temperature. The sample was then subjected to an additional heat treatment for 1 hour.

[0363] Figure 35 shows the XRD spectra of sample A and sample B. In sample A, the peaks derived from crystals However, in sample B, 2θ was observed around 35 deg and 37 deg to 38 deg. A peak derived from crystals was observed in g.

[0364] In this way, oxide semiconductors mainly composed of In, Sn, and Zn are intentionally heated during film formation. and / or by subjecting the film to heat treatment after deposition, the characteristics of the transistor can be improved. Cut.

[0365] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. In other words, it has the effect of preventing the oxide semiconductor from being included in the film or removing it from the film. By removing hydrogen, which acts as a donor impurity in the conductor, high purification can be achieved. This allows the transistor to be normally off, and the oxide semiconductor is highly purified. By this, the off-current can be reduced to 1 aA / μm or less. The unit indicates the current value per 1 μm of channel width.

[0366] Figure 36 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. For simplicity, the reciprocal of the substrate temperature during measurement is multiplied by 1000 (1000 / T) is the horizontal axis.

[0367] Specifically, as shown in FIG. 36, when the substrate temperature is 125° C., the current is 1 aA / μm (1×1 0 -18 A / μm) or less, and at 85°C it is 100zA / μm (1×10 -19 A / μm ) or less, and at room temperature (27°C), it is 1zA / μm (1×10 -21 A / μm or less Preferably, the resistance is 0.1 aA / μm (1×10 -19 A / μ m) or less at 85°C, -20 A / μm) at room temperature At 0.1zA / μm (1×10 -22 It is possible to achieve a value of less than 100 A / μm.

[0368] However, in order to prevent hydrogen and moisture from being mixed into the oxide semiconductor film during the formation of the film, The leakage from the deposition chamber and the outgassing from the inner walls of the deposition chamber are sufficiently suppressed, and the sputtering gas is highly purified. For example, it is preferable that the sputtering gas has a dew point of -70°C or lower so that moisture is not included in the film. It is preferable to use a gas that is within the range of 1000 to 2000 nm. It is preferable to use a target that has been highly purified so that it does not contain any impurities. Oxide semiconductors that are mainly composed of In, Sn, and Zn can be heat-treated to remove moisture from the film. However, the temperature at which moisture is released is higher than that of oxide semiconductors whose main components are In, Ga, and Zn. Therefore, it is preferable to form a film that does not contain moisture from the beginning.

[0369] In addition, the transistor using Sample B, which was subjected to heat treatment at 650° C. after the formation of the oxide semiconductor film The relationship between the substrate temperature and the electrical characteristics was evaluated.

[0370] The transistor used for the measurement had a channel length L of 3 μm, a channel width W of 10 μm, and Lov The thickness is 0 μm and dW is 0 μm. Vd is 10 V. The substrate temperature is -40°C. , -25°C, 25°C, 75°C, 125°C and 150°C. In this case, the overlapping width between the gate electrode and the pair of electrodes is called Lov, and The protrusion of the pair of electrodes is called dW.

[0371] FIG. 37 shows the Vg dependence of Id (solid line) and field effect mobility (dotted line). Fig. 8(A) shows the relationship between the substrate temperature and the threshold voltage, and Fig. 38(B) shows the relationship between the substrate temperature and the field-effect mobility. The relationship is shown below.

[0372] From FIG. 38(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The range was 1.09V to -0.23V from -40℃ to 150℃.

[0373] Moreover, from FIG. 38(B), it can be seen that the higher the substrate temperature, the lower the field effect mobility. The range is -40℃ to 150℃ and the temperature is 36cm 2 / Vs~32cm 2 / Vs. Therefore, it is understood that the fluctuation of the electrical characteristics is small within the above-mentioned temperature range.

[0374] The above-mentioned oxide semiconductor mainly composed of In, Sn, and Zn is used as a channel forming region. According to the transistor, the field effect mobility is increased to 30c while keeping the off-current below 1aA / μm. m 2 / Vsec or more, preferably 40cm 2 / Vsec or more, preferably 60cm 2 / Vsec or more, and the on-current value required by the LSI can be satisfied. For example, A FET with L / W=33nm / 40nm, gate voltage 2.7V, drain voltage 1.0V When the on-state current is 12μA or more, the on-state current required for the transistor to operate is 12μA or more. Even in a wide temperature range, sufficient electrical characteristics can be ensured. For example, a transistor made of oxide semiconductor is embedded in an integrated circuit made of silicon semiconductor. Even if the chip is used in a large number of chips, it is possible to realize an integrated circuit with new functions without sacrificing the operating speed. Cut. EXAMPLES

[0375] In this example, an example of a transistor using an In-Sn-Zn-O film as an oxide semiconductor film will be described. This will be described with reference to FIG.

[0376] Figure 39 shows the top of a coplanar top-gate top-contact transistor. FIG. 39(A) shows a top view of a transistor. FIG. 39B) shows a cross section A1-A2 corresponding to the dashed line A1-A2 in FIG.

[0377] The transistor shown in FIG. 39B includes a substrate 3100 and a base film provided over the substrate 3100. An insulating film 3102, a protective insulating film 3104 provided around the base insulating film 3102, and a base A high resistance region 3106a and a low resistance region 3106b are provided on the insulating film 3102 and the protective insulating film 3104. The oxide semiconductor film 3106 has a resistor region 3106b. The gate insulating film 3108 is formed on the oxide semiconductor film 310 via the gate insulating film 3108. A gate electrode 3110 is provided so as to overlap with the gate electrode 6, and a gate electrode 3110 is provided so as to contact with the side surface of the gate electrode 3110. and a pair of sidewall insulating films 3112 provided in contact with at least the low resistance region 3106b. The electrode 3114, at least the oxide semiconductor film 3106, the gate electrode 3110, and a pair of An interlayer insulating film 3116 is provided to cover the electrode 3114, and a The wiring 31 is connected to at least one of the pair of electrodes 3114 through the opening. 18 and,

[0378] Although not shown, a protective film is provided to cover the interlayer insulating film 3116 and the wiring 3118. By providing the protective film, the surface conduction of the interlayer insulating film 3116 can be prevented. This can reduce the minute leakage current caused by the above problem, thereby reducing the off-state current of the transistor. It is possible. EXAMPLES

[0379] In this embodiment, a transistor using an In-Sn-Zn-O film as an oxide semiconductor film, which is different from the above, was used. Another example of a register is shown below.

[0380] FIG. 40 is a top view and a cross-sectional view showing the structure of the transistor fabricated in this example. FIG. 40(A) is a top view of a transistor. FIG. 40(B) is a dot-chain diagram of FIG. FIG. 2 is a cross-sectional view corresponding to line B1-B2.

[0381] The transistor shown in FIG. 40B includes a substrate 3600 and a base film provided over the substrate 3600. An insulating film 3602, an oxide semiconductor film 3606 provided over the base insulating film 3602, and an oxide A pair of electrodes 3614 in contact with the oxide semiconductor film 3606, and a pair of electrodes 3614 in contact with the oxide semiconductor film 3606 A gate insulating film 3608 is provided on the electrode 3614, and A gate electrode 3610 overlapping with the oxide semiconductor film 3606 and a gate insulating film 36 3. An interlayer insulating film 3616 is provided to cover the gate electrode 3610 and the insulating film 3616. A wiring 3618 is connected to a pair of electrodes 3614 through an opening provided in the interlayer 616. and a protective film 3620 provided to cover the insulating film 3616 and the wiring 3618.

[0382] The substrate 3600 is a glass substrate, the base insulating film 3602 is a silicon oxide film, and The compound semiconductor film 3606 is an In-Sn-Zn-O film, and the pair of electrodes 3614 is A tungsten film is used as the gate insulating film 3608, a silicon oxide film is used as the gate electrode 361 0 is a laminated structure of a tantalum nitride film and a tungsten film, and The layer structure is a silicon oxynitride film and a polyimide film, and the wiring 3618 is a titanium film. The laminated structure in which an aluminum film and a titanium film are formed in this order is used as the protective film 3620. A polyimide film was used, respectively.

[0383] In the transistor having the structure shown in FIG. 40A, the gate electrode 3610 and a pair of electrodes The width of the overlap with the electrode 3614 is called Lov. The protrusion of the counter electrode 3614 is called dW. [Explanation of symbols]

[0384] 100 circuits 101 Transistor 102 areas 120 Semiconductor layer 122 Insulating layer 124 Mask 126 Impurity region 130 Impurity region 132 Impurity region 134 Channel formation region 136 Insulating Layer 138 Insulating Layer 140 Insulating layer 144 Oxide semiconductor layer 146 Gate insulating film 150 Insulating layer 154 Wiring 156 Insulating Layer 160 Transistors 162 Transistor 162A Transistor 162B Transistor 164 Capacitive element 200 circuits 201 Transistor 202 Transistor 203 areas 300 Substrates 301 Device formation layer 302 Wiring 303 Wiring 304 Wiring 305 Interlayer Film 306 Interlayer Film 400 Semiconductor Substrates 401 Insulating layer 404a Oxide conductive layer 404b Oxide conductive layer 410 Single crystal semiconductor substrate 412 Oxide film 414 Embrittlement area 416 Single crystal semiconductor layer 418 Single crystal semiconductor layer 437 Insulating Layer 450a First crystalline oxide semiconductor layer 450b Second crystalline oxide semiconductor layer 453 Oxide Semiconductor Layer 500 Low Decoder 501 Low Driver 502 memory cells 503 NAND Gate 504 NAND gate section 505 Level Shifter 506 Buffer 507 NAND Gate 508 Level Shifter 509 Buffer 601 N-type transistor 603 P-type transistor 605 Signal Line 606 Signal Line 607 area 700 Signal Line 702 NAND Gate 704 Signal Line 705 area 706 Interlayer Film 707 Case 708 Case 709 Display section 710 Keyboard 711 Main unit 712 Stylus 713 Display section 714 Operation button 715 External Interface 720 e-books 721 Case 723 Case 725 Display section 727 Display section 731 Power supply 733 Operation Key 735 Speaker 737 Shaft 740 Case 741 Case 742 Display Panel 743 Speakers 744 Microphone 745 Operation Key 746 Pointing Device 747 Camera Lenses 748 External connection terminal 749 Solar Cells 750 external memory slot 761 Main unit 763 Eyepiece 764 Operation Switch 765 Display section 766 Battery 767 Display section 770 Television Equipment 771 Case 773 Display section 775 Stand 780 Remote Controlled Device 800 Signal Line 802 NAND Gate 804 Signal Line 805 area 900 Inverter 901 N-type transistor 903 P-type transistor 910 Input signal line 911 Inverted signal input line 912 Output signal line 913 Inverted signal output line 1000 transistors 1001 Wiring 1002 Wiring 1003 area 1006 Interlayer film 1100 Transistor 1101 Wiring 1102 Wiring 1103 area 1201 Transistor 1202 Transistor 1203 Capacitive element 122a Gate insulating film 128a Gate electrode 128b Conductive layer 1300 layers 1301 Transistor 1302 Transistor 1400 Inverter 1401 N-type transistor 1403 P-type transistor 1407 N-type transistor 1408 P-type transistor 1410 Input signal line 1411 Inverted signal input line 1412 Output signal line 1413 Inverted signal output line 142a Source electrode 142b Drain electrode 148a Gate electrode 148b Conductive layer 1500 Transistors 1501 Wiring 1502 Wiring 1503 area 1506 Interlayer film 1600 Signal Line 1601 Circuit 1602 Buffer 1603 Circuit 1604 Signal Line 1605 Signal Line 302a Wiring 302b Wiring 303a Wiring 303b Wiring 703a Transistor 703b Transistor 803a Transistor 803b transistor 2101 Undercoat insulating film 2102 Embedded insulation 2103a Semiconductor area 2103b Semiconductor area 2103c Semiconductor area 2104 Gate insulating film 2105 Gate electrode 2106a Sidewall insulation 2106b Sidewall insulation 2107 Insulation 2108a Source electrode 2108b Drain electrode 3100 Substrate 3102 Undercoat insulating film 3104 Protective insulating film 3106 Oxide semiconductor film 3106a High resistance area 3106b Low resistance region 3108 Gate insulating film 3110 Gate electrode 3112 Sidewall insulating film 3114 Pair of electrodes 3116 Interlayer insulating film 3118 Wiring 3600 Board 3602 Undercoat insulating film 3604 Protective insulating film 3606 Oxide Semiconductor Film 3608 Gate insulating film 3610 Gate electrode 3614 Pair of electrodes 3616 Interlayer insulating film 3618 Wiring 3620 Protective film

Claims

1. a first transistor, a second transistor having a channel formation region in an oxide semiconductor layer, and a capacitor; the capacitance element is electrically connected to a gate electrode of the first transistor; a first insulating layer above a gate insulating film of the first transistor; the oxide semiconductor layer has a region in contact with an upper surface of the first insulating layer, the first insulating layer has a region overlapping the gate insulating film of the first transistor; the other of the source electrode and the drain electrode of the second transistor is electrically connected to a wiring; one of a source electrode and a drain electrode of the second transistor is disposed so as to have a region in contact with an upper surface of a gate electrode of the first transistor; a conductive layer in the same layer as a gate electrode of the second transistor overlaps with one of a source electrode or a drain electrode of the second transistor, is disposed so as to overlap with a gate electrode of the first transistor, and functions as an electrode of the capacitance element; the wiring is disposed above a second insulating layer provided above a gate electrode of the second transistor; the wiring has a region overlapping the capacitive element and a region overlapping a gate electrode of the second transistor; a gate electrode of the first transistor and a source electrode or a drain electrode of the second transistor are made of different materials; a third insulating layer and a fourth insulating layer are provided between the first insulating layer and a gate insulating film of the first transistor; the third insulating layer has a region in contact with a gate insulating film of the first transistor; the fourth insulating layer has a region in contact with the third insulating layer and a region in contact with the first insulating layer, one of a source electrode and a drain electrode of the second transistor has a region in contact with the third insulating layer and a region in contact with the fourth insulating layer; the other of the source electrode and the drain electrode of the second transistor has a region in contact with the third insulating layer and a region in contact with the fourth insulating layer.

2. a first transistor, a second transistor having a channel formation region in an oxide semiconductor layer, and a capacitor; the capacitance element is electrically connected to a gate electrode of the first transistor; a first insulating layer above a gate insulating film of the first transistor; the oxide semiconductor layer has a region in contact with an upper surface of the first insulating layer, the first insulating layer has a region overlapping the gate insulating film of the first transistor; the other of the source electrode and the drain electrode of the second transistor is electrically connected to a wiring; one of a source electrode and a drain electrode of the second transistor is disposed so as to have a region in contact with an upper surface of a gate electrode of the first transistor; a conductive layer in the same layer as a gate electrode of the second transistor overlaps with one of a source electrode or a drain electrode of the second transistor, is disposed so as to overlap with a gate electrode of the first transistor, and functions as an electrode of the capacitance element; the wiring is disposed above a second insulating layer provided above a gate electrode of the second transistor, and has a recess in a region electrically connected to the other of the source electrode and the drain electrode of the second transistor; the recess is filled with a fifth insulating layer; the wiring has a region overlapping the capacitive element and a region overlapping a gate electrode of the second transistor; a gate electrode of the first transistor and a source electrode or a drain electrode of the second transistor are made of different materials; a third insulating layer and a fourth insulating layer are provided between the first insulating layer and a gate insulating film of the first transistor; the third insulating layer has a region in contact with a gate insulating film of the first transistor; the fourth insulating layer has a region in contact with the third insulating layer and a region in contact with the first insulating layer, one of a source electrode and a drain electrode of the second transistor has a region in contact with the third insulating layer and a region in contact with the fourth insulating layer; the other of the source electrode and the drain electrode of the second transistor has a region in contact with the third insulating layer and a region in contact with the fourth insulating layer.

3. In claim 1 or 2, a source electrode or a drain electrode of the second transistor having a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated.

4. In any one of claims 1 to 3, The first insulating layer comprises silicon oxide.

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