Semiconductor Device

Abstract

To provide a semiconductor device having a suitable electric characteristic and being capable of high integration.SOLUTION: A semiconductor device includes a first insulator, an oxide on the first insulator, a second insulator on the oxide, a first conductor on the second insulator, a third insulator in contact with an upper surface of the first insulator, a side surface of the oxide, an upper surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor, and a fourth insulator on the third insulator. The third insulator has an opening that exposes the first insulator. The fourth insulator is in contact with the first insulator through an opening.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. One aspect of the invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, memory device, semiconductor circuit, imaging device and electronic There are cases where the equipment and the like can be said to have a semiconductor device.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. One aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. This concerns the [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, and memories are mainly used. A CPU is a semiconductor integrated circuit (at least transistors and It is an assembly of semiconductor elements having a memory and electrodes that serve as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, e.g. It is mounted on a printed wiring board and used as one of the components in various electronic devices.

[0006] In addition, a transistor is formed using a semiconductor thin film formed on a substrate having an insulating surface. The transistor is used in integrated circuits (ICs) and image display devices (simply called displays). It is widely used in electronic devices such as transistors. Silicon-based semiconductor materials are widely known as possible semiconductor thin films, but other materials are also Oxide semiconductors are attracting attention as a solution.

[0007] Furthermore, a transistor including an oxide semiconductor has a very low leakage current in a non-conducting state. For example, the leakage current of a transistor using an oxide semiconductor is known to be small. A low-power CPU that utilizes this characteristic has been disclosed (see Patent Document 1). .

[0008] Furthermore, as a transistor using an oxide semiconductor, a self-aligned transistor As a transistor with this self-aligned structure, a source region and a drain region are A metal film is formed on the in-region, and heat treatment is performed on the metal film to make the metal film highly resistant. A method for increasing the resistance of the source and drain regions and decreasing the resistance of the source and drain regions is disclosed. (See Patent Document 2).

[0009] Further, as a method for manufacturing a transistor using an oxide semiconductor, After forming a metal film on the region, a heat treatment is performed, and then the dopant passes through the metal film. A method for reducing the resistance of the source and drain regions by introducing (See Patent Document 3).

[0010] In recent years, with the miniaturization and weight reduction of electronic devices, transistors and other components have been integrated at high density. There is also a growing demand for improved productivity of semiconductor devices, including integrated circuits. It is being considered.

[0011] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. However, oxide semiconductors are attracting attention as other materials. For example, not only oxides of single metals such as indium oxide and zinc oxide, but also oxides of multi-component metals Among the oxides of multi-component metals, In-Ga-Zn oxide (hereinafter referred to as In-Ga-Zn oxide) is particularly There is a lot of research going on regarding IGZO.

[0012] Research on IGZO has revealed that, among oxide semiconductors, it is neither single crystal nor amorphous. AAC (c-axis aligned crystalline) structure and nc(n A crystalline structure was found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, oxide semiconductors having a CAAC structure are used. The technology for fabricating a transistor is also disclosed. Even oxide semiconductors with lower crystallinity than those containing SiO2 have minute crystals, as reported in Non-Patent Document 4 and and Non-Patent Document 5.

[0013] Furthermore, transistors using IGZO as the active layer have extremely low off-state current (non- Patent Document 6), and LSIs and displays that utilize these properties have been reported (non- See Patent Document 7 and Non-Patent Document 8). [Prior art documents] [Patent documents]

[0014] [Patent Document 1] Special Publication No. 2012-257187

Patent document 2

Patent document 3

Non-licensed literature

[0015] [Non-licensed document 1] S. Yamazaki et al., "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, pp.183-186 [Non-licensed document 2] S. Yamazaki et al., "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, pp.04ED18-1-04ED18-10 [Non-licensed document 3] S. Ito et al., "The Proceedings of AM-FPD'13 Digest of Technical Papers", 2013, pp.151-154

Non-licensed Document 4

Non-licensed Document 5

Non-licensed Document 6

Non-licensed Document 7

[0016] In Patent Document 2, when the resistance of the source region and the drain region is reduced, a metal film is formed on the drain region and the drain region, and the metal film is subjected to a heat treatment in an oxygen atmosphere; By the heat treatment, the source and drain regions of the oxide semiconductor film are The constituent elements of the metal film penetrate into the source and drain regions as dopants. In addition, by performing heat treatment in an oxygen atmosphere, the conductive film is oxidized, and the However, since the heat treatment is performed in an oxygen atmosphere, the resistance of the conductive film is increased. is hardly extracted from the oxide semiconductor film to the metal film.

[0017] Furthermore, Patent Document 2 describes the oxygen concentration in the channel formation region. However, there is no mention of the concentration of impurities such as water and hydrogen. High purification of the synthesis region (reduction of impurities such as water and hydrogen, typically dehydration or dehydrogenation) Therefore, there is a problem that the transistor tends to have normally-on characteristics. Normally-on means that a channel exists even when no voltage is applied to the gate, and the transistor Normally-off is a state in which current flows through the transistor. When no voltage is applied to the transistor, no current flows through it.

[0018] In view of the above-mentioned problems, one aspect of the present invention is to provide a transistor having a source region and a drain region. By stably reducing the resistance of the channel, and by highly purifying the channel formation region, good electrical conductivity is achieved. It is an object of the present invention to provide a semiconductor device having thermal characteristics.

[0019] Another embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity. One of our goals is to provide the following.

[0020] Another embodiment of the present invention is to provide a semiconductor device that can retain data for a long period of time. Another object of one embodiment of the present invention is to provide a semiconductor device with a high data writing speed. Another object of the present invention is to provide a body device having a high degree of design freedom. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of the present invention is to provide a novel semiconductor device. An object of the present invention is to provide a semiconductor device.

[0021] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0022] One aspect of the present invention is a semiconductor device comprising a first insulator, an oxide on the first insulator, and a second insulator on the oxide. a first conductor on the second insulator, a top surface of the first insulator, a side surface of the oxide, and an oxide a third insulator in contact with the top surface of the first conductor, a side surface of the second insulator, and a side surface of the first conductor; a fourth insulator on the first insulator, the third insulator having an opening exposing the first insulator; The fourth insulator is a semiconductor device that is in contact with the first insulator through the opening.

[0023] Also, one aspect of the present invention is a method for manufacturing a semiconductor device comprising: a first insulator; and a first oxide film having an opening on the first insulator. a second oxide on the first oxide; a second insulator on the second oxide; and a second insulator. a first conductor on the body, a top surface of the first insulator, a side surface of the first oxide, and a side surface of the second oxide; a third oxide layer contacting the top surface of the second oxide, the side surface of the second insulator, and the side surface of the first conductor; an insulator and a fourth insulator on the third insulator, the third insulator The fourth insulator has an opening through which the third insulator is exposed, and the fourth insulator is in contact with the first insulator through the opening. It is a semiconductor device.

[0024] In the above, the first insulator and the fourth insulator have a higher oxygen content than the third insulator. It is preferable that it is easily permeable.

[0025] The oxide is a compound of In, an element M (M is Al, Ga, Y, or Sn), and Zn. It is preferable to have

[0026] The first oxide is a mixture of In, an element M (M is Al, Ga, Y, or Sn), and Zn. and the second oxide comprises In and an element M (M is Al, Ga, Y, or Sn); It is preferable that the metal oxide contains Zn.

[0027] In addition, the second oxide is preferably more permeable to oxygen than the first oxide.

[0028] The third insulator may be an oxide containing either or both of aluminum and hafnium. It is preferable that it is an object.

[0029] In addition, one embodiment of the present invention is a method for forming a first insulator on a substrate, and forming an oxide film on the first insulator. A first insulating film and a dummy gate film are sequentially formed on the oxide layer. The insulating film and the dummy gate film are processed to form a second insulator and a dummy gate layer. forming a first film including a metal in contact with the first insulator, the oxide layer, and the dummy gate layer; The first heat treatment is performed in a nitrogen-containing atmosphere to remove the first film, and the first insulator, the oxide, a second insulating film is formed covering the oxide layer and the dummy gate layer, and the second insulating film is processed; By this, a third insulator having an opening is formed, and a third insulating film is formed on the third insulator. The first CMP process is performed to form a dummy gate layer, a third insulator, and a third insulator. A portion of the insulating film is removed until a portion of the dummy gate layer is exposed, and the dummy gate layer is etched. By this, the second insulator is exposed, a conductive film is formed, and a second CMP process is performed. By performing this, a part of the conductive film is removed until the third insulating film is exposed, and the first conductive film is forming a fourth insulator and a fourth conductive layer; injecting oxygen into the fourth insulator; A fifth insulator is formed on the fourth insulator and the fifth insulator, and a second heat treatment is performed in an atmosphere containing oxygen. and a method for manufacturing a semiconductor device.

[0030] In the above, the first film is any one selected from argon, nitrogen, and oxygen. It is preferable that the layer is formed by a sputtering method using one or more gases.

[0031] In the above, by performing the second heat treatment, oxygen is absorbed into the opening and the first insulator. Preferably, the ions are implanted into the oxide layer via a

[0032] The oxygen implantation can be performed by ion implantation, ion doping, plasma treatment, and plasma treatment. Alternatively, one selected from plasma ion implantation and ion implantation may be used.

[0033] The oxygen may be implanted by ion implantation. [Effects of the Invention]

[0034] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. can.

[0035] Alternatively, a semiconductor device capable of retaining data for a long period of time can be provided. Alternatively, a semiconductor device with a high data writing speed can be provided. It is possible to provide a semiconductor device with high flexibility. Alternatively, a novel semiconductor device can be provided.

[0036] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above is self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0037] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 3] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 25] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 26] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 27] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 28] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 29] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 30] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 31] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 32] 1A and 1B are diagrams illustrating the energy band structure of an oxide semiconductor; [Figure 33] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 34] FIG. 1 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Figure 35] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 36] FIG. 1 is a plan view of a semiconductor device according to one embodiment of the present invention. [Figure 37] FIG. 1 is a plan view of a semiconductor device according to one embodiment of the present invention. [Figure 38] FIG. 1 is a cross-sectional view illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 39] FIG. 1 is a cross-sectional view illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 40] FIG. 1 is a cross-sectional view illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 41] FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. [Figure 42] FIG. 1 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 43] FIG. 1 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 44] FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. [Figure 45] 1A and 1B are a block diagram and a circuit diagram illustrating a configuration example of a memory device of one embodiment of the present invention. [Figure 46] FIG. 1 is a block diagram showing an example of the configuration of an AI system according to one embodiment of the present invention. [Figure 47] FIG. 1 is a block diagram illustrating an application example of an AI system according to one embodiment of the present invention. [Figure 48] 1 is a schematic perspective view showing an example of the configuration of an IC incorporating an AI system according to one embodiment of the present invention. [Figure 49] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 50]1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 51] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0038] Hereinafter, embodiments will be described with reference to the drawings. It is possible to implement the invention in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various changes in mode and details may be made. The present invention should not be construed as being limited to the following description of the embodiments.

[0039] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The figures are merely schematic representations of the various elements, and are not limited to the shapes or values ​​shown in the drawings. During the manufacturing process, layers and resist masks may be unintentionally damaged by processes such as etching. However, in order to make it easier to understand, this may not be reflected in the diagram. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. In addition, when referring to similar functions, In some cases, the hatch patterns are the same and no particular symbols are assigned.

[0040] In addition, in particular, top views (also called "plan views") and perspective views are used to make the invention easier to understand. In order to avoid this, some components may be omitted. may be omitted.

[0041] In addition, in this specification and the like, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. The terms "second" or "third" can be used interchangeably to explain the present invention. The ordinal numbers used to identify an aspect of the present invention are the same as those used in the There may not be.

[0042] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the structure with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The terms are not limited to those given above and can be rephrased appropriately depending on the situation.

[0043] For example, in this specification, it is explicitly stated that X and Y are connected. In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are both considered to be disclosed in this specification. Therefore, it is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text. Connections other than those shown in the drawings or text are also included. Let's say.

[0044] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, layer, etc.).

[0045] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements that function as When a diode, display element, light-emitting element, load, etc. is not connected between X and Y, and elements (e.g., switches, transistors, capacitors) that allow electrical connection between X and Y. without using any capacitors, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. In this case, X and Y are connected.

[0046] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state) and allows current to flow. The switch has the function of controlling whether or not current flows. When X and Y are electrically connected, X This includes the case where Y is directly connected to Y.

[0047] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the signal potential level, etc. ), voltage sources, current sources, switching circuits, amplifier circuits (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (synthesis circuit, memory circuit, control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If a signal is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there are cases where X and Y are directly connected and cases where X and Y are functionally connected. This includes the case where Y is electrically connected.

[0048] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain Between the drain electrode and the source terminal The source electrode has a region where a channel is formed, and the source electrode is connected to the region where the channel is formed. It is possible to pass a current between the gate and the drain. The region where a channel is formed refers to the region through which current mainly flows.

[0049] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0050] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source The distance between the drain electrode and the drain region is called the distance between the In this transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. In this specification, the channel length is any one of the values, the maximum value, in the region where the channel is formed. The maximum, minimum or average value.

[0051] The channel width is, for example, the width of the semiconductor (or transistor) in a top view of the transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor where current flows when the semiconductor is on). In the region where the channel is formed, the vertical direction based on the channel length direction The length of the region where the channel is formed. The width is not necessarily the same in all regions. The channel width may not be determined to a single value. Therefore, in this specification, the channel width is defined as It is any one value, maximum value, minimum value or average value in the area where the channel is formed. .

[0052] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter also referred to as the "effective channel width") is shown in the top view of the transistor. The channel width that is actually used (hereinafter also referred to as "apparent channel width") may differ from the For example, if the gate electrode covers the side of the semiconductor, the effective channel width is The effect of the noise may become larger than the channel width and cannot be ignored. In a transistor in which the gate electrode covers the side of the semiconductor, a channel is formed on the side of the semiconductor. In this case, the actual channel width may be larger than the apparent channel width. The effective channel width is larger.

[0053] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, the effective Channel width is difficult to measure accurately.

[0054] Therefore, in this specification, the apparent channel width is referred to as the "enclosed channel width (SCW:S In addition, in this specification, In this document, when simply referring to channel width, it refers to the enclosed channel width or apparent channel width. In this specification, when simply referred to as a channel width, It may refer to the effective channel width. Note that the channel length, channel width, and effective channel The channel width, apparent channel width, and enclosed channel width can be determined by analyzing cross-sectional TEM images. The value can be determined by, for example,

[0055] The impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. The DOS (Density of States) of the semiconductor increases and the crystallinity decreases. When the semiconductor is an oxide semiconductor, the semiconductor properties may be The impurities to be changed include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 14 elements. These include elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as: Examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of semiconductors, water may also function as an impurity. In some cases, oxygen vacancies may be formed due to the inclusion of impurities. In this case, impurities that change the properties of semiconductors include, for example, oxygen and Group 1 elements excluding hydrogen. , Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0056] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a component. For example, the oxygen content is preferably 55 atomic % or more and 65 atomic % or less. , nitrogen is 1 atomic % or more and 20 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen The concentration range of 0.1 atomic % to 10 atomic % is also referred to as nitride oxide. The silicon film has a composition in which the nitrogen content is higher than the oxygen content. Preferably, nitrogen is 55 atomic % or more and 65 atomic % or less, oxygen is 1 atomic % or more and 20 atomic % or less, Silicon concentration is 25 atomic % or more and 35 atomic % or less, and hydrogen concentration is 0.1 atomic % or more and 10 atomic % or less It refers to what is included in the range.

[0057] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer" It may be possible to change the term to

[0058] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." The term "conductor" can also be replaced with "conductive film" or "conductive layer." The term "semiconductor" can also be replaced with "semiconductor film" or "semiconductor layer." can.

[0059] Furthermore, unless otherwise specified, the transistors described in this specification and the like are field-effect transistors. In addition, unless otherwise specified, the transistors shown in this specification and the like are n Therefore, its threshold voltage (also called "Vth") is , shall be greater than 0V unless otherwise specified.

[0060] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes cases where the angle is between -5° and 5°. "Almost parallel" means that the two lines are arranged at an angle of between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. " refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0061] In this specification, the term "barrier film" refers to a film that prevents impurities such as hydrogen and oxygen from permeating. When the barrier film has conductivity, it is called a conductive barrier film. Sometimes I call.

[0062] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the active layer of a transistor, the metal Oxides are sometimes called oxide semiconductors. In other words, the transistor can be a transistor including an oxide or an oxide semiconductor.

[0063] In this specification, normally-off means that no voltage is applied to the gate, or The current per 1 μm of channel width that flows through a transistor when a ground potential is applied to the gate is 1×10 at room temperature -20 A or less, 1 x 10 at 85°C -18 A or below, or 1 x 10 at 125°C -16 This means that it is A or below.

[0064] (Embodiment 1) An example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described below. I will explain.

[0065] <Configuration Example 1 of Semiconductor Device> FIG. 1 shows a transistor 200 according to one embodiment of the present invention and a circuit diagram of the transistor 200. 1A and 1B are top and cross-sectional views.

[0066] FIG. 1A is a top view of a semiconductor device including a transistor 200. 1B) and FIG. 1C are cross-sectional views of the semiconductor device. 1A is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 1A, showing the channel of the transistor 200. Also, Figure 1(C) is a cross-sectional view in the longitudinal direction of the tube. 1 is a cross-sectional view of the portion shown in FIG. In the top view of FIG. 1(A), some elements are omitted for clarity.

[0067] The semiconductor device of one embodiment of the present invention includes a transistor 200 and an insulator serving as an interlayer film. 210, insulator 212, insulator 280, insulator 282 and insulator 283. conductor 203 electrically connected to the transistor 200 and functioning as wiring; The conductive material 240 (conductive material 240a and conductive material 240b) functions as a guide.

[0068] The conductor 203 is formed so as to be embedded in the insulator 212. The height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be made to be approximately the same. 3 shows a single layer structure, but the present invention is not limited to this. For example, the conductor 203 may have a laminated structure of two or more layers. In such cases, ordinal numbers may be assigned to indicate the order of their formation to distinguish them.

[0069] The conductor 240 is made up of an insulator 273, an insulator 280, an insulator 282, and an insulator 28. The conductor 240 is formed in contact with the inner wall of the opening of the insulator 3. The height of the upper surface of 283 can be made to be approximately the same. Although a single layer configuration is shown, the present invention is not limited to this. For example, The conductor 240 may have a laminated structure of two or more layers.

[0070] [Transistor 200] As shown in FIG. 1B, the transistor 200 is disposed on a substrate (not shown). The insulators 214 and 216 and the insulating material 216 are embedded in the insulators 214 and 216. The conductors 205 (conductors 205a and 205b) and the insulator 216 are arranged as shown in FIG. and an insulator 220 disposed on the conductor 205, and an insulating layer 230 disposed on the insulator 220. An edge 222, an insulator 224 disposed on the insulator 222, and a The oxide 230 (oxide 230a, oxide 230b, and oxide 230c) and the oxide An insulator 250 is disposed on the oxide 230, and a conductor 260 is disposed on the insulator 250. (conductor 260a and conductor 260b), the upper surface of insulator 224, oxide 230a Side surface, side surface of oxide 230b, top surface of oxide 230b, side surface of oxide 230c, insulator 2 50 and an insulator 273 disposed in contact with the side of the conductor 260. The insulator 273 has an opening that exposes the insulator 224, and the insulator 280 has the opening. The conductor 260 is in contact with the insulator 224 via the conductor 260a and the conductor 260b. The conductor 260a is disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIG. 1B, the upper surface of the conductor 260 is substantially flush with the upper surface of the insulator 280. .

[0071] In the transistor 200, the oxide 230a, the oxide 230b, and the oxide Although the present invention is not limited to a three-layer structure of the object 230c, For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, A two-layer structure of oxide 230b and oxide 230c or a laminated structure of four or more layers is provided. In addition, in the transistor 200, the conductor 260a and the conductor 260b may be stacked. Although a layered configuration is shown, the present invention is not limited to this.

[0072] The transistor 200 has a region where a channel is formed (hereinafter referred to as a channel forming region). oxide 230 (also referred to as oxide 230a, oxide 230b, and oxide 230c) ) is a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor. It is preferable.

[0073] The transistor 200 having an oxide semiconductor in a channel formation region has a Since the leakage current is extremely small, a semiconductor device with low power consumption can be provided. Conductors can be deposited using methods such as sputtering, making them ideal for constructing highly integrated semiconductor devices. The transistor 200 can be used.

[0074] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium One or more selected from aluminum, tantalum, tungsten, magnesium, etc. In particular, the element M may be an oxide of a metal such as aluminum, gallium, or yttrium. The oxide 230 is preferably an In-Ga oxide or a tin oxide. Alternatively, In-Zn oxide may be used.

[0075] In addition to the elements constituting the oxide semiconductor, aluminum, ruthenium, titanium, thiamin, By adding metal elements such as tantalum, chromium, and tungsten to oxide semiconductors, Metal compounds may form in some of the semiconductors, resulting in low resistance. It is preferable to use titanium, tantalum, tungsten, or the like in the oxide semiconductor. To add an element, for example, a metal film containing the metal element or a metal element is formed on an oxide semiconductor. It is preferable to provide a nitride film containing a metal element or an oxide film containing a metal element. By this, the oxide semiconductor layer located at the interface between the film and the oxide semiconductor or in the vicinity of the interface A part of the oxygen in the oxide semiconductor is absorbed into the film, forming oxygen vacancies. may become low resistance.

[0076] Further, a metal film, a nitride film containing a metal element, or a nitride film containing a metal element may be formed over an oxide semiconductor. After the oxide film is formed, heat treatment may be performed in an atmosphere containing nitrogen. By the heat treatment, the metal elements diffuse from the metal film into the oxide semiconductor, and the metal elements are can be added.

[0077] Furthermore, hydrogen present in the oxide semiconductor diffuses into the low-resistance region of the oxide semiconductor, When the oxygen enters the oxygen vacancy in the resistive region, it becomes relatively stable. The hydrogen in the oxygen vacancies in the oxide semiconductor is converted into oxygen vacancies by heat treatment at 250°C or higher. The oxide semiconductor is then released from the low-resistance region, diffuses into the low-resistance region, and exists in the low-resistance region. It is known that the oxygen vacancies are contained in the crystals and become relatively stable. Therefore, the resistance of the oxide semiconductor is further reduced, and the resistance of the oxide semiconductor is not reduced. Semiconductors tend to be highly purified (reduced impurities such as water and hydrogen) and have higher resistance.

[0078] In addition, when an impurity element such as hydrogen or nitrogen is present in an oxide semiconductor, the carrier density decreases. The hydrogen in the oxide semiconductor reacts with the oxygen that bonds with the metal atoms to form water, Oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, the carrier density increases. In addition, some of the hydrogen bonds with oxygen, which bonds with metal atoms, to generate electrons, which act as carriers. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced. .

[0079] Therefore, metal elements and impurity elements such as hydrogen and nitrogen can be selectively added to the oxide semiconductor. By adding the element, a high resistance region and a low resistance region can be formed in the oxide semiconductor. In other words, by selectively reducing the resistance of the oxide 230, the oxide 230 processed into an island shape can be The source region or drain region is a region that functions as a semiconductor with a low carrier density. It is possible to provide a region with low resistance that functions as a barrier.

[0080] Here, the oxide 230 selectively made low-resistance is enclosed by a dashed line in FIG. 1(B). An enlarged view of the region 239 is shown in FIG.

[0081] As shown in FIG. 2, oxide 230 functions as a channel-forming region for transistor 200. and a region 234 that functions as a source or drain region of the transistor 200. and an area 231 (area 231a and area 231b) that includes the area 231a.

[0082] The region 231 that functions as a source region or a drain region has a low oxygen concentration and The region 2 functions as a channel formation region. 34 has a higher oxygen concentration than the region 231 that functions as a source region or a drain region. It is a high resistance region with low carrier density.

[0083] The region 231 contains at least metal elements and impurity elements such as hydrogen and nitrogen. Preferably, both concentrations are higher than in region 234 .

[0084] For example, the region 231 contains aluminum, ruthenium, and the like in addition to the metal elements contained in the oxide 230. Any of the metallic elements selected from aluminum, titanium, tantalum, tungsten, chromium, etc. It is preferable that the metal oxide contains one or more metal elements.

[0085] To selectively lower the resistance of the oxide 230, for example, aluminum, ruthenium, titanium, Metallic elements that increase electrical conductivity, such as tantalum, tungsten, chromium, and indium, At least one of oxygen and impurities may be added to a desired region. An element that forms a defect or an element that is captured by an oxygen defect may be used. The elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gases. Representative examples of rare gases include helium, neon, argon, and ton, and xenon.

[0086] To form the region 231, for example, a film having a metal element is formed in contact with the oxide 230. The film containing a metal element may be a metal film, an oxide film containing a metal element, or In this case, a film containing a metal element and an oxide film can be used. A compound layer 242 may be formed at the interface with the oxide 230. 2 is a layer having a metal compound containing a component of a film having a metal element and a component of an oxide 230; For example, the layer 242 may be a layer of the metal element in the oxide 230 and the added metal element. However, it may also be an alloyed layer.

[0087] By adding the metal element to the oxide 230 in this way, the layer 24 2 is formed, and the resistance of the region 231 can be reduced. The layer 242 does not have to be formed in the oxide 230. For example, the layer 242 may be formed on the surface of the oxide 230. Alternatively, it may be formed at the interface between the film containing the metal element and the oxide 230.

[0088] Thus, region 231 may include layer 242. That is, as used herein, source region The region that functions as the source region or drain region is referred to as region 231.

[0089] 1 and 2, regions 234 and 231 are formed in oxide 230b. For example, but not limited to, these regions may be oxide 230a and oxide 230b. 1 and 2, the boundaries of the respective regions may be formed in the object 230c. , are shown approximately perpendicular to the top surface of the oxide 230, but this embodiment is not limited to this. For example, the boundary between the region 231a and the region 234 is near the bottom surface of the oxide 230b. In this case, the shape may recede toward the A1 side in FIG. 1(B), and the area 231b and the area The boundary of 234 recedes toward the A2 side in FIG. 1(B) near the bottom surface of the oxide 230b. It may become like this.

[0090] Also, in the oxide 230, it may be difficult to clearly detect the boundaries between the regions. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are as follows: Not only is there a gradual change in each area, but there is also a continuous change within each area (also known as gradation) That is, the closer to the channel forming region, the more the metal element and It is sufficient that the concentrations of impurity elements such as hydrogen and nitrogen are reduced.

[0091] In FIG. 2, the region of the oxide 230 where the resistance is reduced is shown as a layer 242. In this specification and the like, the range of the layer 242 is not limited to the range shown in FIG. , the oxide in the region near the interface between the oxide 230 and the conductor 240 or in the region 231 The low-resistance layer 242 is formed in the region from the upper surface of the oxide 230 to the lower surface of the oxide 230. The same applies to other drawings.

[0092] The region 231 and the metal film, the nitride film containing the metal element, or the oxide film containing the metal element are also The film is preferably subjected to heat treatment in an atmosphere containing nitrogen while in contact with the film. As a result, the metal element diffuses from the metal film to the region 231 of the oxide 230, and the metal In this case, the region 231 of the oxide 230 and the metal element can be added. However, the oxide 230 may be alloyed with the metal element. Metal elements added to semiconductors are in a relatively stable state, making them highly reliable semiconductors. An apparatus can be provided.

[0093] In addition, hydrogen in the oxide 230 diffuses into the region 231, and oxygen vacancies present in the region 231 are eliminated. In addition, when the oxygen vacancy in the region 234 is By heat treatment at 250°C or higher, hydrogen escapes from the oxygen vacancies and diffuses into the region 231. The oxygen enters the oxygen vacancies in the region 231 and becomes relatively stable. Therefore, the region 231 has a lower resistance, and the region 234 has a higher purity (water, hydrogen, etc.) (reduction of materials) and higher resistance.

[0094] Here, the metal film, the oxide film containing a metal element, or the nitride film containing a metal element is If it has absorbing properties, the hydrogen in the oxide 230 will be absorbed into the film. It is possible to reduce hydrogen, which is an impurity in the oxide 230. In addition, it is possible to reduce the amount of metal film and metal element. The oxide film having the metal element or the nitride film having the metal element absorbs the metal element from the oxide 230 in a later process. It may be removed together with the hydrogen.

[0095] It should be noted that the metal film, the oxide film containing a metal element, or the nitride film containing a metal element is not necessarily For example, a metal film, an oxide film containing a metal element, or a film containing a metal element may be removed. The nitride film is oxidized by the oxygen absorbed from the oxide 230, becomes an insulator, and becomes highly resistive. If the film is present, it may be left as it is. In this case, the film may function as an interlayer film. There is a match.

[0096] For example, a metal film, an oxide film containing a metal element, or a nitride film containing a metal element may be If a conductive region remains, the conductive region can be removed by heat treatment. By oxidizing the film, the film becomes an insulator and has high resistance. It is preferable to carry out the treatment in a chemical atmosphere. When there is a structure containing oxygen in the vicinity of a nitride film containing metal elements, heat treatment is performed to remove the metal The metal film, the oxide film containing a metal element, or the nitride film containing a metal element is It may react with oxygen and become oxidized.

[0097] A metal film, an oxide film containing a metal element, or a nitride film containing a metal element is left as an insulator. By allowing the film to exist, it can function as an interlayer film.

[0098] For example, a metal film, an oxide film containing a metal element, or a nitride film containing a metal element has a thickness of 0.5 It is preferable that the film thickness is from 1 nm to 5 nm, and more preferably from 1 nm to 2 nm. For example, if aluminum with a thickness of 0.5 nm or more but less than 5 nm is oxidized by heat treatment, it will become 0. In some cases, aluminum oxide with a thickness of 7 nm to 8 nm may be formed. When the heat treatment is performed at 2000 K, the oxide 230 and the metal film, the oxide film containing a metal element, or the metal The nitride film containing the metal element is in contact with the silicon nitride film, and heat treatment is performed once in an atmosphere containing nitrogen. It is preferable to carry out the heat treatment once in a nitrogen-containing atmosphere. The oxygen in the oxide 230 is a metal film, an oxide film containing a metal element, or a nitride film containing a metal element. It becomes easier to diffuse into the membrane.

[0099] Here, in a transistor using an oxide semiconductor, a channel is formed in the oxide semiconductor. If impurities and oxygen vacancies exist in the region, the electrical characteristics are likely to fluctuate and reliability will decrease. In addition, there are cases where oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor. Therefore, the transistor tends to have normally-on characteristics. It is preferable that oxygen vacancies in region 234 be reduced as much as possible.

[0100] The insulator 273 has a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen. For example, aluminum oxide or hafnium oxide may be used. The insulator 273 is preferably formed by a sputtering method, a CVD method, an MBE method, or a PL method. The insulator 273 can be formed by, for example, ALD or ALD. It is recommended to form an oxide film using the LD method. This allows the deposition of a dense thin film with few defects and excellent coverage, even when depositing on a stepped surface. In addition, the insulators 224 and 280 are more oxygen permeable than the insulator 273. Easy to pass.

[0101] As shown in FIG. 1, the insulator 273 is on the insulator 224 and is located on the side of the oxide 230. The insulating layer 250 is disposed so as to cover the top surface of the oxide 230, the side surface of the insulator 250, and the side surface of the conductor 260. In addition, the insulator 273 has an opening that exposes the insulator 224, and the insulator 280 The conductor 260 is in contact with the insulator 224 through the opening. The upper surface of the conductor 260 is covered with the insulator 282. The insulator 282 is made of impurities such as water or hydrogen, and oxygen, similar to the insulator 273. It is preferable to use an oxide having a function of suppressing the permeation of .

[0102] That is, the transistor 200 is made of an insulating material that is an oxide having a function of suppressing oxygen permeation. The insulating layer 273 and the insulating layer 282 are covered with the stoichiometric oxygen. The insulator 280 containing the most oxygen (also called excess oxygen) is placed on the transistor 200. By disposing the insulator 280 through the insulator 273, the excess oxygen contained in the insulator 280 is The electrons diffuse into the insulator 224 through the openings, and then form channels through the insulator 224. The insulator 282 allows the excess oxygen to be injected into the region 234. The insulator 273 can suppress the upward diffusion of the element. This can prevent excess oxygen contained in the conductive material from diffusing into the conductive material 260. For other paths, the insulator 273 prevents excess oxidation. Oxygen permeation is inhibited.

[0103] By using the configuration shown in FIG. 1, the excess oxygen contained in the insulator 280 can be efficiently removed from the region 2 34, thereby reducing oxygen vacancies in region 234 of oxide 230. It is possible.

[0104] The insulator 280 containing excess oxygen can be formed by injecting oxygen into the insulator 280 after the insulator 280 is formed. The oxygen can be injected by, for example, an oxygen injection process. Aluminum oxide and hafnium oxide are deposited by sputtering using a gas containing A silicon oxide film or the like may be formed.

[0105] In this embodiment, after the insulator 280 is formed, a gas containing oxygen is used as the insulator 282. The aluminum oxide film is formed by sputtering using the aluminum oxide. By forming a film on the insulator 280, oxygen can be injected into the insulator 280.

[0106] Other treatments include plasma treatment using gas containing oxygen, and ion implantation. For example, a process using a device with a high-density plasma source is used to implant oxygen ions. Then, oxygen is injected into the insulator 280 by irradiating it with a plasma of an oxygen-containing gas. Alternatively, oxygen ions can be implanted into the insulator 280 using an ion implanter. It is possible.

[0107] In particular, ion implantation using an ion implanter requires the amount of ion implantation and the depth of ion implantation to be controlled accordingly. This is preferable because the optimum injection amount and the optimum injection time can be controlled independently. Oxygen can be injected into the insulator 280 at a depth, resulting in high performance with little variation in performance. The implantation dose and implantation depth are controlled by the amount of the insulator. 280 film thickness, transistor size, transistor layout density, transistor layout Therefore, it can be optimized as needed.

[0108] By combining the above configurations or the above steps, the resistance of the oxide 230 can be selectively reduced. It is possible.

[0109] When forming a low resistance region in the oxide 230, a conductor 260 that functions as a gate electrode is formed. By using it as a mask, the oxide 230 becomes low resistance in a self-aligned manner. When the transistors 200 are formed simultaneously, the variation in electrical characteristics between the transistors is reduced. The channel length of the transistor 200 is determined by the width of the conductor 260. By making the width of the conductor 260 the minimum processing dimension, the transistor 200 can be miniaturized. This becomes possible.

[0110] From the above, by selecting the range of each area appropriately, it is possible to match the requirements according to the circuit design. Therefore, a transistor having the above electrical characteristics can be easily provided.

[0111] In addition, oxide semiconductors can be deposited by sputtering or other methods, making them suitable for highly integrated semiconductors. It can be used in transistors that constitute semiconductor devices. Transistors using semiconductors have extremely low leakage current (off-state current) when they are off. Because of its small size, a semiconductor device with low power consumption can be provided.

[0112] As described above, a semiconductor device including a transistor with large on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, the fluctuation of the electrical characteristics is suppressed, the electrical characteristics are stable, and the reliability is improved. It is possible to provide a semiconductor device.

[0113] The following describes in detail the configuration of a semiconductor device including a transistor 200 according to one embodiment of the present invention. This article explains:

[0114] As shown in FIGS. 1A and 1C, the conductor 203 extends in the channel width direction. The conductor 203 is connected to the conductor 205 and functions as a wiring for applying a potential to the conductor 205. It is preferable that the insulating layer 212 is embedded in the insulating layer 212 .

[0115] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably provided in contact with the upper surface of the conductor 203. It is preferable that the insulating material 214 and the insulating material 216 are embedded therein.

[0116] Here, the conductor 260 functions as a first gate (also called a top gate) electrode. The conductor 205 may also be used as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 205 may be changed to the potential applied to the conductor 260. The threshold voltage of the transistor 200 is controlled by changing the potential independently of the potential of the transistor 200. In particular, applying a negative potential to the conductor 205 can control the transistor. By increasing the threshold voltage of the transistor 200 to be greater than 0 V, it is possible to reduce the off-state current. Therefore, applying a negative potential to the conductor 205 increases the current density of the conductor 260 compared to when no negative potential is applied. This can reduce the drain current when the potential applied to is 0V.

[0117] Furthermore, by providing a conductor 205 on the conductor 203, a first gate electrode and a wiring The distance between the conductor 260, which functions as a In other words, the insulators 214 and 216 are disposed between the conductor 203 and the conductor 260. By providing the above, the parasitic capacitance between the conductor 203 and the conductor 260 is reduced, and the conductor 2 The dielectric strength between the conductor 260 and the insulating film 03 can be increased.

[0118] In addition, by reducing the parasitic capacitance between the conductor 203 and the conductor 260, the transistor 2 00's switching speed and make it a transistor with high frequency characteristics. In addition, by increasing the dielectric strength between the conductor 203 and the conductor 260, the transistor Therefore, the reliability of the capacitor 200 can be improved. It is preferable to make the film thickness of the conductor 203 thicker. For example, it may be extended in the channel length direction of the transistor 200 .

[0119] As shown in FIG. 1A, the conductor 205 is made of an oxide 230 and a conductor 260. The conductor 205 is arranged so as to overlap the region 234 of the oxide 230. In particular, as shown in FIG. 1C, the conductor 205 is formed of an oxide 23 The region 234 of 0 also extends beyond the end portion intersecting with the channel width direction. It is preferable that

[0120] With the above configuration, when a potential is applied to the conductor 260 and the conductor 205, The electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected, and the oxide 23 The channel forming region formed in the region 0 can be electrically surrounded.

[0121] That is, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the second gate electrode The electric field of the conductor 205, which functions as an electrode, causes the channel forming region 234 In this specification, the first gate electrode and the second gate electrode can be electrically surrounded by the first gate electrode. The structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region This is called the surrounded channel (S-channel) structure.

[0122] In addition, in the conductor 205, the first insulating layer 214 is in contact with the inner walls of the openings of the insulators 214 and 216. The first conductor is formed on the inner side, and the second conductor is formed on the inner side. The height of the upper surfaces of the first and second conductors and the height of the upper surface of the insulator 216 can be made to be approximately the same. Regarding the structure in which the first conductor and the second conductor are stacked in the transistor 200, For example, the conductor 205 may be a single layer, Alternatively, it may have a laminated structure of three or more layers.

[0123] Here, the first conductor of the conductor 205 or the conductor 203 is a hydrogen atom, a hydrogen molecule, Water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. The conductive material has the function of suppressing the diffusion of impurities (the impurities are difficult to penetrate) Alternatively, it is preferable to use oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.). It is preferable to use a conductive material that has a function of suppressing diffusion (i.e., oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen means the above-mentioned The function is to suppress the diffusion of either pure oxygen or any one or all of the above oxygen.

[0124] The first conductor of the conductor 205 or the conductor 203 has a function of suppressing the diffusion of oxygen. As a result, the second conductor of the conductor 205 or the conductor 203 is oxidized, and the conductivity decreases. As a conductive material having a function of suppressing oxygen diffusion, For example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide may be used. Therefore, the first conductor of the conductor 205 or the conductor 203 is preferably The conductive material may be used in a single layer or a multilayer structure. Diffusion to the transistor 200 side through the conductor 203 and the conductor 205 It can be suppressed.

[0125] The second conductor of the conductor 205 is mainly composed of tungsten, copper, or aluminum. It is preferable to use a conductive material having a single layer of the second conductor of the conductor 205. However, it may have a laminated structure, for example, titanium, titanium nitride and the above conductive material. The above may be laminated.

[0126] In addition, the second conductor of the conductor 203 functions as a wiring, so that the second conductor of the conductor 205 It is preferable to use a conductor having a higher conductivity than the conductor of the present invention. For example, copper or aluminum A conductive material containing silicon as a main component can be used. The body may have a laminated structure, for example, a laminate of titanium, titanium nitride and the above conductive material. That's fine.

[0127] In particular, it is preferable to use copper for the second conductor of the conductor 203. Copper has low resistance. Therefore, it is preferable to use it for wiring, etc. On the other hand, copper is easily diffused, so it diffuses into oxide 230. The scattering may deteriorate the electrical characteristics of the transistor 200. The insulator 214 is made of aluminum oxide or hafnium oxide, which has low copper permeability. By using this material, copper diffusion can be suppressed.

[0128] The conductor 205, the insulator 214, and the insulator 216 do not necessarily have to be provided. In this case, a part of the conductor 203 can function as a second gate electrode.

[0129] The insulators 210 and 214 prevent impurities such as water or hydrogen from penetrating the transistor from the substrate side. It is preferable that the insulating film functions as a barrier insulating film that prevents the inclusion of foreign matter in the transistor 200. Therefore, the insulators 210 and 214 are composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, Suppresses the diffusion of impurities such as nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. It is preferable to use an insulating material that has a function of blocking the impurities (that is, an insulating material that is difficult for the impurities to permeate). Or, a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use an insulating material having the above-mentioned properties (which is difficult for the oxygen to permeate).

[0130] For example, aluminum oxide or the like is used as the insulator 210, and silicon nitride is used as the insulator 214. It is preferable to use silicon or the like. This allows impurities such as hydrogen and water to penetrate into the insulator 210. and suppressing diffusion from the substrate side to the transistor 200 side through the insulator 214. Alternatively, oxygen contained in the insulator 224 or the like may be absorbed by the insulator 210 and the insulator 222. Diffusion to the substrate side via 14 can be suppressed.

[0131] In addition, by forming a structure in which the conductor 205 is laminated on the conductor 203, the conductor An insulator 214 may be provided between the body 203 and the conductor 205. Even if a metal that easily diffuses, such as copper, is used for the second conductor 3, the insulator 214 may be made of silicon nitride. By providing a barrier layer or the like, the metal is prevented from diffusing into layers above the insulator 214. It is possible.

[0132] In addition, the insulators 212, 216, and 280, which function as interlayer films, are insulating films. It is preferable that the dielectric constant is lower than that of the insulator 210 or the insulator 214. By using the material as an interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0133] For example, the insulators 212, 216, and 280 may be made of silicon oxide, oxide, or the like. Silicon nitride, silicon oxide nitride, aluminum oxide, hafnium oxide, tantalum oxide , zirconium oxide, lead zirconate titanate (PZT), strontium titanate (Sr Insulators such as (Ba,Sr)TiO3 or (Ba,Sr)TiO3 (BST) are used in single or multilayer configurations. Alternatively, these insulators may contain, for example, aluminum oxide or bismuth oxide. , germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, oxide Yttrium or zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the above insulator. It may also be used.

[0134] The insulators 220, 222, and 224 function as gate insulators. do.

[0135] Here, the insulator 224 in contact with the oxide 230 contains more oxygen than the stoichiometric composition. It is preferable to use an oxide insulator that contains a lot of oxygen. It is preferable that an excess oxygen region is formed. The insulator containing such excess oxygen is an oxide. By providing the oxide 230 in contact with the transistor 2, oxygen vacancies in the oxide 230 are reduced, and the transistor 2 This can improve the reliability of 00.

[0136] As an insulator having an excess oxygen region, specifically, an oxide in which a part of oxygen is released by heating is used. It is preferable to use an oxide material that releases oxygen by heating. Analysis (TDS (Thermal Desorption Spectroscopy) In the precipitation, the amount of oxygen released in terms of oxygen atoms was 1.0 × 10 18 atoms / cm 3 Below above, preferably 1.0 x 10 19 atoms / cm 3 More preferably, 2.0 x 1 0 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm3 That's all The surface temperature of the film during the TDS analysis was 100°C or higher. The temperature is preferably in the range of 00°C or lower, or 100°C or higher and 400°C or lower.

[0137] Also, if the insulator 224 has an excess oxygen region, the insulator 222 may be oxygen-rich (e.g., It has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc. (the oxygen is permeable It is preferable that the temperature is high enough to prevent the temperature from passing through.

[0138] The insulator 222 has a function of suppressing the diffusion of oxygen, and therefore the excess oxygen contained in the insulator 224 is prevented. The oxygen in the excess oxygen region is efficiently supplied to the oxide 230 without diffusing to the insulator 220 side. In addition, the conductor 205 can be made to react with the oxygen in the excess oxygen region of the insulator 224. It is possible to suppress the reaction.

[0139] The insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, or zinc oxide. lead zirconate titanate (PZT), strontium titanate (SrTiO3 ) or (Ba,Sr)TiO3 (BST), which are so-called high-k materials It is preferable to use the body in a single layer or a multilayer structure. As this progresses, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material as an insulator that functions as a thermal insulator, This makes it possible to reduce the gate potential during transistor operation.

[0140] In particular, it has the function of suppressing the diffusion of impurities and oxygen (the oxygen is less likely to permeate). a) Insulating materials containing oxides of one or both of aluminum and hafnium It is recommended to use an insulator containing oxides of either or both aluminum and hafnium. The oxides include aluminum oxide, hafnium oxide, aluminum and hafnium. It is preferable to use oxide (hafnium aluminate) or the like. When the insulator 222 is formed by the above method, the insulator 222 is resistant to oxygen release from the oxide 230 and to The layer serves to prevent impurities such as hydrogen from entering the oxide 230 from the periphery of the transistor 200. It works like this.

[0141] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, or the like may be added to these insulators. um, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0142] Furthermore, the insulator 220 is preferably thermally stable. For example, silicon oxide and Silicon oxide nitride and silicon oxynitride are suitable because they are thermally stable. By combining this insulator with silicon oxide or silicon oxynitride, thermally stable and It is possible to obtain an insulator 220 having a laminated structure with a high relative dielectric constant.

[0143] The insulators 220, 222, and 224 each have a laminated structure of two or more layers. In this case, the laminated structure is not limited to the same material, but may be made of different materials. It may have a laminated structure.

[0144] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230b. The oxide 230c is located on the surface of the oxide 230b. The oxide 230a is located under the oxide 230b. As a result, impurities from the structure formed below the oxide 230a are transferred to the oxide 230b. The diffusion can be suppressed. In addition, by having the oxide 230c on the oxide 230b, Diffusion of impurities from structures formed above oxide 230c into oxide 230b can be suppressed.

[0145] The oxide 230 has a layered structure made of oxides with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the constituent elements are preferably The atomic ratio of element M in the oxide 230b is It is preferable that the atomic ratio of the metal oxide used for the oxide 230a is larger than that of the element M. In the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In. Oxide 230c is a metal oxide that can be used for oxide 230a or oxide 230b. Things can be used.

[0146] The energy of the conduction band minimum of the oxide 230a and the oxide 230c is In other words, the oxide 23 The electron affinity of oxide 230a and oxide 230c is smaller than the electron affinity of oxide 230b. is preferred.

[0147] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, The energy level of the conduction band minimum changes gradually. The energy level of the conduction band minimum at the junction of the oxide 230c and the oxide 230b is It can also be said that the oxide layer is continuously changed or continuously bonded. At the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c In this case, the defect level density of the mixed layer formed in the step (b) is preferably reduced.

[0148] Specifically, oxide 230a and oxide 230b or oxide 230b and oxide 230c However, by having a common element other than oxygen (as the main component), the mixed layer has a low defect level density. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide The oxide 230a and the oxide 230c are In-Ga-Zn oxide and Ga-Zn oxide. , gallium oxide, etc. may be used.

[0149] At this time, the main path of the carriers is the oxide 230b. By configuring 30c as described above, the interface between oxide 230a and oxide 230b and the oxide This can reduce the defect state density at the interface between the oxide 230b and the nitride 230c. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 has high A large on-current can be obtained.

[0150] The electron affinity or energy level Ec at the bottom of the conduction band is the vacuum level as shown in Figure 32. The ionization potential Ip is the difference between the energy Evac and the energy Ev at the top of the valence band, and the The ionization potential Ip can be calculated from the band gap Eg. Ultraviolet Photoelectron S (UPS) The energy gap, Eg, can be measured using a spectroscopic device. can be measured using, for example, a spectroscopic ellipsometer.

[0151] The oxide 230 has a region 231 and a region 234. When 00 is turned on, the region 231a or the region 231b becomes the source region or the drain region. On the other hand, at least a part of the region 234 functions as a channel forming region. It functions as a region.

[0152] In the transistor 200, the regions 23 function as source and drain regions. A region having a higher resistance than the region 231 is formed between the region 231 and the region 234 where the channel is formed. Therefore, the on-state current and mobility of the transistor can be increased. The first gate electrode (conductor 260) does not overlap with the first and drain regions. This can prevent unnecessary capacitance from being created between users.

[0153] The oxide 230 is a metal oxide that functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor). For example, the metal oxide that forms the region 234 is a band gap metal. It is preferable to use a material with a gap of 2 eV or more, preferably 2.5 eV or more. As shown in Fig. 1, by using a metal oxide with a wide band gap, the off-state current of a transistor can be reduced. can be reduced.

[0154] A transistor using an oxide semiconductor has extremely low leakage current in the off state. Therefore, a semiconductor device with low power consumption can be provided. Since the film can be formed using the above, it can be used for transistors that constitute highly integrated semiconductor devices. This can be done.

[0155] The insulator 250 functions as a gate insulator. The insulator 250 is an insulating material that releases oxygen when heated. The insulator 250 is preferably formed using an insulator having a low oxygen content as determined by, for example, TDS analysis. The amount of oxygen released in terms of molecules is 1.0 × 10 18 molecules / cm 3 Above, I like Or 1.0 x 10 19 molecules / cm 3 More preferably, 2.0 x 1 0 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is as above. The surface temperature of the film during the TDS analysis is The temperature is preferably in the range of 100°C or higher and 700°C or lower.

[0156] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, Silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and Silicon oxide doped with nitrogen and silicon oxide having vacancies can be used. Silicon oxide and silicon oxynitride are preferred because they are stable to heat.

[0157] The insulator 250 is an insulator that releases oxygen when heated, and is placed on the top surface of the oxide 230c. By providing the oxide 230b in contact with the insulating material 250, the oxide 230b is effectively transferred to the region 234. In addition, like the insulator 224, water or water in the insulator 250 can be supplied. It is preferable that the concentration of impurities such as silicon is reduced. It is preferable that the upper limit is 20 nm or less.

[0158] In addition, in order to efficiently supply excess oxygen contained in the insulator 250 to the oxide 230, A metal oxide may be provided on the insulator 250. In this case, the metal oxide is removed from the insulator 250. It is preferable to suppress the oxygen diffusion. , the diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. In addition, the amount of excess oxygen supplied to the conductor 2 can be prevented from decreasing. It can suppress the oxidation of 60.

[0159] Note that the metal oxide may function as a part of the gate insulator. When silicon oxide or silicon oxynitride is used for the insulator 250, the metal oxide It is preferable to use a metal oxide, which is a high-k material with a high dielectric constant. This structure makes it possible to create a laminated structure that is stable against heat and has a high relative dielectric constant. Therefore, the gate potential applied during transistor operation can be reduced while maintaining the physical film thickness. In addition, the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator can be reduced. It becomes possible to

[0160] The metal oxide may also function as a part of the first gate electrode. For example, The oxide semiconductor that can be used as the oxide 230 can be used as a metal oxide. In this case, the conductor 260 is formed by sputtering, and the metal oxide It is possible to lower the electrical resistance and make it a conductor. By having the metal oxide, the conductor 260 can be The on-current of the transistor 200 can be improved without weakening the effect of the electric field. do.

[0161] Also, the physical thickness of the insulator 250 and the metal oxide allows the conductor 260 and the oxide By keeping the distance between the conductor 260 and the oxide 230, the leakage current between the conductor 260 and the oxide 230 is suppressed. In addition, by providing a laminated structure of the insulator 250 and the metal oxide, The physical distance between the conductor 260 and the oxide 230 and the distance from the conductor 260 to the oxide The electric field strength applied to 230 can be easily adjusted appropriately.

[0162] Specifically, metal oxides such as hafnium, aluminum, gallium, and yttrium , zirconium, tungsten, titanium, tantalum, nickel, germanium, or Use a metal oxide containing one or more metals selected from magnesium, etc. In addition, by reducing the resistance of the oxide semiconductor that can be used for the oxide 230, , can be used as a metal oxide.

[0163] In particular, it is an insulator containing oxides of either or both of aluminum and hafnium. , aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium It is preferable to use hafnium aluminate. Therefore, the heat resistance of the hafnium oxide film is higher than that of the hafnium oxide film. This is preferable because it is less likely to crystallize.

[0164] The conductor 260 functioning as the first gate electrode is made up of the conductor 260a and the conductor 26 Conductor 260a has a conductor 260b on top of conductor 205. Conductor 260a has the same structure as the first conductor of conductor 205. Similarly, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (NO, NO) , NO2, etc.), and use a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms. Alternatively, the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) is preferred. It is preferable to use a conductive material that has the function of suppressing scattering.

[0165] The conductor 260a has a function of suppressing the diffusion of oxygen, and thus the insulator 250 and The excess oxygen contained in the metal oxide causes the conductor 260b to oxidize and decrease its conductivity. Examples of conductive materials that have the function of suppressing oxygen diffusion include It is preferable to use tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like. stomach.

[0166] The conductor 260b is made of a conductive material mainly composed of tungsten, copper, or aluminum. It is preferable to use a conductive material. It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductive material 260b has a laminated structure. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0167] Also, as shown in FIG. 1C, the conductor 205 is formed in the channel of the region 234 of the oxide 230. When the conductor 260 extends in a region outside the end portion intersecting with the width direction of the cable, In this region, it is preferable that the conductor 205 overlaps with the insulator 250 interposed therebetween. That is, on the outside of the side of the oxide 230, the conductor 205, the insulator 250, and the conductor Preferably, the body 260 forms a laminate structure.

[0168] With the above configuration, when a potential is applied to the conductor 260 and the conductor 205, The electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected, and the oxide 2 The channel forming region formed in 30 can be electrically surrounded.

[0169] That is, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the second gate electrode The electric field of the conductor 205, which functions as an electrode, causes the channel forming region 234 can be electrically surrounded.

[0170] Also, an insulator 280 is provided to cover the oxide 230 and the insulator 273 and function as an interlayer film. The insulator 280, like the insulator 224, is preferably formed by insulating the water or hydrogen in the film. It is preferable that the concentration of impurities such as the above be reduced. It is preferable to have excess oxygen. The insulator 282 may be formed by sputtering. In addition, the insulator 282 can be provided with an insulating layer similar to the insulator 280. A rim 283 may be provided.

[0171] In addition, the openings formed in the insulators 283, 282, 280 and 273 Conductor 240a and conductor 240b are placed in the mouth. The conductors 240a and 240b are provided opposite each other with the conductor 260 in between. The height of the upper surface of 40b may be flush with the upper surface of the insulator 283.

[0172] Conductor 240a serves as one of the source and drain regions of transistor 200. The conductive material 240b is in contact with the source region of the transistor 200. The conductor 2 is in contact with the region 231b which functions as the other of the drain regions. 40a can function as one of the source and drain electrodes, and conductor 240b can function as the source The gate electrode can function as the other of the drain and gate electrodes.

[0173] The inner walls of the openings of the insulators 283, 282, 280 and 273 are A conductor 240a is formed in contact with the opening. 30 is located in region 231a, and conductor 240a contacts region 231a. The conductor 240b is formed in contact with the inner wall of the opening of the insulator 280 and the insulator 273. A region 231b of oxide 230 is located at least partially at the bottom of the opening, and a conductive layer 231b is formed on the oxide 230. The conductor 240b contacts the region 231b.

[0174] FIG. 3 is a cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. 1(A). The cross section of the region where the conductor 240a in the channel width direction of the transistor 200 and the oxide 230 come into contact is The same structure is also applied to the region where the conductor 240b and the oxide 230 contact each other. It is completed.

[0175] As shown in FIG. 3(A), the conductor 240a is in contact with at least the upper surface of the oxide 230. Furthermore, it is preferable that the conductor 240a contacts the side surface of the oxide 230. In particular, the conductor 240a is On the side surfaces of the channel 30 intersecting with the channel width direction, both the side surface on the A5 side and the side surface on the A6 side In other words, it is preferable that the conductor 240a and the oxide 230 are in contact with each other. The area where the conductive material is introduced has a cross-sectional shape like a saddle (it can be called a saddle contact). The side surface of the oxide 230 intersecting with the channel length direction of the oxide 230 is on the A1 side. The region where the conductor 240a and the oxide 230 are in contact with each other may be Not limited to the example of FIG. 3(A), for example, as shown in FIG. 3(B), the conductor 240a may be an oxide. The oxide 230 may have an area in contact with the top surface of the oxide 230 and the side surface of the A5 side of the oxide 230. , the conductor 240a is on the A1 side of the side surface intersecting with the channel length direction of the oxide 230. As shown in FIG. 3(C), the conductor 240a may be in contact with the oxidized surface. The conductive member 230 may have an area in contact with the side surface of the A6 side of the conductive member 230. Since the area of ​​the region where the conductor 240a and the oxide 230 come into contact can be increased, This is preferable because it can reduce the contact resistance between the conductor 240a and the oxide 230. This allows the source and drain electrodes of the transistor to be miniaturized while the on-state The conductor 240a can be made of tungsten, copper, or aluminum. It is preferable to use a conductive material containing silicon as the main component. It may also be constructed as such.

[0176] Here, for example, the insulators 283, 282, 280, and 273 are opened. In forming the opening, the oxide 230 is formed into a layer 24 which is a low-resistivity region of the region 231. In this case, the conductor 240 may be a metal film, a metal element, or the like. It is preferable to use a nitride film containing a metal element or an oxide film containing a metal element. When the oxide 230 contacts the conductor 240, a new low-resistance region is formed in the oxide 230. The formation of the low-resistance region reduces the contact between the oxide 230 and the conductor 240. The conductor 240 can be made of, for example, aluminum, ruthenium, or the like. It is preferable that the alloy contains a metal element such as aluminum, titanium, tantalum, or tungsten.

[0177] In addition, when the conductor 240 has a laminated structure, the insulator 283, the insulator 282, the insulator 28 The conductors in contact with the insulator 273 are the same as the first conductor of the conductor 205, etc. It is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium or ruthenium oxide It is preferable to use ruthenium or the like. In addition, in order to suppress the permeation of impurities such as water or hydrogen, The conductive material having the function of forming a conductive film may be used in a single layer or a multilayer structure. As a result, impurities such as hydrogen and water from the upper layer of the insulator 283 are absorbed into the conductor 240a and the conductor This can prevent the oxide 230 from being mixed in through the body 240b.

[0178] Although not shown, the conductive material 240a and the conductive material 240b are arranged in contact with each other on their upper surfaces. A conductor functioning as a wire may be disposed. The conductor functioning as a wiring may be made of tungsten. It is preferable to use a conductive material containing copper or aluminum as a main component. The conductor may have a laminated structure, for example, a layer of titanium, titanium nitride and the above conductive material. The conductor may be a laminated layer. Note that the conductor is provided on an insulator, similar to the conductor 203. The insulating film may be formed so as to be embedded in the opening.

[0179] <Configuration Example 2 of Semiconductor Device> FIG. 4 illustrates a transistor 200a according to one embodiment of the present invention and the surroundings of the transistor 200a. 1A and 1B are top and cross-sectional views of a side.

[0180] FIG. 4A is a top view of a semiconductor device including a transistor 200a. 4(B) and 4(C) are cross-sectional views of the semiconductor device. 4(A) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 4(A), Also, Fig. 4(C) is a cross-sectional view in the channel length direction. 1 is a cross-sectional view of the area indicated by the line, and is also a cross-sectional view of the transistor 200a in the channel width direction. In the top view of FIG. 4(A), some elements are omitted for clarity.

[0181] The semiconductor device of one embodiment of the present invention includes a transistor 200a and an insulating film serving as an interlayer film. The insulating body 210, the insulating body 212, the insulating body 280, the insulating body 282, and the insulating body 283. In addition, a conductor 203 electrically connected to the transistor 200a and functioning as a wiring, and a conductor 240 that functions as a plug.

[0182] The conductor 203 is formed so as to be embedded in the insulator 212. The height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be made to be approximately the same. 3 shows a single layer structure, but the present invention is not limited to this. For example, the conductor 203 may have a laminated structure of two or more layers. In such cases, ordinal numbers may be assigned to indicate the order of their formation to distinguish them.

[0183] The conductor 240 is also made up of an insulator 273, an insulator 280, an insulator 282, and an insulator 283. The conductor 240 is formed in contact with the inner wall of the opening. The height of the upper surface of the conductor 240 can be made to be approximately the same. Although a single layer configuration is shown, the present invention is not limited to this. For example, The conductor 240 may have a laminated structure of two or more layers. The height of the upper surface of the edge body 280 is approximately the same.

[0184] [Transistor 200a] As shown in FIG. 4, transistor 200a is an insulating semiconductor disposed on a substrate (not shown). The body 214 and the insulator 216, and the insulator 214 and the insulator 216 are embedded therein. The conductor 205 is disposed on the insulating material 216, and the insulating material 220 is disposed on the conductor 205. an insulator 222 disposed on the insulator 220; an insulator 222 disposed on the insulator 222; The insulating layer 224 and the oxide 230 (oxide 230a, oxide 230b) disposed on the insulating layer 224 are 230b, and oxide 230c), an insulator 250 disposed on the oxide 230, and an insulating Conductors 260 (conductors 260a and 260b) disposed on the substrate 250; The insulator 270 on the insulator 260, the top surface of the insulator 224, the side surface of the oxide 230a, and the oxide 2 The side of oxide 230b, the top surface of oxide 230b, the side of oxide 230c, the side of insulator 250, the conductive an insulator 273 arranged in contact with the side surface of the current collector 260 and the side surface of the insulator 270; and an insulator 275 disposed on the side of the conductor 260 via 273. The edge 273 has an opening that exposes the insulator 224, and the insulator 280 is insulated through the opening. The conductor 260 has a conductor 260a and a conductor 260b. The conductor 260a is disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in (B), the upper surface of the insulator 270 is in contact with the upper surface of the insulator 273 and the upper surface of the insulator 275. It roughly coincides with the top surface.

[0185] The transistor 200a has an insulator 270 and an insulator 275, which are different from the insulator 270 and the insulator 275. It is different from transistor 200.

[0186] The insulators 270 and 275 may be, for example, aluminum oxide or silicon oxide. , silicon oxynitride, silicon nitride oxide, and silicon nitride can be used.

[0187] The openings of the insulators 283, 282, 280 and 273 are insulating. The side of the insulator 275 is exposed. When forming the opening in the insulator 280, the etching rate of the insulator 275 is It is preferable to set the opening condition to be significantly smaller than the etching speed. The etching rate of the insulator 280 is preferably 5 or more, more preferably 1. Preferably, the number is 10 or more. By doing so, an opening can be formed in a self-aligned manner. This increases the margin for aligning the opening and the gate electrode, and the distance between the opening and the gate electrode Since the size can be designed to be small, the semiconductor device can be highly integrated. In the configuration of the transistor 200a according to one embodiment of the present invention, for example, when an opening is formed, the opening is formed in an insulator. Even if the conductor 260 is shifted to a position where it overlaps with the upper surface of the conductor 240a or conductor 270, the conductor 260 and the conductor 240b or conductor 270 can be In other words, when forming the opening, the insulating layer 240b is formed. As with insulator 275, the etch rate of insulator 270 is Therefore, the insulator 270 is made of insulator 27 The same materials as in 5 can be used.

[0188] Here, the insulating material 283, the insulating material 282, the insulating material 280, and the insulating material 273 are formed. The conductor 240a and the conductor 240b are placed in the opening. 240b are provided facing each other with the conductor 260 in between. The height of the upper surface of 240b may be flush with the upper surface of the insulator 283.

[0189] Conductor 240a serves as one of the source and drain regions of transistor 200a. The conductor 240b is in contact with the source region 231a of the transistor 200a. The region 231b functions as the other of the drain and conduction regions. Conductor 240a can function as one of a source electrode and a drain electrode, and conductor 240b can function as a source electrode. It can function as the other of the source and drain electrodes.

[0190] The inner walls of the openings of the insulators 283, 282, 280 and 273 are A conductor 240a is formed in contact with the opening. 30 is located in region 231a, and conductor 240a contacts region 231a. Conductors are disposed in contact with the inner walls of the openings of the insulators 283, 282, 280 and 273. The oxide 230 is formed on at least a portion of the bottom of the opening. The region 231b is located, and the conductor 240b contacts the region 231b.

[0191] As shown in FIG. 4B, the transistor 200a includes a conductor 260 and a conductor 2 Similarly, a parasitic capacitance is formed between the conductor 260 and the conductor 240b. The parasitic capacitance is formed between the conductor 260 and the conductor 240a (conductor By increasing the thickness of the insulator disposed between the insulating film 240b and the insulating film 240a in the channel length direction, It will be reduced.

[0192] Therefore, by providing the insulator 275 in addition to the insulator 273 in the transistor 200a, The parasitic capacitance can be reduced. The sum of the thickness in the channel length direction and the thickness in the channel length direction is the equivalent silicon oxide film thickness (EOT: Equ Isovalent Oxide Thickness) of 10nm to 50nm The thickness of the insulator 275 is preferably 15 nm to 30 nm. Aluminum, silicon oxide, silicon oxynitride, silicon nitride oxide and silicon nitride By reducing the parasitic capacitance, the transistor 200a can be operated at high speed. For other configurations, effects, etc., please refer to the description of the transistor 200. You can pour drinks.

[0193] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0194] <Substrate> The substrate on which the transistor 200 and the transistor 200a are formed may be, for example, an insulating substrate. An insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Glass substrate, quartz substrate, sapphire substrate, stabilized zirconia substrate (yttria stabilized zirconia) Silicon substrates, resin substrates, etc. are also available as semiconductor substrates. or a semiconductor substrate such as silicon carbide, silicon germanium, or arsenide. Compound semiconductor substrates made of gallium oxide, indium phosphide, zinc oxide, and gallium oxide are also available. Furthermore, the semiconductor substrate having an insulating region inside the semiconductor substrate, for example, SOI ( Silicon On Insulator (SIL) substrates are available. There are lead substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Or, there are substrates with metal nitrides. There are also substrates with metal oxides, and substrates with conductors or semiconductors on insulating substrates. Substrates provided with conductors, substrates in which conductors or insulators are provided on semiconductor substrates, and conductive substrates There are also substrates with semiconductors or insulators on them. The elements provided on the substrate may include a capacitance element, a resistance element, a switch element, and the like. These include switch elements, light-emitting elements, and memory elements.

[0195] A flexible substrate may be used as the substrate. As a method for providing the transistor, a transistor is formed on a non-flexible substrate, and then the transistor is peeled off. There is also a method of separating the substrate and transferring it to a flexible substrate. It is preferable to provide a release layer between the substrate and the transistor. The substrate may also have flexibility. The plate may have the property of returning to its original shape when the bending or stretching is stopped, or The substrate may have a property of not returning to its original shape. m or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less The thickness of the substrate is less than 1 μm. In addition, by making the substrate thinner, it is possible to reduce the weight of the device when using glass, etc. Some materials have elasticity and return to their original shape when bending or pulling is stopped. Therefore, it is necessary to reduce the shock that may be applied to the semiconductor device on the board when it is dropped. That is, a robust semiconductor device can be provided.

[0196] The flexible substrate may be made of, for example, a metal, an alloy, a resin, or glass, or any of these. These fibers can be used as the substrate. A flexible substrate with a lower linear expansion coefficient is more environmentally friendly. The substrate that is flexible is preferably a substrate having a linear expansion coefficient of 0.05 to 0.15. 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less As the resin, for example, polyester, polyolefin, polyamide ( Nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. Aramid has a low coefficient of linear expansion and is therefore suitable for use as a flexible substrate.

[0197] <Insulator> Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0198] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the physical film thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. Therefore, materials should be selected accordingly.

[0199] Insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. oxides with aluminum, aluminum and hafnium, oxides with silicon and hafnium, oxides with silicon and hafnium, Examples of suitable oxides include oxynitrides with hafnium or nitrides with silicon and hafnium.

[0200] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, Examples include silicon oxide doped with carbon and nitrogen, silicon oxide with pores, or resin. do.

[0201] In particular, silicon oxide and silicon oxynitride are thermally stable. For example, by combining it with resin, it is possible to create a laminated structure that is thermally stable and has a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon), Polyimide, polycarbonate, acrylic, etc. For example, silicon oxide and silicon oxynitride can be combined with insulators with high dielectric constants. By doing so, it is possible to obtain a laminated structure that is thermally stable and has a high relative dielectric constant.

[0202] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the This can be done.

[0203] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttria oxide ammonium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tungsten oxide Metal oxides such as talc, silicon nitride oxide, silicon nitride, etc. can be used. .

[0204] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Even if the hafnium oxide is used, it is possible to suppress the diffusion of hydrogen and nitrogen. Although the barrier properties are lower than those of aluminum oxide, the barrier properties can be improved by increasing the film thickness. Therefore, by adjusting the thickness of the hafnium oxide film, it is possible to The amount of addition can be adjusted appropriately.

[0205] For example, the insulator 224 and the insulator 250, which function as part of the gate insulator, may be formed by excess It is preferable to use an insulator having an oxygen region. For example, silicon oxide having an excess oxygen region. By making the silicon or silicon oxynitride contact with the oxide 230, the oxide 230 The oxygen deficiency can be compensated for.

[0206] Also, for example, in the insulator 222 that functions as part of the gate insulator, aluminum The insulator may include one or more oxides of aluminum, hafnium, and gallium. In particular, insulators containing oxides of either or both aluminum and hafnium Examples include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium. It is preferable to use a material such as hafnium aluminate.

[0207] For example, the insulator 220 may be made of silicon oxide or silicon oxynitride, which is stable against heat. It is preferable to use a gate insulator that is a combination of a thermally stable film and a film with a high dielectric constant. By using a laminated structure with OT) can be made thinner.

[0208] By using the above stacked structure, the on-current can be reduced without weakening the influence of the electric field from the gate electrode. In addition, the physical thickness of the gate insulator allows the gate electrode and By keeping the distance between the gate electrode and the region where the channel is formed, The leakage current between the two electrodes can be suppressed.

[0209] Insulator 212, insulator 216, insulator 270, insulator 275, insulator 280 and insulator The insulator 283 preferably has a low dielectric constant. The insulator 216, the insulator 270, the insulator 275, the insulator 280 and the insulator 283 are made of oxide silicon. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine silicon, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, vacancy-free It is preferable that the insulating material 212 has silicon oxide or resin. The insulator 216, the insulator 270, the insulator 275, the insulator 280 and the insulator 283 are made of oxide silicon. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine Silicon, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide or vacant It is preferable that the silicon oxide layer has a laminated structure of silicon oxide having holes and a resin. Silicon oxynitride is thermally stable, so when combined with resin, A laminated structure that is stable and has a low dielectric constant can be obtained. Polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate Carbonate or acrylic.

[0210] As insulator 210, insulator 214, insulator 222, insulator 273 and insulator 282 For the insulating layer, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used. The insulators 210, 214, 222, 273 and 282 include , for example, aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, oxide Germanium, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide or If a metal oxide such as tantalum oxide, silicon nitride oxide, or silicon nitride is used, good.

[0211] <Conductors> Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Metal elements selected from sodium, zirconium, beryllium, indium, ruthenium, etc. In addition, a polycrystalline material containing impurity elements such as phosphorus can be used. Semiconductors with high electrical conductivity, such as crystalline silicon, and silicides such as nickel silicide A code may also be used.

[0212] Alternatively, a plurality of conductive layers made of the above materials may be stacked. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated layer that combines the material containing the metal element and the conductive material containing nitrogen is also available. In addition, a material containing the above-mentioned metal element, a conductive material containing oxygen, and a material containing nitrogen may be used. A laminated structure may be formed by combining a conductive material containing a silicon dioxide.

[0213] When an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminated structure in which a conductive material containing oxygen is used. It is preferable to provide the conductive material containing oxygen on the channel forming region side. This makes it easier for oxygen released from the conductive material to be supplied to the channel formation region.

[0214] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate electrode. It is preferable to use a conductive material containing a metal element and oxygen. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. Alternatively, a conductive material containing nitrogen, such as indium tin oxide or tungsten oxide, may be used. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may also be used. By using such a material, the channel is formed. In some cases, hydrogen contained in the metal oxides surrounding the outer insulating layer can be captured. It may be possible to capture hydrogen that is mixed in from the surroundings.

[0215] The conductors 260, 203, 205, and 240 are made of aluminum. Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten Iron, hafnium, vanadium, niobium, manganese, magnesium, zirconium, Use a material containing one or more metal elements selected from the group consisting of sodium, indium, and ruthenium. In addition, it is possible to use polycrystalline silicon containing impurity elements such as phosphorus. Semiconductors with high electrical conductivity, silicides such as nickel silicide, etc. may also be used.

[0216] <Metal oxides> The oxide 230 is a metal oxide that functions as an oxide semiconductor (hereinafter referred to as an oxide semiconductor). It is preferable to use a metal oxide 230 according to the present invention. The metal oxides will be explained.

[0217] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, titanium, iron, etc. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or Or, multiple types may be included.

[0218] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, titanium, iron, and nickel. Kel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium However, the element M is In some cases, a combination of the above elements may be used.

[0219] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0220] [Metal oxide composition] Hereinafter, a CAC (C This paper explains the structure of the Cloud-Aligned Composite OS.

[0221] In this specification, CAAC (c-axis aligned crystal) l), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. An example is shown below.

[0222] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has insulating properties in some parts and semiconductor properties in the whole material. Note that CAC-OS or CAC-metal oxide is used as the active material for the transistor. When used in a layer, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making these functions work in a complementary manner, the switching function (On / Off) The function of making the CAC-OS or CAC-metal oxide In CAC-OS or CAC-metal oxide, the respective functions By separating the two, the functions of both can be maximized.

[0223] In addition, CAC-OS or CAC-metal oxide is a conductive area and an insulating area. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive and insulating regions in the material are formed by nanoparticles. The conductive region and the insulating region may be separated by different materials. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0224] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0225] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, when carriers flow, In addition, carriers mainly flow in the narrow gap component. The component with a narrow gap acts complementary to the component with a wide gap. Carriers also flow into the wide-gap component in conjunction with the component that has a wide gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field-effect mobility can be obtained.

[0226] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0227] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c- axis aligned crystalline oxide semiconductor ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox ide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS : amorphous-like oxide semiconductor) and non crystalline oxide semiconductors.

[0228] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the point where the direction of the

[0229] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is difficult to confirm the crystal structure (also called "undary") due to the distortion of the lattice arrangement. This is because the CAAC-OS is aligned in the ab-plane direction. In this case, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated by changing the

[0230] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). It is noted that indium and element M tend to have a structure (also called a layered structure). When the element M in the (M,Zn) layer is replaced with indium, the (In,M,Zn) ) layer. Also, when indium in the In layer is replaced with element M, it can be expressed as (In, It can also be expressed as the M layer.

[0231] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS is designed to avoid impurities and defects (oxygen vacancies (Vo)). Therefore, CAAC- Metal oxides with OS have stable physical properties. Metal oxides are heat resistant and highly reliable.

[0232] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the body.

[0233] Indium gallium oxide, a type of metal oxide containing indium, gallium, and zinc, is used. The IGZO nanocrystals mentioned above are stable. In particular, IGZO tends to have difficulty growing crystals in the atmosphere. Therefore, small crystals (e.g., the above-mentioned crystals) are more suitable than large crystals (here, several mm or several cm). Nanocrystals may be structurally more stable.

[0234] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low density regions. The ke-OS has lower crystallinity than the nc-OS and CAAC-OS.

[0235] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention may be an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li The ke-OS, nc-OS, and CAAC-OS may have two or more of them.

[0236] [Transistors with metal oxides] Next, the case where the above metal oxide is used for a channel formation region of a transistor will be described. do.

[0237] Note that by using the above metal oxide for the channel formation region of a transistor, a high field efficiency can be achieved. It is possible to realize a transistor with high mobility. It can be realized.

[0238] It is also preferable to use a metal oxide with a low carrier density for the transistor. When the carrier density of the metal oxide film is reduced, the impurity concentration in the metal oxide film is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. A low level density is called high purity intrinsic or substantially high purity intrinsic. For example, metal oxides , the carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all. stomach.

[0239] Furthermore, a highly pure intrinsic or substantially highly pure intrinsic metal oxide film has a low density of defect states. Therefore, the trap level density may also be low.

[0240] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, the trap level density is high. A transistor having a metal oxide in a channel formation region may have unstable electrical characteristics. be.

[0241] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide must be kept low. In order to reduce the impurity concentration in the metal oxide, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0242] In addition, a thin film with high crystallinity is used as the metal oxide semiconductor for the transistor. The use of the thin film improves the stability or reliability of the transistor. The thin film may be, for example, a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide. However, thin films of single crystal metal oxides or thin films of polycrystalline metal oxides are also available. To form a thin film on a substrate, a high temperature or laser heating process is required. This increases the cost of the manufacturing process and also reduces throughput.

[0243] In 2009, we developed an In-Ga-Zn oxide (CAAC-IGZO) with a CAAC structure. The discovery of a new compound called 'anti-cancer drug' has been reported in Non-Patent Documents 1 and 2. CAAC-IGZO has a c-axis orientation, the grain boundaries are not clearly visible, and it can be grown at low temperatures. It has been reported that it is possible to form a thin film on a substrate using CAAC-IGZO. The resulting transistors have been reported to have excellent electrical properties and reliability.

[0244] In 2013, we also developed an In-Ga-Zn oxide (nc-IGZO) with an nc structure. Here, nc-IGZO is a material that can be grown in minute regions ( For example, the atomic arrangement has periodicity in the region of 1 nm or more and 3 nm or less, and It has been reported that no regularity is observed in the crystal orientation between the two.

[0245] In Non-Patent Documents 4 and 5, the above-mentioned CAAC-IGZO, nc-IGZO, The average crystal size of IGZO thin films and low-crystalline IGZO thin films was measured by electron beam irradiation. The change in the thickness is shown in Fig. 1. In a thin film of IGZO with low crystallinity, before the electron beam irradiation, Even in thin films, crystalline IGZO of about 1 nm has been observed. In this case, completely amorphous structure Furthermore, it has been reported that the presence of IGZO with low crystallinity could not be confirmed. Compared with the thin films of CAAC-IGZO and nc-IGZO, the thin films of CAAC-IGZO and nc-IGZO are more resistant to electron beam irradiation. Therefore, CAA is a promising semiconductor for transistors. It is preferable to use a thin film of C-IGZO or a thin film of nc-IGZO.

[0246] Transistors using metal oxides have extremely low leakage current when they are off. Specifically, the off-state current per 1 μm of the transistor channel width is yA / μm (10 -2 4 A / μm) order is shown in Non-Patent Document 6. For example, Low-power CPUs that utilize the low leakage current characteristics of the transistors used It has been disclosed (see Non-Patent Document 7).

[0247] In addition, the leakage current of a transistor using a metal oxide is low. The application of transistors to display devices has been reported (see Non-Patent Document 8). The displayed image changes several dozen times per second. The refresh rate is also called the drive frequency. Such high-speed screen switching, which is difficult for the human eye to perceive, is the cause of eye fatigue. Therefore, the refresh rate of the display device is reduced to improve image clarity. It has been proposed to reduce the number of times the display is rewritten. This driving method can reduce the power consumption of the display device. This is called idling stop (IDS) drive.

[0248] The discovery of the CAAC and nc structures was based on the discovery of metal oxides with the CAAC or nc structures. The electrical characteristics and reliability of the transistor using the material are improved, and the manufacturing process cost is reduced. This contributes to improving throughput and reducing power consumption. Taking advantage of this property, research into the application of this transistor to display devices and LSIs is underway. are.

[0249] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0250] When metal oxides contain silicon or carbon, which are elements of Group 14, they become metal oxides. Defect levels are formed in the oxides. This leads to the formation of silicon and carbon concentrations in the metal oxides. The concentration of silicon and carbon near the interface with the metal oxide was measured by secondary ion mass spectrometry (SIM). S: Secondary Ion Mass Spectrometry) concentration) is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0251] In addition, when alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor that uses a metal oxide containing metals in the channel formation region is normally on. Therefore, the concentration of alkali metals or alkaline earth metals in metal oxides It is preferable to reduce the degree of Al in the metal oxide obtained by SIMS. The concentration of potassium metal or alkaline earth metal is 1×10 18 atoms / cm 3 Below, I prefer Or 2 x 10 16 atoms / cm 3 Do the following:

[0252] In addition, when nitrogen is contained in a metal oxide, electrons that act as carriers are generated, and the carriers As a result, the density increases and it becomes easier to make the metal oxide containing nitrogen into a channel type. The transistors used in the metal-doped region tend to be normally-on. In the oxide, it is preferable that the nitrogen content in the channel formation region is reduced as much as possible. For example, the nitrogen concentration in metal oxides is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following .

[0253] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electrons acting as carriers are released. In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, metal oxides containing hydrogen can be used The transistor tends to have normally-on characteristics.

[0254] In addition, hydrogen contained in metal oxides is generated at shallow defect levels (sDOS) in the metal oxides. Low level Density of States may be formed. The shallow defect level refers to the interface state located near the bottom of the conduction band. It is estimated that it exists near the boundary between the high density region and the low density region in the oxide. High density and low density regions in metal oxides are distinguished by the amount of hydrogen contained in the regions. That is, the high density region contains more hydrogen than the low density region. The area near the boundary between the high density and low density regions in the center is subject to microcracks due to the stress and strain between the two regions. This tends to cause oxygen deficiency and indium dangling bonds near the cracks. However, when impurities such as hydrogen or water are localized here, shallow defect levels are formed. It is estimated that.

[0255] Furthermore, the high density regions in the metal oxide may be more crystalline than the low density regions. Furthermore, the high density region in the metal oxide may have a higher film density than the low density region. Furthermore, when the metal oxide has a composition containing indium, gallium, and zinc, The high density region comprises indium, gallium, and zinc, and the low density region comprises indium. In other words, the low density region may have more gallium than the high density region. The proportion of um may be low.

[0256] The shallow defect level is presumed to be caused by oxygen vacancies. As the loss increases, the density of shallow defect states as well as the density of deep defect states (dDOS) increases. It is estimated that the veloci- cal density of states will also increase. This is because the deep defect level is also thought to be due to oxygen vacancies. This refers to a defect level located near the center of the band gap.

[0257] Therefore, by suppressing oxygen vacancies in metal oxides, shallow and deep defect levels can be reduced. It is possible to reduce the density of both shallow defect levels. It may be possible to control this to some extent by adjusting the temperature during metal oxide film formation. The temperature during the deposition of the metal oxide is set to 170°C or thereabouts, preferably 130°C or By setting the temperature at around that temperature, or more preferably at room temperature, the density of shallow defect levels can be reduced. do.

[0258] In addition, the shallow defect levels of metal oxides are It affects the electrical characteristics. That is, the shallow defect level reduces the drain current of the transistor. In the gate voltage (Id-Vg) characteristics, the change in drain current Id with respect to gate voltage Vg The transition from the OFF state to the ON state of the transistor becomes gradual, and the transition from the OFF state to the ON state becomes The S value (also called Subthreshold Swing, SS), which is one of the indicators of This is thought to be due to electrons being trapped in shallow defect levels.

[0259] For this reason, it is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. is the hydrogen concentration obtained by SIMS in metal oxides, expressed as 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than 5x1 0 18 atoms / cm 3less than 1×10 18 atoms / cm 3 less than A metal oxide with sufficiently reduced impurities is used for the channel formation region of a transistor. By doing so, stable electrical properties can be imparted.

[0260] [Effect of vacuum baking] Here, we explain the weak Zn-O bond contained in metal oxides and the components that make up this bond. An example of a method for reducing the amount of oxygen and zinc atoms present will be described below.

[0261] In transistors using metal oxides, defects that lead to poor electrical characteristics of the transistors An example of such a defect is oxygen vacancy. For example, a metal oxide film containing oxygen vacancies is used. The threshold voltage of the transistor tends to shift in the negative direction, and the normally-on characteristics This is because donors are generated due to oxygen vacancies in the metal oxide, This is because the carrier concentration increases. There are various issues, such as malfunctions occurring more frequently and power consumption increasing when not in operation. A problem arises.

[0262] In addition, the thermal history in the process of forming the connection wiring for manufacturing the module The transistor's electrical characteristics, such as threshold voltage fluctuations and increased parasitic resistance, are affected by the This causes problems such as deterioration of electrical characteristics and an increase in the variation in electrical characteristics due to the deterioration of electrical characteristics. These problems directly lead to a decrease in manufacturing yield, so it is important to consider countermeasures. It is possible to quickly evaluate the change in transistor characteristics (aging) that occurs during use. The electrical characteristics deteriorate even in stress tests that can be performed during the manufacturing process. Metal oxidation occurs due to high temperature treatment or electrical stress applied during stress testing. It is presumed that this is due to a lack of oxygen in the material.

[0263] Metal oxides contain oxygen atoms that are weakly bonded to metal atoms and are prone to oxygen deficiency. In particular, when the metal oxide is an In-Ga-Zn oxide, zinc atoms and oxygen atoms It is easy to form weak bonds (also called weak Zn-O bonds). This is due to high temperature processing during manufacturing or electrical stress applied during stress testing. The bond between a zinc atom and an oxygen atom is strong enough to be broken by a force. When weak Zn-O bonds exist in metal oxides, they can be easily broken down by thermal history or current stress. The bond is broken and oxygen vacancies are formed. The stability of the transistor, such as its resistance to heat and electrical stress, is reduced. do.

[0264] The bond between the oxygen atom that is bonded to the zinc atom and the zinc atom is weak Zn -O bond. Compared to gallium atoms, zinc atoms have weaker bonds with oxygen atoms. Therefore, oxygen atoms that are bonded to many zinc atoms are easily lost. The bond that forms between the atom and the oxygen atom is presumably weaker than the bond with other metals.

[0265] In addition, it is thought that when impurities exist in metal oxides, weak Zn-O bonds are more likely to form. Impurities in metal oxides include, for example, water molecules and hydrogen. When water molecules and hydrogen exist in the metal oxide, the hydrogen atoms bond with the oxygen atoms that make up the metal oxide. The oxygen atoms that make up the metal oxides are sometimes called In-Ga-Z n When the oxide is a single crystal, it is bonded to four metal atoms that make up the metal oxide. However, when an oxygen atom bonded to a hydrogen atom is bonded to two or three metal atoms, When the number of metal atoms bonded to an oxygen atom decreases, the oxygen atom is lost. In addition, when a zinc atom is bonded to an oxygen atom that forms an OH bond, The bond between the oxygen atom and the zinc atom is presumed to be weak.

[0266] In addition, weak Zn-O bonds are formed in the strain that exists in the region where multiple nanocrystals are connected. Nanocrystals are basically hexagonal, but in this distortion, pentagonal and heptagonal In this distortion, the bond distance between atoms is not uniform, resulting in weak Zn It is presumed that an -O bond is formed.

[0267] It is also speculated that weak Zn-O bonds are more likely to form when the crystallinity of the metal oxide is low. When the crystallinity of a metal oxide is high, the zinc atoms that make up the metal oxide are separated by four oxygen atoms. However, when the crystallinity of the metal oxide decreases, the zinc atoms bond to the The number of oxygen atoms bonded to the zinc atom tends to decrease. In other words, the bond formed between the zinc atom and the oxygen atom is , which is presumed to be weaker than the bonds that occur in single crystals.

[0268] By reducing the oxygen and zinc atoms that make up the weak Zn-O bonds, Or it suppresses the formation of oxygen vacancies due to electrical stress, improving the stability of transistors. It is possible to reduce only the oxygen atoms that make up the weak Zn-O bond. When the zinc atom constituting the O bond does not decrease, supplying an oxygen atom near the zinc atom results in Weak Zn-O bonds may be reformed. Therefore, It is preferable to reduce the zinc and oxygen atoms.

[0269] One method to reduce the oxygen and zinc atoms that make up the weak Zn-O bond is to After forming a metal oxide film, vacuum baking is performed. This is a heat treatment performed under a vacuum atmosphere. The vacuum atmosphere is evacuated using a turbo molecular pump or similar. The pressure in the processing chamber is maintained at 1×10 -2 Pa or less, preferably 1×10 -3 The substrate temperature during the heat treatment is preferably 300° C. or higher. The temperature should be 400°C or higher.

[0270] By performing vacuum baking, oxygen atoms and zinc atoms that make up the weak Zn-O bond are In addition, the vacuum baking process provides heat to the metal oxide, which reduces the After reducing the oxygen and zinc atoms that form the Zn-O bond, the metal oxide is formed. The atoms are rearranged, and the number of oxygen atoms bonded to four metal atoms increases. , reducing the oxygen and zinc atoms that make up the weak Zn-O bond, and The reformation of O bonds can be inhibited.

[0271] In addition, if impurities exist in the metal oxide, vacuum baking can be performed to remove the impurities from the metal oxide. It can release water molecules or hydrogen in the substance and reduce the OH bond. The reduction in H-bonds increases the proportion of oxygen atoms bonded to four metal atoms. When water molecules or hydrogen are released, the atoms that make up the metal oxide rearrange, resulting in 4 There are more oxygen atoms bonded to each metal atom, so the weak Zn-O bond is reformed. This can prevent the risk of this happening.

[0272] As described above, by performing vacuum baking after forming a metal oxide film, a weak Zn-O The oxygen atoms and zinc atoms that form the bonds can be reduced. This can improve the stability of the transistor. This increases the freedom of choice of materials and forming methods.

[0273] <Method 1 for manufacturing semiconductor device> Next, a semiconductor device having a transistor 200 according to the present invention shown in FIG. 1 will be fabricated. The manufacturing method will be described with reference to Figs. 6 to 20. In Figs. 6 to 20, (A ) shows a top view. Also, (B) of each figure shows the part indicated by the dashed line A1-A2 in (A). 1. This is a cross-sectional view corresponding to the position of the transistor 200, and is also a cross-sectional view taken along the channel length direction of the transistor 200. In addition, (C) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A). 1 and 2, which are cross-sectional views of the transistor 200 in the channel width direction. In the figure, some elements have been omitted for clarity.

[0274] First, a substrate (not shown) is prepared, and an insulator 210 is formed on the substrate. The film formation of 10 is carried out by sputtering, chemical vapor deposition (CVD), r Deposition), molecular beam epitaxy (MBE) beam epitaxy, pulsed laser deposition (PLD) Deposition) method or ALD (Atomic Layer Deposit) This can be done using the ion method or the like.

[0275] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0276] The plasma CVD method can produce high-quality films at relatively low temperatures. This film formation method does not use a plasma, so it is possible to reduce plasma damage to the object being treated. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc. included in a semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage occurs. In addition, the thermal CVD method can increase the yield of semiconductor devices. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0277] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with fewer defects can be produced. It should be noted that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by ALD have a higher thermal conductivity than films formed by other deposition methods. It may contain a large amount of impurities such as carbon. The quantity of impurities is determined by X-ray photoelectron spectroscopy ( XPS (X-ray Photoelectron Spectroscopy) This can be done.

[0278] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is less affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it suitable for forming thin films with high aspect ratios. However, the ALD method is relatively slow in forming films. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a high deposition rate. may be preferable.

[0279] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having the following composition. By changing the flow rate ratio of the source gases while oxidizing, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film using a vacuum, the time required for film formation is shorter because there is no time required for transport or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. There is.

[0280] In this embodiment, the insulator 210 is formed by sputtering aluminum oxide. The insulator 210 may have a multi-layer structure. For example, a sputtering method is used. Then, an aluminum oxide film is formed by the ALD method. Alternatively, aluminum oxide may be deposited by the ALD method. A film of aluminum oxide is formed on the aluminum oxide by a sputtering method. A membrane structure may also be used.

[0281] Next, a conductive film that will become the conductor 203 is formed on the insulator 210. The deposition of the conductive film can be performed by sputtering, CVD, MBE, PLD or ALD. The conductive film that becomes the conductor 203 may be a multilayer film. In this embodiment, a tungsten film is formed as the conductive film to be the conductor 203.

[0282] Next, a conductive film that will become the conductor 203 is processed using lithography. Form.

[0283] In the lithography method, first, the resist is exposed to light through a mask. The resist mask is formed by removing or leaving the resist patterned area using a developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. For example, KrF excimer laser light, ArF excimer laser light, Laser light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the substrate to light. An immersion technique may be used in which the substrate is filled with a liquid (for example, water) and exposed to light. Alternatively, an electron beam or an ion beam may be used. In this case, the mask is not required. Which dry etching process should be performed, which wet etching process should be performed, and which dry etching process should be performed? wet etching after treatment, or wet etching after dry etching A processing can be performed.

[0284] In addition, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating layer that is a hard mask material is formed on the conductive film that is to be the conductor 203. An insulating film or a conductive film is formed, a resist mask is formed on it, and a hard mask material is etched. By this etching, a hard mask of a desired shape can be formed. The etching of the conductive film may be carried out after removing the resist mask, or after removing the resist mask. In the latter case, the resist mask may be removed during etching. After etching the conductive film that becomes the conductor 203, the hard mask is removed by etching. On the other hand, if the hard mask material does not affect the subsequent process or can be used in the subsequent process, If the hard mask can be removed, it is not necessary to remove the hard mask.

[0285] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. (Capacitively Coupled Plasma) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the parallel plate type electrodes. Alternatively, a parallel plate electrode may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching device or the like can be used.

[0286] Next, an insulating film that will become the insulator 212 is formed on the insulator 210 and the conductor 203. The insulating film that becomes the body 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or the like. In this embodiment, the insulating layer 212 is formed by the ALD method. The film is formed by depositing silicon oxide using the CVD method.

[0287] Here, the thickness of the insulating film that becomes the insulator 212 is preferably equal to or greater than the thickness of the conductor 203. For example, if the thickness of the conductor 203 is 1, the thickness of the insulating film that becomes the insulator 212 is In this embodiment, the thickness of the conductor 203 is set to 150 nm. The thickness of the insulating film that becomes the insulator 212 is set to 350 nm.

[0288] Next, the insulating film that will become the insulator 212 is subjected to CMP (chemical mechanical polishing). By performing a polishing process, a part of the insulating film that will become the insulator 212 is removed. The surface of the conductor 203 is exposed. This allows the conductor 203 and the insulator 204 to be separated into a flat upper surface. 212 can be formed (see FIG. 6).

[0289] Here, a method for forming the conductor 203 that is different from the above will be described below.

[0290] An insulator 212 is deposited on the insulator 210. The insulator 212 is deposited by a sputtering method. The deposition can be carried out by using a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0291] Next, an opening is formed in the insulator 212, reaching the insulator 210. The opening may be, for example, a groove or This also includes slits. The area where an opening is formed may also be referred to as an opening. The openings may be formed by wet etching, but it is more preferable to use dry etching. Insulator 210 is preferably formed by etching insulator 212 to form grooves. It is preferable to select an insulator that functions as an etching stopper film when etching. When a silicon oxide film is used for the insulator 212 forming the groove, the insulator 210 is made of silicon nitride. It is preferable to use a tantalum oxide film, an aluminum oxide film, or a hafnium oxide film.

[0292] After the opening is formed, a conductive film is formed to become the conductor 203. The conductive film has properties to suppress the permeation of oxygen. It is desirable to include a conductor having a function of controlling the temperature. For example, tantalum nitride, tungsten nitride, etc. Titanium, titanium nitride, etc. can also be used. Alternatively, tantalum, tungsten, titanium , molybdenum, aluminum, copper, molybdenum-tungsten alloy and laminated film. The conductive film that becomes the conductor 203 can be formed by a sputtering method, a CVD method, an MBE method, or the like. This can be carried out using a PLD method, an ALD method, or the like.

[0293] In this embodiment, the conductive film that becomes the conductor 203 has a multi-layer structure. A tantalum nitride film is formed by a coating method. Alternatively, titanium nitride is stacked on the tantalum nitride. Such a metal nitride is used as the lower layer of the conductive film that will become the conductor 203. This allows copper and the like to be easily diffused as an upper conductive film of the conductive film that will become the conductor 203 described later. Even if a thin metal is used, the metal can be prevented from diffusing out of the conductor 203.

[0294] Next, a conductive film is formed on the conductive film that will become the conductor 203. The conductive film is formed by plating. The method is performed using the deposition method, sputtering method, CVD method, MBE method, PLD method, or ALD method. In this embodiment, the conductive film on the conductive film that becomes the conductor 203 is A film of a low resistance conductive material such as copper is deposited.

[0295] Next, by performing CMP processing, the upper layer of the conductive film that will become the conductor 203 and the conductive film that will become the conductor 2 A part of the lower layer of the conductive film 03 is removed to expose the insulator 212. Only the conductive film that will become the conductor 203 remains. It should be noted that the CMP process removes a part of the insulator 212. The above are the different methods for forming the conductor 203.

[0296] Next, the insulator 214 is formed on the insulator 212 and the conductor 203. The film is formed using the sputtering method, CVD method, MBE method, PLD method, or ALD method. In this embodiment, the insulator 214 is made of nitride by the CVD method. In this way, a silicon film is formed as the insulator 214, which is made of silicon nitride or the like through which copper is transmitted. By using an insulator that is difficult to diffuse, the second conductor of the conductor 203 is free from a metal that is easily diffused, such as copper. The use of metals can also prevent the metals from diffusing into layers above the insulator 214. .

[0297] Next, the insulator 216 is deposited on the insulator 214. The insulator 216 is deposited by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the insulator 216 is formed by depositing silicon oxide by the CVD method.

[0298] Next, openings are formed in the insulators 214 and 216 to reach the conductors 203. The opening may be formed by wet etching, but it is more preferable to use dry etching. is preferable for microfabrication.

[0299] After the opening is formed, a conductive film that will become the conductor 205a is formed. The film preferably contains a conductive material that has the function of suppressing oxygen permeation. Tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. , tungsten, titanium, molybdenum, aluminum, copper, molybdenum-tungsten alloy The conductive film that becomes the conductor 205a can be formed by sputtering. The deposition can be carried out by using a method such as a CVD method, an MBE method, a PLD method, or an ALD method.

[0300] In this embodiment, a conductive film that becomes the conductor 205a is formed by sputtering a nitride film. A tantalum chloride film is formed.

[0301] Next, a conductive film that will become the conductor 205b is formed on the conductive film that will become the conductor 205a. The conductive film is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. This can be done using, for example.

[0302] In this embodiment, the conductive film that becomes the conductor 205b is formed by depositing titanium nitride by the CVD method. A film of titanium nitride is formed, and then a film of tungsten is formed on the titanium nitride by the CVD method.

[0303] Next, a CMP process is performed to remove the conductive film that will become the conductor 205a and the conductive film that will become the conductor 205. A portion of the conductive film that will become b is removed to expose the insulator 216. As a result, the conductive film is left only in the opening. The conductive film that will become the conductor 205a and the conductive film that will become the conductor 205b remain. forming a conductor 205 having a flat top surface, the conductor 205 including the conductor 205a and the conductor 205b; (See FIG. 6.) Note that the CMP process removes a part of the insulator 216. There are cases where this happens.

[0304] Next, the insulator 220 is formed on the insulator 216 and the conductor 205. The film is formed using the sputtering method, CVD method, MBE method, PLD method, or ALD method. In this embodiment, the insulator 220 is made of an oxide film formed by a CVD method. Silicon is deposited.

[0305] Next, an insulator 222 is formed on the insulator 220. The insulator 222 is made of aluminum. It is preferable to form an insulator containing oxides of either or both of aluminum and hafnium. As an insulator containing oxides of one or both of aluminum and hafnium, aluminum oxide Hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminum It is preferable to use aluminum and / or hafnium. The insulator containing the oxide has a barrier property against oxygen, hydrogen, and water. 2 has a barrier property against hydrogen and water, and therefore, it is possible to The hydrogen and water contained in the structure pass through the insulator 222 to the transistor 200. Inward diffusion is suppressed, and the generation of oxygen vacancies in the oxide 230 can be suppressed. do.

[0306] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an A method. This can be done using the LD method or the like.

[0307] Next, an insulating film 224A is formed on the insulator 222. The insulating film 224A is formed by sputtering. This can be done using methods such as deposition, CVD, MBE, PLD, or ALD. In this embodiment, the insulating film 224A is formed by CVD using an oxide film. Silicon is deposited.

[0308] Subsequently, it is preferable to carry out a heat treatment. The heat treatment is preferably carried out at a temperature of 250°C or higher and 650°C or lower. Preferably, the temperature is 300°C or higher and 500°C or lower, more preferably 320°C or higher and 450°C or lower. Heat treatment should be carried out in a nitrogen or inert gas atmosphere, or in an atmosphere containing oxidizing gases at a concentration of 10 ppm or less. The heat treatment is carried out in an atmosphere containing 1% or more, or 10% or more. Alternatively, the heat treatment may be performed in a nitrogen or inert gas atmosphere, followed by desorption. To compensate for the lost oxygen, an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas is used. The heat treatment may be carried out in an atmosphere.

[0309] In this embodiment, after the insulating film 224A is formed, the insulating film 224A is heated at 400° C. for 1 hour in a nitrogen atmosphere. The heat treatment is carried out to remove impurities such as hydrogen and water contained in the insulating film 224A. It is possible to remove impurities.

[0310] The heat treatment is performed after the formation of the insulator 220 and after the formation of the insulator 222. The heat treatment can be carried out under the above-mentioned heat treatment conditions. However, the heat treatment after the formation of the insulator 220 is preferably performed in an atmosphere containing nitrogen.

[0311] Here, in order to form an excess oxygen region in the insulating film 224A, a plasma containing oxygen is used under reduced pressure. The oxygen-containing plasma treatment may be performed using, for example, a high-density microwave plasma. It is preferable to use a device having a power source for generating plasma. Alternatively, RF is applied to the substrate side. The plasma may have a power source that applies radio frequency (RF) to generate high density plasma. By using this, high density oxygen radicals can be generated, and by applying RF to the substrate side, By doing so, oxygen radicals generated by high density plasma are efficiently released into the insulating film 224A. Alternatively, a plasma treatment containing an inert gas can be carried out using this apparatus. After that, a plasma treatment containing oxygen may be performed to compensate for the desorbed oxygen. By appropriately selecting the conditions for the plasma treatment, hydrogen and water contained in the insulating film 224A can be removed. Impurities can be removed, in which case heat treatment is not necessary.

[0312] Next, an oxide film 230A and an oxide film 230B are formed in this order on the insulating film 224A (FIG. 6). It is preferable that the oxide film be formed continuously without exposing it to the air environment. By forming the film without exposing it to the atmosphere, the oxide film 230A and the oxide film 230B are not exposed to the atmosphere. The oxide film 230A and the oxide film 230B can be prevented from being adhered to the oxide film 230A. The area around the interface with B can be kept clean.

[0313] The oxide film 230A and the oxide film 230B are formed by sputtering, CVD, MBE, or the like. The method can be carried out using a PLD method, an ALD method, or the like.

[0314] For example, the oxide film 230A and the oxide film 230B are formed by sputtering. In this case, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the oxygen ratio in the sputtering gas, the excess oxygen in the oxide film to be formed can be reduced. In addition, when the oxide film is formed by sputtering, In this case, the above-mentioned In-M-Zn oxide target can be used.

[0315] In particular, when forming the oxide film 230A, part of the oxygen contained in the sputtering gas is converted into the insulating film. Therefore, the sputtering gas for the oxide film 230A may be supplied to the The oxygen content is 70% or more, preferably 80% or more, and more preferably 100%. That's fine.

[0316] In addition, when the oxide film 230B is formed by sputtering, the oxide film 230B is formed by sputtering. The film is formed by setting the ratio of oxygen to be added at 1% or more and 30% or less, preferably 5% or more and 20% or less. The oxygen-deficient oxide semiconductor is formed in the channel formation region. A transistor used in this region can achieve relatively high field-effect mobility.

[0317] In this embodiment, the oxide film 230A is formed by sputtering In:Ga: The target was Zn = 1:1:0.5 (2:2:1) In addition, the oxide film 230B is formed by sputtering In:Ga:Zn= 4:2:2 [atomic ratio], 4:2:1 [atomic ratio], or 4:2:0 [atomic ratio] ( The film is formed using a target of In:Ga=4:2 (atomic ratio). By appropriately selecting the film formation conditions and atomic ratio, the properties required for oxide 230 can be achieved. It is recommended to form it as follows.

[0318] Next, a heat treatment may be carried out. The heat treatment may be carried out under the heat treatment conditions described above. By the heat treatment, impurities such as hydrogen and water in the oxide film 230A and the oxide film 230B are removed. In this embodiment, the wafer is heated at 400° C. in a nitrogen atmosphere. After one hour of treatment, the sample was treated in an oxygen atmosphere at 400°C for one hour. cormorant.

[0319] Next, the oxide film 230A and the oxide film 230B are processed into islands to form oxides 230a and In this step, the oxide 230b of the insulating film 224A is formed. The thickness of the region not overlapping with the oxide 230a of the insulating film 224A is thinner than the region overlapping with the oxide 230a of the insulating film 224A. The insulator 224 may be formed so that the thickness is smaller (see FIG. 7).

[0320] Here, the oxide 230a and the oxide 230b are at least partially connected to the conductor 205. The oxide 230a and the oxide 230b are formed so as to overlap each other. It is preferable that the oxide 230a and the oxide 222 are approximately perpendicular to the upper surface of the oxide 230a. The side surface of the insulator 222 is substantially perpendicular to the upper surface of the insulator 222, so that the plurality of transistors When providing the capacitor 200, it is possible to reduce the area and increase the density. Alternatively, the angle between the side surface of the oxide 230b and the top surface of the insulator 222 may be acute. In this case, the side surfaces of the oxide 230a and oxide 230b and the top surface of the insulator 222 are The angle is preferably between 60° and 70°. By using such a shape, it is possible to reduce the angle in the subsequent processes. In this case, the covering property of the insulator 273 etc. is improved, and defects such as voids can be reduced.

[0321] In addition, between the side surface of the oxide 230a and the oxide 230b and the top surface of the oxide 230b In other words, the end of the side surface and the end of the top surface are preferably curved. (Hereinafter, also referred to as a rounded shape). The curved surface is, for example, a curved surface at the end of the oxide 230b. The radius of curvature is 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less. The absence of corners improves film coverage in the subsequent film formation process.

[0322] The oxide film may be processed by lithography. Dry etching and wet etching can be used. This method is suitable for microfabrication.

[0323] In addition, by performing processes such as dry etching, the etching gas The impurities adhere to or diffuse onto the surface or inside of the oxide 230a and the oxide 230b. Impurities include, for example, fluorine or chlorine.

[0324] In order to remove the above impurities, cleaning is performed. These include wet cleaning, plasma treatment using plasma, and cleaning by heat treatment. The above cleaning methods may be combined as appropriate.

[0325] Wet cleaning involves the use of oxalic, phosphoric, or hydrofluoric acids in carbonated or pure water. The cleaning process may be carried out using an aqueous solution diluted with water. Alternatively, pure water or carbonated water may be used. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed. Do the following.

[0326] Subsequently, a heat treatment may be carried out. The heat treatment may be carried out under the conditions described above. can be done.

[0327] Next, an oxide film 230C is formed on the insulator 224, the oxide 230a, and the oxide 230b. An oxide film is formed as follows.

[0328] The oxide film that becomes oxide film 230C is formed by sputtering, CVD, MBE, and PLD. The oxide 230c can be formed by a method such as a CVD method or an ALD method. Then, the oxide film 230 is formed by the same film formation method as that for the oxide film 230A or the oxide film 230B. In this embodiment, the oxide film that becomes the oxide film 230C is formed. Then, a target of In:Ga:Zn=1:3:4 [atomic ratio] was deposited by sputtering. The film is formed using a

[0329] Next, the oxide film that will become the oxide film 230C is processed by lithography. 0C (see Figure 8).

[0330] Subsequently, an insulating film 250A and a dummy gate film 262A are formed in this order on the oxide film 230C. (See Figure 8.)

[0331] First, the insulating film 250A is formed. The insulating film 250A can be formed by a method such as a sputtering method, a CVD method, or the like. The insulating film 250 can be formed by using an MBE method, a PLD method, an ALD method, or the like. It is preferable to form a film of silicon oxynitride as A by the CVD method. The film formation temperature for 250A is 350°C or higher and lower than 450°C, especially around 400°C. By forming the insulating film 250A at 400°C, it is possible to obtain an insulating film with few impurities. A film can be formed.

[0332] In addition, oxygen is excited by microwaves to generate high-density oxygen plasma, and the oxygen plasma By exposing the insulating film 250A to the oxygen, oxygen can be introduced into the insulating film 250A.

[0333] Heat treatment may also be carried out. The heat treatment may be carried out under the above-mentioned heat treatment conditions. The heat treatment can reduce the moisture concentration and hydrogen concentration of the insulating film 250A. This can be done.

[0334] The dummy gate film 262A is processed and used as a dummy gate. That is, by processing the dummy gate film 262A, a temporary gate electrode is formed. In a later step, the dummy gate is removed and replaced with a conductive film or the like. Therefore, the dummy gate film 262A can be easily microfabricated. In addition, it is preferable to use a film that is easy to remove.

[0335] The dummy gate film 262A is formed by a sputtering method, a CVD method, an MBE method, or a PLD method. Alternatively, it can be performed using an ALD method or the like. For example, an insulator, a semiconductor, or a conductor Specifically, polysilicon, microcrystalline silicon, amorphous silicon, If metal films such as silicon, aluminum, titanium, and tungsten are used, Alternatively, a resin film may be formed by using a coating method. Resist, polyester, polyolefin, polyamide (nylon, aramid, etc.), Polyimide, polycarbonate, acrylic, etc. Resin film formed by coating method By doing so, the surface of the dummy gate film 262A can be made flat. By flattening the surface of the MI gate film 262A, fine processing becomes easy, and further, removal It also becomes easier.

[0336] The dummy gate film 262A can also be a multi-layer film using different film types. For example, the dummy gate film 262A may have a two-layer structure in which a conductive film and a resin film are formed on the conductive film. By providing the dummy gate film with such a structure, it is possible to reduce the thickness of the dummy gate film in the subsequent CMP process, for example. In this case, the conductive film may function as a stopper film for the CMP process. It may be possible to detect the end point of P processing, which may reduce processing variations. .

[0337] Next, the oxide film 230C, the insulating film 250A and the dummy gate electrode 230B are formed by lithography. The oxide film 230c, the insulator 250, and the dummy gate layer 26 2B (see FIG. 9). The oxide 230c, the insulator 250 and the dummy gate layer 26 2B is formed so as to overlap at least a portion of the conductor 205 and the oxide 230.

[0338] In addition, the side of the oxide 230c, the side of the insulator 250, and the side of the dummy gate layer 262B The faces are preferably coplanar.

[0339] In addition, the side of the oxide 230c, the side of the insulator 250, and the side of the dummy gate layer 262B The common plane shared by the surfaces is preferably approximately perpendicular to the upper surface of the substrate. In plan view, the oxide 230c, the insulator 250, and the dummy gate layer 262B are formed on the substrate. The angle relative to the plane is preferably close to 90°.

[0340] Next, the insulator 224, the oxide 230, the insulator 250 and the dummy gate layer 262B are covered. The film 242A is formed in a thickness of 0.5 nm to 5 nm (see FIG. 10). The film 242A may have a thickness of 1 nm or more and preferably 1 nm or more and 3 nm or less. The film 242A is a metal oxide film, a nitride film containing a metal element, or a metal nitride film. For example, aluminum, ruthenium, titanium, tantalum, tungsten, chromium, etc. The film 242A is a film containing metal elements. The film 242A can be formed by a sputtering method, a CVD method, an MB method, or the like. This can be done using the E method, PLD method, ALD method, or the like.

[0341] Next, a heat treatment is carried out. The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or lower. The heating temperature may be from 320°C to 500°C, more preferably from 320°C to 450°C. The heat treatment is carried out in a nitrogen or inert gas atmosphere. The heat treatment can also be carried out under reduced pressure. For example, after the film 242A is formed, a heat treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere. Do the following.

[0342] By the heat treatment in the atmosphere containing nitrogen, the above-mentioned metal elements are converted into oxides 2 from the film 242A. 30, and the metal element can be added to the oxide 230. Oxygen near the interface with the film 242A may be absorbed into the film 242A. The oxide 230 becomes a metal compound near the interface with the film 242A, resulting in a low resistance. In this case, a part of the oxide 230 may be alloyed with the above-mentioned metal element. The metal elements added to the oxide 230 are relatively stable due to alloying with some of the metal elements. Since the state is stable, a highly reliable semiconductor device can be provided.

[0343] In addition, hydrogen in the oxide 230 diffuses into the region 231, and oxygen vacancies present in the region 231 are eliminated. In addition, when the oxygen vacancy in the region 234 is By heat treatment at 250°C or higher, hydrogen escapes from the oxygen vacancies and diffuses into the region 231. The oxygen enters the oxygen vacancies in the region 231 and becomes relatively stable. Therefore, the region 231 has a lower resistance, and the region 234 has a higher purity (water, hydrogen, etc.) (reduction of materials) and higher resistance.

[0344] In addition, after heat treatment in a nitrogen or inert gas atmosphere, oxidizing gas is reduced to 10 ppm or more. The heat treatment may be carried out in an atmosphere containing 1% or more, or 10% or more. 0°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, more preferably 320°C or higher The heating temperature may be between 0.5°C and 450°C.

[0345] Furthermore, if a conductive region remains in the film 242A, the film 242A is subjected to heat treatment in an oxidizing atmosphere. By performing this, the conductive region is oxidized, and the film 242A becomes an insulator. The film 242A is left as an insulator, and functions as an interlayer film. It is possible.

[0346] In the film formation process or heat treatment of the film 242A, the oxide 230 is added to the film 242A. The absorption of oxygen may cause oxygen vacancies in the region 231. As hydrogen enters the oxygen vacancies, the carrier density in the region 231 increases. The region 231 of the oxide 230 becomes n-type and has low resistance.

[0347] Subsequently, the film 242A is removed. The nitride film containing the element does not necessarily have to be removed. The oxide film containing the metal element or the nitride film containing the metal element absorbs oxygen from the oxide 230. If the film has turned into an insulator and has high resistance, the film may be left. This film may function as an interlayer film. In this process, dry etching or wet etching is used. An etching method can be used. By removing the film 242A, the The hydrogen in the oxide 230 can be removed at the same time. The hydrogen impurities in the oxide 230 can be reduced. The vicinity is shown shaded as layer 242 (see FIG. 11).

[0348] Next, the insulating film 273A is formed (see FIG. 12). The insulating film 273A is formed by sputtering. The deposition can be performed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. do.

[0349] The insulating film 273A is preferably formed by the ALD method, which has excellent coating properties. By using the above, even in the step portion formed by the dummy gate layer 262B, etc., oxidation can be prevented. The thickness of the insulating layer 230c, the insulating layer 250, and the dummy gate layer 262B is uniform. In addition, by using the ALD method, a dense insulating film 273A can be formed. Thin films can be deposited.

[0350] The insulating film 273A may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like. Silicon, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen It is preferable that the silicon oxide layer contains silicon dioxide doped with silicon dioxide, silicon dioxide having pores, or resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. .

[0351] On the other hand, aluminum oxide or the like having a barrier property may be provided as the insulating film 273A. For example, if the conductor 260 is a metal film that is easily oxidized, an insulator having a barrier property is used. By doing so, the conductor 260 is prevented from being oxidized by oxygen from the outside of the insulator 273. This makes it possible to prevent the resistance value of the conductor 260 from increasing.

[0352] When aluminum oxide is provided as the insulating film 273A by the ALD method, The film thickness of 3A is 0.5 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less. do.

[0353] Next, the insulating film 273A is processed by lithography to form an insulator 27 having an opening. Form 3B. (See Figure 13).

[0354] Next, an insulating film that will become the insulator 280 is formed on the insulator 273B. The insulating film is formed by a method such as sputtering, CVD, MBE, PLD, or ALD. This can be done using, for example.

[0355] Next, the insulating film that will become the insulator 280, the dummy gate layer 262B, and the insulator 273B are A portion of the dummy gate layer 262B is removed until a portion of the dummy gate layer 262B is exposed. 14. The insulator 280, the dummy gate 262, and the insulator 273 are formed (see FIG. 14). Preferably, CMP is used to form 62 and insulator 273 .

[0356] As described above, the dummy gate film 262A is formed by, for example, forming a conductive film and a resin film on the conductive film. By forming a two-layer structure film, the conductive film can be prevented from being damaged by the CMP process. It may function as a stopper film. Alternatively, the conductive film may enable detection of the end point of the CMP process. This may enable the height variation of the dummy gate 262 to be reduced. As shown in FIG. 14, the upper surface of the dummy gate 262, the insulator 273, and the insulator 28 The top surfaces of 0 are approximately the same.

[0357] Next, the dummy gate 262 is removed by wet etching. This can be done by using a suitable method such as etching, dry etching, or ashing. If desired, a combination of the above processes may be performed. For example, after the ashing process, By removing the dummy gate 262, the insulator The surface of 250 is exposed (see FIG. 15).

[0358] Next, the conductive film 260Aa and the conductive film 260Ab are formed. The conductive film 260Ab can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an A method. This can be done using the LD method or the like. For example, it is preferable to use the CVD method. In this embodiment, the conductive film 260Aa is formed by the ALD method, and the conductive film 260B is formed by the CVD method. 260Ab is deposited (see Figure 16).

[0359] Next, the conductive film 260Aa and the conductive film 260Ab are bonded to the insulator 280 by CMP processing. By polishing the conductive layer 260 until the conductive layer 260a and the conductive layer 260b are exposed, a conductive layer 260a and a conductive layer 260b are formed. The conductive body 260 is formed (see FIG. 17).

[0360] Next, a process of implanting oxygen into the insulator 280 may be performed. The method involves plasma treatment using a gas containing oxygen, and implanting oxygen ions using an ion implantation device. For example, a device with a high-density plasma source is used to treat the surface with a gas containing oxygen. By irradiating the insulator with a plasma, oxygen can be implanted into the insulator 280. In this embodiment, oxygen ions are implanted using an ion implantation device (see FIG. 17).

[0361] Ion implantation using an ion implanter requires the ion implantation amount and ion implantation depth to be individually controlled. This is preferable because it allows precise control of the injection amount and the injection depth. Oxygen can be injected into the insulator 280, allowing for high-performance transistors with minimal performance variation. The implantation dose and implantation depth are determined by the thickness of the insulator 280. The film thickness, size of the transistor, density of the transistor, and layout of the transistor , and can be optimized as appropriate.

[0362] In addition, by forming an insulating film to be the insulator 282 on the insulator 280, oxygen can be The insulating film that becomes the insulator 282 may be formed by sputtering. This can be done using a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film that becomes the body 282 is formed by, for example, sputtering aluminum oxide. It is preferable to form a film by sputtering using an oxygen-containing gas. By depositing an aluminum film, oxygen can be implanted into the insulator 280. In other words, the insulator 280 has excess oxygen. Also, the hydrogen in the insulator 280 is converted into oxide. 230 (see FIG. 18).

[0363] Heat treatment may be performed in a subsequent step. The excess oxygen contained in the insulating layer 273 passes through the openings in the insulating layer 273 and is transferred to the oxide layer 230 via the insulating layer 224. The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher. The heating temperature is preferably from 320 to 450°C. The treatment is preferably carried out in an atmosphere containing oxygen gas. For example, heat treatment may be performed at 400° C. for 1 hour in an atmosphere containing oxygen.

[0364] Next, an insulator that will become the insulator 283 may be formed on the insulator 282. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. This can be done using the method described above (see FIG. 19).

[0365] Next, oxide 23 is applied to insulators 273, 280, 282 and 283. An opening is formed that reaches the region 231 of 0 (see FIG. 20). This can be done using the 'Bee' method.

[0366] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that becomes the conductor 240b has a function of suppressing the permeation of impurities such as water or hydrogen. For example, tantalum nitride, titanium nitride, etc. The conductive material may be a laminate of a conductive material such as tungsten, molybdenum, or copper. The conductive film 240 is formed by sputtering, CVD, MBE, PLD or This can be done using an ALD method or the like.

[0367] Here, for example, the insulators 273, 280, 282, and 283 are opened. In forming the opening, the low resistance region of region 231 in oxide 230 may be removed. When a conductive film that becomes the conductor 240a and the conductor 240b is formed in the opening, the oxide 230 and the conductive film that becomes the conductor 240a and the conductor 240b are in contact with each other. Therefore, a metal compound or oxygen vacancy is formed in the region, and the oxide 230 and the conductor 240 a and the conductive film that becomes the conductor 240b can have low resistance. By reducing the resistance of the contact area, the oxide 230 and the conductors 240a and 240b Therefore, the conductor 240a and the conductor 240b can be in sufficient ohmic contact with each other. The conductive film that becomes the conductive body 240b is made of, for example, aluminum, ruthenium, titanium, tantalum, It is preferable that the alloy contains a metal element such as tungsten or chromium.

[0368] Next, a CMP process is performed to remove the conductive film that will become the conductors 240a and 240b. A portion of the insulating film is removed to expose the insulator 283. As a result, the conductive film remains only in the opening. By doing so, it is possible to form the conductors 240a and 240b with flat upper surfaces ( See Figure 1).

[0369] After forming aluminum oxide on the sidewall of the opening, the conductor 240a and the conductor By forming aluminum oxide on the side wall of the opening, This can suppress the permeation of oxygen from the conductive material 240a and the conductive material 240b, thereby preventing oxidation of the conductive material 240a and the conductive material 240b. Furthermore, impurities such as water and hydrogen can be released from the conductors 240a and 240b to the outside. The aluminum oxide can be formed by using the ALD method or the like in the opening. The insulating film can be formed by forming an aluminum oxide film and then anisotropically etching it.

[0370] As described above, by using the manufacturing method of the semiconductor device shown in FIGS. 6 to 20, A semiconductor device including the transistor 200 can be manufactured.

[0371] <Method 2 for manufacturing semiconductor device> Next, regarding the semiconductor device having the transistor 200a according to the present invention shown in FIG. The manufacturing method will be described with reference to FIGS. 21 to 31. (A) in each figure shows a top view. (B) in each figure shows the area indicated by the dashed line A1-A2 in (A). (C) in each figure is a cross-sectional view corresponding to the portion indicated by A3-A4. It should be noted that in the top view of each figure (A), the cross-sectional view corresponds to the part indicated by the line. For this reason, some elements have been omitted.

[0372] The process up to the formation of the insulating film 273A shown in FIG. 12 is the same as that shown in <Method 1 for manufacturing a semiconductor device>. A method for manufacturing a semiconductor device having the transistor 200 will be described below.

[0373] Next, the insulating film 275A is formed on the insulating film 273A. It can be performed using methods such as sputtering, CVD, MBE, PLD, or ALD. This is possible (see Figure 21).

[0374] Next, the insulating film 275A is subjected to an anisotropic etching process to form an insulator 275B ( See Figure 22).

[0375] As the anisotropic etching process, a dry etching process is preferably performed. This removes the insulating film formed on the surface approximately parallel to the substrate surface, and the insulator 275B is removed. It can be formed in a self-aligned manner.

[0376] Next, the insulating film 273A is processed by lithography to form an insulator 27 having an opening. Form 3B. (See Figure 23).

[0377] Next, the insulator 273B, the oxide 230, the insulator 275B, and the dummy gate layer 262 An insulating film that will become the insulator 280 is formed to cover B. The deposition method can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. This can be done.

[0378] Next, the insulating film that will become the insulator 280, the dummy gate layer 262B, the insulator 273B and the insulating film are A portion of the insulator 275B is removed until a portion of the dummy gate layer 262B is exposed, and the insulator 28 0, forming dummy gate 262, insulator 273, and insulator 275 (see FIG. 24). The insulator 280, the dummy gate 262, the insulator 273, and the insulator 275 are formed using C. It is preferable to use MP treatment.

[0379] As described above, the dummy gate film 262A is formed by, for example, forming a conductive film and a resin film on the conductive film. By forming a two-layer structure film, the conductive film can be prevented from being damaged by the CMP process. It may function as a stopper film. Alternatively, the conductive film may enable detection of the end point of the CMP process. This may enable the height variation of the dummy gate 262 to be reduced. As shown in the figure, the upper surface of the dummy gate 262 and the insulators 273 and 280 are The top surfaces are approximately the same.

[0380] Next, the dummy gate 262 is removed by wet etching. This can be done by using a suitable method such as etching, dry etching, or ashing. If desired, a combination of the above processes may be performed. For example, after the ashing process, By removing the dummy gate 262, the insulator The surface of 250 is exposed (see FIG. 25).

[0381] Next, the conductive film 260Aa and the conductive film 260Ab are formed. The conductive film 260Ab can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an A method. This can be done using the LD method or the like. For example, it is preferable to use the CVD method. In this embodiment, the conductive film 260Aa is formed by the ALD method, and the conductive film 260B is formed by the CVD method. 260Ab is deposited (see Figure 26).

[0382] Next, the conductive film 260Aa and the conductive film 260Ab are bonded to the insulator 280 by CMP processing. By polishing the conductive layer 260B until the conductive layer 260Ba and the conductive layer 260Bb are exposed, A conductor 260B is formed (see FIG. 27).

[0383] Next, a part of the conductor 260Ba and the conductor 260Bb is removed, and the conductor 260B is thinned. The thinning is performed by wet etching. The thickness of the thin film can be determined by the thickness of the conductor 260. It is preferable that the thickness is about 1 / 4 of the thickness of B (see FIG. 28).

[0384] Next, an insulating film that will become the insulator 270 is formed. It can be performed using methods such as sputtering, CVD, MBE, PLD, or ALD. For example, the insulating film that becomes the insulator 270 can be made of the same material as the insulator 275. It is preferable.

[0385] Next, the insulating film that will become the insulator 270 is etched by CMP until the insulator 280 is exposed. By polishing, an insulator 270 can be formed (see FIG. 28).

[0386] Next, a process of implanting oxygen into the insulator 280 may be performed. The method involves plasma treatment using a gas containing oxygen, and implanting oxygen ions using an ion implantation device. For example, a device with a high-density plasma source is used to treat the surface with a gas containing oxygen. By irradiating the insulator with a plasma, oxygen can be implanted into the insulator 280. In this embodiment, oxygen ions are implanted using an ion implantation device (see FIG. 28).

[0387] Ion implantation using an ion implanter requires the ion implantation amount and ion implantation depth to be individually controlled. This is preferable because it allows precise control of the injection amount and the injection depth. Oxygen can be injected into the insulator 280, allowing for high-performance transistors with minimal performance variation. The implantation dose and implantation depth are determined by the thickness of the insulator 280. The film thickness, size of the transistor, density of the transistor, and layout of the transistor , and can be optimized as appropriate.

[0388] In addition, by forming an insulating film to be the insulator 282 on the insulator 280, oxygen can be The insulating film that becomes the insulator 282 may be formed by sputtering. This can be done using a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film that becomes the body 282 is formed by, for example, sputtering aluminum oxide. It is preferable to form a film by sputtering using an oxygen-containing gas. By depositing an aluminum film, oxygen can be implanted into the insulator 280. In other words, the insulator 280 has excess oxygen. Also, the hydrogen in the insulator 280 is converted into oxide. 230 (see FIG. 29).

[0389] Heat treatment may be performed in a subsequent step. The excess oxygen contained in the insulating layer 273 passes through the openings in the insulating layer 273 and is transferred to the oxide layer 230 via the insulating layer 224. The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher. The heating temperature is preferably from 320 to 450°C. The treatment is preferably carried out in an atmosphere containing oxygen gas. For example, heat treatment may be performed at 400° C. for 1 hour in an atmosphere containing oxygen.

[0390] Next, an insulator that will become the insulator 283 may be formed on the insulator 282. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. This can be done using the method described above (see FIG. 30).

[0391] Next, oxide 23 is applied to insulators 273, 280, 282 and 283. An opening is formed that reaches the region 231 of 0 (see FIG. 31). The formation of the opening is performed by lithography. Here, the conductor 240 is provided in contact with the side surface of the insulator 275. The opening is formed so that the insulator 275 is almost completely etched away. It is preferable that the insulating layer 275 is formed under the condition that the etching rate of the insulating layer 275 is not high. It is preferable that the etch rate of the insulator 280 is high. Then, the etching rate of the insulator 280 is preferably 5 or more, more preferably 1 0 or more. By setting such an opening condition, the opening is self-alignedly arranged in the region 231. This allows for the fabrication of minute transistors. Even if the insulator 270 is shifted to a position where it overlaps with the upper surface of the insulator 270, the etching rate of the insulator 270 is As with 275, if the opening condition is significantly smaller than the etching rate of the insulator 280, The opening does not reach the conductor 260. That is, the conductor 260 and the conductor 240a or Therefore, the conductor 240b can be prevented from being electrically short-circuited. In the die forming process, the tolerance for misalignment between the conductor 260 and the opening becomes large. Therefore, an improvement in yield can be expected.

[0392] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that becomes the conductor 240b has a function of suppressing the permeation of impurities such as water or hydrogen. For example, tantalum nitride, titanium nitride, etc. The conductive material may be a laminate of a conductive material such as tungsten, molybdenum, or copper. The conductive film 240 is formed by sputtering, CVD, MBE, PLD or This can be done using an ALD method or the like.

[0393] Here, for example, the insulators 273, 280, 282, and 283 are opened. In forming the opening, the low resistance region of region 231 in oxide 230 may be removed. When a conductive film that becomes the conductor 240a and the conductor 240b is formed in the opening, the oxide 230 and the conductive film that becomes the conductor 240a and the conductor 240b are in contact with each other. Therefore, a metal compound or oxygen vacancy is formed in the region, and the oxide 230 and the conductor 240 a and the conductive film that becomes the conductor 240b can have low resistance. By reducing the resistance of the contact area, the oxide 230 and the conductors 240a and 240b Therefore, the conductor 240a and the conductor 240b can be in sufficient ohmic contact with each other. The conductive film that becomes the conductive body 240b is made of, for example, aluminum, ruthenium, titanium, tantalum, It is preferable that the alloy contains a metal element such as tungsten or chromium.

[0394] Next, a CMP process is performed to remove the conductive film that will become the conductors 240a and 240b. A portion of the insulating film is removed to expose the insulator 283. As a result, the conductive film remains only in the opening. By doing so, it is possible to form the conductors 240a and 240b with flat upper surfaces ( See Figure 4).

[0395] After forming aluminum oxide on the sidewall of the opening, the conductor 240a and the conductor By forming aluminum oxide on the side wall of the opening, This can suppress the permeation of oxygen from the conductive material 240a and the conductive material 240b, thereby preventing oxidation of the conductive material 240a and the conductive material 240b. Furthermore, impurities such as water and hydrogen can be released from the conductors 240a and 240b to the outside. The aluminum oxide can be formed by using the ALD method or the like in the opening. The insulating film can be formed by forming an aluminum oxide film and then anisotropically etching it.

[0396] As described above, by using the manufacturing method of the semiconductor device shown in FIGS. 21 to 31, A semiconductor device including the transistor 200a can be manufactured.

[0397] According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0398] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0399] <Modification of Semiconductor Device> Hereinafter, the above-mentioned <Configuration Example 1 of Semiconductor Device> and <Configuration Example 2 of Semiconductor Device> will be described with reference to FIG. 2> A semiconductor device having a transistor 200 according to one embodiment of the present invention, which is different from that shown in An example of the device will be described.

[0400] FIG. 5A is a top view of a semiconductor device including a transistor 200. FIG. 5(B) and FIG. 5(C) are cross-sectional views of the semiconductor device. 5(A) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. FIG. 5(C) is also a cross-sectional view in the longitudinal direction of the panel. 1 is a cross-sectional view of the portion indicated by the arrow ⇋ in the channel width direction of the transistor 200. In the top view of FIG. 5(A), some elements are omitted for clarity.

[0401] In the semiconductor device shown in FIG. 5, <Configuration Example 1 of Semiconductor Device> and <Semiconductor Device> The semiconductor device shown in the configuration example 2 (see FIGS. 1 and 4) has the same functions as the components constituting the semiconductor device shown in the configuration example 2. The same reference numerals are used to designate the components that have the same functions.

[0402] The configuration of the transistor 200 will be described below with reference to FIG. In the item, the constituent materials of the transistor 200 are the same as those in <Configuration Example 1 of the Semiconductor Device> and In addition, the materials described in detail in <Structure example 2 of semiconductor device> can be used.

[0403] The semiconductor device shown in FIG. 5 includes <Configuration Example 1 of the semiconductor device> and <Configuration Example 2 of the semiconductor device>. The semiconductor device shown in FIG. 1 and FIG. 4 is a semiconductor device including an insulator 224 and an oxide 230a. The difference is that an oxide 230d having an opening is provided between the oxide 230a and the oxide 230b. The insulating layer 224 contacts the insulating layer 224 through an opening formed in the insulating layer 230d.

[0404] The material used for the oxide 230d is different from that used for the oxide 230a and the oxide 230b. It is preferable that the ratio of Ga and Zn is large. Specifically, the oxide 230d is In the metal oxide, the atomic ratio of element M among the constituent elements is The atomic ratio of element M in the constituent elements in the oxide 230b is smaller than that of the metal used in the oxide 230b. It is preferable that the atomic ratio of the element M in the constituent elements of the oxide is larger than that of the element M. In the metal oxide used in the product 230d, the atomic ratio of element M to In is The atomic ratio of element M to In in the metal oxide used in 0a, and the oxide 230 It is preferable that the atomic ratio of element M to In in the metal oxide used in b is larger than that of element M to In. For example, the oxide 230d may be formed by sputtering In:Ga:Zn=1 An oxide film formed using a target with an atomic ratio of 3:4 can be used.

[0405] It is preferable to use a material that is difficult for oxygen to permeate as the oxide 230d. The object 230d has an opening at a position overlapping the region 234. The oxygen contained in the oxide 230a diffuses through the openings into the oxide 230b. The arrows in FIG. 5B indicate that oxygen contained in the insulator 280 and the insulator 224 is diffusing. The oxygen contained in the insulator 280 is absorbed by the insulator 273. The oxygen in the insulator 224 diffuses through the openings. 0d to the oxide 230a and the region 234 of the oxide 230b. The oxygen supplied to the oxide 230a and the oxide 230b is diffused in the region 23 1. By providing the transistor 200 with oxide 230d, the efficiency Oxygen can be supplied to region 234 .

[0406] When the transistor 200 having the oxide 230d is fabricated, the oxide is formed on the insulator 224. Next, an oxide film 230d (hereinafter referred to as oxide film 230D) is formed. An opening is formed in the 0D. The opening is shaped to overlap the conductor 205 and the conductor 203. The opening is formed so as to overlap a region 234 of the oxide 230, which will be formed in a later step. It is preferable that the ion exchange layer is formed as follows.

[0407] Next, on the oxide film 230D, in the same manner as in the above-mentioned <Method 1 for manufacturing a semiconductor device>, the oxide film 230 A. An oxide film 230B is formed. Before or after the formation of the film, a heat treatment may be carried out as appropriate.

[0408] Next, the oxide film 230B, the oxide film 230A, and the oxide film 23 0D is processed into an island shape to form oxide 230b, oxide 230a, and oxide 230d. This processing can be performed using dry etching or wet etching. The etching method is suitable for microfabrication.

[0409] Thereafter, the oxide 230 is formed by carrying out the same steps as in the above-described <Method for manufacturing a semiconductor device 1>. A transistor 200 having d can be fabricated.

[0410] The configurations, structures, methods, etc. described in this embodiment may be the same as those described in other embodiments. It can be used in appropriate combination.

[0411] (Embodiment 2) In this embodiment mode, a semiconductor device functioning as a memory device, which is different from the above embodiment modes, will be described. One embodiment will be described with reference to FIGS.

[0412] <Storage device 1> 33(A) and (B) show a cell 600 that constitutes a memory device. The cell 600 is a transistor. The capacitor includes a capacitor 200a, a transistor 200b, a capacitor 100a, and a capacitor 100b. FIG. 33(A) is a top view of the cell 600. FIG. 33(B) is a top view of the cell 600. 33(A) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. In the figure, some elements have been omitted for clarity.

[0413] The cell 600 includes a transistor 200a and a transistor 200b. The capacitor 100a is overlapped on the transistor 200a, and the capacitor 100b is overlapped on the transistor 200b. The cell 600 has a capacitor element 100b. 00b, and the capacitive elements 100a and 100b may be arranged symmetrically. Therefore, it is preferable that the transistors 200a and 200b have the same configuration. It is preferable that the capacitive element 100a and the capacitive element 100b have the same configuration.

[0414] Cell 600 is a transistor 200a and a transistor 200b. The insulating layer 130 is disposed on the insulating layer 130, and the insulating layer 150 is disposed on the insulating layer 130. The insulator 50 may be any insulator that can be used for the insulator 283 .

[0415] Furthermore, the conductor 160 is disposed on the insulator 150. Also, the insulator 273 and the insulator 28 0, openings formed in the insulator 282, the insulator 283, the insulator 130, and the insulator 150 The conductor 240 is provided so as to be embedded in the region 231. The lower surface of the conductor 240 is in contact with the region 231. The upper surface of the conductor 240 is in contact with the conductor 160 .

[0416] The transistor 200a and the transistor 200b are the same as those described in the above embodiment. Therefore, transistor 200a and transistor 2 The description of the transistor 200 can be referred to for the structure of 00b. 33(A) and (B), the elements of the transistor 200a and the transistor 200b The reference numerals are omitted. The transistor 200b is an example, and is not limited to this structure. An appropriate transistor may be used.

[0417] Both transistor 200a and transistor 200b share oxide 230. The source and drain of the transistor 200a and the drain of the transistor 200b are connected to each other. One of the source and drain of the transistor 200a is shared. and one of the source and drain of transistor 200b are conductive. 240. This allows the transistor 200a and the transistor The contact portion of the contact 200b is shared, which reduces the number of plugs and contact holes. In this way, the wiring electrically connected to either the source or the drain can be shared. As a result, the area occupied by the memory cell array can be reduced.

[0418] [Capacitor element 100a and capacitor element 100b] As shown in FIGS. 33A and 33B, the capacitor 100a overlaps with the transistor 200a. Similarly, the capacitor 100b is provided in a region overlapping with the transistor 200b. The capacitor element 100b has a structure corresponding to that of the capacitor element 100a. The detailed structure of the capacitor element 100a will be described below. Unless otherwise specified, the description of the capacitance element 100a is to be taken into consideration for the capacitance element 100b. It is possible.

[0419] The capacitance element 100a includes a conductor 110, an insulator 130, and a conductor 120 on the insulator 130. Here, the conductor 110 and the conductor 120 are conductors 203, 205, or Alternatively, a conductor that can be used for the conductor 260 may be used.

[0420] The capacitive element 100a includes an insulator 273, an insulator 280, an insulator 282, and an insulator 28 The lower electrode and the side surface of the opening are formed in the opening. The conductor 110 functions as a dielectric, and the conductor 120 functions as a top electrode. The conductors 110 of the capacitance element 100a are opposed to each other with a functional insulator 130 sandwiched therebetween. It is formed in contact with the other of the source or drain of the transistor 200a.

[0421] In particular, by increasing the depth of the openings in the insulators 280 and 283, the projection The capacitance of the capacitor element 100a can be increased without changing the area. The element 100a is preferably cylindrical (having a side area larger than the bottom area). It's nice.

[0422] With the above configuration, the capacitance per unit area of ​​the capacitance element 100a can be increased, This allows for miniaturization or high integration of semiconductor devices. The capacitance value of the capacitance element 100a can be appropriately set by adjusting the thickness of the insulator 283. Therefore, a semiconductor device with a high degree of freedom in design can be provided.

[0423] It is preferable to use an insulator with a large relative dielectric constant for the insulator 130. Insulators containing oxides of aluminum and / or hafnium can be used. As an insulator containing oxides of one or both of aluminum and hafnium, aluminum oxide is Aluminum, hafnium oxide, oxides containing aluminum and hafnium (hafnium oxide) It is preferable to use a laminate.

[0424] The insulator 130 may also have a laminated structure, for example, silicon oxide, silicon oxynitride, etc. Silicon, silicon oxide nitride, silicon nitride, aluminum oxide, hafnium oxide, aluminum Two or more layers are made from oxides containing tungsten and hafnium (hafnium aluminate) For example, hafnium oxide and aluminum oxide can be deposited by the ALD method. It is preferable to form a laminated structure by depositing hafnium oxide and hafnium oxide in this order. The thickness of the aluminum and aluminum oxide layers is 0.5 nm or more and 5 nm or less. By using such a layered structure, a capacitance element with a large capacitance value and a small leakage current can be produced. It can be 100a.

[0425] The conductor 110 or the conductor 120 may have a laminated structure. The body 110, or the conductor 120, may be titanium, titanium nitride, tantalum, or tantalum nitride. Conductive materials based on copper and conductive materials based on tungsten, copper, or aluminum The conductor 110 or the conductor 120 may be a single layer. It may have a layer structure or a laminated structure of three or more layers.

[0426] [Cell array structure] Next, an example of a cell array in which the above cells are arranged in rows and columns or a matrix is ​​as follows: This will be explained using Figures 34 to 37.

[0427] FIG. 34 is a circuit diagram showing an embodiment in which the cells 600 shown in FIG. 33 are arranged in a matrix. FIG. 35 shows a circuit diagram of a cell 600 and a cell 601 adjacent to the cell 600. 36 is a schematic diagram showing a cross-sectional structure in the vicinity of the wiring WL and the wiring 34 to 37 are schematic diagrams showing the layout of the BL and oxide 230. The extension direction of the wiring BL is the x direction, the extension direction of the wiring WL is the y direction, and the The direction is the z direction. In Figures 34, 36, and 37, the cells are arranged in 3x3 rows. However, the present embodiment is not limited to this example. The number and arrangement of recells or wirings may be set as appropriate. 34. In the top view of FIG. 7, some elements shown in FIG. 34 are omitted for clarity.

[0428] As shown in FIG. 34, the transistors 200a and 200b that make up the cell One of the source and drain is electrically connected to the common wiring BL (BL01, BL02, BL03). The wiring BL is connected to the transistors 2 of the cells arranged in the x direction. 00a is electrically connected to one of the source and drain of transistor 200b. On the other hand, the first gate of the transistor 200a and the second gate of the transistor 200b, which constitute the cell, The first gates are electrically connected to different wirings WL (WL01 to WL06). These wirings WL are connected to the transistors 200a of the cells arranged in the y direction. and the first gate of the transistor 200b are electrically connected to each other. .

[0429] In addition, one electrode of the capacitor 100a and one electrode of the capacitor 100b included in the cell The electrode is electrically connected to the wiring PL. For example, if the wiring PL is formed to extend in the y direction, That's fine.

[0430] In addition, the transistor 200a and the transistor 200b of each cell are provided with a second gate. A potential applied to the second gate BG can turn on or off the transistor. The second gate BG can control the threshold voltage of the transistor 400. The potential applied to the second gate BG is controlled by the transistor 400. It can be controlled.

[0431] For example, as shown in FIG. 35, the conductor 160 is extended in the x direction to function as the wiring BL. The conductor 260 is extended in the y direction to function as a wiring WL, and the conductor 120 is extended in the y direction to function as a wiring WL. The conductor 203 can be extended in the y direction to function as a wiring PL. It can also be extended to function as wiring connected to the second gate BG.

[0432] As shown in FIG. 35, one electrode of the capacitor element 100b of the cell 600 is The functional conductor 120 also serves as one electrode of the capacitor element 100a of the cell 601. Although not shown, the capacitance element 100a of the cell 600 The conductor 120 that functions as one electrode of the cell 600 is connected to the capacitive element of the cell adjacent to the left of the cell 600. The cell to the right of cell 601 has a similar configuration. Therefore, a cell array can be configured. By configuring this cell array, The spacing between adjacent cells can be reduced, reducing the projection area of ​​the cell array. This allows for high integration.

[0433] Also, as shown in FIG. 36, the oxide 230 and the wiring WL are arranged in a matrix. Thus, the semiconductor device having the circuit diagram shown in FIG. 34 can be formed. It is preferable to provide the wiring WL and the oxide 230 in a different layer. In addition, by providing the capacitor element 100a and the capacitor element 100b in the lower layer, the oxide 230 It is possible to realize a layout in which the long side direction and the wiring BL are approximately parallel. This simplifies the cell layout, improves design freedom, and reduces process costs. It is possible.

[0434] 36, the oxide 230 is formed so that its long side is substantially perpendicular to the direction in which the wiring WL extends. Although the oxide 230 and the wiring WL are provided, the present invention is not limited to this. For example, in FIG. As shown in FIG. 1, the long side of the oxide 230 is not perpendicular to the extending direction of the wiring WL. The wiring WL may be arranged in a tilted manner with respect to the extending direction of the wiring WL. By arranging the capacitor elements 100a and 100b in parallel, for example, the capacitor elements 100a and 100b and the wiring B L can be arranged without intersecting with each other, so that the capacitance element 100a and the capacitance element 100b can extend in the z direction, and the capacitance elements 100a and 100b The capacitance can be increased. Preferably, the angle between the long side of the oxide 230 and the wiring WL is , the oxide 230 is set to have an angle of 20° or more and 70° or less, preferably 30° or more and 60° or less. Then, wiring WL is provided.

[0435] Furthermore, the cell array may be configured not only as a flat surface but also as a stacked structure. By stacking the cells, the cells can be integrated and arranged without increasing the occupied area of ​​the cell array. In other words, a 3D cell array can be configured.

[0436] As described above, one embodiment of the present invention provides a semiconductor device that can be miniaturized or highly integrated. According to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a transistor having a large on-state current can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. It is possible.

[0437] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0438] (Embodiment 3) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0439] <Storage device 1> The memory device shown in FIGS. 38 and 40 includes a transistor 300, a transistor 200, and a capacitance element 100. FIGS. 38 and 40 show a transistor 200 and 39 is a cross-sectional view of the transistor 300 in the channel length direction. 1 shows a cross-sectional view of the channel width direction and its vicinity.

[0440] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 200 is used in a memory device because its off-state current is small. This allows the memory contents to be retained for a long period of time. Since no refresh operation is required or the frequency of refresh operations is extremely low, Power consumption can be reduced sufficiently.

[0441] In the memory devices shown in FIGS. 38 and 40, the wiring 1001 is connected to the transistor 300. The wiring 1002 is electrically connected to the source of the transistor 300. It continues. Also, wiring 1003 is connected to one of the source and drain of transistor 200 electrically, and wiring 1004 is connected to the top gate of transistor 200 electrically and wiring 1006 is connected to the bottom gate of transistor 200 electrically. Thus, the gate of transistor 300, and the other of the source and drain of transistor 200 are connected to one of the electrodes of capacitor 100 electrically, and wiring 1005 is connected to the other of the electrodes of capacitor 100 electrically.

[0442] The memory devices shown in FIGS. 38 and 40 have the property that the potential of the gate of transistor 300 can be held, and thus, as shown below, writing, holding, and reading of information are possible.

[0443] Explanation will be given about writing and holding of information. First, set the potential of wiring 1004 to a potential at which transistor 200 becomes conductive, and make transistor 200 conductive. Thereby, the potential of wiring 1003 is applied to node SN which is electrically connected to the gate of transistor 300 and one of the electrodes of capacitor 100. That is, a predetermined charge is applied to the gate of transistor 300 (writing). Here, either of two different charge levels (hereinafter referred to as Low level charge and High level charge) is applied. Then, set the potential of wiring 1004 to a potential at which transistor 200 becomes non-conductive, and make transistor 200 non-conductive, whereby the charge is held at node SN (holding).

[0444] When the off-current of transistor 200 is small, the charge at node SN is held for a long time.

[0445] Next, the reading of information will be explained. When a predetermined potential (constant potential) is applied to the wiring 1001, In this state, when an appropriate potential (read potential) is applied to the wiring 1005, the wiring 1002 The potential depends on the amount of charge held in the node SN. In the case of a transistor of the type, when a high level charge is applied to the gate of the transistor 300, The apparent threshold voltage V th_H applies a low level voltage to the gate of transistor 300. The apparent threshold voltage V under load th_L Because it will be lower. Here, the apparent threshold voltage is the voltage required to make the transistor 300 "conductive." This refers to the required potential of the wiring 1005. Therefore, the potential of the wiring 1005 is V th _H and V th_L By setting the potential V0 between For example, in a write operation, a high level charge is applied to the node SN. In this case, the potential of the wiring 1005 is V0 (>V th_H ), then transistor 300 is On the other hand, if a low-level charge is applied to node SN, The potential of the wiring 1005 is V0( <V th_L ), transistor 300 remains "non-conducting" Therefore, by determining the potential of the wiring 1002, the node SN is kept in the "state". The information stored in the memory can be read.

[0446] <Structure of memory device 1> As shown in FIG. 38, a memory device according to one embodiment of the present invention includes a transistor 300, a transistor The transistor 200 is disposed above the transistor 300. The capacitor element 100 is provided above the transistor 300 and the transistor 200. It is being done.

[0447] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 315, and a substrate A semiconductor region 313 consisting of a part of 311 and functioning as a source region or a drain region. The semiconductor device has a low resistance region 314a that functions as a dielectric film, and a low resistance region 314b.

[0448] As shown in FIG. 39, the transistor 300 includes an upper surface of a semiconductor region 313 and a channel The side surfaces in the width direction are covered with the conductor 316 via the insulator 315. By making the resistor 300 a fin type, the effective channel width is increased, This can improve the on-characteristics of the transistor 300. In addition, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300. .

[0449] Transistor 300 can be either p-channel or n-channel.

[0450] The region where the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the source region, or In the low resistance region 314a which becomes the drain region and the low resistance region 314b, silicon It preferably contains a semiconductor such as a silicon-based semiconductor, and it preferably contains single crystal silicon. Or Ge (germanium), SiGe (silicon germanium), GaAs (gallium It may be made of materials containing gallium aluminum arsenide (GaAlAs) or GaAlAs (Gallium Aluminum Arsenide). Silicon with effective mass controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, GaAs and GaAlAs may be used to form a transistor. The Star 300 is a HEMT (High Electron Mobility Transistor) stor) can also be used.

[0451] The low resistance region 314a and the low resistance region 314b are formed by the semiconductor layer applied to the semiconductor region 313. In addition to the conductive material, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron, are added. It contains elements that impart electrical conductivity to the material.

[0452] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used. .

[0453] In addition, since the work function is determined by the material of the conductor, by changing the material of the conductor, The threshold voltage can be adjusted by using titanium nitride or tantalum nitride as the conductor. It is preferable to use a material such as the following. It is preferable to use a metal material such as tungsten or aluminum as a laminate. Tungsten is preferred in terms of heat resistance.

[0454] The transistor 300 shown in FIG. 38 is an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the structure and driving method.

[0455] Over the transistor 300 are insulators 320, 322, 324, and The edge members 326 are stacked in order.

[0456] The insulators 320, 322, 324, and 326 may be, for example, an acid. silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used.

[0457] The insulator 322 serves to eliminate a step caused by the transistor 300 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process using chemical mechanical polishing (CMP) or other methods. It may be possible.

[0458] The insulator 324 is also provided with a substrate 311 or a transistor 300 or the like. A film having a barrier property to prevent diffusion of hydrogen and impurities is formed in the area where the sta 200 is provided. It is preferable to use

[0459] An example of a film having a barrier property against hydrogen is silicon nitride formed by CVD. Here, a semiconductor having an oxide semiconductor such as the transistor 200 can be used. The diffusion of hydrogen into the semiconductor element may cause a deterioration in the characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between the transistor 200 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that desorbs a small amount of hydrogen. do.

[0460] The amount of desorbed hydrogen can be analyzed using, for example, TDS. The amount of hydrogen desorption of 324 was measured by TDS analysis when the surface temperature of the film was in the range of 50°C to 500°C. In the range, the amount of desorption converted into hydrogen atoms is 10 x10 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 Below That would be good.

[0461] It is preferable that the insulator 326 has a lower relative dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 326 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the body 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, of the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. can be reduced.

[0462] In addition, the insulators 320, 322, 324, and 326 are provided with capacitive elements. 100, or a conductor 328 electrically connected to the transistor 200, and a conductor 33 0 and the like are embedded. The conductor 328 and the conductor 330 are plugs or wiring. Conductors that function as plugs or wiring also function as a group of multiple structures. In addition, in this specification and the like, the wiring and the wiring and the electrical In other words, a part of the conductor functions as a wiring. In some cases, a part of the conductor functions as a plug.

[0463] The materials for each plug and wiring (conductor 328, conductor 330, etc.) are metal. Conductive materials such as metals, alloy materials, metal nitride materials, or metal oxide materials are applied as single layers or can be used in laminated layers. Materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, It is preferable to use a high melting point material such as tungsten, and it is particularly preferable to use tungsten. It is preferable that the conductive layer is made of a low resistance conductive material such as aluminum or copper. By using such materials, the wiring resistance can be reduced.

[0464] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. In this case, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same material.

[0465] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 350 has a barrier property against hydrogen. It is preferable that a conductor having a barrier property against hydrogen is formed in the opening. By construction, transistor 300 and transistor 200 are separated by a barrier layer. This makes it possible to suppress the diffusion of hydrogen from the transistor 300 to the transistor 200. can.

[0466] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the overall conductivity. In this case, the tantalum nitride layer having a barrier property against hydrogen is It is preferable that the insulating body 350 has a structure in which the insulating body 350 is in contact with the insulating body 350.

[0467] A wiring layer may be provided on the insulator 350 and the conductor 356. For example, in FIG. In this case, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same material.

[0468] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulating material 360 has a barrier property against hydrogen. It is preferable that a conductor having a barrier property against hydrogen is formed in the opening. By construction, transistor 300 and transistor 200 are separated by a barrier layer. This makes it possible to suppress the diffusion of hydrogen from the transistor 300 to the transistor 200. can.

[0469] A wiring layer may be provided on the insulator 364 and the conductor 366. For example, in FIG. In this case, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed on the insulators 370, 372, and 374. The conductor 376 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same material.

[0470] For example, the insulator 370 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. In particular, an insulator 370 having a barrier property against hydrogen is useful. It is preferable that a conductor having a barrier property against hydrogen is formed in the opening. By construction, transistor 300 and transistor 200 are separated by a barrier layer. This makes it possible to suppress the diffusion of hydrogen from the transistor 300 to the transistor 200. can.

[0471] A wiring layer may be provided on the insulator 374 and the conductor 376. For example, in FIG. In this case, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed on the insulators 380, 382, ​​and 384. The conductor 386 functions as a plug or wiring. The conductive body 328 and the conductive body 330 may be formed using the same material.

[0472] For example, the insulator 380 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator having a barrier property against hydrogen. It is preferable that the insulator 380 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 300 and the transistor 200 can be separated by a barrier layer. This makes it possible to suppress the diffusion of hydrogen from the transistor 300 to the transistor 200.

[0473] In the above, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the conductor 376 The wiring layer including the conductor 386 has been described. The memory device is not limited to this. The number of layers may be three or less, or may be five or more.

[0474] On the insulator 384, the insulators 210, 212, 214, and 216 are are stacked in this order. It is preferable that the insulator 216 is made of a material that has a barrier property against oxygen and hydrogen. It's nice.

[0475] For example, the insulator 210 and the insulator 214 may include, for example, a substrate 311 or a transformer. The region where the transistor 300 is provided is filled with hydrogen and impurities. It is preferable to use a film having a barrier property that prevents the diffusion of the insulator 324. The same materials as those mentioned above can be used.

[0476] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, a semiconductor element including an oxide semiconductor, such as the transistor 200, However, the diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. It is preferable to use a film that suppresses hydrogen diffusion between the gate electrode 200 and the transistor 300. A film that suppresses hydrogen diffusion is preferably a film that desorbs a small amount of hydrogen.

[0477] In addition, as a film having a barrier property against hydrogen, for example, an insulator 210 and an insulator 214 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable that

[0478] In particular, aluminum oxide is highly resistant to oxygen and water, which can cause fluctuations in the electrical characteristics of transistors. It has a high blocking effect that prevents impurities such as oxygen and moisture from penetrating the membrane. Aluminum oxide is a material that can withstand hydrogen, moisture, and other chemicals during and after the transistor manufacturing process. This can prevent impurities from entering the transistor 200. This can suppress the release of oxygen from the oxide that makes up the transistor. It is suitable for use as a protective film for the capacitor 200.

[0479] For example, the insulators 212 and 216 may be made of the same material as the insulator 320. In addition, by using a material with a relatively low dielectric constant as the interlayer film, For example, the insulators 212 and 216 can reduce the parasitic capacitance. As the insulating film, a silicon oxide film, a silicon oxynitride film, or the like can be used.

[0480] In addition, the insulators 210, 212, 214, and 216 are made of conductive materials. 218, and conductors and the like that constitute the transistor 200 are embedded. 218 is a plug electrically connected to the capacitor element 100 or the transistor 300, The conductor 218 functions as a wiring. The various materials can be used to form the substrate.

[0481] In particular, the insulator 210 and the conductor 218 in the area in contact with the insulator 214 are resistant to oxygen, hydrogen, It is preferable that the conductive material has a barrier property against water. The transistor 300 and the transistor 200 have a barrier property against oxygen, hydrogen, and water. The layer having the hydrogen atoms can be separated from the transistor 300 to the transistor 200. The diffusion of the substance can be suppressed.

[0482] The transistor 200 is provided above the insulator 216. The structure of 200 includes the structure of a transistor included in the semiconductor device described in the previous embodiment. The transistor 200 shown in FIG. 38 is an example, and the present invention is not limited to this structure. It is only necessary to use an appropriate transistor depending on the circuit configuration and driving method.

[0483] Above the transistor 200, an insulator 280 is provided.

[0484] An insulator 282 is provided on the insulator 280. The insulator 282 is resistant to oxygen and hydrogen. Therefore, the insulator 282 is preferably made of a material having a barrier property against the insulator. The insulator 282 can be made of the same material as 214. For example, the insulator 282 can be made of aluminum oxide. It is preferable to use metal oxides such as titanium, hafnium oxide, and tantalum oxide.

[0485] In particular, aluminum oxide is highly resistant to oxygen and water, which can cause fluctuations in the electrical characteristics of transistors. It has a high blocking effect that prevents impurities such as oxygen and moisture from penetrating the membrane. Aluminum oxide is a material that can withstand hydrogen, moisture, and other chemicals during and after the transistor manufacturing process. This can prevent impurities from entering the transistor 200. This can suppress the release of oxygen from the oxide that makes up the transistor. It is suitable for use as a protective film for the capacitor 200.

[0486] Further, an insulator 283 is provided on the insulator 282. The insulator 283 is The same materials as those in 320 can be used. In addition, materials with a relatively low dielectric constant can be used as the interlayer film. For example, the insulator 283 and the As the insulating film, a silicon oxide film, a silicon oxynitride film, or the like can be used.

[0487] Also, the insulators 220, 222, 280, 282, and 28 3 has conductors 246, 248, etc. embedded therein.

[0488] The conductor 246 and the conductor 248 are connected to the capacitor 100, the transistor 200, or The conductor 24 functions as a plug or wiring that is electrically connected to the transistor 300. 6 and conductor 248 are formed using the same material as conductor 328 and conductor 330. It can be achieved.

[0489] Next, the capacitor 100 is provided above the transistor 200. 100 includes a conductor 110, a conductor 120, and an insulator .

[0490] The conductor 112 may be provided on the conductor 246 and the conductor 248. 112 is electrically connected to the capacitor element 100, the transistor 200, or the transistor 300. The conductor 110 functions as a plug or wiring for connection. The conductor 112 and the conductor 110 can be formed simultaneously. do.

[0491] The conductor 112 and the conductor 110 may be made of molybdenum, titanium, tantalum, tungsten, or the like. Metal film containing elements selected from the group consisting of silicon, aluminum, copper, chromium, neodymium, and scandium or a metal nitride film containing the above-mentioned elements (tantalum nitride film, titanium nitride film, nitride Molybdenum film, tungsten nitride film, etc. can be used. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide, Conductive materials such as indium zinc oxide and indium tin oxide doped with silicon oxide are used. It is also possible to do so.

[0492] In FIG. 38, the conductor 112 and the conductor 110 are shown as a single layer structure, but this structure is not limited thereto. For example, a conductive material having a barrier property and a conductive material having a high conductivity may be used. Conductors with barrier properties between weak conductors and highly conductive conductors with good adhesion may form a highly conductive material.

[0493] In addition, an insulating layer is formed on the conductor 112 and the conductor 110 as a dielectric of the capacitance element 100. The insulator 130 is made of, for example, silicon oxide, silicon oxynitride, or silicon nitride. Silicon nitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide Aluminum, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride , hafnium nitride, or the like may be used, and the insulating layer may be provided as a laminated layer or a single layer.

[0494] For example, if a material with high dielectric strength such as silicon oxynitride is used for the insulator 130, With this configuration, the capacitance element 100 has an improved dielectric strength due to the insulator 130. Furthermore, electrostatic breakdown of the capacitance element 100 can be suppressed.

[0495] The conductor 120 is provided over the insulator 130 so as to overlap with the conductor 110. The conductive body 120 may be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum are used, which have both heat resistance and electrical conductivity. It is preferable to use tungsten, and it is particularly preferable to use other materials such as conductors. When forming the structure at the same time, low-resistance metal materials such as Cu (copper) and Al (aluminum) are used. ) etc. can be used.

[0496] An insulator 150 is provided on the conductor 120 and the insulator 130. The insulator 50 can be made of the same material as the insulator 320. , and may function as a planarizing film that covers the underlying unevenness.

[0497] By using this structure, a semiconductor device using a transistor having an oxide semiconductor This makes it possible to suppress fluctuations in electrical characteristics and improve reliability. A transistor including an oxide semiconductor with a large current can be provided. It is possible to provide a transistor including an oxide semiconductor with low current. It is possible to provide a semiconductor device with low power consumption.

[0498] <Modification of Storage Device 1> An example of a memory device according to one embodiment of the present invention will be described below with reference to FIG.

[0499] FIG. 40 shows a circuit having a capacitance element 100, a transistor 200, and a transistor 300. 40 is a cross-sectional view of a storage device. In the storage device shown in FIG. and the semiconductor device shown in <Structure of memory device 1>, and the components constituting the memory device and the same function The components having the same functions are denoted by the same reference numerals.

[0500] The storage device shown in FIG. 40 is a combination of the storage device shown in <Structure of Storage Device 1> and the storage device shown in the previous embodiment. 1. is different in that the cell 600 described in the previous section is provided.

[0501] Specifically, the memory device shown in FIG. 40 has a part of a configuration including a capacitor element 100 and a transistor 2. 00 and has cell 600 shared by

[0502] With the above structure, the cell 600 and the transistor 300 are partially or entirely overlapped. By doing so, the projected area of ​​the memory device can be reduced. This also makes it easier to achieve high integration, and shortens the manufacturing process.

[0503] (Fourth embodiment) In this embodiment, a semiconductor device using an oxide according to one embodiment of the present invention will be described with reference to FIGS. The transistors used in the body (hereinafter referred to as OS transistors) and the capacitance elements are applied. As an example of a storage device, NOSRAM (registered trademark) will be described. M stands for "Nonvolatile Oxide Semiconductor RAM" It is an abbreviation for RAM with gain cell type (2T type, 3T type) memory cells. In the following, a memory device using OS transistors such as NOSRAM will be referred to as OS It may be called memory.

[0504] NOSRAM is a memory device that uses OS transistors in memory cells (hereinafter referred to as The OS memory is composed of at least a capacitive element and a This is a memory with an OS transistor that controls the charging and discharging of the cells. Since the OS memory is an off-state transistor, it has excellent retention characteristics and is nonvolatile. It can function as a library.

[0505] <nosram> FIG. 41 shows an example of the configuration of the NOSRAM 1600. The NOSRAM 1600 shown in FIG. , memory cell array 1610, controller 1640, row driver 1650, column driver 1660 and an output driver 1670. The NOSRAM 1600 is a memory It is a multi-level NOSRAM that stores multi-level data in cells.

[0506] The memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL, RW L, bit lines BL, and source lines SL. Word lines WWL are write word lines. The word line RWL is the read word line. In NOSRAM1600, one memory cell 1611 stores 3-bit (8-value) data.

[0507] The controller 1640 controls the entire NOSRAM 1600 and outputs the data WDA Writes data to [31:0] and reads data from RDA[31:0]. Controller 1 640 is an external command signal (for example, a chip enable signal, a write enable signal, etc.). 1650, column drivers 1660, and output drivers 1670 control signals are generated.

[0508] The row driver 1650 has the function of selecting a row to access. has a row decoder 1651 and a word line driver 1652.

[0509] The column driver 1660 drives the source lines SL and bit lines BL. 60 includes a column decoder 1661, a write driver 1662, and a DAC (digital-to-analog conversion circuit) 1663.

[0510] The DAC1663 converts 3-bit digital data into an analog voltage. 3 converts the 32-bit data WDA[31:0] into an analog voltage every 3 bits. .

[0511] The write driver 1662 has a function of precharging the source line SL, A function for electrically floating a source line SL, a function for selecting a source line SL, and a function for selecting a source line SL. This function inputs the write voltage generated by the DAC1663 and precharges the bit line BL. and the function of electrically floating the bit line BL.

[0512] The output driver 1670 includes a selector 1671, an ADC (analog-to-digital conversion circuit), 1672 and an output buffer 1673. The selector 1671 selects the source line to be accessed. SL is selected and the voltage of the selected source line SL is sent to the ADC1672. 72 has the function of converting an analog voltage into 3-bit digital data. The voltage is converted into 3-bit data by the ADC 1672 and output to the output buffer 1673. holds the data output from the ADC1672.

[0513] In this embodiment, the row driver 1650, the column driver 1660, and the output driver The configuration of the driver 1670 is not limited to the above. Depending on the configuration or driving method, these drivers and the wiring connected to the drivers may be The layout of the lines may be changed, and the layout of these drivers and the wiring connected to them may be changed. The functions of the source line SL may be changed or added. The portion may be provided on the bit line BL.

[0514] In the above, the amount of information stored in each memory cell 1611 is set to 3 bits. The configuration of the memory device shown in this embodiment is not limited to this. The amount of information to be transmitted may be 2 bits or less, or 4 bits or more. When the amount of information stored in memory cell 1611 is set to 1 bit, the DAC1663 and AD A configuration without C1672 is also possible.

[0515] <Memory cell> 42A is a circuit diagram showing a configuration example of the memory cell 1611. is a 2T type gain cell, and the memory cell 1611 is connected to word lines WWL, RWL, and bit lines BL, a source line SL, and a wiring BGL. The transistor MO61 has a node SN, an OS transistor MP61, and a capacitance element C61. The OS transistor MO61 is a write transistor. The OS transistor MP61 is a read transistor. The capacitance element is a transistor that is a p-channel Si transistor, for example. The capacitor C61 is a storage capacitor for holding the voltage of the node SN. The node SN is a data storage capacitor. This node corresponds to the gate of transistor MP61 in this example.

[0516] The write transistor of memory cell 1611 is composed of OS transistor MO61. Therefore, the NOSRAM 1600 can retain data for a long time.

[0517] In the example of FIG. 42(A), a common bit line is provided for writing and reading. As shown in 42(B), a bit line WBL functions as a write bit line, and a read bit line WBL functions as a read bit line. A bit line RBL may also be provided, which functions as a bit line.

[0518] Other examples of memory cell configurations are shown in Figures 42(C) to 42(E). (E) shows an example in which a write bit line WBL and a read bit line RBL are provided. However, even if a bit line is provided that is shared between writing and reading as shown in FIG. good.

[0519] The memory cell 1612 shown in FIG. 42C is a modified example of the memory cell 1611. The output transistor has been changed to an n-channel transistor (MN61). The transistor MN61 may be an OS transistor or a Si transistor. stomach.

[0520] In the memory cells 1611 and 1612, the OS transistor MO61 has a back gate An OS transistor without the gate insulating film may be used.

[0521] The memory cell 1613 shown in FIG. 42(D) is a 3T type gain cell, and is connected to the word line WWL , RWL, bit lines WBL, RBL, source lines SL, and wirings BGL and PCL. The memory cell 1613 includes a node SN, an OS transistor MO62, and a transistor The OS transistor MO 62 is a write transistor. Transistor MP62 is a read transistor. The transistor MP63 is a selection transistor.

[0522] The memory cell 1614 shown in FIG. 42(E) is a modified example of the memory cell 1613. The output transistor and the selection transistor are n-channel transistors (MN62, MN 63). Transistors MN62 and MN63 are OS transistors. Alternatively, a Si transistor may be used.

[0523] The OS transistors provided in the memory cells 1611-1614 have no back gate. The transistor may be a transistor having a back gate.

[0524] In the above, memory cells 1611 and the like are connected in parallel, so-called NOR type memory cells. Although the storage device has been described above, the storage device shown in this embodiment is not limited to this. For example, the following memory cells 1615 are connected in series, so-called NAND The storage device may be of the same type.

[0525] 43 is a circuit diagram showing an example of the configuration of a NAND-type memory cell array 1610. The memory cell array 1610 shown in FIG. 1 includes source lines SL, bit lines RBL, bit lines WBL, It has word lines WWL, word lines RWL, wiring BGL, and memory cells 1615. The memory cell 1615 includes a node SN, an OS transistor MO63, a transistor MN64, The transistor MN64 is, for example, an n-channel Si transistor. The transistor MN64 is not limited to this, but may be a p-channel Si The transistor may be a silicon nitride semiconductor (SiN) transistor or an OS transistor.

[0526] In the following, memory cells 1615a and 1615b shown in FIG. 43 will be taken as examples. Here, the connection to either memory cell 1615a or memory cell 1615b is The symbols of the wiring or circuit elements are indicated by adding the symbol a or b.

[0527] In the memory cell 1615a, the gate of the transistor MN64a and the gate of the OS transistor One of the source and drain of the capacitor MO63a and one of the electrodes of the capacitance element C63a are connected to a potential The bit line WBL and the source and The other of the drains is electrically connected to the word line WWLa. The gate of the transistor MO63a is electrically connected to the wiring BGLa. The back gate of the OS transistor MO63a is electrically connected to the The wire RWLa and the other electrode of the capacitance element C63a are electrically connected to each other.

[0528] The memory cell 1615b is symmetrical about the contact portion with the bit line WBL. Therefore, the memory cell 1615b can be provided symmetrically to the memory cell 1615a. The circuit elements are connected to the wiring in the same manner as the memory cell 1615a.

[0529] Furthermore, the source of the transistor MN64a of the memory cell 1615a is connected to the The drain of the transistor MN64b in the memory cell 1615b is electrically connected to the drain of the transistor MN64b in the memory cell 1615b. The drain of the transistor MN64a in the 615a is electrically connected to the bit line RBL. The source of the transistor MN64b in the memory cell 1615b is connected to a plurality of memory The resistor 1615 is electrically connected to the source line SL through a transistor MN64. In this way, in the NAND type memory cell array 1610, the bit line RBL and the source A plurality of transistors MN64 are connected in series between the lines SL.

[0530] In the memory device having the memory cell array 1610 shown in FIG. or word line RWL) (hereinafter referred to as a memory cell column) For example, a write operation is performed as follows: The OS transistor is connected to the word line WWL connected to the memory cell column to be written. The OS transistor of the memory cell row to be written is applied with a potential that turns on the transistor MO63. This turns on the transistor MN The potential of the bit line WBL is applied to the gate of the capacitor C64 and one of the electrodes of the capacitor C63. A predetermined charge is applied to the gate of the OS transistor MO6 of the memory cell column. When 3 is turned off, the predetermined charge given to the gate can be maintained. In this way, data can be written to the memory cell 1615 in the specified memory cell column. do.

[0531] Also, for example, a read operation can be performed as follows. First, A word line RWL not connected to a memory cell column is connected to the gate of transistor MN64. A potential is applied so that the transistor MN64 is turned on regardless of the charge stored in the memory cell. The transistors MN64 in the memory cell columns other than the one to be read are turned on. The gate of the transistor MN64 is connected to the word line RWL connected to the memory cell column to be read. The charge stored in the transistor MN64 selects the on or off state. A constant potential is applied to the source line SL, and a constant potential is applied to the bit line RB. The read circuit connected to the source line SL and the bit line R is set to an operating state. The multiple transistors MN64 between the BLs are in the on state except for the memory cell column to be read. Therefore, the conductance between the source line SL and the bit line RBL is This is determined by the state (on or off) of transistor MN64 in the memory cell column. The charge on the gate of the transistor MN64 in the memory cell column to be read is Therefore, the conductance of the transistors is different, and the voltage of the bit line RBL is accordingly The potential of the bit line RBL is read by the read circuit. This allows information to be read from the memory cells 1615 in the specified memory cell column.

[0532] Data is written by charging and discharging the capacitor C61, capacitor C62, or capacitor C63. Therefore, in principle, NOSRAM1600 has no restrictions on the number of times it can be rewritten, and It is possible to write and read data with low energy consumption. Since it is possible to maintain the data, the frequency of refreshing can be reduced.

[0533] The semiconductor device shown in the above embodiment is 4, 1615, the transistors MO61, MO62, and MO63 are used as The capacitor 200 is used, and the capacitor 100 is used as the capacitors C61, C62, and C63. Transistors MP61, MP62, MP63, MN61, MN62, MN63, MN64 The transistor 300 can be used as the capacitor. Since the area occupied by each set in top view can be reduced, Therefore, the memory device according to this embodiment can be more highly integrated. The storage capacity per unit area can be increased.

[0534] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0535] (Embodiment 5) In this embodiment, a semiconductor device using an oxide according to one embodiment of the present invention will be described with reference to FIGS. 44 and 45. A transistor using an OS transistor as a conductor and a capacitor are applied. As an example of a commonly used memory device, DOSRAM (registered trademark) will be described. AM stands for "Dynamic Oxide Semiconductor RAM" It is a name for RAM that has 1T (transistor) 1C (capacitor) type memory cells.

[0536] DOSRAM is a memory device that uses OS transistors in memory cells (hereinafter referred to as The OS memory is composed of at least a capacitive element and a This is a memory with an OS transistor that controls the charging and discharging of the cells. Since the OS memory is an off-state transistor, it has excellent retention characteristics and is nonvolatile. It can function as a library.

[0537] <dosram1400> An example of the configuration of the DOSRAM is shown in Figure 44. As shown in Figure 44, the DOSRAM 1400 , controller 1405, row circuit 1410, column circuit 1415, memory cells and sense amplifiers The MC-SA array 1420 includes a MC-SA array 1420.

[0538] The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 14 13, sense amplifier driver circuit 1414. Column circuit 1415 is a global sense The global sense amplifier array 1416 includes an amplifier array 1416 and an input / output circuit 1417. 416 has a plurality of global sense amplifiers 1447. The MC-SA array 1420 Memory cell array 1422, sense amplifier array 1423, global bit line GBLL , with GBLR.

[0539] (MC-SA Array 1420) The MC-SA array 1420 connects the memory cell array 1422 to the sense amplifier array 142 The global bit lines GBLL and GBLR are connected to the memory cell array. In the DOSRAM 1400, the bit line structure is A hierarchical bit line structure is adopted, which is hierarchical with local bit lines and global bit lines. .

[0540] The memory cell array 1422 is a local memory cell array of N (N is an integer of 2 or more). 1425 <0> -1425 <n-1>FIG. 45(A) shows a local memory cell array. The local memory cell array 1425 includes a plurality of memory cells 1 445, a plurality of word lines WL, a plurality of bit lines BLL, BLR. In the example, the local memory cell array 1425 has an open bit line structure. It may be of the hard-dead bit line type.

[0541] FIG. 45B shows a set of memory cells 14 connected to a common bit line BLL (BLR). The memory cell 1445a is a transistor. The memory cell has a word line WLa, a bit line MW1a, a capacitor CS1a, and terminals B1a and B2a. The memory cell 1445b is connected to the transistor MW1. b, a capacitor CS1b, terminals B1b and B2b, and a word line WLb, a bit line BLL( BLR). In the following, memory cell 1445a and memory cell 1 445b are not particularly limited, the memory cell 1445 and its associated The configuration may not be marked with the letter a or b.

[0542] The transistor MW1a has the function of controlling the charge and discharge of the capacitance element CS1a. The transistor MW1b has the function of controlling the charging and discharging of the capacitance element CS1b. The gate is electrically connected to the word line WLa, and the first terminal is electrically connected to the bit line BLL (BLR). The second terminal is electrically connected to the first terminal of the capacitive element CS1a. The gate of the transistor MW1b is electrically connected to the word line WLb, and the first terminal is connected to the bipolar transistor MW1b. The second terminal is electrically connected to the bit line BLL (BLR), and the second terminal is connected to the first terminal of the capacitance element CS1b. are electrically connected.

[0543] The second terminal of the capacitance element CS1 is electrically connected to the terminal B2. A voltage (for example, a low power supply voltage) is input.

[0544] When the semiconductor device described in the above embodiment is used for the memory cells 1445a and 1445b, The transistor MW1a is the transistor 200a, and the transistor MW1b is the transistor 200b. The capacitor CS1a is connected to the capacitor 100a and the capacitor CS1b is connected to the capacitor 200b. The capacitor 100b can be used as a pair of a transistor and a capacitor. Since the area occupied by the hits in a top view can be reduced, the memory according to this embodiment Therefore, the memory device according to this embodiment can achieve a high degree of integration. This allows for an increase in storage capacity.

[0545] Transistor MW1 has a back gate that is electrically connected to terminal B1. Therefore, the voltage at terminal B1 controls the threshold voltage of transistor MW1. For example, the voltage at terminal B1 is a fixed voltage (e.g., a constant negative voltage). Alternatively, the voltage at the terminal B1 may be changed depending on the operation of the DOSRAM 1400. stomach.

[0546] The back gate of transistor MW1 is connected to the gate, first terminal, or Alternatively, a back gate may be provided to the transistor MW1. It is not necessary.

[0547] The sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> - 1426 <n-1>The local sense amplifier array 1426 has one switch amplifier. The array 1444 includes a plurality of sense amplifiers 1446. The sense amplifiers 1446 include a bit The sense amplifier 1446 precharges the bit line pair. The function of this transistor is to amplify the voltage difference between the bit line pair, and to maintain this voltage difference. The switch array 1444 selects a bit line pair and connects the selected bit line pair to the global bit line. It has the function of establishing electrical continuity between the line pair.

[0548] Here, a bit line pair is a pair of two bit lines that are compared simultaneously by a sense amplifier. The global bit line pair is a pair of lines that are simultaneously compared by a global sense amplifier. A bit line pair is also called a pair of bit lines. and the global bit line pair can be called a pair of global bit lines. In the example, the bit line BLL and the bit line BLR form a bit line pair. The BLL and the global bit line GBLR form a global bit line pair. They are also referred to as a bit line pair (BLL, BLR) and a global bit line pair (GBLL, GBLR).

[0549] (Controller 1405) The controller 1405 has a function of controlling the overall operation of the DOSRAM 1400 . The controller 1405 performs logical operations on command signals input from the outside and determines the operation mode. The row circuit 1410 and the column circuit 1420 are provided to determine the operation mode. 415 control signal generation function, the function of holding the address signal input from the outside, It has the function of generating an external address signal.

[0550] (row circuit 1410) The row circuit 1410 functions to drive the MC-SA array 1420. The word line driver circuit 1412 has the function of decoding the address signal. A selection signal is generated to select the word line WL of the row to be accessed.

[0551] The column selector 1413 and the sense amplifier driver circuit 1414 are connected to the sense amplifier array 142. 3. The column selector 1413 selects the bit line of the column to be accessed. The column selector 1413 has a function of generating a selection signal for selecting The switch array 1444 of each local sense amplifier array 1426 is controlled. The control signals of the amplifier driver circuit 1414 control the local sense amplifier arrays 1 The 426 is independently driven.

[0552] (column circuit 1415) The column circuit 1415 has a function of controlling the input of the data signal WDA[31:0], The data signal WDA[31:0] has the function of controlling the output of RDA[31:0]. The data signal RDA[31:0] is a write data signal, and the data signal RDA[31:0] is a read data signal.

[0553] The global sense amplifier 1447 supplies power to the global bit line pair (GBLL, GBLR). The global sense amplifier 1447 is electrically connected to the global bit line pair (GB It has the function of amplifying the voltage difference between the Globe and Globe (LL, GBLR) and the function of maintaining this voltage difference. Data is written to and read from the global bit line pair (GBLL, GBLR) This is done by the output circuit 1417.

[0554] The write operation of the DOSRAM 1400 will be briefly described. The data is written to the global bit line pair. The address signal is held by the global sense amplifier array 1416. The switch array 1444 of the sense amplifier array 1426 controls the global bit The data on the line pair is written to the bit line pair of the target column. 26 amplifies and stores the written data. In 1425, the row circuit 1410 selects the word line WL of the target row, and the selected row The data held in the local sense amplifier array 1426 is written to the memory cell 1445 of the do.

[0555] The outline of the read operation of the DOSRAM1400 is explained below. One row of the local memory cell array 1425 is specified. In row 1425, the word line WL of the target row is selected, and the data of memory cell 1445 is The local sense amplifier array 1426 writes data to the bit lines. The voltage difference between the bit line pair is detected as data and stored. The address signal is specified among the data held in the local sense amplifier array 1426. The data of the corresponding column is written to the global bit line pair. The global sense amplifier 1416 detects and holds the data on the global bit line pair. The data held in the amplifier array 1416 is output to the input / output circuit 1417. The operation is completed.

[0556] In order to rewrite data by charging and discharging the capacitance element CS1, DOSRAM1400 has In principle, there is no limit to the number of times it can be rewritten, and data can be written and rewritten with low energy. In addition, since the circuit configuration of the memory cell 1445 is simple, it is possible to read large capacity data. It is easy to convert.

[0557] The transistor MW1 is an OS transistor. Since it is small, it is possible to prevent the charge from leaking from the capacitance element CS1. Therefore, the retention time of DOSRAM1400 is much longer than that of DRAM. This reduces the frequency of refresh operations, thereby reducing the power required for refresh operations. DOSRAM1400 is a memory device that frequently rewrites large amounts of data, such as images. It is suitable for the frame memory used in processing.

[0558] The MC-SA array 1420 has a stacked structure, and thus the local sense amplifier array The bit line can be shortened to a length similar to that of 1426. This reduces the bit line capacitance and reduces the storage capacitance of the memory cell 1445. In addition, the local sense amplifier array 1426 can be provided with a switch array 1444. This reduces the number of long bit lines. The load to be driven when accessing 0 is reduced, and power consumption can be reduced.

[0559] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. It is possible.

[0560] (Sixth embodiment) In this embodiment mode, a semiconductor device according to the above embodiment mode is applied to a semiconductor device A shown in FIG. I will explain the system.

[0561] FIG. 46 is a block diagram showing an example of the configuration of the AI ​​system 4041. 1 includes a calculation unit 4010, a control unit 4020, and an input / output unit 4030.

[0562] The calculation unit 4010 includes an analog calculation circuit 4011, a DOSRAM 4012, and a NOSR. It has AM4013, FPGA4014, DOSRAM4012 and NOSR As the AM4013, DOSRAM1400 and NOSRAM shown in the above embodiment are used. 1600 can be used.

[0563] The control unit 4020 includes a CPU (Central Processing Unit) 40 21, GPU (Graphics Processing Unit) 4022, and P LL (Phase Locked Loop) 4023 and SRAM (Static R andom Access Memory) 4024 and PROM (Programma ble Read Only Memory) 4025 and memory controller 4026 , a power supply circuit 4027, and a PMU (Power Management Unit) 40 28 and has.

[0564] The input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, and a video a codec 4033, a general-purpose input / output module 4034, and a communication module 4035; It has.

[0565] The calculation unit 4010 can perform learning or inference using a neural network. Cut.

[0566] The analog arithmetic circuit 4011 is an A / D (analog / digital) conversion circuit, a D / A (digital It has a digital / analog conversion circuit and a multiply-and-accumulate circuit.

[0567] The analog arithmetic circuit 4011 is preferably formed using an OS transistor. The analog arithmetic circuit 4011 using a transistor has an analog memory and performs learning or This makes it possible to perform the multiply-and-accumulate operations required for inference with low power consumption.

[0568] The DOSRAM4012 is a DRAM formed using OS transistors. The SRAM4012 temporarily stores digital data sent from the CPU4021. The DOSRAM4012 is a memory that uses memory cells that include OS transistors and Si The memory cell and the readout circuit section are stacked. Since the DOSRAM4012 can be placed on different layers, the total circuit area can be reduced It can be made smaller.

[0569] Calculations using neural networks can involve more than 1,000 pieces of input data. When storing the above input data in SRAM4024, the circuit area of ​​SRAM4024 is limited. Since the memory capacity is small, the input data must be stored in small chunks. The OSRAM4012 allows memory cells to be highly integrated even in a limited circuit area. It has a larger memory capacity than SRAM4024. 2 can store the above input data efficiently.

[0570] NOSRAM4013 is a non-volatile memory that uses OS transistors. The M4013 is a memory card that can be used with flash memory and ReRAM (Resistive Random Access Memory). Access Memory), MRAM (Magnetoresistive Ran Compared to other non-volatile memories such as DDR Memory (DDR3), writing data is It consumes less power when writing data. The elements do not deteriorate when writing, and there is no limit to the number of times data can be written.

[0571] In addition to 1-bit binary data, the NOSRAM4013 can also handle multi-level data of 2 or more bits. NOSRAM4013 can store multi-value data. The memory cell area per bit can be reduced.

[0572] In addition, NOSRAM4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 converts the NOSRAM 4013 into an analog memory. The NOSRAM4013 can also be used as a memory. Therefore, D / A conversion circuits and A / D conversion circuits are not required. The RAM 4013 can reduce the area of ​​the peripheral circuits. Analog data refers to data with a resolution of 3 bits (8 values) or more. Multi-valued data may also be included in analog data.

[0573] The data and parameters used in the neural network calculations are stored in NOSRA. The above data and parameters can be stored in the M4013 via the CPU4021. The data may be stored in a memory provided outside the AI ​​system 4041, but may also be stored in a memory provided inside the AI ​​system 4041. The NOSRAM4013, which is equipped with the DDR3 RAM, stores the above data and parameters at higher speeds and with lower power consumption. The NOSRAM4013 also has a higher bit rate than the DOSRAM4012. Since the bit lines can be made longer, the storage capacity can be increased.

[0574] The FPGA 4014 is an FPGA using OS transistors. GA can apply OS memory to configuration memory and registers. Here, we call this type of FPGA "OS-FPGA." AI System 40 41 uses FPGA4014 to implement deep neural networks, which will be described later. Neural Networks (DNN), Convolutional Neural Networks (CNN), Recurrent Neural Networks Network (RNN), Autoencoder, Deep Boltzmann Machine (DBM), Deep Belief Network Hardware configuration of neural network connections, such as DBNs By configuring the above neural network connections in hardware, It can be executed at high speed.

[0575] FPGA4014 is an OS-FPGA. OS-FPGA is composed of SRAM. The memory area can be smaller than that of FPGA. Even if additional functions are added, the area increase is small. It can transmit data and parameters at high speed.

[0576] The AI ​​system 4041 is composed of an analog arithmetic circuit 4011, a DOSRAM 4012, and an NOS The RAM4013 and FPGA4014 can be mounted on a single die (chip). Therefore, the AI ​​system 4041 is designed to be fast and low power consumption, and to use neural networks. In addition, the analog arithmetic circuit 4011 and the DOSRAM4 The 012, NOSRAM4013, and FPGA4014 are manufactured using the same manufacturing process. Therefore, the AI ​​system 4041 can be manufactured at low cost. .

[0577] The calculation unit 4010 includes a DOSRAM 4012, a NOSRAM 4013, and an FP It is not necessary to have all of GA4014. Depending on the problem that AI system 4041 wants to solve, DOSRAM4012, NOSRAM4013, and FPGA4014. A plurality of the above may be selected and provided.

[0578] AI System 4041 uses deep neural networks to solve various problems. (DNN), Convolutional Neural Network (CNN), Recurrent Neural Network RNN, autoencoder, deep Boltzmann machine (DBM), deep belief network The PROM4025 can implement techniques such as DBN. It is possible to store a program for executing at least one program. Some or all of the program may be stored in NOSRAM 4013.

[0579] Existing programs that exist as libraries are based on GPU processing. Therefore, it is preferable that the AI ​​system 4041 has a GPU 4022. The system 4041 performs the multiply-and-accumulate operation, which is the rate-limiting operation used in learning and inference. The multiplication and accumulation operations can be executed by the calculation unit 4010, and other multiplication and accumulation operations can be executed by the GPU 4022. This allows for faster learning and inference.

[0580] The power supply circuit 4027 not only generates a low power supply potential for the logic circuit but also The power supply circuit 4027 may also use an OS memory. 27 can reduce power consumption by storing the reference potential in the OS memory.

[0581] PMU4028 has the function of temporarily turning off the power supply to AI System 4041. do.

[0582] The CPU 4021 and the GPU 4022 preferably have OS memory as a register. The CPU 4021 and the GPU 4022 have OS memory, so the power supply is Even when the power is turned off, the data (logical values) can still be stored in the OS memory. As a result, the AI ​​system 4041 can save power.

[0583] The PLL 4023 has the function of generating a clock. It operates based on the clock generated by PLL4023. PLL4023 has OS memory. It is preferable that the PLL4023 has an OS memory, which allows the clock oscillation period to be adjusted. The analog potential to be controlled can be held.

[0584] The AI ​​system 4041 may store data in external memory such as DRAM. Therefore, the AI ​​System 4041 uses memory that acts as an interface with external DRAM. It is preferable that the memory controller 4026 is included. It is preferable to place it near the CPU 4021 or the GPU 4022. This allows for high-speed data exchange.

[0585] Some or all of the circuits shown in the control unit 4020 are formed on the same die as the operation unit 4010. By doing so, the AI ​​system 4041 can achieve high speed and low power consumption. Neural network calculations can be performed.

[0586] The data used for neural network calculations is stored in an external storage device (HDD). Hard Disk Drive, SSD (Solid State Drive), etc.) Therefore, the AI ​​system 4041 does not have an interface with an external storage device. It is preferable that the external memory control circuit 4031 functions as an interface.

[0587] Learning and inference using neural networks often involves audio and video, so The I system 4041 has an audio codec 4032 and a video codec 4033 . The audio codec 4032 encodes and decodes audio data. The video codec 4033 encodes and decodes the video data.

[0588] The AI ​​system 4041 performs learning or inference using data obtained from external sensors. Therefore, the AI ​​system 4041 has a general-purpose input / output module 4034. The general-purpose input / output module 4034 is, for example, a USB (Universal Ser ial Bus) and I2C (Inter-Integrated Circuit), etc. Includes:

[0589] The AI system 4041 can learn or perform inference using data obtained via the Internet. Therefore, the AI system 4041 preferably has a communication module 403 5.

[0590] The analog arithmetic circuit 4011 may use a multi-valued flash memory as an analog memory. However, the flash memory has a limited number of rewritable times. Also, it is very difficult to form a multi-valued flash memory embedded (forming the arithmetic circuit and the memory on the same die).

[0591] Also, the analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limited number of rewritable times and also has problems in terms of storage accuracy. Furthermore, since it is a two-terminal element, the circuit design for separating data writing and reading becomes complicated.

[0592] Also, the analog arithmetic circuit 4011 may use MRAM as an analog memory. However, MRAM has a low resistance change rate and has problems in terms of storage accuracy.

[0593] In view of the above, it is preferable for the analog arithmetic circuit 4011 to use an OS memory as an analog memory.

[0594] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments and the like.

[0595] (Embodiment 7) <Application Examples of AI System> In this embodiment, regarding the application examples of the AI system shown in the above embodiment, FIG. 47 is used The explanation will be given below.

[0596] FIG. 47(A) shows the AI ​​system 4041 described in FIG. 46 arranged in parallel and connected via a bus line. This is AI system 4041A, which enables signals to be sent and received between systems.

[0597] The AI ​​system 4041A shown in FIG. 47(A) includes a plurality of AI systems 4041_1 to AI systems 4041_n (n is a natural number). The AI ​​systems 4041_n are connected to each other via a bus line 4098.

[0598] 47(B) shows the AI ​​system 4041 described in FIG. 46 in the same manner as in FIG. 47(A). AI systems are arranged in parallel, enabling signals to be sent and received between systems via a network. The stem is 4041B.

[0599] The AI ​​system 4041B shown in FIG. 47(B) is a system including a plurality of AI systems 4041_1 The AI ​​systems 4041_1 to 4041_n are 041_n are connected to each other via a network 4099.

[0600] The network 4099 is a network of the AI ​​systems 4041_1 to 4041_n. Each of them may be provided with a communication module, and configured to perform wireless or wired communication. The communication module can communicate via an antenna. For example, World Wi The Internet, intranets, and extranets that form the foundation of the World Wide Web (WWW) PAN (Personal Area Network), LAN (Local A rea Network), CAN (Campus Area Network), MA N (Metropolitan Area Network), WAN (Wide Ar Network), GAN (Global Area Network), etc. It is possible to connect each electronic device to a computer network and communicate with it. In this case, LTE (Long Term Evolution) is used as the communication protocol or technology. tion), GSM (Global System for Mobile Commu) nication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Divisio n Multiple Access 2000), W-CDMA (registered trademark), etc. Communication standards, such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigBe IEEE communication standard specifications such as IEEE e (registered trademark) can be used.

[0601] By using the configuration shown in Figure 47(A) and (B), analog signals obtained from external sensors etc. can be It can be processed by separate AI systems. For example, biometric information such as brain waves, pulse, Information such as blood pressure and body temperature is transmitted via a brain wave sensor, pulse wave sensor, blood pressure sensor, and temperature sensor. It is possible to acquire data from various sensors and process the analog signals with separate AI systems. Each AI system processes signals or learns, creating a single AI system. Therefore, the amount of information processing required for signal processing or learning can be reduced. As a result, recognition accuracy can be improved. The information obtained by the system allows for instant, integrated understanding of complexly changing biological information. We can expect the following to happen.

[0602] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0603] (Embodiment 8) This embodiment is a system incorporating the AI ​​system shown in the above embodiment. An example of an IC is shown below.

[0604] The AI ​​system shown in the above embodiment is a digital processor such as a CPU, which is made up of Si transistors. logic circuits, analog arithmetic circuits using OS transistors, OS-FPGA and DOSR OS memory such as AM and NOSRAM can be integrated onto a single die.

[0605] Figure 48 shows an example of an IC incorporating an AI system. The IC7000 has leads 7001 and a circuit section 7003. For example, the IC chip is mounted on a printed circuit board 7002. These are electrically connected to each other on the printed circuit board 7002, and electronic components are mounted on them. The circuit portion 7003 has the same structure as that shown in the above embodiment mode. The circuit section 7003 is similar to the circuit section 7001 shown in the previous embodiment. As shown, it has a stacked structure, and is made up of a Si transistor layer 7031, a wiring layer 7032, an OS transistor, The OS transistor layer 7033 is divided into a Si transistor layer 7031 and a Since the ICs can be stacked on top of each other, it is easy to miniaturize the AI ​​system IC7000.

[0606] In Figure 48, the AI ​​system IC7000 is packaged in a QFP (Quad Flat Packaging) However, the form of the package is not limited to this.

[0607] Digital processing circuits such as CPUs and analog arithmetic circuits using OS transistors, FPGAs and OS memories such as DOSRAM and NOSRAM are all made of Si transistors. layer 7031, a wiring layer 7032, and an OS transistor layer 7033. In other words, the elements that make up the AI ​​system can be formed in the same manufacturing process. Therefore, the IC shown in this embodiment can be manufactured in a simple manner even if the number of constituent elements increases. There is no need to increase the number of servers, and the AI ​​system can be incorporated at low cost.

[0608] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0609] (Embodiment 9) <Electronic equipment> The semiconductor device according to one embodiment of the present invention can be used in various electronic devices. 50A and 50B illustrate specific examples of electronic devices using a semiconductor device according to one embodiment of the present invention.

[0610] The robot 2000 shown in FIG. 49(A) includes a computing device 2001, a sensor 2002, a light 2003, a lift 2004, a drive unit 2005, and a moving mechanism 2011. These robots can be used in security systems and surveillance equipment. It can be used as a visual system.

[0611] The robot 2000 further includes a communication means 2006, a speaker 2007, a microphone 2008, a display unit 2009, a light emitting unit 2010, etc.

[0612] The semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 2001. The arithmetic device 2001 uses an IC incorporating an AI system according to one embodiment of the present invention. The sensor 2002 acts as a camera that captures the surroundings of the robot 2000. The light 2003 captures the surroundings of the robot 2000 using the sensor 2002. It can be used as a light when taking a still image with the sensor 2002. Preferably, the light 2003 functions as a flashlight. 2002 is connected to the robot body via a lift 2004. The height can be adjusted by the lift 2004. The lift 2004 is telescopic. The lift 2004 is preferably a foldable type consisting of multiple booms. The robot 2000 may also include a driving unit 2005 and a Since the moving mechanism 2011 is provided, the imaging range of the sensor 2002, i.e. This is preferable as it broadens the monitoring range.

[0613] The communication means 2006 communicates the information captured by the sensor 2002 to the administrator or the person in charge of the information. The information captured by the sensor 2002 can be transmitted to a server that performs calculations. If the device 2001 analyzes the data and determines that it is an emergency such as a crime, accident, or fire, the security committee You can contact the company, police, fire department, medical institution, land or building owner. In 2007, robots were used to warn criminals, question injured or suddenly ill people, and guide people to evacuations. The microphone 2008 can transmit information to the surroundings. It can be used to acquire surrounding sounds. By using it in conjunction with 07, Robot 2000 can function as a telephone. People around the robot 2000 can converse with the administrator or any other person. The display unit 2009 can display any information. In the event of an emergency, disaster information and evacuation information can be displayed. The route can be displayed. Also, the communication means 2006, the speaker 2007, and the microphone When used in conjunction with Crophone 2008, Robot 2000 functions as a videophone. The people around the robot 2000 can be displayed as administrators or other people. You can have a conversation while watching Part 2009.

[0614] The light emitting unit 2010 can indicate the direction of travel and the stopped state of the robot 2000 with letters and light. It may also indicate an emergency.

[0615] Figure 49(B) is a block diagram showing the configuration of the robot 2000. Based on information such as images obtained by the sensor 2002, the system determines whether the light 2003 is turned on or off, The brightness can be adjusted. Also, the height of the lift 2004 or the drive unit 2005 can be adjusted. It controls the robot 2000 and the sensor 2002 and aligns them. The operating status of the communication means 200 can be displayed using the light emitting unit 2010. 6, the robot 2000's information obtained from the sensor 2002 and the microphone 2008 is It can send information about the surroundings to the administrator or a server owned by the a...

Claims

1. A first insulator; an oxide on the first insulator; a second insulator on the oxide; and a first conductor on the second insulator; and a second conductor on the first conductor; and a third insulator on the oxide; and a fourth insulator on the third insulator; and a fifth insulator on the fourth insulator; The oxide contains In, the third insulator has a region in contact with an upper surface of the first insulator, a region in contact with a side surface of the oxide, a region in contact with an upper surface of the oxide, a region in contact with a side surface of the second insulator, and a region in contact with a side surface of the first conductor; the third insulator has an opening exposing the first insulator; the fourth insulator has a region in contact with the first insulator through an opening in the third insulator, a fifth insulator having a region in contact with the fourth insulator, a region in contact with the third insulator, a region in contact with the second conductor, and a region in contact with the first conductor;

2. In claim 1, The semiconductor device, wherein the first insulator and the fourth insulator are more permeable to oxygen than the third insulator.

3. In claim 1 or 2, The semiconductor device, wherein the third insulator comprises an oxide of aluminum or an oxide of hafnium.

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