Semiconductor device and power conversion device

Abstract

To provide a semiconductor device and a power conversion device capable of suppressing an increase in capacitance characteristics without causing a decrease in breakdown voltage.SOLUTION: The peak concentration of a carrier accumulation layer 7 is 1.0E16 / cm3 or more, the bottom of a trench 2 is located in the carrier accumulation layer 7, and the concentration ratio is obtained by dividing the concentration of the carrier accumulation layer 7 at the depth of the bottom of the trench 2 by the concentration of the drift layer 6, and the concentration ratio of the depth of the bottom of the trench 2 is greater than 1 and 10 or less.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a power conversion device. [Background technology]

[0002] A power semiconductor device has a carrier accumulation layer and a trench gate structure in order to reduce an on-state voltage. In conventional semiconductor devices, a trench is formed so as to penetrate the carrier accumulation layer (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-89700 A Summary of the Invention [Problem to be solved by the invention]

[0004] There was a problem that the capacitance characteristic increased as the trench depth became deeper, while there was a problem that the breakdown voltage decreased when a reverse bias was applied when the trench gate was simply placed inside the carrier accumulation layer.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to obtain a semiconductor device and a power conversion device that can suppress an increase in capacitance characteristics without causing a decrease in voltage resistance. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a semiconductor substrate having a first conductivity type drift layer provided between a first main surface and a second main surface opposed to each other, a carrier accumulation layer of the first conductivity type provided on the first main surface side of the drift layer, a base layer of a second conductivity type provided on the first main surface side of the carrier accumulation layer, an emitter layer of the first conductivity type selectively provided on the first main surface side of the base layer, a plurality of trenches provided side by side with the first main surface of the semiconductor substrate and penetrating the emitter layer and the base layer, a gate electrode provided in the trench with a gate insulating film interposed therebetween, and a collector layer of the second conductivity type provided in a surface layer on the second main surface side of the semiconductor substrate, 3 That's all. the concentration of the carrier accumulation layer decreases from a position of a concentration peak of the carrier accumulation layer toward the drift layer, The bottom of the trench is in the carrier accumulation layer. between the position of the concentration peak of the carrier accumulation layer and the drift layer the concentration of the carrier accumulation layer at the depth of the bottom of the trench is divided by the concentration of the drift layer to obtain a concentration ratio, and the depth of the bottom of the trench is a position where the concentration ratio is greater than 1 and is not greater than 10. Effect of the Invention

[0007] In the present disclosure, the bottom of the trench is located in the n-type carrier accumulation layer, and the depth of the bottom of the trench is a position where the concentration ratio is greater than 1 and equal to or less than 10. This makes it possible to suppress an increase in capacitance characteristics without causing a decrease in breakdown voltage. [Brief description of the drawings]

[0008] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line I-II of FIG. [Diagram 3] FIG. 11 is a cross-sectional view showing a semiconductor device according to a comparative example. [Figure 4] 11 is a diagram showing the correlation between trench depth and on-state voltage for each peak concentration of the carrier accumulation layer. [Diagram 5] FIG. 13 is a diagram showing the correlation between the trench depth and each capacitance of an IGBT. [Figure 6] FIG. 13 is a diagram showing the correlation between trench depth and VCES ratio. [Figure 7] 4 is a diagram showing the relationship between the carrier concentration distribution in a p-type base layer and the carrier concentration distribution in an n-type carrier accumulation layer according to the first embodiment. FIG. [Figure 8] FIG. 13 is a diagram showing the correlation between trench depth and turn-on loss. [Figure 9] FIG. 11 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 10] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 11] FIG. 11 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] A semiconductor device and a power conversion device according to the embodiments will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

[0010] Embodiment 1 1 is a plan view showing a semiconductor device according to a first embodiment. A cell region 1 is a region through which a main current flows, and has an IGBT cell. In the cell region 1, trenches 2 are provided in a striped pattern, and the planar shape of the unit cell is a striped type. However, the planar shape of the unit cell may also be a lattice type consisting of a square, hexagon, circle, or the like.

[0011] A gate pad is provided in the pad region 3, but is not limited thereto and may be provided with, for example, a current sense pad, a Kelvin emitter pad, or a temperature sense diode pad. The gate pad is a control pad to which a gate drive voltage for controlling the on / off of the semiconductor device is applied, and is electrically connected to the gate trench electrode of the cell region. The current sense pad is a control pad for detecting the current flowing in the cell region of the semiconductor device, and is electrically connected to a part of the cell region so that when a current flows in the cell region of the semiconductor device, a current that is one fraction to one ten-thousandth of the current flowing in the entire cell region flows. The Kelvin emitter pad is electrically connected to the p-type base layer of the IGBT cell, but the p + The temperature sensing diode pad may be electrically connected to the p-type base layer via a p-type contact layer. The temperature sensing diode pad is a control pad electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device. The temperature of the semiconductor device is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0012] A termination region 4 for maintaining the breakdown voltage of the semiconductor device is provided around the cell region 1 and the pad region 3. In the termination region 4, on the first main surface side, which is the front surface side of the semiconductor device, for example, a field limiting ring (FLR) in which the cell region 1 is surrounded by a p-type termination well layer, or a variation of lateral doping (VLD) in which the cell region is surrounded by a p-type well layer with a concentration gradient is provided as a breakdown voltage maintaining structure. The number of ring-shaped p-type termination well layers of the FLR or the concentration distribution of the VLD are appropriately selected depending on the breakdown voltage design of the semiconductor device.

[0013] Fig. 2 is a cross-sectional view taken along line I-II of Fig. 1. The semiconductor substrate 5 has a first main surface and a second main surface opposed to each other, and a n-type semiconductor layer provided between the first main surface and the second main surface. - and a type drift layer 6.

[0014] n - The first main surface side of the n-type drift layer 6 -The n-type carrier accumulation layer 7 has a higher concentration of n-type impurities than the n-type drift layer 6. The peak concentration of the n-type carrier accumulation layer 7 is 1.0E16 / cm 3 The above is the case. By providing the n-type carrier accumulation layer 7, it is possible to reduce the current loss when a current flows. The n-type carrier accumulation layer 7 is - The n-type impurity is ion-implanted into the semiconductor substrate 5 having the n-type drift layer 6, and then the implanted n-type impurity is diffused into the semiconductor substrate 5 by annealing.

[0015] The p-type base layer 8 is provided on the first major surface side of the n-type carrier accumulation layer 7. The n-type emitter layer 9 and the p + A type contact layer 10 is selectively provided on a portion of the surface layer on the first main surface side of the p-type base layer 8. The p-type contact layer 10 has a higher impurity concentration than the p-type base layer 8.

[0016] A plurality of trenches 2 are provided side by side on the first main surface of the semiconductor substrate 5, penetrating the n-type emitter layer 9 and the p-type base layer 8. The bottoms of the trenches 2 are located in the n-type carrier accumulation layer 7. A gate electrode 11 is provided in the trenches 2 via a gate insulating film 12. An interlayer insulating film 13 covers the upper surface of the gate electrode 11.

[0017] An emitter electrode 14 is provided on the first main surface of the semiconductor substrate 5 and the interlayer insulating film 13. The emitter electrode 14 is, for example, an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy). The emitter electrode 14 may be an electrode made of a multi-layer metal film formed by electroless plating or electrolytic plating on an electrode made of an aluminum alloy. The plating film may be, for example, a nickel (Ni) plating film. If the width of the contact hole provided in the interlayer insulating film 13 is narrow and satisfactory embedding cannot be obtained with the emitter electrode 14, tungsten, which has better embedding properties than the emitter electrode 14, may be placed in the contact hole, and the emitter electrode 14 may be provided on the tungsten.

[0018] A barrier metal may be provided between the first main surface of the semiconductor substrate 5, the interlayer insulating film 13, and the emitter electrode 14. The barrier metal is a conductor containing titanium (Ti), such as titanium nitride, or may be TiSi, which is an alloy of titanium and silicon (Si). + The semiconductor layer 10 is in ohmic contact with the semiconductor layer 10 and electrically connected thereto.

[0019] n - On the second main surface side of the n-type drift layer 6, - The n-type buffer layer 15 has an impurity concentration higher than that of the p-type drift layer 6. The n-type buffer layer 15 is provided to suppress punch-through of a depletion layer extending from the p-type base layer 8 to the second main surface side when the semiconductor device is in an off state. The n-type buffer layer 15 is formed by doping the p-type base layer 8 with, for example, phosphorus (P) or protons (H + ) to form phosphorus (P) and protons (H + ) may be implanted. The n-type buffer layer 15 may not be provided.

[0020] A p-type collector layer 16 is provided on the surface layer on the second main surface side of the semiconductor substrate 5. The p-type collector layer 16 is provided not only in the cell region 1 but also in the termination region 4. The portion of the p-type collector layer 16 provided in the termination region 4 constitutes a p-type termination collector layer. A collector electrode 17 is provided on the second main surface of the semiconductor substrate 5. The collector electrode 17 is made of an aluminum alloy or an aluminum alloy and a plating film, similar to the emitter electrode 14. The collector electrode 17 may have a different configuration from the emitter electrode 14. The collector electrode 17 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0021] Here, the concentration ratio is the concentration of n-type carrier accumulation layer 7 at the depth of the bottom of trench 2 divided by the concentration of drift layer 6, and the depth of the bottom of trench 2 is a position where the concentration ratio is greater than 1 and equal to or less than 10. The depth of trench 2 is 3.5 um or more and 5.0 um or less.

[0022] Next, the effect of this embodiment will be described in comparison with a comparative example. Fig. 3 is a cross-sectional view showing a semiconductor device according to the comparative example. In the comparative example, the trench 2 penetrates the n-type carrier accumulation layer 7 in order to ensure the capability of the reverse bias voltage application. Since the trench 2 is deeper than when it does not penetrate, the perimeter of the trench 2 becomes longer, and the capacitance around the gate tends to increase.

[0023] Capacitance C of the gate insulating film 12 ox is C ox =(ε 0 ε 0x Here, L is the perimeter of the trench 2, W is the width (depth) of the trench 2, d is the thickness of the gate insulating film 12, and ε 0 is the dielectric constant of a vacuum, ε 0x is the relative dielectric constant of the gate insulating film 12. The perimeter L is expressed as L=2α+πβ, where α is the length of the straight line portion of the trench 2, and β is the radius of the circumferential portion of the trench 2. Since W and d are fixed values ​​here, the capacitance C of the gate insulating film 12 is ox It can be seen that is determined by the perimeter L of trench 2.

[0024] In the comparative example, the trench 2 penetrates the n-type carrier accumulation layer 7, so that the perimeter L of the trench 2 is long and the capacitance C ox In contrast, in the present embodiment, the bottom of the trench 2 is located in the n-type carrier accumulation layer 7. Therefore, the perimeter L of the trench 2 is short, and an increase in the capacitance characteristic can be suppressed.

[0025] 4 is a graph showing the correlation between the trench depth and the on-state voltage for each peak concentration of the carrier accumulation layer. The on-state voltage (VCE(sat)) is the voltage drop when a forward bias is applied to the gate electrode 11 and a current is passed between the collector electrode 17 and the emitter electrode 14. When the n-type carrier accumulation layer 7 does not exist or the peak concentration of the n-type carrier accumulation layer 7 is 1.0E16 / cm 3 When the peak concentration is lower than 1.0E16 / cm, the increase in on-state voltage tends to be highly dependent on the depth of trench 2. 3When the depth of trench 2 is in the range of 3.5 um to 5.0 um, the on-state voltage change rate is the lowest (legend 6.3E15 / cm 3 On the other hand, in this embodiment, the peak concentration of n-type carrier accumulation layer 7 is 1.0E16 / cm 3 For the above reasons, the correlation between the depth of trench 2 and the on-voltage is gentle.

[0026] Fig. 5 is a diagram showing the correlation between the trench depth and each capacitance of the IGBT. By making the depth of the trench 2 between 3.5 um and 5.0 um, it is possible to reduce the input capacitance (Cies) while preventing a sudden increase in the feedback capacitance (Cres) and output capacitance (Coes).

[0027] 6 is a diagram showing the correlation between the trench depth and the VCES ratio. VCES indicates the maximum non-repetitive voltage when the gate electrode 11 and the emitter electrode 14 are connected to GND and a reverse bias is applied to the collector electrode 17. - In a structure in which the bottom of trench 2 is located on type drift layer 6, the VCES is sufficiently stable. The VCES ratio is the ratio of the VCES in a structure in which trench 2 is shallower, relative to the VCES in this structure in which VCES is sufficiently stable (trench 2 depth 6 μm). There is a tendency for the VCES ratio to decrease with depth up to a trench 2 depth of 5.0 um. It can also be seen that the VCES ratio is stable in the region where the concentration ratio is 10 or less.

[0028] FIG. 7 is a diagram showing the relationship between the carrier concentration distribution of the p-type base layer and the carrier concentration distribution of the n-type carrier accumulation layer according to the first embodiment. In the diagram, A indicates the distance from the intersection of the carrier profile (solid line) of the p-type base layer 8 and the carrier profile (dashed line) of the n-type carrier accumulation layer 7 to the peak concentration of the n-type carrier accumulation layer 7. In other words, A indicates the distance from the junction position of the p-type base layer 8 and the n-type carrier accumulation layer 7 to the peak concentration position of the n-type carrier accumulation layer 7. When A is long, it is necessary to deepen the depth of the n-type carrier accumulation layer 7 in order to make the concentration ratio 10 or less. As a result, the depth of the trench 2 also becomes deeper, making it difficult to measure the reduction in capacitance characteristics. Therefore, it is preferable that A is within 0.4 um.

[0029] FIG. 8 is a diagram showing the correlation between trench depth and turn-on loss. When the depth of trench 2 is between 3.5 um and 5.0 um, the rate of increase in turn-on loss is gentle. Line: A is a linear approximation of this range where the correlation between trench depth and turn-on loss is gentle. When the depth of trench 2 exceeds 5.0 um, the rate of increase in turn-on loss becomes steep. Line: B is a linear approximation of this range where the correlation between trench depth and turn-on loss is steep. The depth of trench 2 is 5.0 um at the intersection of Line: A and Line: B. By making the depth of trench 2 5.0 um or less, a significant increase in turn-on loss during switching can be prevented.

[0030] Embodiment 2 9 is a cross-sectional view showing a semiconductor device according to a second embodiment. FIG. 9 corresponds to the cross section taken along line I-II in FIG. 1. A recess 18 penetrating the n-type emitter layer 9 is selectively provided in the surface layer on the first main surface side. The recess 18 is called a trench contact. At the bottom of the recess 18, a p + During switching of the IGBT having the n-type contact layer 10, the collector current flows through the recess 18 without passing through the n-type emitter layer 9. This makes it possible to improve the latch-up resistance. The other configurations and effects are the same as those of the first embodiment.

[0031] Embodiment 3 Fig. 10 is a cross-sectional view showing a semiconductor device according to embodiment 3. Fig. 10 corresponds to the cross section taken along line I-II in Fig. 1. This semiconductor device is an RC-IGBT having an IGBT region 19 and a diode region 20 provided adjacent to each other on a semiconductor substrate 5.

[0032] The IGBT region 19 has an n-type carrier accumulation layer 7, a p-type base layer 8, an n-type emitter layer 9, a trench 2, a gate electrode 11, and a p-type collector layer 16. The diode region 20 has a p-type anode layer 21 provided in a surface layer on the first main surface side of the semiconductor substrate 5, and an n-type cathode layer 22 provided in a surface layer on the second main surface side of the semiconductor substrate 5. The other configurations are the same as those in the first embodiment. This makes it possible to obtain an RC-IGBT that exhibits the effects of the first embodiment.

[0033] The semiconductor substrate 5 is not limited to being made of silicon, and may be made of a wide band gap semiconductor having a larger band gap than silicon. The wide band gap semiconductor is, for example, silicon carbide, gallium nitride-based material, or diamond. A semiconductor chip made of such a wide band gap semiconductor has high voltage resistance and allowable current density, and can be miniaturized. By using this miniaturized semiconductor chip, a semiconductor device incorporating this semiconductor chip can also be miniaturized and highly integrated. In addition, since the semiconductor chip has high heat resistance, the heat dissipation fins of the heat sink can be miniaturized, and the water-cooled part can be air-cooled, so the semiconductor device can be further miniaturized. In addition, since the power loss of the semiconductor chip is low and highly efficient, the efficiency of the semiconductor device can be increased.

[0034] Embodiment 4 In this embodiment, the semiconductor device according to the above-mentioned first to third embodiments is applied to a power conversion device. The power conversion device is, for example, an inverter device, a converter device, a servo amplifier, a power supply unit, etc. Although the present disclosure is not limited to a specific power conversion device, the following describes a case where the present disclosure is applied to a three-phase inverter.

[0035] Fig. 11 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied. This power conversion system includes a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 can be configured from various sources, for example, a DC system, a solar cell, or a storage battery, or may be configured from a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 100 may also be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0036] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. The power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201.

[0037] The load 300 is a three-phase motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is a motor mounted on various electric devices, and is used as, for example, a motor for a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioner.

[0038] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and free wheel diodes (not shown), and converts DC power supplied from the power source 100 into AC power by switching the switching elements, and supplies the AC power to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full bridge circuit, and can be configured with six switching elements and six free wheel diodes connected in reverse parallel to each switching element. Each switching element and each free wheel diode of the main conversion circuit 201 is configured by a semiconductor device 202 corresponding to any one of the above-mentioned embodiments 1 to 4. Two switching elements of the six switching elements are connected in series to configure upper and lower arms, and each upper and lower arm configures each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0039] The main conversion circuit 201 also includes a drive circuit (not shown) for driving each switching element, but the drive circuit may be built in the semiconductor device 202, or the semiconductor device 202 may include a drive circuit separately. The drive circuit generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with a control signal from a control circuit 203 (described later), the drive signal for turning the switching element on and the drive signal for turning the switching element off are output to the control electrodes of each switching element. When maintaining the switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.

[0040] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that a desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) for each switching element of the main conversion circuit 201 to be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on time of the switching elements according to the voltage to be output. Then, a control command (control signal) is output to a drive circuit provided in the main conversion circuit 201 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state. The drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.

[0041] In the power conversion device according to the present embodiment, the semiconductor device according to any one of the first to third embodiments is applied as the semiconductor device 202, and therefore an increase in the capacitance characteristic can be suppressed without causing a decrease in the withstand voltage.

[0042] In the present embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described, but the present disclosure is not limited thereto and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may be used. In addition, when power is supplied to a single-phase load, the present disclosure may be applied to a single-phase inverter. In addition, when power is supplied to a DC load or the like, the present disclosure may be applied to a DC / DC converter or an AC / DC converter.

[0043] Furthermore, the power conversion device to which the present disclosure is applied is not limited to the case where the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system, etc. [Explanation of symbols]

[0044] 2 trench, 5 semiconductor substrate, 6 drift layer, 7 n-type carrier accumulation layer, 8 p-type base layer, 9 n-type emitter layer, 11 gate electrode, 12 gate insulating film, 16 p-type collector layer, 18 recess, 19 IGBT region, 20 diode region, 21 p-type anode layer, 22 n-type cathode layer, 200 power conversion device, 201 main conversion circuit, 202 semiconductor device, 203 control circuit

Claims

1. a semiconductor substrate having a first conductivity type drift layer provided between a first main surface and a second main surface opposed to each other; a carrier accumulation layer of a first conductivity type provided on the first principal surface side of the drift layer; a second conductivity type base layer provided on the first principal surface side of the carrier accumulation layer; an emitter layer of a first conductivity type selectively provided on the first main surface side of the base layer; a plurality of trenches provided side by side on the first main surface of the semiconductor substrate and penetrating the emitter layer and the base layer; a gate electrode provided in the trench via a gate insulating film; a collector layer of a second conductivity type provided on a surface layer on the second main surface side of the semiconductor substrate, The peak concentration of the carrier accumulation layer is 1.0E16 / cm ３ That's all. the concentration of the carrier accumulation layer decreases from a position of a concentration peak of the carrier accumulation layer toward the drift layer, a bottom of the trench is located in the carrier accumulation layer between a position of a concentration peak of the carrier accumulation layer and the drift layer; a concentration ratio obtained by dividing the concentration of the carrier accumulation layer at a depth of the bottom of the trench by the concentration of the drift layer, and the depth of the bottom of the trench is a position where the concentration ratio is greater than 1 and not greater than 10.

2. 2. The semiconductor device according to claim 1, wherein a concentration peak of the carrier accumulation layer is located within 0.4 μm from a junction between the base layer and the carrier accumulation layer in a direction from the first main surface toward the second main surface.

3. 3. The semiconductor device according to claim 1, wherein the depth of the trench is 5.0 [mu]m or less.

4. 3. The semiconductor device according to claim 1, wherein the depth of the trench is not less than 3.5 [mu]m and not more than 5.0 [mu]m.

5. 5. The semiconductor device according to claim 1, wherein a recess penetrating said emitter layer is selectively provided in a surface layer on said first main surface side.

6. the semiconductor device is an RC-IGBT having an IGBT region and a diode region provided adjacent to each other on the semiconductor substrate, the IGBT region includes the carrier accumulation layer, the base layer, the emitter layer, the trench, the gate electrode, and the collector layer; The semiconductor device according to any one of claims 1 to 5, characterized in that the diode region has an anode layer of a second conductivity type provided on a surface layer on the first main surface side of the semiconductor substrate, and a cathode layer of a first conductivity type provided on a surface layer on the second main surface side of the semiconductor substrate.

7. 7. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of a wide band gap semiconductor.

8. A main conversion circuit having the semiconductor device according to any one of claims 1 to 7, which converts input power and outputs the converted power; a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

Images