Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device that can be miniaturized.SOLUTION: A semiconductor device comprises: a substrate 10; a first source finger 12a provided on the substrate; a first gate finger 14a; a second source finger 12b extending in an extending direction and having a width smaller than a width of the first source finger, the width being within the width of the first source finger; a second gate finger 14b extending in the extending direction; a first source wire 19b that connects the first source finger and the second source finger; a first gate wire 18a that holds the second source finger with the second gate finger and has a width falling within the width of the first source finger; a second gate wire 18b crossing the first source wire in a non-contact manner, connecting the first gate wire and the first gate finger; and a first drain finger 16a that holds the first and second gate fingers with the first and second source fingers.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, for example, a semiconductor device having a field effect transistor and a manufacturing method thereof. [Background technology]

[0002] 2. Description of the Related Art In a field effect transistor (FET) having a source, a gate, and a drain, it is known to arrange a plurality of unit FETs having source fingers, gate fingers, and drain fingers in the extension direction of the fingers (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-299351 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the gate fingers in the unit FETs can be shortened by arranging a plurality of unit FETs in the extension direction of the fingers. This makes it possible to suppress the gate resistance. However, the gate wiring for supplying a gate potential (gate signal) to the gate fingers of the unit FETs arranged in the extension direction of the fingers extends in the extension direction of the fingers. This causes the gate wiring and the source fingers to overlap, increasing the gate-source capacitance. If the gate wiring and the source fingers are arranged so as not to overlap, the area of ​​the gate wiring and the area of ​​the source fingers must be provided separately, which results in an increase in the size of the semiconductor device.

[0005] The present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a semiconductor device that can be miniaturized and a manufacturing method thereof. [Means for solving the problem]

[0006] One embodiment of the present disclosure includes a substrate, a first source finger provided on the substrate, a first gate finger provided on the substrate adjacent to the first source finger in the width direction and extending in the extending direction of the first source finger, a second source finger provided on the substrate having a width smaller than the width of the first source finger, the width in the width direction being within the width of the first source finger and extending in the extending direction, a second gate finger provided on the substrate adjacent to the second source finger in the width direction and extending in the extending direction, a first source wiring provided on the substrate connecting the first source finger and the second source finger, a first gate wiring provided on the substrate sandwiching the second source finger with the second gate finger and the width in the width direction being within the width of the first source finger, a second gate wiring provided on the substrate intersecting the first source wiring non-contactingly and connecting the first gate wiring and the first gate finger, and a first drain finger provided on the substrate sandwiching the first gate finger and the second gate finger with the first source finger and the second source finger.

[0007] One embodiment of the present disclosure includes the steps of forming, in a substrate, a first active region and a second active region in which a semiconductor layer is activated and separated from each other, and an inactive region provided between the first active region and the second active region in which the semiconductor layer is inactive; forming, on the first active region, a first source ohmic layer and a first drain ohmic layer extending in an extension direction of the first source ohmic layer, and forming, on the second active region, a second source ohmic layer having a width smaller than a width of the first source ohmic layer, the width in the width direction of the first source ohmic layer being within the width of the first source ohmic layer, extending in the extension direction, and a second drain ohmic layer extending in the extension direction; forming, on the first active region, a first gate finger sandwiched between the first source ohmic layer and the first drain ohmic layer and extending in the extension direction, and forming, on the second active region, a first gate finger extending in the extension direction, the first gate finger being sandwiched between the first source ohmic layer and the first drain ohmic layer, and forming, on the second active region, a first gate finger extending in the extension direction. forming a second gate finger on the substrate, the second gate finger sandwiching the second source ohmic layer and the second drain ohmic layer and extending in the extension direction; forming a first gate wiring on the substrate, the first gate finger sandwiching the second source ohmic layer and the first gate wiring having a width in the width direction that falls within a width of the first source ohmic layer; forming a second gate wiring on the inactive region connecting the first gate finger and the first gate wiring; forming a first source low resistance layer in contact with the first source ohmic layer and a second source low resistance layer in contact with the second source ohmic layer, and forming a source wiring on the inactive region, the first source low resistance layer and the second source low resistance layer, and crossing the first gate wiring layer in a non-contact manner, simultaneously with the first source low resistance layer and the second source low resistance layer. Effect of the Invention

[0008] According to the present disclosure, it is possible to provide a semiconductor device that can be miniaturized and a method for manufacturing the same. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] FIG. 3 is a cross-sectional view taken along line BB of FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line CC of FIG. [Diagram 5] FIG. 5 is a cross-sectional view taken along line DD of FIG. [Figure 6] FIG. 6 is a plan view of a semiconductor device according to a first modification of the first embodiment. [Figure 7] FIG. 7 is a plan view of a semiconductor device according to a second modification of the first embodiment. [Figure 8] FIG. 8 is a plan view of a semiconductor device according to a third modification of the first embodiment. [Figure 9] FIG. 9 is a plan view of a semiconductor device in accordance with a second embodiment. [Figure 10] FIG. 10 is a plan view of a semiconductor device according to a first modification of the second embodiment. [Figure 11] FIG. 11 is a plan view of a semiconductor device according to a second modification of the second embodiment. [Figure 12] FIG. 12 is a plan view of a semiconductor device according to a third modification of the second embodiment. [Figure 13] FIG. 13 is a plan view of a semiconductor device according to a fourth modification of the second embodiment. [Figure 14A] FIG. 14A is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the third embodiment. [Figure 14B] FIG. 14B is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the third embodiment. [Figure 14C] FIG. 14C is a cross-sectional view illustrating a method for manufacturing a semiconductor device in accordance with the third embodiment. [Figure 15A] FIG. 15A is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the third embodiment. [Figure 15B] FIG. 15B is a cross-sectional view illustrating a method for manufacturing a semiconductor device in accordance with the third embodiment. [Figure 15C] FIG. 15C is a cross-sectional view illustrating a method for manufacturing a semiconductor device in accordance with the third embodiment. [Figure 16]FIG. 16 is a plan view illustrating a method for manufacturing a semiconductor device according to the third embodiment. [Figure 17] FIG. 17 is a plan view illustrating a method for manufacturing a semiconductor device according to the third embodiment. [Figure 18] FIG. 18 is a plan view illustrating a method for manufacturing a semiconductor device according to the third embodiment. [Figure 19] FIG. 19 is a plan view of a semiconductor device according to a first modification of the third embodiment. [Figure 20] FIG. 20 is a plan view of a semiconductor device according to a first modification of the third embodiment. [Figure 21] FIG. 21 is a plan view of a semiconductor device according to a second modification of the third embodiment. [Figure 22] FIG. 22 is a plan view of a semiconductor device according to a second modification of the third embodiment. [Diagram 23] FIG. 23 is a plan view of a semiconductor device according to a third modification of the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0011] [Details of the embodiment of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a substrate, a first source finger provided on the substrate, a first gate finger provided on the substrate adjacent to the first source finger in a width direction and extending in an extension direction of the first source finger, a second source finger provided on the substrate and having a width smaller than a width of the first source finger, the width in the width direction being within a width of the first source finger, and extending in the extension direction, a second gate finger provided on the substrate adjacent to the second source finger in the width direction and extending in the extension direction, and a gate electrode provided on the substrate and connected to the first source finger. a first source wiring connecting a first gate finger and the second source finger, a first gate wiring provided on the substrate, sandwiching the second source finger with the second gate finger and having a width in the width direction that falls within a width of the first source finger, a second gate wiring provided on the substrate, intersecting the first source wiring without contacting the first gate wiring and connecting the first gate wiring and the first gate finger, and a first drain finger provided on the substrate, sandwiching the first gate finger and the second gate finger with the first source finger and the second source finger. This makes it possible to provide a semiconductor device that can be miniaturized. (2) It is preferable to provide a via that penetrates the substrate and connects the first source finger with a metal layer provided below the substrate. (3) A third gate finger provided on the substrate and sandwiching the first source finger with the first gate finger; a third source finger provided on the substrate and having a width smaller than that of the first source finger, the width in the width direction being within the width of the first source finger, extending in the extension direction, adjacent to the first gate wiring in the width direction and sandwiching the first gate wiring with the second source finger; a fourth gate finger provided on the substrate and extending in the extension direction, sandwiching the third source finger with the first gate wiring; a second drain finger provided on the substrate and sandwiching the third gate finger and the fourth gate finger with the first source finger and the third source finger; and a second source wiring provided on the substrate and connecting the first source finger and the third source finger, wherein it is preferable that the second gate wiring intersects the second source wiring without contacting it and connects the first gate wiring and the third gate finger. (4) It is preferable that a gate bus bar be provided on the substrate on the opposite side of the first source finger with respect to the second source finger, and connected to the first gate wiring. (5) It is preferable that a first end of the second gate finger is connected to the gate bus bar, and a second end of the second gate finger is spaced apart from the second gate wiring. (6) It is preferable that a first end of the second gate finger is separated from the gate bus bar and a second end of the second gate finger is connected to the second gate wiring. (7) It is preferable that a first end of the second gate finger is connected to the gate bus bar, and a second end of the second gate finger is connected to the second gate wiring. (8) a third gate finger provided on the substrate and sandwiching the first source finger with the first gate finger; a third source finger provided on the substrate and having a width smaller than a width of the first source finger, the width in the width direction being within a width of the first source finger, extending in the extension direction and sandwiching the first gate wiring with the second source finger; and a fourth gate finger provided on the substrate and extending in the extension direction and sandwiching the third source finger with the first gate wiring; It is preferable that the semiconductor device further comprises: a second drain finger provided on the substrate, the first source finger and the third source finger sandwiching the third gate finger and the fourth gate finger; a second source wiring provided on the substrate and connecting the first source finger and the third source finger; a third gate wiring provided on the substrate and between the third source finger and the first gate wiring, the width in the width direction being within the width of the first source finger and separated from the first gate wiring on the substrate; and a fourth gate wiring provided on the substrate, intersecting the second source wiring without contacting it, separated from the second gate wiring on the substrate, and connecting the third gate wiring and the third gate finger. (9) It is preferable that the semiconductor device further comprises a first gate bus bar provided on the substrate opposite the first source finger with respect to the second source finger, the first gate bus bar connecting to the first gate wiring, a second gate bus bar provided on the substrate opposite the first source finger with respect to the third source finger, connected to the third gate wiring and separated from the first gate bus bar on the substrate, and resistors electrically connecting the first gate wiring and the first gate bus bar, and the third gate wiring and the second gate bus bar. (10) The substrate comprises a first active region and a second active region in which a semiconductor layer in the substrate is activated and separated from each other, and an inactive region provided between the first active region and the second active region in which the semiconductor layer is inactive, the first source finger comprises a first source ohmic layer in ohmic contact with the first active region, and a first source low-resistance layer provided on and in contact with the first source ohmic layer and having a sheet resistance lower than that of the first source ohmic layer, the second source finger comprises a second source ohmic layer in ohmic contact with the second active region, and a second source low-resistance layer provided on and in contact with the second source ohmic layer and having a sheet resistance lower than that of the first source ohmic layer, and the second gate wiring is provided on the inactive region, and it is preferable that the first source wiring is formed continuously from the same material as the first source low-resistance layer and the second source low-resistance layer. (11) It is preferable that the first drain finger comprises a first drain ohmic layer in ohmic contact with the first active region, a second drain ohmic layer in ohmic contact with the second active region, and a drain low resistance layer in contact with the first drain ohmic layer and the second drain ohmic layer and having a sheet resistance lower than that of the first drain ohmic layer and the second drain ohmic layer. (12) The material of the second gate wiring is preferably the same as the material of the first gate finger and the second gate finger. (13) The second gate wiring preferably has a sheet resistance lower than the sheet resistances of the first gate finger and the second gate finger. (14) One embodiment of the present disclosure includes the steps of: forming, in a substrate, a first active region and a second active region in which a semiconductor layer is activated and separated from each other, and an inactive region provided between the first active region and the second active region in which the semiconductor layer is inactive; forming, on the first active region, a first source ohmic layer and a first drain ohmic layer extending in an extension direction of the first source ohmic layer; and forming, on the second active region, a second source ohmic layer having a width smaller than a width of the first source ohmic layer, the width of the first source ohmic layer in the width direction being within the width of the first source ohmic layer, extending in the extension direction, and a second drain ohmic layer extending in the extension direction; forming, on the first active region, a first gate finger sandwiched between the first source ohmic layer and the first drain ohmic layer and extending in the extension direction, and forming, on the second active region, a first gate finger extending in the extension direction, the first gate finger being sandwiched between the first source ohmic layer and the first drain ohmic layer, and forming, on the second active region, a first gate finger extending in the extension direction. forming a second gate finger on the substrate, the second gate finger sandwiching the second source ohmic layer and the second drain ohmic layer and extending in the extension direction, forming a first gate wiring on the substrate, the first gate finger sandwiching the second source ohmic layer and the first gate wiring having a width in the width direction that is within the width of the first source ohmic layer, forming a second gate wiring on the substrate, the first gate finger connecting the first gate wiring, and forming a first source low resistance layer in contact with the first source ohmic layer and a second source low resistance layer in contact with the second source ohmic layer, and forming a source wiring on the substrate, the first source low resistance layer and the second source low resistance layer in contact with the second source ohmic layer, the first source low resistance layer and the second source low resistance layer in contact with the second source ohmic layer, and forming a source wiring on the substrate, the first source low resistance layer and the second source low resistance layer in contact with the first gate wiring layer, and crossing the first gate wiring layer in a non-contact manner, simultaneously with the first source low resistance layer and the second source low resistance layer. This makes it possible to provide a method for manufacturing a semiconductor device that can be miniaturized.

[0012] Specific examples of semiconductor devices and manufacturing methods thereof according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0013] [Example 1] Fig. 1 is a plan view of a semiconductor device according to Example 1. Figs. 2 to 5 are cross-sectional views taken along lines AA to DD in Fig. 1. The normal direction to the upper surface of substrate 10 is designated as Z direction, the extension direction of each finger is designated as Y direction, and the width direction of each finger is designated as X direction.

[0014] 1 to 5, substrate 10 includes substrate 10a and semiconductor layer 10b provided on substrate 10a. A region of semiconductor layer 10b that has been inactivated by ion implantation or the like is inactive region 11a, and a region that has not been inactivated is active region 11. Source fingers 12a to 12c, gate fingers 14a to 14d, drain fingers 16a, 16b, gate wirings 18a, 18b, gate bus bar 22, and drain bus bar 24 are provided on substrate 10.

[0015] The source fingers 12a to 12c and the drain fingers 16a and 16b each have an ohmic metal layer 40 provided on the active region 11 and a low resistance layer 50 provided on the ohmic metal layer 40. The ohmic metal layer 40 is in ohmic contact with the semiconductor layer 10b. The low resistance layer 50 has a lower resistivity and is thicker than the ohmic metal layer 40. In the source fingers 12a to 12c and the drain fingers 16a and 16b, the widths of the ohmic metal layer 40 in the X and Y directions may be larger than or equal to the widths of the low resistance layer 50 in the X and Y directions. The source wiring 19b connects the source fingers 12a and 12b, and the source wiring 19c connects the source fingers 12a and 12c. The source wirings 19b and 19c are provided on the inactive region 11a, and have the low resistance layer 50 but do not have the ohmic metal layer 40. The portions of the drain fingers 16 a and 16 b above the inactive region 11 a have the low resistance layer 50 and do not have the ohmic metal layer 40 .

[0016] The gate fingers 14a to 14d have a gate metal layer 45 provided on the active region 11, and do not have a low-resistance layer 50. The gate wiring 18b has a gate metal layer 45 provided on the inactive region 11a, and does not have a low-resistance layer 50. The gate wiring 18a has a gate metal layer 45 and a low-resistance layer 50 provided on the semiconductor layer 10b. The low-resistance layer 50 has a lower resistivity and is thicker than the gate metal layer 45.

[0017] The source finger 12a extends in the Y direction and has a width W2a in the X direction and a length L2a in the Y direction. The source fingers 12b and 12c extend in the Y direction from both ends of the source finger 12a in the X direction. The source fingers 12b and 12c each have a width W2b in the X direction and a length L2b in the Y direction. The drain finger 16a is provided extending in the Y direction in the +X direction of the source fingers 12a and 12b. The drain finger 16b is provided extending in the Y direction in the -X direction of the source fingers 12a and 12c. The drain fingers 16a and 16b each have a width W6 in the X direction. The gate fingers 14a and 14b are provided between the source fingers 12a and 12b and the drain finger 16a, and the gate fingers 14c and 14d are provided between the source fingers 12a and 12c and the drain finger 16b. The gate fingers 14a to 14d extend in the Y direction, and their width in the X direction corresponds to the gate length Lg.

[0018] Sauce Finger 12bBetween the gate fingers 14a and 14c and between the gate fingers 14b and 14d, a gate wiring 18a is provided that extends in the Y direction and has a width W8a in the X direction. Between the gate fingers 14a and 14c and between the gate fingers 14b and 14d, a gate wiring 18b is provided. The gate wiring 18b has a width W8b in the Y direction and extends in the X direction, connecting the ends of the gate fingers 14a and 14c in the -Y direction and the end of the gate wiring 18a in the +Y direction, respectively. The gate wiring 18b and the source wirings 19b and 19c cross each other via an insulating film 26 and are not electrically connected to each other. The ends of the gate fingers 14b and 14d and the gate wiring 18a in the -Y direction are connected to a gate bus bar 22. The ends of the drain fingers 16a and 16b in the +Y direction are connected to a drain bus bar 24. The source finger 12a is connected to a metal layer 28 provided under the substrate 10 through a via 20 that penetrates the substrate 10. An insulating film 26 is provided to cover the source fingers 12a to 12c, the gate fingers 14a to 14d, the drain fingers 16a and 16b, and the gate wirings 18a and 18b.

[0019] The FET regions 30a and 30b are arranged in the Y direction. In the FET region 30a, the active region 11 including the source finger 12a extends in the X direction. The source finger 12a, the gate finger 14a, and the drain finger 16a form a unit FET 32a, and the source finger 12a, the gate finger 14c, and the drain finger 16b form a unit FET 32c. The gate width Wga of the unit FETs 32a and 32c corresponds to the length in the Y direction of the active region 11 including the source finger 12a. The source potential of the unit FETs 32a and 32c is supplied to the source finger 12a from the metal layer 28 through the via 20. The gate potential (and gate signal) is supplied to the gate fingers 14a and 14c from the gate bus bar 22 through the gate wirings 18a and 18b. The drain potential is supplied to the drain fingers 16a and 16b from the drain bus bar 24. The unit FETs 32a and 32c are arranged alternately in the X direction.

[0020] In the FET region 30b, the active region 11 is provided except for the gate wiring 18a. The source finger 12b, the gate finger 14b, and the drain finger 16a form a unit FET 32b, and the source finger 12c, the gate finger 14d, and the drain finger 16b form a unit FET 32d. The gate width Wgb of the unit FETs 32b and 32d corresponds to the length in the Y direction in the active region 11 including the source fingers 12b and 12c. The source potential of the unit FETs 32b and 32d is supplied to the source fingers 12b and 12c from the metal layer 28 through the via 20 and the source finger 12a. The gate potential (and gate signal) is supplied from the gate bus bar 22 to the gate fingers 14b and 14d. The drain potential is supplied from the drain bus bar 24 to the drain fingers 16a and 16b. The unit FETs 32b and 32d are arranged alternately in the X direction. When the overall gate width of the semiconductor device is to be increased, a plurality of unit FETs 32a to 32d are arranged in the X direction.

[0021] When the semiconductor device is, for example, a nitride semiconductor device, the substrate 10a is, for example, a SiC substrate, a silicon substrate, a GaN substrate, or a sapphire substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a GaN layer, an AlGaN layer, and / or an InGaN layer. When the semiconductor device is, for example, a GaAs-based semiconductor device, the substrate 10a is, for example, a GaAs substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a GaAs layer, an AlGaAs layer, and / or an InGaAs layer. The ohmic metal layer 40 is a metal film, for example, an adhesion film (for example, titanium) and a low resistance film (for example, aluminum) having a lower resistivity than the adhesion layer from the substrate 10 side. The gate metal layer 45 is a metal film, for example, an adhesion film (for example, nickel) and a low resistance film (for example, gold) having a lower resistivity than the adhesion layer from the substrate 10 side. The low resistance layer 50 is a metal layer, for example, a barrier layer (for example, titanium tungsten) and a low resistance layer (for example, gold) having a lower resistivity than the barrier layer. The source fingers 12a to 12c and the drain fingers 16a and 16b may not have the low resistance layer 50. The gate wiring 18a may not have the gate metal layer 45. The gate bus bar 22 may have the gate metal layer 45 and the low resistance layer 50, or may have the low resistance layer 50 and not have the gate metal layer 45. The drain bus bar 24 may have the ohmic metal layer 40 and the low resistance layer 50, or may have the low resistance layer 50 and not have the ohmic metal layer 40. The via 20 and the metal layer 28 are, for example, an adhesion layer and a layer (e.g., gold) having a lower resistivity than the adhesion layer from the substrate 10 side. The insulating film 26 is, for example, a silicon nitride film.

[0022] The width W2a of the source finger 12a in the X direction is, for example, 50 μm to 100 μm, and the length L2a in the Y direction is, for example, 100 μm to 400 μm. The width W2b of the source fingers 12b and 12c in the X direction is, for example, 5 μm to 20 μm, and the length L2b in the Y direction is, for example, 110 μm to 410 μm. The gate length Lg of the gate fingers 14a to 14d in the X direction is, for example, 0.25 μm to 2 μm. The width W6 of the drain fingers 16a and 16b in the X direction is, for example, 5 μm to 100 μm. The widths W8a and W8b of the gate wirings 18a and 18b are, for example, 5 μm to 20 μm. The gate width Wga of the unit FETs 32a and 32c is, for example, 100 μm to 400 μm, and the gate width Wgb of the unit FETs 32b and 32d is, for example, 100 μm to 400 μm. The width W20 of the via 20 is, for example, 10 μm to 60 μm.

[0023] According to the first embodiment, the gate finger 14a (first gate finger) is provided adjacent to the source finger 12a (first source finger) in the X direction (width direction). The source finger 12b (second source finger) has a width in the X direction within the width of the source finger 12a and extends in the Y direction (extension direction). The source wiring 19b (first source wiring) connects the source fingers 12a and 12b. The gate finger 14b (second gate finger) is provided adjacent to the source finger 12b in the X direction. The drain finger 16a (first drain finger) sandwiches the gate fingers 14a and 14b between the source fingers 12a and 12b, respectively. The source finger 12a, the gate finger 14a, and the drain finger 16a form a unit FET 32a, and the source finger 12b, the gate finger 14b, and the drain finger 16a form a unit FET 32b. The gate wiring 18b (second gate wiring) intersects the source wiring 19b without contact between the gate fingers 14a and 14b, and connects the gate wiring 18a (first gate wiring) to the gate finger 14a. At this time, the source wiring 19b connecting the source finger 12a and the source finger 12b intersects the gate wiring 18b without contacting it while riding on it. This is because the source wiring 19b and the gate wiring 18b intersect with the insulating film 26 interposed therebetween. This allows a gate potential to be supplied to the gate finger 14a via the gate wirings 18a and 18b. This allows the gate resistance of the unit FET 32a to be reduced.

[0024] The width W2a of the source finger 12a in the X direction may be designed to be wide. For example, the source inductance can be reduced by supplying a source potential to the source finger 12a through the via 20. However, the width W2a of the source finger 12a becomes wide. On the other hand, the width W2b of the source fingers 12b and 12c for supplying a source potential in the Y direction does not need to be as wide as the width W2a. Therefore, the gate wiring 18a is provided so as to sandwich the source finger 12b between the gate finger 14b. As a result, the gate wiring 18a and the source finger 12b do not overlap in a plan view. This makes it possible to suppress the gate-source capacitance. Also, the width W2b of the source finger 12b in the Y direction and the width W8a of the gate wiring 18a are each smaller than the width W2a, and the width W8a of the gate wiring 18a when viewed from the Y direction is smaller than the width W8a. W8a The gate wiring 18a is provided so that its width falls within the width W2a of the source finger 12a. That is, when viewed from the Y direction, the gate wiring 18a and the source fingers 12b and 12c overlap the source finger 12a, but do not overlap with any area other than the source finger 12a. This makes it possible to suppress the width of the semiconductor device in the X direction even if the gate wiring 18a is provided. This allows the semiconductor device to be miniaturized.

[0025] Gate finger 14c (third gate finger) sandwiches source finger 12a with gate finger 14a. Source finger 12c (third source finger) has width W2b smaller than width W2a, its width in the X direction falls within the width of source finger 12a, extends in the Y direction, and is adjacent to gate wiring 18a, sandwiching gate wiring 18a with source finger 12b. Source wiring 19c (second source wiring) connects source fingers 12a and 12c. Gate finger 14d (fourth gate finger) sandwiches source finger 12c with gate wiring 18a and extends in the Y direction. Drain finger 16b (second drain finger) connects source finger 12a and 12cThe gate fingers 14c and 14d are sandwiched between the gate fingers 14c and 14d. The gate wiring 18b crosses the source wiring 19c without contact between the gate fingers 14c and 14d, and connects the gate wiring 18a and the gate finger 14c. At this time, the source wiring 19c connecting the source finger 12a and the source finger 12c crosses the gate wiring 18b without contacting it while riding on the gate wiring 18b. This is because the source wiring 19c and the gate wiring 18b cross each other via the insulating film 26. As a result, the source finger 12a, the gate finger 14c, and the drain finger 16b form a unit FET 32c, and the source finger 12c, the gate finger 14d, and the drain finger 16b form a unit FET 32d.

[0026] The via 20 penetrates the substrate 10 and connects the source finger 12a to the metal layer 28 provided under the substrate 10. When the via 20 is directly connected to the source finger 12a in this manner, the width W2a of the source finger 12a is increased, so that the gate wiring 18a can be provided between the source fingers 12b and 12c.

[0027] The gate bus bar 22 is provided on the opposite side of the source fingers 12b and 12c from the source finger 12a, and is connected to the gate wiring 18a, so that a gate potential can be supplied from the gate bus bar 22 to the gate wiring 18a.

[0028] First ends of the gate fingers 14b and 14d are connected to the gate bus bar 22, and second ends are separated from the gate wiring 18b. This causes a phase difference between the gate signal supplied from the gate bus bar 22 to the gate fingers 14b and 14d and the gate signal supplied from the gate wirings 18a and 18b to the gate fingers 14a and 14c. However, gate signals are supplied to the gate fingers 14a to 14d from the same -Y direction, and signals are output from the drain fingers 16a and 16b in the +Y direction. This makes it possible to suppress loss due to the phase difference. As a result, it is possible to improve high frequency characteristics.

[0029] [Modification 1 of Example 1] Fig. 6 is a plan view of a semiconductor device according to Modification 1 of Example 1. As shown in Fig. 6, in Modification 1 of Example 1, two vias 20 are provided in one source finger 12a. By providing a plurality of vias 20 in one source finger 12a in this way, the source inductance can be further reduced. The other configurations are the same as those in Example 1, and therefore description thereof will be omitted.

[0030] [Modification 2 of Example 1] 7 is a plan view of a semiconductor device according to Modification 2 of Example 1. As shown in FIG. 7, in Modification 2 of Example 1, first ends of the gate fingers 14b and 14d in the -Y direction are connected to the gate bus bar 22, and second ends in the +Y direction are connected to the gate wiring 18b. This allows the gate fingers 14b and 14d to be supplied with a gate potential from the ±Y directions. This makes it possible to further suppress the gate resistance in the unit FETs 32b and 32d. In addition, the gate width Wgb of the unit FETs 32b and 32d can also be increased. The other configurations are the same as those of Example 1, and therefore description thereof will be omitted.

[0031] [Modification 3 of Example 1] 8 is a plan view of a semiconductor device according to Modification 3 of Example 1. As shown in FIG. 8, in Modification 3 of Example 1, first ends of the gate fingers 14b and 14d in the -Y direction are separated from the gate bus bar 22, and second ends in the +Y direction are connected to the gate wiring 18b. This allows the unit FETs 32a and 32b to be symmetrical, and the unit FETs 32c and 32d to be symmetrical. Therefore, the phases of the gate signals supplied to the unit FETs 32a to 32d are aligned, thereby improving the high-frequency characteristics. The other configurations are the same as those of Example 1, and a description thereof will be omitted.

[0032] [Example 2] FIG. 9 is a plan view of a semiconductor device according to a second embodiment. As shown in FIG. 9, in the second embodiment, three FET regions 30a to 30c are provided in the Y direction. Between the FET regions 30b and 30c, a gate wiring 18c is provided that connects the gate fingers 14b and 14d to the gate wiring 18a. The gate wiring 18c is provided between the active regions 11. In the FET region 30c, the source finger 12b, the gate finger 14b, and the drain finger 16a form a unit FET 32e, and the source finger 12c, the gate finger 14d, and the drain finger 16b form a unit FET 32f. As in the second embodiment, the gate wiring 18c that supplies a gate potential to the gate fingers 14b and 14d may be provided. This allows three or more FET regions 30a to 30c to be provided in the Y direction. The other configurations are the same as those of the third modification of the first embodiment, and a description thereof will be omitted.

[0033] [Modification 1 of Example 2] Fig. 10 is a plan view of a semiconductor device according to Modification 1 of Example 2. As shown in Fig. 10, in Modification 1 of Example 2, gate fingers 14b and 14d are not connected to gate bus bar 22. The rest of the configuration is the same as in Example 2, and a description thereof will be omitted. If a gate potential is supplied to gate fingers 14a to 14d of each unit FET 32a to 32f, the connection or non-connection of each gate finger 14b and 14d to gate wirings 18b, 18c and gate bus bar 22 can be appropriately designed.

[0034] [experiment] We fabricated GaN-based HEMTs (High Electron Mobility Transistors). The following four types of samples were fabricated. Samples A and B are comparative examples having one FET region. Sample A: 2 unit FETs with a gate width of 440 μm Sample B: 2 unit FETs with a gate width of 380 μm Sample C is an example in which, in addition to Example 2, a gate wiring is provided that connects the gate fingers 14b and 14d to the gate wiring 18a, and four unit FETs are provided in the Y direction. Sample C: The total gate width of the four unit FETs arranged in the Y direction is 440 μm × 2 Sample D is a second modification of the first embodiment. Sample D: The total gate width of two unit FETs arranged in the Y direction is 380 μm × 2

[0035] The linear gain was measured for samples A to D. The measurement conditions were a frequency of 4.8 GHz, a drain bias voltage of 50 V, and a drain bias current of 8 mA / mm. Samples C and D had linear gains that were 1 dB higher than those of samples A and B, respectively. This is believed to be because samples C and D had lower gate resistance than samples A and B. In addition, in samples C and D, the gate wiring and source fingers do not overlap, so degradation of high-frequency characteristics caused by an increase in gate-source capacitance is suppressed.

[0036] [Modification 2 of Example 2] FIG. 11 is a plan view of a semiconductor device according to a second modification of the second embodiment. As shown in FIG. 11, in the second modification of the second embodiment, the gate wiring 18a is divided into gate wirings 18a1 and 18a2, the gate wiring 18b is divided into gate wirings 18b1 and 18b2, and the gate wiring 18c is divided into gate wirings 18c1 and 18c2. The gate wirings 18b1 and 18c1 connect the gate finger 14b and the gate wiring 18a1, and the gate wirings 18b2 and 18c2 connect the gate finger 14d and the gate wiring 18a2. The gate wirings 18a1, 18b1, and 18c1 are not connected to the gate wirings 18a2, 18b2, and 18c2 on the substrate 10. The other configurations are the same as those of the first modification of the second embodiment, and therefore description thereof will be omitted.

[0037] According to the second modification of the second embodiment, the gate wiring 18a2 (third gate wiring) is provided between the source finger 12c and the gate wiring 18a1 (first gate wiring), the width in the X direction is within the width of the source finger 12a, and is separated from the gate wiring 18a1 on the substrate 10. The gate wiring 18b2 (fourth gate wiring) crosses the source wiring 19c without contact, is separated from the gate wiring 18b1 (second gate wiring) on ​​the substrate 10, and connects the gate wiring 18a2 and the gate finger 14c. As a result, the high-frequency signal transmitted to the gate finger 14a and the high-frequency signal transmitted to the gate finger 14b are separated in the gate wiring 18a. Therefore, oscillation can be suppressed. In the first embodiment, its modifications, and the second embodiment, the gate wirings 18a and 18b may be divided as in the second modification of the second embodiment.

[0038] [Modification 3 of Example 2] FIG. 12 is a plan view of a semiconductor device according to Modification 3 of Example 2. As shown in FIG. 12, in Modification 3 of Example 2, gate bus bar 22 is divided into gate bus bars 22a and 22b. Gate bus bars 22a and 22b are connected via resistor 25. Resistor 25 is, for example, a semiconductor resistor using semiconductor layer 10b, a metal resistor using a metal with high resistivity such as nickel-chromium alloy, tantalum, or tungsten, or a metal resistor using thin wiring such as gold or aluminum using ohmic metal layer 40, gate metal layer 45, or low resistance layer 50. The other configurations are the same as Modification 2 of Example 2, and description thereof will be omitted.

[0039] [Modification 4 of Example 2] 13 is a plan view of a semiconductor device according to Modification 4 of Example 2. As shown in FIG. 13, in Modification 4 of Example 2, gate wirings 18a1 and 18a2 are connected via resistor 25. Gate bus bars 22a and 22b are spaced apart from each other as compared to Modification 3 of Example 2. The other configurations are the same as those in Modification 4 of Example 2. 3 Since this is the same as the above, the explanation will be omitted.

[0040] As in the third and fourth modifications of the second embodiment, the gate bus bar 22a (first gate bus bar) connected to the gate wiring 18a1 and the gate bus bar 22b (second gate bus bar) connected to the gate wiring 18a2 are separated on the substrate 10. A resistor 25 is provided to electrically connect the gate wiring 18a1 and the gate bus bar 22a to the gate wiring 18a2 and the gate bus bar 22b. This separates the high-frequency signal transmitted to the gate finger 14a from the high-frequency signal transmitted to the gate finger 14b at the gate wiring 18a and the gate bus bar 22. This makes it possible to suppress oscillation more effectively than in the second modification of the second embodiment. By providing the resistor 25, the signal transmitted through the loop in the FET is attenuated, and oscillation can be further suppressed. In the first embodiment, its modifications, and the second embodiment, the gate bus bar 22 may be divided as in the third and fourth modifications of the second embodiment, and the resistor 25 may be provided.

[0041] [Example 3] Example 3 is an example of a manufacturing method of Examples 1 and 2 and their modified examples. Figs. 14A to 15C are cross-sectional views showing a manufacturing method of a semiconductor device according to Example 3. Figs. 16 to 18 are plan views showing a manufacturing method of a semiconductor device according to Example 3. As shown in Fig. 14A, an inactive region 11a is formed in the semiconductor layer 10b by implanting ions into the semiconductor layer 10b. The region where the inactive region 11a is not formed is the active region 11.

[0042] 16, an active region 11b is formed in the FET region 30a, and active regions 11c1 and 11c2 are formed in the FET region 30b. One strip-shaped active region 11b extending in the X-direction is formed in the FET 30a. A plurality of active regions 11c1 and 11c2 arranged in the X-direction are formed in the FET region 30b. An inactive region 11a is between the active region 11b and 11c1 and between the active region 11c1 and 11c2, and an inactive region 11a is between the active region 11b and 11c1 and 11c2.

[0043] As shown in FIG. 14B and FIG. 16, an ohmic metal layer 40 is formed on the active regions 11b and 11c. The ohmic metal layer 40 is formed, for example, by vacuum deposition and lift-off. A source ohmic layer 42a and drain ohmic layers 46a1 and 46b1 are formed on the active region 11b. A source ohmic layer 42b and drain ohmic layer 46a2 are formed on the active region 11c1. A source ohmic layer 42c and drain ohmic layer 46b2 are formed on the active region 11c2. Then, a heat treatment is performed. As a result, the source ohmic layer 42a and the drain ohmic layers 46a1 and 46b1 are in ohmic contact with the active region 11b. The source ohmic layer 42b and drain ohmic layer 46a2 are in ohmic contact with the active region 11c1. The source ohmic layer 42c and drain ohmic layer 46b2 are in ohmic contact with the active region 11c2.

[0044] As shown in FIG. 14C and FIG. 17, a gate metal layer 45 is formed on the substrate 10. For example, a vacuum deposition method and a lift-off method are used to form the gate metal layer 45. On the active region 11b, a gate finger 14a is formed between the source ohmic layer 42a and the drain ohmic layer 46a1, and a gate finger 14c is formed between the source ohmic layer 42a and the drain ohmic layer 46b1. On the active region 11c1, a gate finger 14b is formed between the source ohmic layer 42b and the drain ohmic layer 46a2. On the active region 11c2, a gate finger 14d is formed between the source ohmic layer 42c and the drain ohmic layer 46b2. A gate wiring 18b is formed on the inactive region 11a between the active region 11b and 11c1 and 11c2. A gate metal layer 48a is formed on the inactive region 11a between the active regions 11c1 and 11c2. A gate metal layer 49 is formed on the -Y side of FET region 30b, connected to gate fingers 14b and 14d and gate metal layer 48a.

[0045] 15A, an insulating film 26a is formed on the substrate 10 so as to cover the ohmic metal layer 40 and the gate metal layer 45. The insulating film 26a is formed by using, for example, a CVD (Chemical Vapor Deposition) method.

[0046] 15B, an opening is formed in a desired region of the insulating film 26a by etching. A low-resistance layer 50 is formed in the opening and on the insulating film 26a. The low-resistance layer 50 is formed by, for example, plating.

[0047] As shown in FIG. 15B and FIG. 18, a low resistance layer 50 is formed on the ohmic metal layer 40 and the gate metal layer 45. The sheet resistance of the low resistance layer 50 is lower than the sheet resistance of the ohmic metal layer 40 and the gate metal layer 45. The source finger 12a is formed by the source ohmic layer 42a and the source low resistance layer 52a formed on the source ohmic layer 42a. The drain finger 16a1 is formed by the drain ohmic layer 46a1 and the drain low resistance layer 56a formed on the drain ohmic layer 46a1. The drain finger 16b1 is formed by the drain ohmic layer 46b1 and the drain low resistance layer 56b formed on the drain ohmic layer 46b1.

[0048] The source finger 12b is formed by the source ohmic layer 42b and the source low resistance layer 52b formed on the source ohmic layer 42b. The source finger 12c is formed by the source ohmic layer 42c and the source low resistance layer 52c formed on the source ohmic layer 42c. The drain finger 16a2 is formed by the drain ohmic layer 46a2 and the drain low resistance layer 56a formed on the drain ohmic layer 46a2. The drain finger 16b2 is formed by the drain ohmic layer 46b2 and the drain low resistance layer 56b formed on the drain ohmic layer 46b2.

[0049] Drain wirings 19d and 19e are formed by drain low resistance layers 56a and 56b formed on inactive region 11a, respectively. Drain finger 16a1, drain wiring 19d, and drain finger 16a2 form drain finger 16a of Example 1. Drain finger 16b1, drain wiring 19e, and drain finger 16b2 form drain finger 16b of Example 1. A drain bus bar 24 connected to drain low resistance layers 56a and 56b is formed on the +Y side of FET region 30a.

[0050] The gate metal layer 48a and a low resistance layer 58a formed on the gate metal layer 48a form the gate wiring 18a. A low resistance layer 59 connected to the low resistance layer 58a is formed on the gate metal layer 49. The gate metal layer 49 and the low resistance layer 59 form a gate bus bar 22.

[0051] 15C, an insulating film 26b is formed on the insulating film 26a so as to cover the low-resistance layer 50. For example, a CVD method is used to form the insulating film 26b. The insulating films 26a and 26b form the insulating film 26. Thereafter, a via 20 is formed in the substrate 10, and a metal layer 28 is formed in the via 20 and on the lower surface of the substrate 10. In this way, the semiconductor device according to the first embodiment is manufactured.

[0052] In the third embodiment, the gate wiring 18a is formed of the gate metal layer 45 and the low resistance layer 50, so that the resistance of the gate wiring 18a can be reduced. The source fingers 12a to 12c and the drain fingers 16a1, 16a2, 16b1, and 16b2 can be formed of the ohmic metal layer 40 and the low resistance layer 50, so that the source fingers 12a to 12c and the drain fingers 16a1, 16a2, 16b1, and 16b2 can be reduced in resistance. The source wirings 19b and 19c are formed of the low resistance layer 50, and the gate wiring 18b is formed of the gate metal layer 45. Therefore, the source wirings 19b and 19c can cross the gate metal layer 45 without contacting each other through the insulating film 26a. The gate wirings 18a and 18b are formed on the inactive region 11a, so that the gate parasitic capacitance can be suppressed.

[0053] According to the third embodiment and its modified example, as shown in FIGS. 14A and 16, an active region 11b (first active region) and an active region 11c1 (second active region) in which the semiconductor layer 10b is activated and separated from each other, and an inactive region 11a provided between the active regions 11b and 11c1 in which the semiconductor layer 10b is inactivated are formed in the substrate 10.

[0054] 16, a source ohmic layer 42a (first source ohmic layer) and a drain ohmic layer 46a1 (first drain ohmic layer) are formed on the active region 11b. A source ohmic layer 42b (second source ohmic layer) and a drain ohmic layer 46a2 (second drain ohmic layer) are formed on the active region 11c1.

[0055] As shown in FIG. 17, a gate finger 14a (first gate finger) is formed on the active region 11b. A gate finger 14b (second gate finger) is formed on the active region 11c1. A gate metal layer 48a, which is a part of the gate wiring 18a (first gate wiring), is formed on the inactive region 11a. A gate wiring 18b (second gate wiring) is formed on the inactive region 11a.

[0056] 18, a source low resistance layer 52a (first source low resistance layer) in contact with the source ohmic layer 42a and a source low resistance layer 52b (second source low resistance layer) in contact with the source ohmic layer 42b are formed, and a source wiring 19b that connects the source low resistance layers 52a and 52b and crosses the gate wiring 18b in a non-contact manner is formed on the inactive region 11a simultaneously with the source low resistance layers 52a and 52b. As a result, the source wiring 19b is formed continuously from the same material as the source low resistance layers 52a and 52b.

[0057] The source wiring 19b is formed continuously from the same material as the source low resistance layers 52a and 52b. The sheet resistance of the source low resistance layers 52a and 52b is lower than the sheet resistance of the source ohmic layers 42a and 42b. This allows the resistance between the source fingers 12a and 12b to be low, and allows the gate wiring 18b and the source wiring 19b to cross each other without contacting each other.

[0058] The drain finger 16a also includes a drain ohmic layer 46a1 (first drain ohmic layer), a drain ohmic layer 46a2 (second drain ohmic layer), and a drain low resistance layer 56a. The drain low resistance layer 56a is in contact with the drain ohmic layers 46a1 and 46a2 and has a sheet resistance lower than that of the drain ohmic layers 46a1 and 46a2. This allows the resistance of the drain finger 16a to be low.

[0059] The sheet resistance of the low resistance layer 50 is preferably ½ or less, more preferably ⅕ or less, and even more preferably ⅙ or less, of the sheet resistance of the ohmic metal layer 40. As a method for making the sheet resistance of the low resistance layer 50 smaller than the sheet resistance of the ohmic metal layer 40, there is a method for making the resistivity of the main metal layer (e.g., gold) of the low resistance layer 50 lower than the resistivity of the main metal layer (e.g., aluminum) of the ohmic metal layer 40. There is also a method for making the low resistance layer 50 thicker than the ohmic metal layer 40.

[0060] The gate wiring 18b is formed simultaneously with the gate fingers 14a and 14b, that is, the material and thickness of the gate wiring 18b are the same as those of the gate fingers 14a and 14b, which simplifies the manufacturing process.

[0061] At least a part of the layer of the gate wiring 18a (gate metal layer 48a) is formed simultaneously with the gate wiring 18b. That is, the material and thickness of the gate metal layer 48a are the same as those of the gate wiring 18b. This simplifies the manufacturing process.

[0062] [Modification 1 of Example 3] 19 and 20 are plan views of a semiconductor device according to Modification 1 of Example 3. As shown in Fig. 19, when the gate metal layer 45 is formed, the gate metal layer 48a is not formed.

[0063] 20, the gate wiring 18a is formed of a low resistance layer 50, and does not have a gate metal layer 45. The other steps are the same as those in the third embodiment, and therefore a description thereof will be omitted.

[0064] Since the gate wiring 18a has the low resistance layer 58a, the resistance can be sufficiently reduced, and therefore the gate wiring 18a does not need to have the gate metal layer 48a.

[0065] [Modification 2 of Example 3] 21 and 22 are plan views of a semiconductor device according to Modification 2 of Example 3. As shown in Fig. 21, when the gate metal layer 45 is formed, the gate wiring 18b and the gate metal layer 48a are not formed.

[0066] As shown in FIG. 22, a gate metal layer 55 is formed on the inactive region 11a. For example, a vacuum deposition method and a lift-off method are used to form the gate metal layer 55. The gate wiring 18b and the gate metal layer 48a are formed by the gate metal layer 55. The gate metal layer 55 is made of a material having a lower resistivity than the gate metal layer 45. For example, when gold is used for the gate metal layer 45, the gate metal layer 55 Silver or copper is used for the gate metal layer 55. Furthermore, the gate metal layer 55 is made thicker than the gate metal layer 45. This allows the sheet resistance of the gate metal layer 55 to be lower than the sheet resistance of the gate metal layer 45. Therefore, in the second modification of the third embodiment, the resistance of the gate wirings 18a and 18b can be reduced. The other steps are the same as those in the third embodiment, and therefore a description thereof will be omitted.

[0067] [Modification 3 of Example 3] FIG. 23 is a plan view of a semiconductor device according to Modification 3 of Example 3. As shown in FIG. 23, the gate metal layer 55 has the gate wiring 18b, and may not have the gate metal layer 48a. The other steps are the same as those of Modification 2 of Example 3, and the description will be omitted. As in Modification 3 of Example 3, the gate wiring 18b intersects with the source wirings 19b and 19c, and therefore the low resistance layer 50 cannot be provided. For this reason, the gate wiring 18b is formed of the gate metal layer 55. Since the gate wiring 18a has the low resistance layer 50, it can be sufficiently reduced in resistance. For this reason, the gate wiring 18a does not need to have the gate metal layer 48a.

[0068] According to the second and third modified examples of the third embodiment, the sheet resistance of the gate wiring 18b is lower than that of the gate fingers 14a and 14b. This allows the resistance of the gate wiring 18b to be lowered. The sheet resistance of the gate wiring 18b is preferably 1 / 2 or less, more preferably 1 / 5 or less, of the sheet resistance of the gate fingers 14a and 14b. As a method for making the sheet resistance of the gate wiring 18b lower than that of the gate fingers 14a and 14b, there is a method for making the resistivity of the main metal layer (e.g., silver or copper) of the gate wiring 18b lower than that of the main metal layer (e.g., gold) of the gate fingers 14a and 14b. There is also a method for making the gate wiring 18b thicker than the gate fingers 14a and 14b.

[0069] In the first to third embodiments and their modified examples, an example has been described in which four unit FETs are arranged in the X direction, but the number of unit FETs in the X direction may be one, two, three, or five or more. Four unit FETs arranged in the X direction are regarded as one group, and a plurality of groups may be arranged in the X direction.

[0070] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0071] 10, 10a Board 10b Semiconductor layer 11, 11c2 active region 11a Inactive area 11b Active region (1st active region) 11c1 Active area (second active area) 12a to 12c source fingers (first to third source fingers) 14a to 14d Gate fingers (first to fourth gate fingers) 16a, 16b Drain fingers (first and second drain fingers) 16a1, 16a2, 16b1, 16b2 drain fingers 18a, 18a1 Gate wiring (first gate wiring) 18a2 Gate wiring (third gate wiring) 18b, 18b1 Gate wiring (second gate wiring) 18b2 Gate wiring (4th gate wiring) 18c, 18c1, 18c2 Gate wiring 19b Source wiring (first source wiring) 19c Source wiring (second source wiring) 19d, 19e Drain wiring 20 Via 22, 22a, 22b Gate busbar 24 Drain busbar 25 Resistance 26, 26a, 26b Insulating film 28 Metal layer 30a~30b FET area 32a~32f Unit FET 40 Ohmic metal layer 42a Source ohmic layer (first source ohmic layer) 42b Source ohmic layer (second source ohmic layer) 42c Source Ohmic Layer 45, 55 Gate metal layer 46a1 Drain ohmic layer (first drain ohmic layer) 46a2 Drain ohmic layer (second drain ohmic layer) 46b1, 46b2 Drain ohmic layers 48a, 49 Gate metal layers 50, 58a, 59 Low resistance layers 52a Source low resistance layer (first source low resistance layer) 52b Source low resistance layer (second source low resistance layer) 52c Source low resistance layer 56a, 56b Drain low resistance layers

Claims

1. A substrate; a first source finger disposed on the substrate; a first gate finger provided on the substrate adjacent to the first source finger in a width direction and along the first source finger; a second source finger provided on the substrate, the second source finger having a width smaller than that of the first source finger, the width of the second source finger being within the width of the first source finger, and extending in an extension direction in which the first source finger extends; a second gate finger provided along the second source finger on a region of the substrate adjacent to the second source finger in the width direction and located from the first gate finger in the extension direction; a first source wiring provided on the substrate and connecting the first source finger and the second source finger; a first gate wiring provided on the substrate, sandwiching the second source finger between the first gate finger and the second gate finger, and having a width in the width direction within a width of the first source finger; a second gate wiring provided on the substrate, intersecting the first source wiring without contacting the first gate wiring and connecting the first gate wiring and the first gate finger; a first drain finger provided on the substrate, the first source finger and the second source finger sandwiching the first gate finger and the second gate finger; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, further comprising a via extending through the substrate and connecting the first source finger to a metal layer provided below the substrate.

3. A third gate finger provided on the substrate adjacent to the first source finger in a width direction and along the first source finger, the third gate finger sandwiching the first source finger with the first gate finger; a third source finger provided on the substrate, the third source finger having a width smaller than that of the first source finger, the width in the width direction being within the width of the first source finger, extending in the extension direction, adjacent to the first gate wiring in the width direction, and sandwiching the first gate wiring between the third source finger and the second source finger; a fourth gate finger provided along the third source finger on a region of the substrate adjacent to the third source finger in the width direction and located from the third gate finger in the extension direction, the fourth gate finger sandwiching the third source finger between the first gate wiring and the fourth gate finger; a second drain finger provided on the substrate, the first source finger and the third source finger sandwiching the third gate finger and the fourth gate finger; a second source wiring provided on the substrate and connecting the first source finger and the third source finger; Equipped with 3. The semiconductor device according to claim 1, wherein the second gate wiring intersects the second source wiring without contacting the first gate wiring and connects the first gate wiring to the third gate finger.

4. 4. The semiconductor device according to claim 1, further comprising: a gate bus bar provided on a region of the substrate opposite the first source finger with respect to the second source finger, the gate bus bar being connected to the first gate wiring.

5. 5 . The semiconductor device according to claim 4 , wherein a first end of the second gate finger is connected to the gate bus bar, and a second end of the second gate finger is spaced from the second gate wiring.

6. 5. The semiconductor device according to claim 4, wherein a first end of the second gate finger is spaced from the gate bus bar, and a second end of the second gate finger is connected to the second gate wiring.

7. 5. The semiconductor device according to claim 4, wherein a first end of the second gate finger is connected to the gate bus bar, and a second end of the second gate finger is connected to the second gate wiring.

8. A third gate finger provided on the substrate adjacent to the first source finger in a width direction and along the first source finger, the third gate finger sandwiching the first source finger with the first gate finger; a third source finger provided on the substrate, the third source finger having a width smaller than that of the first source finger, the width in the width direction being within the width of the first source finger, the third source finger extending in the extension direction, and sandwiching the first gate wiring between the third source finger and the second source finger; a fourth gate finger provided along the third source finger on a region of the substrate adjacent to the third source finger in the width direction and located from the third gate finger in the extension direction, the fourth gate finger sandwiching the third source finger between the first gate wiring and the fourth gate finger; a second drain finger provided on the substrate, the first source finger and the third source finger sandwiching the third gate finger and the fourth gate finger; a second source wiring provided on the substrate and connecting the first source finger and the third source finger; a third gate wiring provided on the substrate, between the third source finger and the first gate wiring, the width in the width direction being within the width of the first source finger, and separated from the first gate wiring on the substrate; a fourth gate wiring provided on the substrate, intersecting the second source wiring without contacting the second source wiring, and separated from the second gate wiring on the substrate, and connecting the third gate wiring and the third gate finger; The semiconductor device according to claim 1 , further comprising:

9. a first gate bus bar provided on a region of the substrate opposite the first source finger with respect to the second source finger, the first gate bus bar being connected to the first gate wiring; a second gate bus bar provided on a region of the substrate opposite the first source finger with respect to the third source finger, connected to the third gate wiring, and separated from the first gate bus bar on the substrate; a resistor electrically connecting the first gate wiring and the first gate bus bar to the third gate wiring and the second gate bus bar; The semiconductor device according to claim 8 .

10. the substrate includes a first active region and a second active region in which a semiconductor layer in the substrate is activated and separated from each other, and an inactive region provided between the first active region and the second active region in which the semiconductor layer is inactive; the first source finger includes a first source ohmic layer in ohmic contact with the first active region, and a first source low-resistance layer provided on and in contact with the first source ohmic layer and having a sheet resistance lower than that of the first source ohmic layer; the second source finger includes a second source ohmic layer in ohmic contact with the second active region, and a second source low-resistance layer provided on and in contact with the second source ohmic layer and having a sheet resistance lower than that of the second source ohmic layer; the second gate wiring is provided on the inactive region, 10. The semiconductor device according to claim 1, wherein the first source wiring is formed continuously with the first source low resistance layer and the second source low resistance layer from the same material.

11. 11. The semiconductor device according to claim 10, wherein the first drain finger comprises a first drain ohmic layer in ohmic contact with the first active region, a second drain ohmic layer in ohmic contact with the second active region, and a drain low resistance layer in contact with the first drain ohmic layer and the second drain ohmic layer and having a sheet resistance lower than that of the first drain ohmic layer and the second drain ohmic layer.

12. 12. The semiconductor device according to claim 1, wherein the second gate wiring is made of the same material as the first gate finger and the second gate finger.

13. 12 . The semiconductor device according to claim 1 , wherein the sheet resistance of the second gate wiring is lower than the sheet resistances of the first gate finger and the second gate finger.

14. forming, in a substrate, a first active region and a second active region in which a semiconductor layer is activated and separated from each other, and an inactive region provided between the first active region and the second active region in which the semiconductor layer is inactive; forming, on the first active region, a first source ohmic layer and a first drain ohmic layer adjacent to the first source ohmic layer in a width direction and provided along the first source ohmic layer, and forming, on the second active region, a second source ohmic layer having a width smaller than that of the first source ohmic layer, a width in the width direction that falls within the width of the first source ohmic layer, and extending in an extension direction in which the first source ohmic layer extends, and a second drain ohmic layer adjacent to the second source ohmic layer in the width direction and provided along the second source ohmic layer; forming a first gate finger on the first active region, the first gate finger being sandwiched between the first source ohmic layer and the first drain ohmic layer, adjacent to the first source ohmic layer in the width direction and provided along the first source ohmic layer; and forming a second gate finger on the second active region, the second gate finger being sandwiched between the second source ohmic layer and the second drain ohmic layer, adjacent to the second source ohmic layer in the width direction and provided along the second source ohmic layer in a region located from the first gate finger in the extension direction; forming a first gate wiring on the substrate, the first gate wiring sandwiching the second source ohmic layer with the second gate finger and having a width in the width direction that falls within a width of the first source ohmic layer; forming a second gate wiring on the inactive region connecting the first gate finger and the first gate wiring; A method for manufacturing a semiconductor device comprising the steps of:

15. A method for manufacturing a semiconductor device as described in claim 14, further comprising the steps of forming a first source low-resistance layer in contact with the first source ohmic layer and a second source low-resistance layer in contact with the second source ohmic layer, connecting the first source low-resistance layer and the second source low-resistance layer on the inactive region, and forming a source wiring that crosses the second gate wiring in a non-contact manner simultaneously with the first source low-resistance layer and the second source low-resistance layer.

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