Semiconductor Device

Abstract

To provide a semiconductor device having improved reliability.SOLUTION: A semiconductor device includes: a substrate having a first region and a second region; gate electrodes stacked along a first direction perpendicular to the substrate's top surface so as to be separated from each other; first separation regions that penetrate the gate electrodes in the first region and the second region, are extended in a second direction, and are disposed along a third direction so as to be separated from each other; second separation regions that between the first separation regions, penetrate the gate electrodes and are extended in the second direction; a lower part separation region that between the second separation regions, penetrates at least one grounding selection gate electrode; substrate insulation layers that in the second region, are disposed in the substrate among the first separation regions and the second separation regions; channel structures that in the first region, penetrate the gate electrodes and are extended vertically; and first dummy channel structures that outside the lower part separation region along the third direction, penetrate the gate electrodes and the substrate insulation layers and are extended vertically.SELECTED DRAWING: Figure 3a

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] While the volume of semiconductor devices is gradually decreasing, they are required to process large amounts of data. Therefore, it is necessary to increase the integration density of the semiconductor elements that constitute such semiconductor devices. As one method for increasing the integration density of semiconductor devices, a semiconductor device having a vertical transistor structure instead of the conventional planar transistor structure has been proposed. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the technical problems that the technical concept of the present invention aims to solve is to provide a semiconductor device with improved reliability. [Means for solving the problem]

[0004] According to an exemplary embodiment, a semiconductor device includes a substrate having first and second regions; gate electrodes including at least one ground selection gate electrode, a memory cell gate electrode, and at least one string selection gate electrode stacked in sequence from above the substrate, the gate electrodes being stacked in the first region and spaced apart from each other along a first direction perpendicular to an upper surface of the substrate and extending to different lengths along a second direction perpendicular to the first direction in the second region; first isolation regions penetrating the gate electrode in the first and second regions and extending in the second direction, the first isolation regions being spaced apart from each other along a third direction perpendicular to the first and second directions; and gate electrodes including at least one ground selection gate electrode, a memory cell gate electrode, and at least one string selection gate electrode stacked in sequence from above the substrate, the gate electrodes being stacked in the first region and extending in the second direction, the memory cell gate electrode, and at least one string selection gate electrode stacked in sequence from above the substrate. a lower isolation region penetrating the at least one ground selection gate electrode between the second isolation regions and isolating the at least one ground selection gate electrode together with the second isolation region; a substrate insulating layer disposed in the substrate between the first isolation region and the second isolation region in the second region; a channel structure penetrating the gate electrode in the first region and extending vertically onto the substrate; and a first dummy channel structure penetrating the gate electrode and the substrate insulating layer at an outer side of the lower isolation region along the third direction and extending vertically onto the substrate.

[0005] According to another exemplary embodiment, a semiconductor device may include a substrate having a conductive region and an insulating region; gate electrodes stacked apart from each other along a first direction perpendicular to an upper surface of the substrate and extending along a second direction perpendicular to the first direction, and a gate connector connecting the sub-gate electrodes arranged at the same height; a channel structure extending through the gate electrode on the conductive region of the substrate; and a first dummy channel structure extending through the gate electrode in the insulating region of the substrate and arranged adjacent to at least one side of the gate connector in a third direction perpendicular to the first and second directions.

[0006] According to yet another exemplary embodiment, a semiconductor device may include a substrate having first and second regions; gate electrodes stacked and spaced apart from each other along a first direction perpendicular to an upper surface of the substrate in the first region and extending to different lengths along a second direction perpendicular to the first direction in the second region to provide a pad region; through isolation regions penetrating the gate electrodes in the first and second regions and extending in the second direction and disposed and spaced apart from each other along the second direction in the second region; lower isolation regions penetrating at least one of the gate electrodes including a lowermost gate electrode between the through isolation regions; a substrate insulating layer disposed within a portion of the substrate in the second region; a channel structure penetrating the gate electrodes in the first region and extending vertically onto the substrate; a first dummy channel structure penetrating at least a portion of the gate electrodes and the substrate insulating layer in the second region and extending vertically onto the substrate, and disposed adjacent to the lower isolation region around the lower isolation region; and a second dummy channel structure regularly disposed in the pad region of the gate electrodes. Effect of the Invention

[0007] By optimizing the arrangement of the dummy channel structure in consideration of the arrangement of the substrate insulating layer and the lower isolation region, a semiconductor device with improved reliability can be provided.

[0008] The various yet significant advantages and effects of the present invention are not limited to the above, but can be more easily understood in the course of describing specific embodiments of the present invention. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic block diagram of a semiconductor device according to an exemplary embodiment; [Diagram 2] 1 is an equivalent circuit diagram of a cell array of a semiconductor device according to an exemplary embodiment; [Figure 3a] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 3b] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 3c] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 4a] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 4b] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 4c] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 5a] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 5b] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 6a] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 6b] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 7a] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 7b] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 8] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 9] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 10a] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 10b] 1 is a schematic plan view of a semiconductor device according to an exemplary embodiment; [Figure 11] 1 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment; [Figure 12a] 1 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 12b] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 13a] 1 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 13b] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 14a] 1 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 14b] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 15a] 1 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 15b] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. [Figure 16a] 1 is a schematic plan view for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment; [Figure 16b] 1A to 1C are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0011] FIG. 1 is a schematic block diagram of a semiconductor device according to an exemplary embodiment.

[0012] 1, a semiconductor device 10 may include a memory cell array 20 and a peripheral circuit 30. The peripheral circuit 30 may include a row decoder 32, a page buffer 34, an input / output buffer 35, a control logic 36, and a voltage generator 37.

[0013] FIG. 2 is an equivalent circuit diagram of a cell array of a semiconductor device according to an exemplary embodiment.

[0014] 2, the memory cell array 20 may include a plurality of memory cell strings S, each including memory cells MC connected in series to each other, ground selection transistors GST connected in series to both ends of the memory cells MC, and string selection transistors SST1, SST2. The plurality of memory cell strings S may be connected in parallel to bit lines BL0-BL2, respectively. The plurality of memory cell strings S may be commonly connected to a common source line CSL. That is, a plurality of memory cell strings S may be arranged between the plurality of bit lines BL0-BL2 and one common source line CSL. In an exemplary embodiment, a plurality of common source lines CSL may be arranged two-dimensionally.

[0015] The memory cell array 20 may further include a ground selection line GSL coupled to the ground selection transistor GST of each memory cell string S, and a plurality of word lines WL0...WLn-1, WLn coupled to the memory cells MC of the memory cell string S. In addition, a dummy word line DWL may be provided under the string selection line SSL1 (e.g., string selection lines SSL1_1, SSL1_2, SSL1_3) and coupled to the memory cells MC immediately below the string selection transistor SST1. In some embodiments, the memory cells MC immediately below the string selection transistor SST1 in the memory cell string S may be dummy memory cells.

[0016] 3a to 3c are schematic plan views of a semiconductor device according to an exemplary embodiment. FIG. 3b is an enlarged view of the "R" region of FIG. 3a, and FIG. 3c is a view showing only the configuration of one memory gate electrode 130M in the "R" region. To facilitate understanding, only the main configuration of the semiconductor device 100 is shown in FIG. 3a and FIG. 3b.

[0017] 4a to 4c are schematic cross-sectional views of a semiconductor device according to an exemplary embodiment, taken along lines II', II-II', and III-III' in FIG. 3a, respectively.

[0018] 3a to 4c, the semiconductor device 100 includes a substrate 101 having a first region A and a second region B, a substrate insulating layer 110 disposed in the substrate 101 in the second region B, a gate electrode 130 stacked on the substrate 101, a channel structure CH and a dummy channel structure DCH disposed to penetrate the gate electrode 130, first and second isolation regions MS1, MS2a, and MS2b extending through the gate electrode 130, an upper isolation region SS penetrating a portion of the gate electrode 130 disposed at the top, and a lower isolation region GS penetrating a portion of at least one gate electrode 130 disposed at the bottom. The channel structure CH may include a channel layer 140, a gate dielectric layer 145, a channel insulating layer 150, and a channel pad 155. The semiconductor device 100 may further include an interlayer insulating layer 120 alternately stacked with the gate electrode 130 on the substrate 101, and a cell region insulating layer 190 on the interlayer insulating layer 120 and the gate electrode 130.

[0019] The first region A of the substrate 101 is a region where the gate electrodes 130 are vertically stacked and channel structures CH are arranged, and may correspond to the memory cell array 20 of FIG. 1, and the second region B is a region where the gate electrodes 130 are extended to different lengths and dummy channel structures DCH are arranged, and may correspond to a region electrically connecting the memory cell array 20 and the peripheral circuit 30 of FIG. 1. The second region B may be arranged at least at one end of the first region A in at least one direction, for example, the X direction. For example, the second region B may be arranged adjacent to the first region A in at least one direction.

[0020] The substrate 101 may have a top surface extending in the X-direction and the Y-direction. The substrate 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer or an epitaxial layer.

[0021] The substrate insulating layer 110 may be disposed in the substrate 101 in the second region B of the substrate 101. The substrate insulating layer 110 may be disposed between the first isolation region MS1, the second central isolation region MS2a, the lower isolation region GS, and the second auxiliary isolation region MS2b in the second region B as shown in FIGS. 3a and 3b. The substrate insulating layer 110 may not extend to the region where the second central isolation region MS2a is spaced apart along the X direction. The substrate insulating layer 110 extends to a part of the region where the second auxiliary isolation region MS2b is spaced apart along the X direction (for example, the spaced apart region between the second auxiliary isolation region MS2b adjacent to the first region A), but does not extend to other spaced apart regions. However, depending on the embodiment, the substrate insulating layer 110 may extend to the entire region where the second auxiliary isolation region MS2b is spaced apart along the X direction.

[0022] The substrate insulating layer 110 may be formed by, for example, a shallow trench isolation (STI) process. The substrate insulating layer 110 may extend from an upper surface of the substrate 101 to a predetermined depth within the substrate 101. The substrate insulating layer 110 may be made of an insulating material, for example, an oxide, a nitride, or a combination thereof. The substrate insulating layer 110 may also be described as serving to configure an insulating region of the substrate 101. In this case, the substrate 101 may include an insulating region corresponding to the substrate insulating layer 110 and a conductive region due to a semiconductor region.

[0023] The gate electrodes 130 are stacked vertically on the first region A at a distance from each other, and may extend to different lengths from the first region A to the second region B. The gate electrodes 130 may include a ground selection gate electrode 130G forming the gate of the ground selection transistor GST of FIG. 2, a memory cell gate electrode 130M forming a plurality of memory cells MC, and a string selection gate electrode 130S forming the gates of the string selection transistors SST1 and SST2. The number of memory cell gate electrodes 130M forming the memory cells MC may be determined according to the capacity of the semiconductor device 100. Depending on the embodiment, the string selection gates 130S of the string selection transistors SST1 and SST2 and the ground selection gate 130G of the ground selection transistor GST may each be one or more, and may have the same structure as or different from the gate electrode 130M of the memory cell MC. Some of the gate electrodes 130, for example, the memory cell gate electrodes 130M adjacent to the ground selection gate electrode 130G and the string selection gate electrode 130S, may be dummy gate electrodes.

[0024] As shown in FIG. 3a and FIG. 3c, the gate electrodes 130 may be arranged in a predetermined unit separated in the Y direction by a first isolation region MS1 ​​extending in the X direction. The gate electrodes 130 between a pair of the first isolation regions MS1 may form one memory block, but the scope of the memory block is not limited thereto. A part of the gate electrodes 130, for example, the memory cell gate electrodes 130M, may form one layer in one memory block. Specifically, as shown in FIG. 3c, the memory cell gate electrodes 130M may include four sub-gate electrodes 130M_S1, 130M_S2, 130M_S3, and 130M_S4 each extending in the X direction, and the second isolation regions MS2a and MS2b may be connected via a gate connection part GC in a region spaced apart from each other along the X direction and arranged in one layer. The gate connection part GC refers to a region where the gate electrodes 130 are horizontally connected at the same level. The string selection gate electrode 130S may be completely separated into four sub-gate electrodes by the first and second isolation regions MS1, MS2a, and MS2b between a pair of first isolation regions MS1. For example, the four sub-gate electrodes of the string selection gate electrode 130S may not be connected to each other by the gate connection part GC in the separation region between the second isolation regions MS2a and MS2b. The ground selection gate electrode 130G may be connected between some of the second isolation regions MS2a and MS2b via the gate connection part, but may be separated into two sub-gate electrodes by the second central isolation region MS2a and the lower isolation region GS between the second central isolation region MS2a.

[0025] As shown in FIG. 4c, in the second region B of the substrate 101, the gate electrodes 130 may extend to different lengths in the X direction to form a stepped portion, and a pad region may be provided in which the lower gate electrodes 130 are exposed to the upper portion. For example, the pad region of the gate electrodes 130 may be a portion of the gate electrodes 130 that does not overlap with one or more other gate electrodes 130 disposed on the upper portion in the Z direction. Depending on the embodiment, the gate electrodes 130 may form a stepped portion along the Y direction. Each of the gate electrodes 130 may be exposed to the upper portion in the pad region and connected to a contact plug (not shown). Thus, the gate electrodes 130 may be connected to an upper wiring structure. In the pad region, the gate electrodes 130 may have a region where the thickness is increased so as to be stably connected to the contact plug, but is not limited thereto.

[0026] The gate electrode 130 may include a metal material, such as tungsten (W). Depending on the embodiment, the gate electrode 130 may include polysilicon or a metal silicide material. In an exemplary embodiment, the gate electrode 130 may further include a diffusion barrier. The diffusion barrier may include, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0027] The interlayer insulating layers 120 may be disposed between the gate electrodes 130. Similar to the gate electrodes 130, the interlayer insulating layers 120 may be disposed to be spaced apart from each other in a direction perpendicular to the top surface of the substrate 101 and extend in the X direction. The interlayer insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride.

[0028] The first and second isolation regions MS1, MS2a, MS2b may be arranged to extend along the X direction in the first region A and the second region B. The first and second isolation regions MS1, MS2a, MS2b may be arranged parallel to each other. The first isolation region MS1 ​​and the second isolation regions MS2a, MS2b may be arranged to form a certain pattern in the Y direction, and the second isolation regions MS2a, MS2b may be arranged spaced apart from each other on a straight line along the X direction. The first and second isolation regions MS1, MS2a, MS2b may be penetrating isolation regions that penetrate the entire gate electrode 130 stacked on the substrate 101 and are connected to the substrate 101. For example, the lower surfaces of the first and second isolation regions MS1, MS2a, MS2b may contact the upper surface of the substrate 101.

[0029] The second isolation regions MS2a and MS2b may include a second central isolation region MS2a disposed in the center of the pair of first isolation regions MS1, and a second auxiliary isolation region MS2b disposed between the first isolation region MS1 ​​and the second central isolation region MS2a. The second central isolation region MS2a may be disposed throughout the first region A and the second region B, and the second auxiliary isolation region MS2b may be disposed only in the second region B. The second central isolation region MS2a may be disposed to extend from the first region A to a part of the second region B as a single region, and may be disposed to extend again as a single region in the second region B, spaced apart from the first region A. For example, each of the second isolation regions MS2a and MS2b may include two segments extending adjacent to each other in the X direction, and a short sidewall of the first segment (e.g., a segment extending from the first region A to a part of the second region B) may face a short sidewall of the second segment (e.g., a segment extending within the second region B). The second auxiliary isolation regions MS2b may be arranged in a plurality of rows, separated by a predetermined interval on a straight line. For example, each of the second auxiliary isolation regions MS2b may include a plurality of segments extending adjacent to each other in the X direction. In some embodiments, a first segment (e.g., a segment closest to the first region A) may have a first short sidewall facing the first region A and a second short sidewall facing the first short sidewall of an adjacent second segment. The second segment may have the first short sidewall facing the first segment and a second short sidewall facing the first short sidewall of an adjacent third segment. The remaining segments may be arranged in a similar manner. However, the arrangement order and number of the first and second isolation regions MS1, MS2a, and MS2b are not limited to those shown in FIG. 3a. For example, in an exemplary embodiment, the second isolation regions MS2a and MS2b may be arranged in four or more rows between a pair of first isolation regions MS1 along the Y direction.

[0030] As shown in FIGS. 4a and 4b, the first and second isolation regions MS1, MS2a, and MS2b may include an isolation layer 107. The isolation layer 107 may include only an insulating material, or may include an insulating material and a conductive material. In an exemplary embodiment, when the isolation layer 107 includes a conductive layer separated from the gate electrode 130 by the insulating layer in addition to the insulating layer, the first isolation region MS1 ​​may include the common source line CSL described with reference to FIG. 2, and the second isolation regions MS2a and MS2b may include a dummy common source line. In this case, the dummy common source line may be in a floating state in which it is not connected to an element that drives the semiconductor device 100 or to which no electrical signal is applied. In an exemplary embodiment, when the isolation layer 107 includes only an insulating layer, the common source line CSL may be located within the substrate 101 or may be disposed on the substrate 101 so as to contact an upper surface of the substrate 101.

[0031] The upper isolation region SS may extend in the X direction between the first isolation region MS1 ​​and the second central isolation region MS2a in the first region A. The upper isolation region SS may be arranged side by side with the second auxiliary isolation region MS2b. The upper isolation region SS may be arranged to penetrate a part of the gate electrode 130 including the string selection gate electrode 130S. The string selection gate electrodes 130S separated by the upper isolation region SS may form different string selection lines SSL1_1, SSL1_2, SSL1_3, SSL2_1, SSL2_2, and SSL2_3 (see FIG. 2). In some embodiments, the upper isolation region SS may further penetrate the uppermost memory cell gate electrode 130M. In such an embodiment, the uppermost memory cell gate electrode 130M separated by the upper isolation region SS may be a dummy gate electrode.

[0032] The upper isolation region SS may include an upper insulating layer 103. As shown in Fig. 4b, the upper insulating layer 103 may separate a total of three gate electrodes 130 (e.g., two string select gate electrodes 130S and the top memory cell gate electrode 130M) from each other in the Y direction. However, the number of gate electrodes 130 separated by the upper insulating layer 103 may be changed in various ways depending on the embodiment.

[0033] The lower isolation region GS may be disposed at the same level as the bottom ground selection gate electrode 130G. The lower isolation region GS and the ground selection gate electrode 130G may have the same thickness. For example, the upper surfaces of the lower isolation region GS and the ground selection gate electrode 130G may be coplanar with each other, and the lower surfaces of the lower isolation region GS and the ground selection gate electrode 130G may be coplanar with each other. The lower isolation region GS may separate or divide the ground selection gate electrode 130G into two layers along the Y direction between a pair of first isolation regions MS1. For example, the first section may be located between the first first isolation region MS1 ​​and the lower isolation region GS, and the second section may be located between the lower isolation region GS and the second first isolation region MS1. In particular, the lower isolation region GS may be disposed to connect the second central isolation region MS2a by including regions where the second central isolation regions MS2a are spaced apart from each other.

[0034] As shown in FIG. 4a, the lower isolation region GS may include a lower insulating layer 170. The lower insulating layer 170 may be made of, for example, silicon oxide, and may have the same material as the interlayer insulating layer 120. At least a portion of the interlayer insulating layer 120 and the gate electrode 130 may have a recessed portion DP toward the center of the lower isolation region GS in the upper portion of the lower isolation region GS. As the interlayer insulating layer 120 and the gate electrode 130 move away from the lower isolation region GS, the recessed portion DP may be less curved, or may not have a recessed portion DP. For example, the interlayer insulating layer 120 and the gate electrode 130 closer to the lower isolation region GS may have a relatively large recessed portion DP, and the interlayer insulating layer 120 and the gate electrode 130 farther from the lower isolation region GS may have a relatively small recessed portion DP, or may not have a recessed portion DP. In an exemplary embodiment, the process of forming the lower isolation region GS may not form a recessed portion DP, and the interlayer insulating layer 120 on the lower isolation region GS may have a flat upper surface.

[0035] The channel structures CH may be arranged in rows and columns on the first region A, spaced apart from each other. The channel structures CH may be arranged to form a lattice pattern or may be arranged in a zigzag pattern in one direction. The channel structures CH may have a columnar shape and may have an inclined surface that narrows toward the substrate 101 according to the aspect ratio. In an exemplary embodiment, the channel structure CH arranged at the end of the first region A adjacent to the second region B may be a dummy channel. Also, the channel structure CH overlapping the upper isolation region SS may be a dummy channel. In this case, the dummy channel may have the same or similar structure as the channel structure CH and may be formed simultaneously in the same process as the channel structure CH, but may not perform a substantial function in the semiconductor device 100. For example, the dummy channel structure DCH does not perform a function for a read or write operation (for example, the dummy channel structure DCH is not electrically connected to a bit line contact and is not connected to a bit line).

[0036] Referring to the enlarged view of FIG. 4c, a channel layer 140 may be disposed in the channel structure CH. In the channel structure CH, the channel layer 140 may be formed in an annular shape surrounding an internal channel insulating layer 150, but may have a columnar shape such as a cylinder or a rectangular column without the channel insulating layer 150 according to an embodiment. The channel layer 140 may be connected to an epitaxial layer 105 disposed in the lower part of the channel structure CH, and an insulating layer may be further disposed between the channel layer 140 and the epitaxial layer 105. The channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon. The semiconductor material may be an undoped material or a material containing p-type or n-type impurities. The channel structures CH disposed on a straight line in the Y direction may be connected to different bit lines BL0-BL2 (see FIG. 2) according to the arrangement of an upper wiring structure connected to the channel pad 155.

[0037] In the channel structure CH, a channel pad 155 may be disposed on the channel layer 140. The channel pad 155 may be disposed to cover an upper surface of the channel insulating layer 150 and to be electrically connected to the channel layer 140. The channel pad 155 may include, for example, doped polycrystalline silicon.

[0038] The gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically illustrated, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer, which are stacked in this order from the channel layer 140. The tunneling layer may tunnel charges to the charge storage layer, and may be, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4), silicon oxynitride (SiON), or a combination thereof. The charge storage layer can be a charge trapping layer or a floating gate conductive layer. The blocking layer can be silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof. Depending on the exemplary embodiment, at least a portion of the gate dielectric layer 145 may extend horizontally along the gate electrode 130.

[0039] The epitaxial layer 105 may be disposed on the substrate 101 at the bottom of the channel structure CH and on the side of at least one gate electrode 130. The epitaxial layer 105 may be disposed in a recessed region of the substrate 101. The height of the top surface of the epitaxial layer 105 may be higher than the top surface of the bottom gate electrode 130 and lower than the bottom surface of the top gate electrode 130, but is not limited to what is shown in the figure. Depending on an exemplary embodiment, the epitaxial layer 105 may be omitted. In this case, the channel layer 140 may be directly connected to the substrate 101.

[0040] The dummy channel structure DCH may be disposed in the second region B and may have the same or similar structure as the channel structure CH, but may not perform a substantial function in the semiconductor device 100. In particular, the dummy channel structure DCH may be disposed to penetrate the substrate insulating layer 110 and be connected to the substrate 101. For example, the dummy channel structure DCH may be extended through the lower surface of the substrate insulating layer 110. The dummy channel structure DCH may include a first dummy channel structure DCH1 disposed on the outer side of the lower isolation region GS in the Y direction, a second dummy channel structure DCH2 regularly disposed in columns and rows in the pad region of the gate electrode 130, and a third dummy channel structure DCH3 disposed in at least a part of the region separated from the second auxiliary isolation region MS2b in the X direction. As described above, in the first region A, the channel structure CH may also include some dummy channel structures.

[0041] The first dummy channel structure DCH1 may be disposed on both sides of the lower isolation region GS along the Y direction. The first dummy channel structure DCH1 may be disposed between the adjacent second dummy channel structures DCH2 along the X direction. The first dummy channel structure DCH1 may have a maximum diameter (or width) larger than the maximum diameters of the channel structure CH and the second and third dummy channel structures DCH2, DCH3. Specifically, the first dummy channel structure DCH1 may have a second width W2 larger than the first width W1, which is the maximum diameter (or width) of the channel structure CH, and the second width W2 may be larger than the third width W3, which is the maximum diameter of the third dummy channel structure DCH3. Also, the second width W2 may be larger than the maximum diameter of the second dummy channel structure DCH2. For example, the first width W1 may be in the range of about 50 nm to about 150 nm, and the second width W2 may be in the range of about 120 nm to 220 nm. While the channel structure CH and the second and third dummy channel structures DCH2 and DCH3 have a circular or nearly circular shape, the first dummy channel structure DCH1 may have a shape in which the width along the Y direction is larger than the width along the X direction. The first dummy channel structure DCH1 may have an elongated, rectangular, or elliptical shape that is elongated along the Y direction.

[0042] The second dummy channel structures DCH2 may be arranged according to a certain rule. When a minimum unit surrounded by the first and second isolation regions MS1, MS2a, and MS2b in the pad region is referred to as a unit pad region, the second dummy channel structures DCH2 may be arranged at four ends of one unit pad region, and a pattern of four second dummy channel structures DCH2 arranged per unit pad region may be repeated. The maximum diameter of the second dummy channel structure DCH2 may be smaller than the maximum diameter of the first dummy channel structure DCH1 and may be equal to or smaller than the maximum diameter of the third dummy channel structure DCH3.

[0043] The third dummy channel structure DCH3 may be disposed in a straight line along the Y direction with the first dummy channel structure DCH1, and the second auxiliary isolation region MS2b may be disposed in a region spaced apart from the first dummy channel structure DCH1 in the X direction. In this embodiment, the third dummy channel structure DCH3 may be disposed only in a straight line along the Y direction with the first dummy channel structure DCH1, and may not be disposed in other regions spaced apart from the second auxiliary isolation region MS2b along the X direction. In this case, as shown in the drawing, the substrate insulating layer 110 may not be extended to the other regions spaced apart from the second auxiliary isolation region MS2b. However, depending on the embodiment, the third dummy channel structure DCH3 may be disposed in all the regions spaced apart from the second auxiliary isolation region MS2b along the X direction.

[0044] Since the dummy channel structure DCH is disposed to penetrate the substrate insulating layer 110, the lower end of the dummy channel structure DCH may be located at a lower height than the lower end of the channel structure CH. Thus, the dummy channel structure DCH may have a higher height than the channel structure CH. Also, the epitaxial layer 105 in the dummy channel structure DCH may be disposed such that at least a part of the side surface is surrounded by the substrate insulating layer 110. For example, the upper surface of the epitaxial layer 105 in the dummy channel structure DCH may be located lower than the upper surface of the substrate insulating layer 110, and the lower surface of the epitaxial layer 105 in the dummy channel structure DCH may be located lower than the lower surface of the substrate insulating layer 110. The epitaxial layer 105 in the dummy channel structure DCH may have a relatively low height or a thin thickness when the diameters of the first to third dummy channel structures DCH1, DCH2, and DCH3 are relatively large. For example, the epitaxial layer 105 of the channel structure CH may have a first height H1, the epitaxial layer 105 of the first dummy channel structure DCH1 may have a second height H2 lower than the first height H1, and the epitaxial layer 105 of the third dummy channel structure DCH3 may have a third height H3 that is the same as or lower than the first height H1 and higher than the second height H2.

[0045] The dummy channel structure DCH may play a role in supporting the stacked structure including the interlayer insulating layer 120 so as not to collapse during the manufacturing process of the semiconductor device 100. In particular, the region where the lower isolation region GS is located may be one of the fragile regions that are prone to collapse during the manufacturing process of the semiconductor device 100. According to the present embodiment, the dummy channel structure DCH is not disposed so as to overlap the lower isolation region GS, but the first dummy channel structure DCH1 is disposed on both sides of the lower isolation region GS to prevent the upper part of the lower isolation region GS from collapsing.

[0046] In addition, the first dummy channel structure DCH1 can be formed relatively large since there is less size restriction compared to when it is arranged overlapping the lower isolation region GS, and the occurrence of defects due to misalignment can be prevented. In addition, the first dummy channel structure DCH1 is arranged apart from the center of the depression DP, so that the occurrence of defects due to the structure of the depression DP can be prevented. In particular, the dummy channel structure DCH penetrates the substrate insulating layer 110 and has a lower end located at a height lower than the channel structure CH, so that the occurrence of defects such as a short circuit or leakage current between the epitaxial layer 105 and the gate electrode 130 can be fundamentally prevented.

[0047] A cell region insulating layer 190 is disposed over the gate electrode 130 stack and may include insulating materials such as silicon oxide or silicon nitride.

[0048] 5a to 6b are schematic plan and cross-sectional views of a semiconductor device according to an exemplary embodiment, where Fig. 5a and Fig. 6a are views showing an area corresponding to Fig. 3b, and Fig. 5b and Fig. 6b are views showing an area corresponding to Fig. 4a.

[0049] 5a and 5b, in the semiconductor device 100a, the dummy channel structure DCHa may include only the first and second dummy channel structures DCH1 and DCH2. That is, unlike the embodiment of FIGS. 3a to 4c, the dummy channel structure DCHa may not include the third dummy channel structure DCH3. In this case, in the substrate 101, the substrate insulating layer 110a does not extend between the second central isolation regions MS2a adjacent to each other along the X direction, nor between the second auxiliary isolation regions MS2b adjacent to each other along the X direction.

[0050] 6a and 6b, in the semiconductor device 100b, unlike the embodiment of Figures 3a to 4c, the substrate insulating layer 110b may extend not only between parts of the second auxiliary isolation regions MS2b adjacent to each other in the X direction, but also between parts of the second central isolation regions MS2a adjacent to each other in the X direction, so that the substrate insulating layer 110b may be disposed to overlap the lower isolation region GS in a plane or in the Z direction.

[0051] Figures 7a and 7b are schematic plan views of a semiconductor device according to an exemplary embodiment, showing an area corresponding to Figure 3b.

[0052] 7a, unlike the embodiment of FIG. 3b, the semiconductor device 100c may have a second dummy channel structure DCH2 in the dummy channel structure DCHc having a shape close to an ellipse, not a circular shape. In particular, the four second dummy channel structures DCH2 arranged in one unit pad region may be arranged inclined toward the center of the unit pad region. In this case, the maximum diameter of the first dummy channel structure DCH1 may be larger than the maximum diameter of the second dummy channel structure DCH2. As described above, the shapes of the first to third dummy channel structures DCH1, DCH2, and DCH3 constituting the dummy channel structure DCHc may be variously changed according to the embodiment.

[0053] Referring to FIG. 7b, the semiconductor device 100d may have a shape in which the first dummy channel structure DCH1 has an expanded length in the dummy channel structure DCHd, unlike the embodiment of FIG. 3b. The first dummy channel structure DCH1 may have a maximum diameter W4 expanded to be adjacent to the extension lines of both ends of the second isolation region MS2a, MS2b in the Y direction between the second auxiliary isolation region MS2b and the second central isolation region MS2a. Thus, in one unit pad region, the first dummy channel structure DCH1 may be disposed to overlap with each of the second dummy channel structures DCH2 along the X direction. In this way, the size and shape of the first dummy channel structure DCH1 may be variously changed within a range in which it is separated from the second dummy channel structures DCH2 on both sides according to the embodiment.

[0054] FIG. 8 is a schematic plan view of a semiconductor device according to an exemplary embodiment.

[0055] 8, unlike the embodiment of FIG 3a, the semiconductor device 100e does not have a single second central isolation region MS2a extended to the right of the lower insulating region GS in the drawing, but has a plurality of second central isolation regions MS2a spaced apart from each other in at least one region along the X direction. This is to further enhance the collapse prevention function of the stacked structure including the interlayer insulating layer 120 during the manufacturing process when the number of gate electrodes 130 of the semiconductor device 100e is increased. Thus, the lower insulating region GSa may also be additionally disposed in the region spaced apart from the second central isolation region MS2a so that the ground selection gate electrodes 130G are separated.

[0056] However, in this embodiment, the first dummy channel structure DCH1 may be disposed only outside the region where the second central isolation region MS2a is separated from the upper part (e.g., the region close to the first region A) of the stacked structure of the gate electrode 130, and may not be disposed outside the region where the second central isolation region MS2a is separated from the lower part (e.g., the region far from the first region A) of the stacked structure. That is, the first dummy channel structure DCH1 may be disposed only on both sides of the lower insulating region GS adjacent to the first region A, and may not be disposed on both sides of the other lower insulating regions GSa. This is in consideration of the arrangement of the contact plug MCP. This will be described in more detail with reference to FIGS. 10a and 10b below.

[0057] FIG. 9 is a schematic plan view of a semiconductor device according to an exemplary embodiment.

[0058] Referring to FIG. 9, the semiconductor device 100f may differ from the embodiment of FIG. 3a in the arrangement of the second dummy channel structure DCH2 of the dummy channel structure DCHf. The second dummy channel structure DCH2 may be arranged along the end of the gate electrode 130. For example, the second dummy channel structure DCH2 may connect the end of the gate electrode 130 and be arranged across the end of the gate electrode 130. Thus, the second dummy channel structure DCH2 may be arithmetically arranged two per unit pad region, not four per unit pad region, but four halves. For example, the first half of the second dummy channel structure DCH2 may be arranged in the first pad region, and the second half may be arranged in the second pad region. In this case, the first dummy channel structure DCH1 may be arranged on the outside of the lower insulating region GS along the Y direction. Thus, in the exemplary embodiment, the first dummy channel structure DCH1 may have an expanded size in the X direction compared to the embodiment of FIG. 3a.

[0059] 10a and 10b are schematic plan views of a semiconductor device according to an exemplary embodiment.

[0060] Referring to FIG. 10a, the semiconductor device 100g may further include contact plugs MCP disposed in the step regions of the gate electrodes 130, i.e., the pad regions. The contact plugs MCP may connect each gate electrode 130 to an upper wiring structure and may be made of a conductive material. As shown in FIG. 10a, the contact plugs MCP may be omitted in a region where the second central isolation region MS2a is separated, i.e., in a region of the pad adjacent to the region where the lower insulating region GS is disposed along the Y direction. For example, the contact plugs MCP may be regularly arranged and may be omitted in the uppermost memory gate electrode 130M around the first dummy channel structure DCH1. As a result, the region where the first dummy channel structure DCH1 is disposed may be secured. Also, in this case, the uppermost memory gate electrode 130M forms a layer between a pair of first isolation regions MS1, and therefore may be electrically connected to the wiring structure via the contact plugs MCP disposed in other pad regions.

[0061] 10b, in the semiconductor device 100h, unlike the embodiment of FIG 10a, a contact plug MCP is disposed in one unit pad region among unit pad regions adjacent in the Y direction to a region in which a lower insulating region GS is disposed, and a contact plug MCP is not disposed in the other unit pad region. Thus, a first dummy channel structure DCH1 may be disposed not in the unit pad region on the one side in which the contact plug MCP is disposed, but only in the unit pad region on the other side in which the contact plug MCP is not disposed.

[0062] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0063] 11, the semiconductor device 100i may include a memory cell region CELL and a peripheral circuit region PERI. The memory cell region CELL may be disposed at an upper end of the peripheral circuit region PERI. In an exemplary embodiment, the memory cell region CELL may be disposed at a lower end of the peripheral circuit region PERI.

[0064] The memory cell region CELL may include a substrate 101, a substrate insulating layer 110, a gate electrode 130, a channel structure CH, a dummy channel structure DCH, first and second isolation regions MS1, MS2a, MS2b, and a lower isolation region GS, as described above with reference to Figures 3a to 4c. The memory cell region CELL may have a structure according to various embodiments as described above with reference to Figures 5a to 10b.

[0065] The peripheral circuit region PERI may include a base substrate 201 , circuit elements 220 disposed on the base substrate 201 , circuit contact plugs 270 , and wiring lines 280 .

[0066] The base substrate 201 may have a top surface extending in an X direction and a Y direction. An active region may be defined in the base substrate 201 by forming another element isolation layer. A source / drain region 205 containing impurities may be disposed in a portion of the active region. The base substrate 201 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor.

[0067] The circuit elements 220 may include planar transistors. Each of the circuit elements 220 may include a circuit gate insulating layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 may be disposed within the base substrate 201 on either side of the circuit gate electrode 225.

[0068] A peripheral region insulating layer 290 may be disposed on the circuit element 220 on the base substrate 201. A circuit contact plug 270 may be connected to the source / drain region 205 through the peripheral region insulating layer 290. An electrical signal may be applied to the circuit element 220 through the circuit contact plug 270. In a region not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. A wiring line 280 may be connected to the circuit contact plug 270 and may be disposed in a plurality of layers. In a region not shown, the gate electrode 130 of the memory cell region CELL may be connected to the circuit element 220 of the peripheral circuit region PERI through another through region that passes through the peripheral circuit region PERI and a through via in the through region.

[0069] In the semiconductor device 100i, the peripheral circuit region PERI may be fabricated first, and then the substrate 101 for the memory cell region CELL may be formed thereon to fabricate the memory cell region CELL. The substrate 101 may have the same size as the base substrate 201 or may be smaller than the base substrate 201.

[0070] 12a to 16b are schematic plan views and cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary embodiment, in which the cross-sectional views show a region corresponding to FIG. 4a.

[0071] 12a and 12b, in a second region B, a substrate insulating layer 110 may be formed in the substrate 101. As shown in FIG.

[0072] First, a portion of the substrate 101 may be anisotropically etched to form a trench region. The trench region may have a narrower width toward the bottom due to an aspect ratio. For example, the width of each trench region may be narrower toward the bottom surface of the substrate 101 and may be wider toward the top surface of the substrate 101. Next, to form the substrate insulating layer 110, the trench region may be filled with an insulating material and then a planarization process may be performed along the top surface of the substrate 101. The planarization process may allow the top surface of the substrate insulating layer 110 to be coplanar with the top surface of the substrate 101.

[0073] The substrate insulating layer 110 may be formed in a subsequent process in the second region B of the substrate 101 excluding the regions where the first and second isolation regions MS1, MS2a, and MS2b are to be located. Depending on the embodiment, when an isolation layer defining an active region of the substrate 101 is formed in a region not shown, the substrate insulating layer 110 may be formed in the same process step as the isolation layer.

[0074] Referring to Figures 13a and 13b, a sacrificial layer 180 and an interlayer insulating layer 120 are alternately stacked on a substrate 101, and a lower isolation region GS and an upper isolation region SS can be formed by removing portions of the sacrificial layer 180 and the interlayer insulating layer 120 so that the sacrificial layer 180 is extended to different lengths in the X direction.

[0075] The sacrificial layer 180 may be a layer that becomes the gate electrode 130 through a subsequent process. The sacrificial layer 180 may be formed of a material that can be etched with etching selectivity to the interlayer insulating layer 120. For example, the interlayer insulating layer 120 may be made of at least one of silicon oxide and silicon nitride, and the sacrificial layer 180 may be made of a material different from the interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide, and silicon nitride. Depending on the embodiment, the thickness of the interlayer insulating layer 120 may not be the same. For example, the lowermost interlayer insulating layer 120 may be formed relatively thin, and the uppermost interlayer insulating layer 120 may be formed relatively thick. The thicknesses of the interlayer insulating layer 120 and the sacrificial layer 180 and the number of layers that constitute them may be variously changed from those shown in the drawings.

[0076] Photolithography and etching processes may be repeatedly performed on the sacrificial layer 180 so that the upper sacrificial layer 180 in the second region B is extended shorter than the lower sacrificial layer 180. This allows the sacrificial layer 180 to have a stepped shape. Depending on the embodiment, the material constituting the sacrificial layer 180 may be further deposited in the region where the sacrificial layer 180 is extended longer than the upper sacrificial layer 180 and exposed, so that the sacrificial layer 180 may be formed to have a relatively large thickness at the end portion.

[0077] The lower isolation region GS may be formed to include the lower insulating layer 170 by performing a patterning process and a deposition process of an insulating material after forming the lowermost sacrificial layer 180. The lower insulating layer 170 may be made of a material having an etching selectivity with respect to the sacrificial layer 180. According to an exemplary embodiment, the lower isolation region GS may be formed as a part of the material of the interlayer insulating layer 120 by forming the interlayer insulating layer 120 thereon after removing the sacrificial layer 180 in the region. In this case, if a separate planarization process is not performed on the upper interlayer insulating layer 120, the upper interlayer insulating layer 120 may have a depressed portion DP as shown in FIG. 13b. If a separate planarization process is performed on the upper interlayer insulating layer 120, the depressed portion DP is not formed.

[0078] The string isolation region SS may extend in the X direction from the first region A to a portion of the second region B. A region where the string isolation region SS is to be formed may be exposed using another mask layer, and a predetermined number of the sacrificial layers 180 and the interlayer insulating layer 120 may be removed from the top. The string isolation region SS may extend below a region where the string selection gate electrode 130S is to be formed, as shown in FIG. 4b. An insulating material may be deposited in the region where the sacrificial layer 180 and the interlayer insulating layer 120 are removed, to form the upper insulating layer 103. The upper insulating layer 103 may be made of a material having an etching selectivity with respect to the sacrificial layer 180, for example, the same material as the interlayer insulating layer 120.

[0079] Next, a cell region insulating layer 190 may be formed to cover the upper portion of the stacked structure of the sacrificial layer 180 and the interlayer insulating layer 120 .

[0080] 14a and 14b, a channel structure CH and a dummy channel structure DCH penetrating a stacked structure of a sacrificial layer 180 and an interlayer insulating layer 120 may be formed.

[0081] The channel structure CH and the dummy channel structure DCH may be formed by anisotropically etching the sacrificial layer 180 and the interlayer insulating layer 120, and may be formed in the form of a hole. Depending on the height of the stacked structure, the sidewalls of the channel structure CH and the dummy channel structure DCH may not be perpendicular to the upper surface of the substrate 101. The channel structure CH may be formed in the first region A of the substrate 101, and the dummy channel structure DCH may be formed in the second region B. The dummy channel structure DCH may be formed to penetrate at least a portion of the substrate insulating layer 110. In an exemplary embodiment, the channel structure CH and the dummy channel structure DCH may be formed to recess a portion of the substrate 101. However, depending on the embodiment, the dummy channel structure DCH may not completely penetrate the substrate insulating layer 110, but may extend only into the substrate insulating layer 110, and may not contact the substrate 101.

[0082] Next, the epitaxial layer 105, at least a portion of the gate dielectric layer 145, the channel layer 140, the channel insulating layer 150, and the channel pad 155 may be formed in the channel structure CH and the dummy channel structure DCH. If a dummy channel structure is further disposed in the first region A together with the channel structure CH in addition to the dummy channel structure DCH, the dummy channel structure may also be formed together with the channel structure CH at this stage.

[0083] The epitaxial layer 105 may be formed using a selective epitaxial growth (SEG) process. The epitaxial layer 105 may be composed of a single layer or multiple layers. The epitaxial layer 105 may include polycrystalline silicon, single crystal silicon, polycrystalline germanium, or single crystal germanium, which may be doped or undoped with impurities. The epitaxial layer 105 in the dummy channel structure DCH may be formed such that an upper end is located in the substrate insulating layer 110 and at least a portion of a side surface is surrounded by the substrate insulating layer 110. Thus, the epitaxial layer 105 in the dummy channel structure DCH may be located apart from the sacrificial layer 180.

[0084] The gate dielectric layer 145 may be formed to have a uniform thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this step, the gate dielectric layer 145 may be formed in whole or in part, and may be formed to extend vertically to the substrate 101 along the channel structure CH and the dummy channel structure DCH. The channel layer 140 may be formed on the gate dielectric layer 145 in the channel structure CH and the dummy channel structure DCH. The channel insulating layer 150 is formed to fill the channel structure CH and the dummy channel structure DCH and may be made of an insulating material. However, depending on the embodiment, the gap between the channel layer 140 may be filled with a conductive material instead of the channel insulating layer 150. The channel pad 155 may be made of a conductive material, for example, polycrystalline silicon.

[0085] 15a and 15b, an opening OP penetrating the stacked structure of the sacrificial layer 180 and the interlayer insulating layer 120 may be formed, and the sacrificial layer 180 may be removed through the opening OP.

[0086] First, the opening OP may be formed by forming a mask layer using a photolithography process and anisotropically etching the laminated structure. Before forming the opening OP, a cell region insulating layer 190 may be further formed on the channel structure CH and the dummy channel structure DCH to protect the lower structure. The opening OP may be formed in the form of a trench at a position corresponding to the first and second isolation regions MS1, MS2a, and MS2b. Thus, the opening OP is formed to extend along the X direction, and a part of the opening OP may extend along the entire first and second regions A and B, and a part of the opening OP may extend only to the second region B. According to this step, the substrate 101 may be exposed at the bottom of the opening OP.

[0087] Next, the sacrificial layer 180 may be selectively removed with respect to the interlayer insulating layer 120, for example, by wet etching. Accordingly, a plurality of side openings may be formed between the interlayer insulating layers 120, and a portion of a sidewall of the gate dielectric layer 145 of the channel structure CH and a side of the lower insulating layer 170 may be exposed through the side openings. In this step, after the sacrificial layer 180 is removed, the stacked structure of the interlayer insulating layer 120 may be degraded in stability, but the stacked structure may be more stably supported by the region where the openings OP are separated and the dummy channel structure DCH1. In particular, the first dummy channel structure DCH1 may be disposed outside the lower isolation region GS with a relatively large size, and thus the support for the stacked structure of the interlayer insulating layer 120 may be strengthened.

[0088] 16a and 16b, the gate electrode 130 may be formed by filling the area from which the sacrificial layer 180 has been removed with a conductive material.

[0089] The gate electrode 130 may include a metal, polysilicon, or metal silicide material. The openings OP may provide a transfer path of a material for forming the gate electrode 130. The gate electrodes 130 may be connected between the openings OP spaced apart from each other in a straight line in the X direction without being separated, to form a gate connection portion. After the gate electrode 130 is formed, the material forming the gate electrode 130 deposited in the openings OP may be removed through an additional process.

[0090] Next, referring jointly to Figures 3a and 4a, an isolation layer 107 may be formed in the opening OP.

[0091] The separation layer 107 may include an insulating material, and may further include a conductive material in addition to the insulating material depending on the embodiment. In this way, the first and second separation regions MS1, MS2a, and MS2b may be formed, and the first and second separation regions MS1, MS2a, and MS2b may be formed in the same process step and have the same structure as each other.

[0092] Thereafter, upper wiring structures such as contact plugs and bit lines may be further formed on the channel structure CH.

[0093] Although the embodiments of the present invention have been described in detail above, it will be apparent to those having ordinary skill in the art that the scope of the present invention is not limited thereto, and that various modifications and variations are possible within the scope that does not deviate from the technical idea of ​​the present invention described in the claims. [Explanation of symbols]

[0094] CH Channel structure DCH Dummy Channel Structure DP Depression GS lower separation area MC Contact Plug MS1 1st separation area MS2a, MS2b 2nd separation area SS upper separation area 101 Substrate 103 Upper insulating layer 105 Epitaxial layer 107 Separation layer 110 Substrate insulation layer 120 Interlayer insulation layer 130 Gate electrode 140 Channel Layer 145 Gate Dielectric Layer 150 Channel Insulation Layer 155 Channel Pad 170 Lower insulation layer 180 Sacrificial Layer 190 Cell area insulating layer

Claims

1. a substrate having first and second regions; gate electrodes including at least one ground selection gate electrode, a memory cell gate electrode, and at least one string selection gate electrode, which are stacked in the first region and spaced apart from each other along a first direction perpendicular to an upper surface of the substrate, and which extend in the second region along a second direction perpendicular to the first direction and have different lengths, stacked in sequence from above the substrate; first isolation regions extending in the second direction through the gate electrode in the first and second regions and spaced apart from each other along a third direction perpendicular to the first and second directions; second isolation regions extending in the second direction between the first isolation regions and penetrating the gate electrode, the second isolation regions being spaced apart from each other along the second direction in the second region; a lower isolation region penetrating the at least one ground selection gate electrode between the second isolation regions and isolating the at least one ground selection gate electrode together with the second isolation region; a substrate insulating layer disposed within the substrate in the second region between the first isolation region and the second isolation region; a channel structure extending vertically onto the substrate through the gate electrode in the first region; a first dummy channel structure extending vertically onto the substrate, the first dummy channel structure penetrating the gate electrode and the substrate insulating layer at an outer side of the lower isolation region in the third direction; and second dummy channel structures arranged in a matrix in the second region; the first dummy channel structures are disposed between the second dummy channel structures adjacent to each other along the second direction, The second dummy channel structure has a different size or shape than the first dummy channel structure.

2. The semiconductor device according to claim 1 , wherein the first dummy channel structure has a first width along the second direction and a second width along the third direction that is larger than the first width.

3. The semiconductor device of claim 2 , wherein the channel structure has a first maximum width, the first maximum width being smaller than the second width of the first dummy channel structure.

4. 4. The semiconductor device according to claim 3, wherein the first maximum width is in a range of 50 nm to 150 nm, and the second width is in a range of 120 nm to 220 nm.

5. The semiconductor device according to claim 1 , wherein the substrate insulating layer is not disposed in a region where the second isolation regions are separated from each other along the second direction.

6. The semiconductor device according to claim 1 , wherein the second dummy channel structures are arranged in the second region to penetrate the gate electrode and the substrate insulating layer and to form a matrix.

7. The semiconductor device according to claim 6 , wherein the first dummy channel structure has an elongated, rectangular or elliptical shape, and the second dummy channel structure has a circular or elliptical shape.

8. The semiconductor device according to claim 6 , wherein the first dummy channel structure is arranged so as to be surrounded by four of the second dummy channel structures.

9. The semiconductor device according to claim 6 , wherein the second dummy channel structure is disposed along an edge of the gate electrode.

10. 2. The semiconductor device of claim 1, further comprising third isolation regions extending in the second direction, penetrating the gate electrode between the first isolation region and the second isolation region, and spaced apart from each other in the second direction in the second region with an isolation region therebetween.

11. the substrate insulating layer is disposed on the substrate under a first isolation region that is the closest to the first region among the isolation regions; The semiconductor device of claim 10 , further comprising a third dummy channel structure extending vertically onto the substrate in the first isolation region through the gate electrode and the substrate insulating layer.

12. The semiconductor device of claim 11 , wherein the third dummy channel structure has a smaller maximum diameter than the first dummy channel structure.

13. The semiconductor device according to claim 11 , wherein the substrate insulating layer is not disposed in any of the isolation regions other than the first isolation region.

14. the gate electrode extends in the second direction longer than the lower gate electrode to provide a pad region; 2. The semiconductor device of claim 1, further comprising a contact plug connected to the gate electrode in the pad region.

15. 15. The semiconductor device of claim 14, wherein the first dummy channel structure is disposed on a first side of the lower isolation region along the third direction, and one of the contact plugs is disposed on a second side of the lower isolation region along the third direction.

16. a substrate having a conductive region and an insulating region; a gate electrode including sub-gate electrodes stacked apart from each other along a first direction perpendicular to an upper surface of the substrate and extending along a second direction perpendicular to the first direction, and a gate connection part connecting the sub-gate electrodes arranged at the same height to each other; a channel structure extending through the gate electrode over a conductive region of the substrate; a first dummy channel structure extending through the gate electrode in the insulating region of the substrate and disposed adjacent to at least one side of the gate connector in a third direction perpendicular to the first and second directions; along the first direction, the channel structure has a first height, and the first dummy channel structure has a second height greater than the first height.

17. a substrate having first and second regions; gate electrodes stacked in the first region and spaced apart from each other along a first direction perpendicular to an upper surface of the substrate and extending in the second region to different lengths along a second direction perpendicular to the first direction to provide pad regions; through-hole isolation regions extending in the second direction through the gate electrode in the first and second regions and spaced apart from each other along the second direction in the second region; a lower isolation region penetrating at least one of the gate electrodes including the lowermost gate electrode between the penetrating isolation regions; a substrate insulating layer disposed within a portion of the substrate in the second region; a channel structure extending vertically onto the substrate through the gate electrode in the first region; a first dummy channel structure extending vertically above the substrate in the second region through the gate electrode and at least a portion of the substrate insulating layer and disposed adjacent to the lower isolation region around the lower isolation region, and a second dummy channel structure disposed to form a matrix in the pad region of the gate electrode; the channel structure and the dummy channel structure each include an epitaxial layer disposed below the channel structure, The epitaxial layer of the channel structure has a first thickness, and the epitaxial layer of the dummy channel structure has a second thickness that is thinner than the first thickness.

18. The semiconductor device of claim 17 , wherein the first dummy channel structures are disposed on both sides of the lower isolation region along a third direction perpendicular to the first and second directions.

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