Transmitter circuit, electronic control unit, and vehicle

Abstract

This transmission circuit comprises a first terminal configured such that a first voltage is applied, a second terminal, a third terminal, and a fourth terminal configured such that a second voltage lower than the first voltage is applied. The transmission circuit furthermore includes a first variable resistor part provided between the first and second terminals, a variable resistor part provided between the third and fourth terminals, and a control part configured so as to control the resistance values of the first and second variable resistor parts. Each of the first and the second variable resistor parts is a circuit in which a plurality of resistor and switch series circuits are connected in parallel. The first variable resistor part is provided with a first charge adjustment part configured such that a charge to at least some of the plurality of switches provided in the first variable resistor part can be absorbed and discharged. The second variable resistor part is provided with a second charge adjustment part configured such that a charge to at least some of the plurality of switches provided in the second variable resistor part can be absorbed and discharged.

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a transmission circuit that transmits a differential signal, and an electronic control unit and a vehicle that include the transmission circuit. [Background technology]

[0002] Vehicles such as automobiles are equipped with a large number of electronic control units (ECUs). For example, CAN (Controller Area Network) communication is used for communication between the large number of ECUs (see, for example, Patent Document 1).

[0003] The transmit signal and receive signal in CAN communication are each a differential signal. The differential signal formed by the first signal and the second signal can be decomposed into a common mode component and a differential mode component.

[0004] The common mode component is the average of the first and second signals, and the differential mode component is the difference between the first and second signals. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 61-195453 Summary of the Invention [Problem to be solved by the invention]

[0006] When the symmetry between the first and second signals constituting a differential signal is lost, noise occurs in the common mode component. The noise occurring in the common mode component (common mode noise) deteriorates EMC (Electromagnetic Compatibility) characteristics. Therefore, suppressing common mode noise is an issue in transceiver circuits that include a transmitting circuit that transmits differential signals and a receiving circuit that receives differential signals. [Means for solving the problem]

[0007] The transmission circuit disclosed in this specification comprises a first terminal configured to receive a first voltage, a second terminal, a third terminal, a fourth terminal configured to receive a second voltage lower than the first voltage, a first variable resistance unit provided between the first terminal and the second terminal and configured to vary a resistance value, a second variable resistance unit provided between the third terminal and the fourth terminal and configured to vary a resistance value, and a control unit configured to control the resistance values ​​of the first variable resistance unit and the second variable resistance unit based on transmission data, wherein the first variable resistance unit and the second variable resistance unit are each a circuit in which a plurality of series circuits of a resistor and a switch are connected in parallel, the first variable resistance unit comprises a first charge adjustment unit configured to be capable of absorbing and releasing charge for at least some of the multiple switches provided in the first variable resistance unit, and the second variable resistance unit comprises a second charge adjustment unit configured to be capable of absorbing and releasing charge for at least some of the multiple switches provided in the second variable resistance unit.

[0008] The electronic control unit disclosed in this specification is configured to include the transmission circuit configured as described above, and a computer that sends the transmission data to the transmission circuit.

[0009] The vehicle disclosed in this specification is configured to include a communication bus and a plurality of electronic control units of the above configuration connected to the communication bus. Effect of the Invention

[0010] According to the invention disclosed in this specification, it is possible to provide a transmission circuit that suppresses common mode noise. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is an external view of a vehicle according to an embodiment. [Diagram 2]FIG. 2 is a schematic diagram of a CAN communication system. [Diagram 3] FIG. 3 is a diagram illustrating an example of the configuration of the ECU. [Figure 4] FIG. 4 is a diagram illustrating an example of a configuration of a transceiver circuit. [Diagram 5] FIG. 5 is a time chart showing a differential signal. [Figure 6] FIG. 6 is a diagram showing a first configuration example of the first variable resistance section. [Figure 7] FIG. 7 is a diagram showing a first configuration example of the second variable resistance section. [Figure 8] FIG. 8 is a diagram showing a second configuration example of the first variable resistance section. [Figure 9] FIG. 9 is a diagram showing a second configuration example of the second variable resistance section. [Figure 10] FIG. 10 is a diagram illustrating a third configuration example of the first variable resistance section. [Figure 11] FIG. 11 is a diagram showing a third configuration example of the second variable resistance section. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In this specification, a MOS transistor refers to a transistor whose gate structure is composed of at least three layers: "a layer made of a conductor or a semiconductor such as polysilicon with a low resistance value," "an insulating layer," and "a P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOS transistor is not limited to a three-layer structure of a metal, an oxide, and a semiconductor.

[0013] In this specification, a constant current means a current that is constant under ideal conditions, but in reality, it is a current that may fluctuate slightly due to temperature changes and the like.

[0014] In this specification, a constant voltage means a voltage that is constant under ideal conditions, but in reality, it is a voltage that may fluctuate slightly due to temperature changes and the like.

[0015] <Vehicle and CAN communication system> 1 is an external view of a vehicle X according to an embodiment. The vehicle X includes a plurality of ECUs 1 (not shown in FIG. 1). The vehicle X also includes a battery (not shown).

[0016] Fig. 2 is a schematic diagram of a CAN communication system provided in a vehicle X. The CAN communication system shown in Fig. 2 includes a plurality of ECUs 1, a first bus line BL1, a second bus line BL2, and resistors R101 and R102.

[0017] One end of a resistor R101 is connected to one end of a first bus line BL1, and one end of a resistor R102 is connected to the other end of the first bus line BL1. The other end of the resistor R101 is connected to one end of a second bus line BL2, and the other end of the resistor R102 is connected to the other end of the second bus line BL2. Each of the multiple ECUs 1 is connected to the first bus line BL1 and the second bus line BL2. A voltage VBAT output from a battery is supplied to each of the multiple ECUs 1. Each of the multiple ECUs 1 is connected to a ground potential. The multiple ECUs 1 use the voltage VBAT as a power supply voltage.

[0018] <ecu> 3 is a diagram showing an example of the configuration of the ECU 1. The ECU 1 of the example configuration shown in FIG.

[0019] A voltage VBAT is supplied to the terminal T1. The anode of the diode 5 is connected to the terminal T1. The cathode of the diode 5 is connected to the input terminal of the power supply circuit 2 and the capacitor 6.

[0020] The output terminal of the power supply circuit 2 is connected to a power supply voltage input terminal of the microcomputer 3, a terminal VCC of the transceiver circuit 4, and one end of a capacitor 7. A constant voltage is output from the output terminal of the power supply circuit 2.

[0021] The microcomputer 3 sends transmission data to a terminal TXD of the transceiver circuit 4, and receives reception data from a terminal RXD of the transceiver circuit 4. The transmission data and reception data are each a single signal.

[0022] The terminal CANH of the transceiver circuit 4 is connected to the terminal T2, and the terminal CANL of the transceiver circuit 4 is connected to the terminal T3. The terminal T2 is connected to the first bus line BL1 shown in FIG. 2, and the terminal T3 is connected to the second bus line BL2 shown in FIG.

[0023] The transceiver circuit 4 converts transmission data into a differential signal (CAN signal) composed of a first signal SCANH (see FIG. 5 described later) and a second signal SCANL (see FIG. 5 described later) and outputs the converted data. The transceiver circuit 4 also converts the differential signal (CAN signal) composed of the first signal and the second signal into reception data and outputs the reception data. That is, the transceiver circuit 4 includes a transmission circuit that transmits the differential signal and a reception circuit that receives the differential signal. The first signal is transmitted by the first bus line BL1, and the second signal is transmitted by the second bus line BL2.

[0024] The ground terminal of the power supply circuit 2 is connected to the other end of the capacitor 6, the terminal T4, the terminal GND of the transceiver circuit 4, the ground terminal of the microcomputer 3, and the other end of the capacitor 7. The terminal T4 is connected to the ground potential.

[0025] <Transceiver circuit> Fig. 4 is a diagram showing an example of the configuration of the transceiver circuit 4. The transceiver circuit 4 of the example configuration shown in Fig. 4 includes a terminal VCC, a terminal GND, a terminal TXD, a terminal RXD, a terminal CANH, and a terminal CANL.

[0026] The transceiver circuit 4 of the configuration example shown in FIG. 4 further includes a first variable resistance unit VR1, a second variable resistance unit VR2, a P-channel MOS transistor (PMOS transistor) Q1 which is a first current limiting unit, an N-channel MOS transistor (NMOS transistor) Q7 which is a second current limiting unit, and a control unit CNT1.

[0027] The transceiver circuit 4 of the configuration example shown in FIG. 4 further includes a pull-up resistor R1, a pull-down resistor R2, diodes D1 and D3 for preventing reverse current, and a PMOS transistor Q2 and an NMOS transistor Q6 which are clamp elements.

[0028] The pull-up resistor R1 stabilizes the potential of the node N1 (the connection point between the first variable resistance section VR1 and the diode D1) when the first variable resistance section VR1 is in a high impedance state. The pull-down resistor R2 stabilizes the potential of the node N2 (the connection point between the second variable resistance section VR2 and the NMOS transistor Q6) when the second variable resistance section VR2 is in a high impedance state.

[0029] The PMOS transistor Q2 and the NMOS transistor Q6 are double-diffused MOS transistors with a high breakdown voltage. The PMOS transistor Q2 clamps the source potential of the PMOS transistor Q2, and the NMOS transistor Q6 clamps the source potential of the NMOS transistor Q6.

[0030] The transceiver circuit 4 of the configuration example shown in FIG. 4 includes a receiver circuit RCV1, a diode D2, a PMOS transistor Q3, an NMOS transistor Q4, an NMOS transistor Q5, and a Zener diode ZD1.

[0031] The terminal VCC is connected to the source of the PMOS transistor Q1 and one end of the pull-up resistor R1. A bias voltage Vbp, which is a constant voltage, is supplied to the gate of the PMOS transistor Q1. Therefore, the PMOS transistor Q1 serves as a constant current source. If the terminal CANH is short-circuited to a voltage equal to or lower than the voltage applied to the terminal GND, the PMOS transistor Q1 limits the current flowing from the terminal VCC to the terminal CANH. This makes it possible to suppress overcurrent flowing from the terminal VCC to the terminal CANH.

[0032] The drain of the PMOS transistor Q1 is connected to one end of a first variable resistance section VR1, the other end of which is connected to the other end of the pull-up resistor R1 and the anode of the diode D1.

[0033] The cathode of the diode D1 is connected to the source of a PMOS transistor Q2, the drain of which is connected to the terminal CANH and to a first input terminal of the receiver circuit RCV1.

[0034] A gate drive signal generating circuit composed of a PMOS transistor Q3, an NMOS transistor Q4, an NMOS transistor Q5, a diode D2, and a Zener diode ZD1 generates a gate drive signal for the PMOS transistor Q2. An internal voltage VREG1 generated inside the transceiver circuit 4 is applied to the source of the PMOS transistor Q3. The drain of the PMOS transistor Q3 is connected to the anode of the diode D2. The cathode of the diode D2 is connected to the anode of the Zener diode ZD1 and the drain of the NMOS transistor Q4. The cathode of the Zener diode ZD1 is connected to the source of the PMOS transistor Q1. An enable signal EN is supplied to each gate of the PMOS transistor Q3 and the NMOS transistor Q4. When the enable signal EN is at a high level, the transceiver circuit 4 is enabled. On the other hand, when the enable signal EN is at a low level, the transceiver circuit 4 is disabled. The source of the NMOS transistor Q4 is connected to the drain of the NMOS transistor Q5. The source of the NMOS transistor Q5 is connected to the ground potential. A bias voltage Vbn1, which is a constant voltage, is supplied to the gate of the NMOS transistor Q5.

[0035] The anode of the diode D3 is connected to the terminal CANL and the second input terminal of the receiver circuit RCV1. The cathode of the diode D3 is connected to the drain of the NMOS transistor Q6. The source of the NMOS transistor Q6 is connected to one end of the second variable resistance section VR2 and one end of the pull-down resistor R2. An enable signal EN is supplied to the gate of the NMOS transistor Q6.

[0036] The other end of the second variable resistor VR2 is connected to the drain of an NMOS transistor Q7. The source of the NMOS transistor Q7 is connected to the other end of the pull-down resistor R2 and the terminal GND. A bias voltage Vb, which is a constant voltage, is applied to the gate of the NMOS transistor Q7. n 2 is supplied to terminal VCC. Therefore, NMOS transistor Q7 functions as a constant current source. If terminal CANL is shorted to a voltage equal to or higher than the voltage supplied to terminal VCC, NMOS transistor Q7 limits the current flowing from terminal CANL to terminal GND. This makes it possible to suppress overcurrent flowing from terminal CANL to terminal GND.

[0037] The control unit CNT1 receives transmission data supplied to a terminal TXD, and controls the resistance values ​​of the first variable resistance unit VR1 and the second variable resistance unit VR2 based on the transmission data.

[0038] The above-mentioned first signal SCANH is a binary signal of V1 and (V1+V2) as shown in Fig. 5, and the above-mentioned second signal SCANL is a binary signal of V1 and (V1-V2) as shown in Fig. 5. A differential signal (CAN signal) constituted by the first signal SCANH and the second signal SCANL can be decomposed into a common mode component COM which is the average of the first signal SCANH and the second signal SCANL, and a differential mode component DIFF which is the difference between the first signal SCANH and the second signal SCANL.

[0039] When a time difference (skew) occurs between the first signal SCANH and the second signal SCANL, noise occurs in the common mode component COM. However, by making the first signal SCANH and the second signal SCANL signals with waveforms that have small high-frequency components, it is possible to suppress the common mode noise caused by the skew.

[0040] 4, the resistance value of the first variable resistance unit VR1 is gradually decreased in a first transition period in which the voltage value of the first signal SCANH transitions from V1 to (V1+V2) and in a second transition period in which the voltage value of the second signal SCANL transitions from V1 to (V1-V2), and the resistance value of the first variable resistance unit VR1 is gradually increased in a third transition period in which the voltage value of the first signal SCANH transitions from (V1+V2) to V1 and in a fourth transition period in which the voltage value of the second signal SCANL transitions from (V1-V2) to V1, making the first signal SCANH and the second signal SCANL signals with waveforms with small high-frequency components. In addition, in periods other than the above-mentioned transition periods, the control unit CNT1 sets the resistance value of the first variable resistance unit VR1 to a maximum value.

[0041] Similarly, in the transceiver circuit 4 of the configuration example shown in Fig. 4, the resistance value of the second variable resistance unit VR2 is gradually decreased in a first transition period in which the voltage value of the first signal SCANH transitions from V1 to (V1+V2) and in a second transition period in which the voltage value of the second signal SCANL transitions from V1 to (V1-V2), and the resistance value of the second variable resistance unit VR2 is gradually increased in a third transition period in which the voltage value of the first signal SCANH transitions from (V1+V2) to V1 and in a fourth transition period in which the voltage value of the second signal SCANL transitions from (V1-V2) to V1, making the first signal SCANH and the second signal SCANL signals with waveforms with small high-frequency components. Note that, except for the above-mentioned transition periods, the control unit CNT1 sets the resistance value of the second variable resistance unit VR2 to a maximum value.

[0042] 4 further includes resistors R3 and R4, diodes D3 and D4, PMOS transistors Q8 and Q9, NMOS transistors Q10 to Q12, and a Zener diode ZD2. The dummy circuit formed by these components improves the symmetry between the first signal SCANH and the second signal SCANL.

[0043] One end of the resistor R3 is connected to the terminal VCC. The other end of the resistor R3 is connected to the anode of the diode D3. The cathode of the diode D3 is connected to the source of the PMOS transistor Q8. The drain of the PMOS transistor Q8 is connected to the terminal CANL.

[0044] A gate drive signal generating circuit composed of a PMOS transistor Q9, a diode D4, an NMOS transistor Q10, an NMOS transistor Q11, and a Zener diode ZD2 generates a gate drive signal for the PMOS transistor Q8. An internal voltage VREG1 generated inside the transceiver circuit 4 is applied to the source of the PMOS transistor Q9. A drain of the PMOS transistor Q9 is connected to the anode of the diode D4. A cathode of the diode D4 is connected to the anode of the Zener diode ZD2 and the drain of the NMOS transistor Q10. A cathode of the Zener diode ZD2 is connected to the source of the PMOS transistor Q8. An enable signal EN is supplied to each gate of the PMOS transistor Q9 and the NMOS transistor Q10. A source of the NMOS transistor Q10 is connected to the drain of the NMOS transistor Q11. A source of the NMOS transistor Q11 is connected to the ground potential. A bias voltage Vbn1, which is a constant voltage, is supplied to the gate of the NMOS transistor Q11.

[0045] One end of the resistor R4 is connected to the terminal CANH. The other end of the resistor R4 is connected to the drain of the NMOS transistor Q12. The source of the NMOS transistor Q12 is connected to the terminal GND. An enable signal EN is supplied to the gate of the NMOS transistor Q12.

[0046] The improvement in symmetry between the first signal SCANH and the second signal SCANL by the above-mentioned dummy circuit is not necessarily sufficient. Therefore, in this embodiment, the symmetry between the first signal SCANH and the second signal SCANL is improved by improving the configuration of the first variable resistance unit VR1 and the second variable resistance unit VR2.

[0047] Hereinafter, a configuration example of the first variable resistance unit VR1 and the second variable resistance unit VR2 that can improve the symmetry between the first signal SCANH and the second signal SCANL will be described.

[0048] Fig. 6 is a diagram showing a first configuration example of the first variable resistance unit VR1, and Fig. 7 is a diagram showing a first configuration example of the second variable resistance unit VR2. The first variable resistance unit VR1 according to the first configuration example shown in Fig. 6 and the second variable resistance unit VR2 according to the first configuration example shown in Fig. 7 are used in a pair.

[0049] The first variable resistance unit VR1 according to the first configuration example shown in FIG. 6 includes PMOS transistors M1-M60, which are switches, and resistors Z1-Z60, and is a circuit in which 60 series circuits of resistors and switches are connected in parallel. The PMOS transistors M1-M60 are controlled to be turned on / off by control signals S1-S60 output from the control unit CNT1. The number of the series circuits may be any number other than 60. In the configuration example shown in FIG. 6, the resistance value of the first variable resistance unit VR1 is determined by the combined resistance of the resistors Z1-Z60, so that the resistance value of the first variable resistance unit VR1 can be controlled with high precision.

[0050] The first variable resistance section VR1 according to the first configuration example shown in FIG. 6 further includes dummy switches DSW1 to DSW60 and AND gates A1 to A60. The dummy switches DSW1 to DSW60 are charge adjustment sections capable of absorbing and discharging charges from the PMOS transistors M1 to M60, respectively. The dummy switch DSW1 is a PMOS transistor whose source and drain are shorted and connected to the drain of the PMOS transistor M1. When the PMOS transistor M1 is on, the dummy switch DSW1 can be turned on. The AND gate A1 supplies the logical product of the control signal S1 and the adjustment signal ADJ1 to the gate of the dummy switch DSW1. Therefore, when the adjustment signal ADJ1 is at a high level, the dummy switch DSW1 can absorb and discharge charges from the PMOS transistor M1. On the other hand, when the adjustment signal ADJ1 is at a low level, the dummy switch DSW1 cannot absorb and discharge charges from the PMOS transistor M1.

[0051] The dummy switches DSW2 to DSW60 and the AND gates A2 to A60 are similar to the dummy switch DSW1 and the AND gate A1, and therefore a detailed description thereof will be omitted.

[0052] The second variable resistance unit VR2 according to the first configuration example shown in FIG. 7 includes NMOS transistors M101-M160, which are switches, and resistors Z101-Z160, and is a circuit in which 60 series circuits of resistors and switches are connected in parallel. The NMOS transistors M101-M160 are controlled to be turned on / off by control signals S101-S160 output from the control unit CNT1. The number of the series circuits may be any number other than 60. In the configuration example shown in FIG. 7, the resistance value of the second variable resistance unit VR2 is determined by the combined resistance of the resistors Z101-Z160, so that the resistance value of the second variable resistance unit VR2 can be controlled with high precision.

[0053] The first configuration example shown in FIG. 2 Variable resistor VR 2 further includes dummy switches DSW101-DSW160, AND gates A101-A160, and dummy capacitances DC101-DC160. The dummy switches DSW101-DSW160 are charge adjustment units capable of absorbing and discharging charges from the NMOS transistors M101-M160, respectively. The dummy switch DSW101 is an NMOS transistor whose source and drain are shorted and connected to the drain of the NMOS transistor M101. When the NMOS transistor M101 is on, the dummy switch DSW101 can be turned on. The AND gate A101 supplies the logical product of the control signal S101 and the adjustment signal ADJ101 to the gate of the dummy switch DSW1. Therefore, when the adjustment signal ADJ101 is at a high level, the dummy switch DSW101 can absorb and discharge charges from the NMOS transistor M101. On the other hand, when the adjustment signal ADJ101 is at a low level, the dummy switch DSW101 cannot absorb or release charges from the NMOS transistor M101.

[0054] Since the dummy switches DSW102 to DSW160 and the AND gates A102 to A160 are similar to the dummy switch DSW101 and the AND gate A101, detailed description thereof will be omitted.

[0055] The dummy capacitors DC101 to DC160 are capacitors provided between the gates and sources of the NMOS transistors M101 to M160, respectively. The dummy capacitors DC101 to DC160 are NMOS transistors whose source and drain are short-circuited and connected to the sources of the NMOS transistors M101 to M160, respectively. The gates of the dummy capacitors DC101 to DC160 are connected to the gates of the NMOS transistors M101 to M160, respectively.

[0056] The control unit CNT1 sets some of the adjustment signals ADJ1 to ADJ60 and ADJ101 to ADJ161 to a high level and the remaining adjustment signals to a low level so that the waveforms of the first signal SCANH and the second signal SCANL become more gentle. Which adjustment signals are to be set to a high level and which adjustment signals are to be set to a low level may be determined based on the results of, for example, a simulation, an experiment, or the like. Also, which adjustment signals are to be set to a high level and which adjustment signals are to be set to a low level may be determined, for example, for each type of product, for example, for each rod of the product, or for example, for each product. The transceiver circuit 4 of the configuration example shown in FIG. 4 includes the dummy switches DSW1 to DSW60 and DSW101 to DSW160, so that the waveforms of the first signal SCANH and the second signal SCANL can be made more gentle. This makes it possible to further suppress common mode noise.

[0057] The dummy capacitances DC101 to DC160 compensate for the difference between the parasitic capacitance between the gate and source of the PMOS transistors M1 to M60 and the parasitic capacitance between the gate and source of the NMOS transistors M101 to M160, thereby suppressing the deviation between the switching timing of each of the PMOS transistors M1 to M60 and the switching timing of each of the NMOS transistors M101 to M160. Therefore, the capacitance value of the dummy capacitance DC101 may be set based on the ratio of the capacitance value of the parasitic capacitance between the gate and source of the PMOS transistor M1 to the capacitance value of the parasitic capacitance between the gate and source of the NMOS transistor M101. The capacitance values ​​of the dummy capacitances DC102 to DC160 may be set in the same manner. The transceiver circuit 4 of the configuration example shown in FIG. 4 further suppresses the symmetry of the first signal SCANH and the second signal SCANL from being broken by providing the dummy capacitances DC101 to DC160. This makes it possible to further suppress common mode noise.

[0058] Fig. 8 is a diagram showing a second configuration example of the first variable resistance unit VR1, and Fig. 9 is a diagram showing a second configuration example of the second variable resistance unit VR2. The first variable resistance unit VR1 according to the second configuration example shown in Fig. 8 and the second variable resistance unit VR2 according to the second configuration example shown in Fig. 9 are used in a pair.

[0059] The first variable resistance section VR1 according to the second configuration example shown in FIG. 8 and the second variable resistance section VR2 according to the second configuration example shown in FIG. 9 differ from the first configuration example in that a dummy capacitance is provided in the first variable resistance section VR1 rather than in the second variable resistance section VR2, but are otherwise identical to the first embodiment.

[0060] The first variable resistance section VR1 according to the second configuration example shown in FIG. 8 includes dummy capacitances DC1 to DC60.

[0061] The dummy capacitances DC1 to DC60 are capacitances provided between the gates and sources of the PMOS transistors M1 to M60, respectively. The dummy capacitances DC1 to DC60 are NMOS transistors with their sources and drains shorted and connected to the sources of the PMOS transistors M1 to M60, respectively. The gates of the dummy capacitances DC1 to DC60 are connected to the gates of the PMOS transistors M1 to M60, respectively. The capacitance value of the dummy capacitance DC1 may be set based on the ratio of the capacitance value of the gate-source parasitic capacitance of the PMOS transistor M1 to the capacitance value of the gate-source parasitic capacitance of the NMOS transistor M101. The capacitance values ​​of the dummy capacitances DC2 to DC60 may be set in a similar manner.

[0062] The first variable resistance unit VR1 according to the second configuration example shown in FIG. 8 and the second variable resistance unit VR2 according to the second configuration example shown in FIG. 9 have the same effect as the first variable resistance unit VR1 according to the first configuration example shown in FIG. 6 and the second variable resistance unit VR2 according to the first configuration example shown in FIG. 7.

[0063] Fig. 10 is a diagram showing a third configuration example of the first variable resistance unit VR1, and Fig. 10 is a diagram showing a third configuration example of the second variable resistance unit VR2. The first variable resistance unit VR1 according to the third configuration example shown in Fig. 10 and the second variable resistance unit VR2 according to the third configuration example shown in Fig. 11 are used in pairs.

[0064] The first variable resistance unit VR1 according to the third configuration example shown in Fig. 10 is configured by removing the dummy switches DSW1-DSW50 and the AND gates A1-A50 from the first variable resistance unit VR1 according to the first configuration example shown in Fig. 6. This allows the first variable resistance unit VR1 according to the third configuration example shown in Fig. 10 to have a smaller circuit area than the first variable resistance unit VR1 according to the first configuration example shown in Fig. 6.

[0065] The second variable resistance section VR2 according to the third configuration example shown in Fig. 11 has a configuration in which the dummy switches DSW101-DSW150 and the AND gates A101-A150 are removed from the second variable resistance section VR2 according to the first configuration example shown in Fig. 7. This allows the second variable resistance section VR2 according to the third configuration example shown in Fig. 11 to have a smaller circuit area than the second variable resistance section VR2 according to the first configuration example shown in Fig. 7.

[0066] The control unit CNT1 turns off the PMOS transistor M60 last when sequentially turning off the PMOS transistors M1 to M60, and turns off the NMOS transistor M160 last when sequentially turning off the NMOS transistors M101 to M160.

[0067] The dummy switch DSW60 can absorb and release charge from the PMOS transistor M60, which is the last to be turned off among the PMOS transistors M1 to M60. The absorption and release of charge from the PMOS transistor M60, which is the last to be turned off, has a high effect of adjusting the waveforms of the first signal SCANH and the second signal SCANL. Therefore, by removing some of the dummy switches while leaving the dummy switch DSW60 in the first configuration example, it is possible to reduce the circuit area while suppressing a decrease in the effect of adjusting the waveform.

[0068] The dummy switch DSW160 can absorb and release charge from the NMOS transistor M160 that is the last to be turned off among the NMOS transistors M101 to M160. The absorption and release of charge from the NMOS transistor M160 that is the last to be turned off has a high effect of adjusting the waveforms of the first signal SCANH and the second signal SCANL. Therefore, by removing some of the dummy switches while leaving the dummy switch DSW160 in the first configuration example, it is possible to reduce the circuit area while suppressing a decrease in the effect of adjusting the waveform.

[0069] <Points to note> In addition to the above-described embodiment, the configuration of the present invention can be modified in various ways without departing from the spirit of the invention. The above-described embodiment is illustrative in all respects and should be considered as not limiting, and the technical scope of the present invention is indicated by the claims, not the description of the above-described embodiment, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0070] For example, in the above embodiment, the communication performed by the transceiver circuit is CAN communication, but the communication performed by the transceiver circuit may be communication other than CAN communication.

[0071] The transmission circuit described above includes a first terminal (VCC) configured to receive a first voltage, a second terminal (CANH), a third terminal (CANL), a fourth terminal (GND) configured to receive a second voltage lower than the first voltage, a first variable resistance unit (VR1) provided between the first terminal and the second terminal and configured to vary a resistance value, a second variable resistance unit (VR2) provided between the third terminal and the fourth terminal and configured to vary a resistance value, and a control unit (CNT1) configured to control each resistance value of the first variable resistance unit and the second variable resistance unit based on transmission data, and the second variable resistance section is a circuit in which multiple series circuits of resistors (Z1 to Z60, Z101 to Z160) and switches (M1 to M60, M101 to M160) are connected in parallel, the first variable resistance section includes a first charge adjustment section (DSW1 to DSW60) configured to be capable of absorbing and discharging charge for at least some of the multiple switches provided in the first variable resistance section, and the second variable resistance section includes a second charge adjustment section (DSW101 to DSW160) configured to be capable of absorbing and discharging charge for at least some of the multiple switches provided in the second variable resistance section (first configuration).

[0072] The transmission circuit of the first configuration can suppress common mode noise caused by skew by controlling the resistance values ​​of the first variable resistance unit and the second variable resistance unit by the control unit. Moreover, the transmission circuit of the first configuration can further suppress common mode noise by including the first charge adjustment unit and the second charge adjustment unit.

[0073] In the transmission circuit of the above-mentioned first configuration, the first charge adjustment unit and the second charge adjustment unit each may include at least one first MOS transistor whose source and drain are short-circuited, and the first MOS transistor may be configured to be turned on when the switch to which the first MOS transistor is connected is turned on (second configuration).

[0074] The transmission circuit of the second configuration described above can achieve miniaturization and cost reduction of the first charge adjustment section and the second charge adjustment section.

[0075] In the transmission circuit of the above first or second configuration, the first charge adjustment unit may be capable of absorbing and discharging charge from the switch that is the last to be turned off among the multiple switches provided in the first variable resistance unit, and the second charge adjustment unit may be configured (third configuration) to be capable of absorbing and discharging charge from the switch that is the last to be turned off among the multiple switches provided in the second variable resistance unit.

[0076] The transmission circuit of the third configuration described above can reduce the circuit area while suppressing a decrease in the effect of adjusting the waveforms of the signals output from the second terminal and the third terminal.

[0077] In the transmission circuit of any of the first to third configurations, the first variable resistance section may be configured (fourth configuration) to include a capacitance (DC1 to DC60) provided between the gate and source of a P-channel MOS transistor that is the switch.

[0078] The transmission circuit of the fourth configuration can further suppress the loss of symmetry between the signal output from the second terminal and the signal output from the third terminal, and therefore can further suppress common-mode noise.

[0079] In the transmission circuit of any of the first to third configurations, the second variable resistance section may be configured (fifth configuration) to include a capacitance (DC101 to DC160) provided between the gate and source of the N-channel MOS transistor that is the switch.

[0080] The transmission circuit of the fifth configuration can further suppress the loss of symmetry between the signal output from the second terminal and the signal output from the third terminal, and therefore can further suppress common mode noise.

[0081] In the transmission circuit of the fourth or fifth configuration, the capacitance may be a second MOS transistor having a source and a drain shorted (sixth configuration).

[0082] The transmission circuit of the sixth configuration can achieve a reduction in capacity and cost.

[0083] In the transmission circuit of any of the fourth to sixth configurations, the capacitance value of the capacitor may be a value based on a ratio between the capacitance value of a gate-source parasitic capacitance of a P-channel MOS transistor that is the switch of the first variable resistance section and the capacitance value of a gate-source parasitic capacitance of a P-channel MOS transistor that is the switch of the second variable resistance section (seventh configuration).

[0084] The transmission circuit of the seventh configuration can suppress a shift between the switching timing of each of the multiple switches provided in the first variable resistance section and the switching timing of each of the multiple switches provided in the second variable resistance section.

[0085] The electronic control unit (1) described above has a configuration (eighth configuration) including a transmission circuit of any one of the first to seventh configurations and a computer (3) that sends the transmission data to the transmission circuit.

[0086] The electronic control unit of the eighth configuration can suppress common mode noise in the transmission circuit.

[0087] The vehicle (X) described above has a configuration (ninth configuration) including communication buses (BL1, BL2) and a plurality of electronic control units of the eighth configuration connected to the communication buses.

[0088] The vehicle having the ninth configuration described above can suppress common mode noise in the transmission circuit. [Explanation of symbols]

[0089] 1 ECU 2 Power circuit 3. Microcomputer 4 Transceiver Circuit 5. D1~D4 Diodes 6, 7 Capacitor A1~A60, A101~A160 AND gate CNT1 control unit BL1 1st Bus Line BL2 2nd Bus Line DC1~DC60, DC101~DC160 Dummy capacity DSW1~DSW60, DSW101~DSW160 Dummy switches M1~M60 PMOS transistors M101~M160 NMOS transistors Q1 PMOS transistor (an example of the first current limiter) Q7 NMOS transistor (an example of the second current limiter) Q2, Q3, Q8, Q9 PMOS transistors Q4~Q6, Q10~Q12 NMOS transistors R1 Pull-up resistor R2 Pull-down resistor R3, R4, R101, R102, Z1~Z60, Z101~Z160 Resistor RCV1 Receiver circuit T1~T4, VCC, GND, TXD, RXD, CANH, CANL terminal VR1 First variable resistor VR2 Second variable resistor X Vehicle ZD1, ZD2 Zener diode< / ecu>

Claims

1. a first terminal configured to receive a first voltage; A second terminal; A third terminal; a fourth terminal configured to receive a second voltage lower than the first voltage; a first variable resistance unit provided between the first terminal and the second terminal and configured to vary a resistance value; a second variable resistance unit provided between the third terminal and the fourth terminal and configured to vary a resistance value; a control unit configured to control the resistance values ​​of the first variable resistance unit and the second variable resistance unit based on transmission data; Equipped with each of the first variable resistance unit and the second variable resistance unit is a circuit in which a plurality of series circuits each including a resistor and a switch are connected in parallel; the first variable resistance unit includes a first charge adjustment unit configured to be able to absorb and release charge from at least some of the switches provided in the first variable resistance unit; A transmission circuit, wherein the second variable resistance section includes a second charge adjustment section configured to be able to absorb and release charge from at least some of the multiple switches provided in the second variable resistance section.

2. 2. The transmission circuit according to claim 1, wherein the first charge adjustment unit and the second charge adjustment unit each include at least one first MOS transistor having a source and a drain shorted together, and the first MOS transistor can be turned on when the switch to which the first MOS transistor is connected is on.

3. the first charge adjustment unit is capable of absorbing and discharging charges from a switch that is turned off last among the plurality of switches provided in the first variable resistance unit, 3. The transmission circuit according to claim 1, wherein the second charge adjustment section is capable of absorbing and discharging charge from the switch that is turned off last among the plurality of switches provided in the second variable resistance section.

4. 4. The transmission circuit according to claim 1, wherein the first variable resistance portion comprises a capacitance provided between a gate and a source of a P-channel MOS transistor which is the switch.

5. 4. The transmission circuit according to claim 1, wherein the second variable resistance section includes a capacitance provided between a gate and a source of an N-channel MOS transistor that is the switch.

6. 6. The transmission circuit according to claim 4, wherein the capacitance is a second MOS transistor having a source and a drain shorted together.

7. A transmission circuit according to any one of claims 4 to 6, wherein the capacitance value of the capacitance is a value based on a ratio between the capacitance value of a gate-source parasitic capacitance of a P-channel MOS transistor that is the switch of the first variable resistance section and the capacitance value of a gate-source parasitic capacitance of a P-channel MOS transistor that is the switch of the second variable resistance section.

8. A transmission circuit according to any one of claims 1 to 7; a computer that sends the transmission data to the transmission circuit.

9. A communication bus; A plurality of electronic control units according to claim 8 connected to the communication bus; A vehicle equipped with:

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