Semiconductor Device

Abstract

To provide a semiconductor device which uses an oxide semiconductor and achieves fining while maintaining good electrical characteristics.SOLUTION: A semiconductor device has: an oxide semiconductor film and a blocking film; a source electrode and a drain electrode which are electrically connected with the oxide semiconductor film; a gate insulation film contacting the oxide semiconductor film, the source electrode and the drain electrode; and a gate electrode contacting the gate insulation film. The blocking film uses the same material with the oxide semiconductor film formed on the same surface with the oxide semiconductor film and has higher conductivity than the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. The present invention relates to a method, manufacture, or composition of matter. One embodiment of the present invention is a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, or any of these devices. The present invention relates to a driving method thereof or a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Display devices, electro-optical devices, semiconductor circuits, and electrical equipment all refer to devices that incorporate semiconductor devices. This may be the case. [Background technology]

[0003] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology of constructing thin-film transistors (also called thin-film transistors (TFTs)) is attracting attention. It is widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. As another material, oxide semiconductors are attracting attention.

[0004] For example, amorphous oxides containing indium (In), gallium (Ga), and zinc (Zn) Patent Document 1 discloses a transistor using a compound semiconductor film. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0006] As circuits become more highly integrated, openings are provided in the interlayer insulating film between elements, and electrodes are inserted into the openings. In some cases, elements are electrically connected to each other by providing a wiring or the like. In the case of a transistor having such an opening, impurities such as hydrogen enter the oxide semiconductor film through the opening. In addition, oxygen vacancies and hydrogen in the oxide semiconductor film reduce the resistance, which leads to poor electrical characteristics of the transistor. It will lead to good things.

[0007] In view of the above problems, one embodiment of the present invention is a semiconductor device including an oxide semiconductor. Another object of the present invention is to provide a highly reliable semiconductor device. Another object of the present invention is to provide a novel semiconductor device.

[0008] In addition, transistors are becoming faster, more power-efficient, less expensive, and more highly integrated. In order to achieve this, miniaturization of transistors is essential.

[0009] In view of the above, one embodiment of the present invention is a semiconductor device including an oxide semiconductor, which has good electrical characteristics. It is an object of the present invention to provide a semiconductor device that achieves miniaturization while maintaining performance.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary to solve all of these problems. Problems other than those mentioned above are not necessarily solved. It will become clear from the description of the specification, etc., and problems other than those mentioned above will not be identified from the description of the specification, etc. It is possible to extract [Means for solving the problem]

[0011] One embodiment of the present invention is a method for manufacturing an oxide semiconductor film and a blocking film, a source electrode and a drain electrode connected to the oxide semiconductor film; a gate insulating film in contact with the gate electrode, and a gate electrode in contact with the gate insulating film; The insulating film is formed on the same surface as the oxide semiconductor film using the same material. The semiconductor device is characterized by having higher conductivity.

[0012] Another embodiment of the present invention is a semiconductor device including an oxide semiconductor film, a blocking film, and an oxide semiconductor A source electrode and a drain electrode electrically connected to the film, an oxide semiconductor film, a source electrode and a gate insulating film in contact with the drain electrode, and a gate electrode in contact with the gate insulating film. The blocking film is made of a material different from that of the oxide semiconductor film, the source electrode, and the drain electrode. The insulating film is formed on the same surface as the oxide semiconductor film and has higher electrical conductivity than the oxide semiconductor film. The semiconductor device is characterized by the above.

[0013] In the above structure, an insulating film is provided directly below the oxide semiconductor film and the blocking film. An opening is provided in the insulating film, and the distance between the blocking film and the oxide semiconductor film is set to be equal to or smaller than the opening. The distance is shorter than the distance to the nitride semiconductor film.

[0014] In the above structure, a first transistor is provided under the insulating film. The capacitor includes a substrate including a semiconductor material and is connected to a source electrode or a drain electrode through an opening. are spiritually connected. Effect of the Invention

[0015] According to one embodiment of the present invention, a blocking film can prevent water from entering the oxide semiconductor film from another layer. It has the function of suppressing the intrusion of impurities such as silicon, etc., and therefore prevents defects in the electrical characteristics of semiconductor devices. Therefore, a highly reliable semiconductor device can be provided. However, the present invention is not limited to these effects. may have effects other than those mentioned above depending on the circumstances. Alternatively, for example, one aspect of the present invention may, in some cases or depending on the situation, However, these effects may not be observed. [Brief description of the drawings]

[0016] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Diagram 2] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 3] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 4] 1A to 1C illustrate a method for manufacturing a transistor. [Diagram 5] 1 is a cross-sectional view illustrating a transistor. [Figure 6] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 7] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 8] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 9] 1A to 1C illustrate a method for manufacturing a transistor. [Figure 10] 1 is a cross-sectional view illustrating a transistor. [Figure 11] 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device according to an embodiment. [Figure 12] 1 shows a configuration example of a storage device according to an embodiment. [Figure 13] 3 shows an example of the configuration of an RF tag according to the embodiment. [Figure 14] 3 shows an example of the configuration of a CPU according to the embodiment. [Figure 15]1 is a circuit diagram of a memory element according to an embodiment. [Figure 16] 1 is an electronic device according to an embodiment. [Figure 17] 1 shows an example of use of an RF device according to an embodiment. [Figure 18] 13A to 13C are diagrams illustrating characteristics of a transistor according to an embodiment; [Figure 19] 1A to 1C are diagrams illustrating a display device according to an embodiment. [Figure 20] FIG. 1 is a top view illustrating a transistor. [Figure 21] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various modifications and variations in form and detail may be made without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention should not be construed as being limited to the description of the embodiments. In the configuration, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. will be used throughout and repeated explanations may be omitted.

[0018] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. When using a current source, or when the direction of the current changes during circuit operation, For this reason, in this specification, the terms "source" and "drain" are interchangeable. can be used instead.

[0019] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components. It should be noted that the numbers are added for the purpose of convenience and are not intended to be limiting.

[0020] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0021] 1A and 1B are a top view and a cross-sectional view of a transistor of one embodiment of the present invention. FIG. 1(A) is a top view, and the cross section taken along the dashed line A1-A2 shown in FIG. In the top view of FIG. 1(A), some elements have been omitted for clarity. The dashed line A1-A2 direction is the channel length direction, and the dashed line A1-A The direction perpendicular to the two directions is sometimes called the channel width direction. The present invention is not limited to (A), and may be, for example, a top view as shown in FIG.

[0022] The transistor 150 shown in FIG. 1A and FIG. 1B is a transistor including a base insulating film on a substrate 100. 102, and a conductive film 104a, a conductive film 104b, and a conductive film 104c on the base insulating film 102. and interlayers on the base insulating film 102, the conductive film 104a, the conductive film 104b, and the conductive film 104c. The insulating film 106, the oxide semiconductor film 108a on the interlayer insulating film 106, and the blocking film 108 b and the blocking film 108c, and an opening 120a provided in the interlayer insulating film 106. The insulating film 104 is electrically connected to the conductive film 104b and is also electrically connected to the oxide semiconductor film 108a and the blocking film 104b. The source electrode 110a on the insulating film 108b and the opening 120b in the interlayer insulating film 106 are The conductive film 104c is electrically connected to the oxide semiconductor film 108a through a The drain electrode 110b on the insulating film 108c, the oxide semiconductor film 108a, and the source electrode 110b are The gate insulating film 112 on the gate electrode 10a and the drain electrode 110b, and the oxide semiconductor film 108a The gate electrode 114 on the gate insulating film 112 and the gate insulating film 112 overlap each other. and an oxide insulating film 116 on the contact electrode 114.

[0023] The channel length is the length in a region where the semiconductor film and the gate electrode overlap in a top view. The source (source region or source electrode) and the drain (drain region or drain electrode) That is, in FIG. 1A, the channel length is the distance from the oxide semiconductor film 108 The source electrode 110a and the drain electrode 11a overlap with the gate electrode 114. 0b. The channel width is the distance between the semiconductor film and the gate electrode in the region where the semiconductor film and the gate electrode overlap. The width of the source or drain. In other words, in FIG. 1(A), the channel width is the width of the oxide semiconductor. In the region where the conductive film 108a and the gate electrode 114 overlap, the source electrode 110a or This refers to the width of the drain electrode 110b.

[0024] When miniaturizing the channel length and width of a transistor, the resist mask is removed. When electrodes, semiconductor films, etc. are processed while being heated, the upper ends of the electrodes, semiconductor films, etc. become rounded (curved). In this case, the oxide semiconductor film 108a may have a surface. The gate insulating film 112, the gate electrode 114, and the oxide insulating film 116 are formed by the above-mentioned method. In addition, the ends of the source electrode 110a and the drain electrode 110b can be This can mitigate electric field concentration that may occur, and suppress the deterioration of transistors. can.

[0025] In addition, the blocking film 108b is closer to the oxide semiconductor film 108a than the opening 120a. In other words, the distance between the blocking film 108b and the oxide semiconductor film 108a is set to be equal to or smaller than the opening 120a. The distance between the opening 1 and the oxide semiconductor film 108a is shorter than the distance between the opening 1 and the oxide semiconductor film 108a. 20b, that is, the blocking film 108c is closer to the oxide semiconductor film 108a than the oxide semiconductor film 108b. The distance between the opening 120b and the conductive film 108a is shorter than the distance between the opening 120b and the oxide semiconductor film 108a. .

[0026] By providing the blocking film as described above, other layers (e.g., silicon transistors) can be prevented from being blocked by the blocking film. The blocking film absorbs impurities such as hydrogen that penetrate through the openings from the layer between the This has the function of preventing impurities from entering the oxide semiconductor film. This can suppress defects in the electrical characteristics of the device.

[0027] In addition, the blocking film is formed on the same surface as the oxide semiconductor film using the same material. Therefore, the blocking film can be formed without increasing the number of steps. The blocking film is not limited to this, and may be an oxide semiconductor film, a source electrode (or a drain electrode), etc. It may be made of a different material.

[0028] The blocking film adsorbs impurities such as hydrogen, and therefore has a higher impurity concentration than the oxide semiconductor film. Therefore, the blocking film has higher electrical conductivity than the oxide semiconductor film.

[0029] In addition, the oxide semiconductor film 108a is electrically surrounded by the electric field of the gate electrode 114. (The electric field of the gate electrode can be used to electrically surround the oxide semiconductor film.) The structure of the star is called the surrounded channel (s-channel) structure. As a result, a channel is formed in the entire oxide semiconductor film 108a (bulk). In the -channel structure, a large current can flow between the source and drain of the transistor. Therefore, a high on-current can be obtained.

[0030] Because of the high on-current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor The device can be a highly integrated, high density semiconductor device. For example, The channel length of the transistor is preferably 40 nm or less, more preferably 30 nm or less. , more preferably 20 nm or less, and the channel width of the transistor is preferably 4 0 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less.

[0031] The substrate 100 is not limited to being a simple support, but also has other elements such as transistors and capacitors formed thereon. In this case, the gate electrode, source electrode, drain electrode, and At least one of the in-electrodes may be electrically connected to the other element.

[0032] The base insulating film 102 has a function of preventing the diffusion of impurities from the substrate 100 and also has a function of preventing oxidation. Therefore, the insulating layer 104 can supply oxygen to the oxide semiconductor film 108a. The film 102 is preferably an insulating film containing oxygen. For example, It is more preferable that the insulating film contains oxygen. In the case where the base insulating film 102 is a substrate on which a layer is formed, the base insulating film 102 also functions as an interlayer insulating film. In this case, the surface of the base insulating film 102 may be flattened. 2. CMP (Chemical Mechanical Polishing) method A smoothing treatment may be carried out.

[0033] The conductive film 104a can be used as a second gate electrode, and can further increase the on-current. In order to increase the on-current, the conductive film 10 can be thinned to a thickness of 1000 nm. 4a and the gate electrode 114 are electrically connected to have the same potential, forming a dual gate transistor. In order to control the threshold voltage, the conductive film 104a and the gate The gate electrode 114 is not electrically connected to the gate electrode 114, and a constant potential different from that of the gate electrode 114 is applied. It is sufficient to supply the conductive film 104a.

[0034] The conductive film 104b functions as a wiring that electrically connects to the source electrode 110a. The conductive film 104c functions as a wiring that is electrically connected to the drain electrode 110b. The film 104b and the conductive film 104c are electrically connected to other elements such as transistors and capacitors. may be connected to

[0035] However, one aspect of the embodiment of the present invention is not limited to this. The conductive film 104b and the conductive film 104c do not necessarily have to be provided. The conductive film 104a, the conductive film 104b, and the conductive film 104c may not be provided. A top view and a cross-sectional view in the case where no bracket is attached are shown in FIG. 21(A) and FIG. 21(B).

[0036] The interlayer insulating film 106, like the base insulating film 102, has the role of preventing the diffusion of impurities. In addition, the oxide semiconductor film 108a can also supply oxygen. The interlayer insulating film 106 is preferably an insulating film containing oxygen.

[0037] The oxide semiconductor film 108a will be described in detail below.

[0038] The oxide semiconductor film 108a is an oxide containing indium. When the oxide semiconductor film 10 contains Cr, the carrier mobility (electron mobility) is increased. 8a preferably contains the element M. Examples of the element M include aluminum, gallium, and indium. The element M is, for example, an element with a high bond energy with oxygen. The element M is, for example, an element that has the function of increasing the energy gap of the oxide. The oxide semiconductor film 108a preferably contains zinc. For example, the oxide becomes easier to crystallize. The energy of the top of the valence band of the oxide is, for example, For example, it can be controlled by the ratio of the number of zinc atoms.

[0039] However, the oxide semiconductor film 108a is not limited to an oxide containing indium. The semiconductor film 108a may be, for example, Zn--Sn oxide or Ga--Sn oxide. .

[0040] The oxide semiconductor film 108a is formed using an oxide with a wide energy gap. The energy gap of the organic semiconductor film 108a is, for example, 2.5 eV or more and 4.2 eV or less. Preferably, the voltage is 2.8 eV or more and 3.8 eV or less, and more preferably, the voltage is 3 eV or more and 3.5 eV or less. Let us assume that.

[0041] Note that in the case where the oxide semiconductor film 108a is formed by a sputtering method, the number of particles is reduced. In order to reduce the amount of indium, it is preferable to use a target containing indium. When a high oxide target is used, the conductivity of the target may be reduced. When using a target containing uranium, the conductivity of the target can be increased, and the DC discharge This makes AC discharge easier, making it easier to handle large-area substrates. This can increase the productivity of the facility.

[0042] When the oxide semiconductor film 108a is formed by a sputtering method, the atomic ratio of the target is , In:M:Zn is 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1 , 1:1:2, etc.

[0043] When the oxide semiconductor film 108a is formed by a sputtering method, the atomic ratio of the target In particular, zinc may form a film with a different atomic ratio than that of the target. In particular, the ratio of the number of atoms in the film may become smaller. The child ratio may be between 40 atomic % and 90 atomic %.

[0044] The effect of impurities in the oxide semiconductor film 108a will be described below. In order to stabilize the electrical characteristics of the transistor, the impurity concentration in the oxide semiconductor film 108a is It is effective to reduce the amount of the oxide semiconductor to lower the carrier density and to increase the purity. The carrier density of the film 108a is 1×10 17 pieces / cm 3 Less than 1×10 15 pieces / cm 3 Not yet Full, or 1×10 13 pieces / cm 3 The impurity concentration in the oxide semiconductor film 108a is less than In order to reduce this, it is preferable to also reduce the impurity concentration in the adjacent films.

[0045] For example, silicon in the oxide semiconductor film 108a serves as a carrier trap or a carrier generation source. Therefore, the oxide semiconductor film 108a and the interlayer insulating film 106 may be The silicon concentration was measured by secondary ion mass spectrometry (SIMS). Ass Spectrometry) is 1×10 19 atoms / cm 3 less than, Preferably 5 x 10 18 atoms / cm 3 less than 2×10 18 ato ms / cm 3 In addition, the thickness between the oxide semiconductor film 108a and the gate insulating film 112 is less than 100 nm. The silicon concentration in the SIMS was 1×10 19 atoms / cm 3 Less than, preferred Or 5×10 18 atoms / cm 3 less than 2×10 18 atoms / cm 3 Less than.

[0046] Furthermore, when hydrogen is contained in the oxide semiconductor film 108a, the carrier density increases. The hydrogen concentration in the oxide semiconductor film 108a was measured by SIMS at a concentration of 2×10 20 a toms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 The following is more preferable: is 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 atoms / c m 3 When nitrogen is contained in the oxide semiconductor film 108a, the carrier density is The nitrogen concentration in the oxide semiconductor film 108a is measured by SIMS. , 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Below or less, more preferably 1×10 18 atoms / cm 3 Less than 5×10, more preferably 1 7 atoms / cm 3 The following applies.

[0047] In order to reduce the hydrogen concentration in the oxide semiconductor film 108a, the base insulating film 102 and the interlayer insulating film 108b are It is preferable to reduce the hydrogen concentration in the insulating film 106. The hydrogen concentration was 2×10 20 atoms / cm 3 Below, preferably 5 x 1 0 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 below, More preferably, 5 × 10 18 atoms / cm 3 The oxide semiconductor film 1 In order to reduce the nitrogen concentration of 08a, the nitrogen concentration of the base insulating film 102 and the interlayer insulating film 106 is The nitrogen concentration in the base insulating film 102 and the interlayer insulating film 106 is preferably reduced by SIMS. 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than or equal to 5×1, more preferably 0 17 atoms / cm 3 The following applies.

[0048] In order to reduce the hydrogen concentration in the oxide semiconductor film 108a, the hydrogen concentration in the gate insulating film 112 is reduced. It is preferable to reduce the hydrogen concentration in the gate insulating film 112. 10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Below, More preferably 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 at oms / cm 3 In order to reduce the nitrogen concentration in the oxide semiconductor film 108a, It is preferable to reduce the nitrogen concentration in the gate insulating film 112. is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Further details are below. Preferably 5 x 10 17 atoms / cm 3 The following applies.

[0049] The structure of an oxide semiconductor film applicable to the oxide semiconductor film 108a will be described below. do.

[0050] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The non-single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystal-Oxide Semiconductor Film). (stalline oxide semiconductor) film, polycrystalline oxide semiconductor The oxide semiconductor film includes a film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0051] First, we will explain the CAAC-OS film.

[0052] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is small enough to fit inside a cube with one side less than 100 nm. The crystals contained in the C-OS film are vertically aligned with a side length of less than 10 nm, less than 5 nm, or less than 3 nm. This also includes cases where the size fits within a square.

[0053] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed using a quartz crystal microscope, clear boundaries between crystal parts were observed, i.e. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0054] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When the metal atoms are observed, it can be confirmed that they are arranged in layers in the crystal part. Each layer of the CAAC-OS film is formed on the surface (also called the surface on which the film is to be formed) or on the upper surface. The shape is a reflection of the CAAC-OS film and is aligned parallel to the surface on which the CAAC-OS film is formed or the top surface.

[0055] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0056] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that...

[0057] X-ray diffraction (XRD) of CAAC-OS film When the structure is analyzed using the device, for example, InGaZnO 4 CAAC-OS with crystals of In the out-of-plane analysis of the film, the diffraction angle (2θ) peaked at around 31°. This peak may appear in InGaZnO 4 It is assigned to the (009) plane of the crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that it is oriented in a roughly vertical direction.

[0058] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0059] On the other hand, in-p X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the lane method, a peak may appear at 2θ around 56°. InGaZnO 4 It is attributed to the (110) plane of the InGaZnO crystal. 4 Single crystal of acid In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to Even when φ is fixed at around 56° and scanned, no clear peak appears.

[0060] From the above, it is considered that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layers confirmed by the cross-sectional TEM observation mentioned above are aligned in the same direction. Each layer of metal atoms arranged in a lattice pattern is parallel to the ab plane of the crystal.

[0061] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization process such as a heat treatment. As described above, the c-axis of the crystal is aligned to the surface on which the CAAC-OS film is to be formed. Orientation is parallel to the normal vector of the top surface. When the shape of the film is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the forming surface or the top surface.

[0062] In addition, the crystallinity in the CAAC-OS film does not have to be uniform. When the crystalline part of the film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, The area near the surface may have a higher crystallinity than the area near the surface on which it is formed. When impurities are added to the AC-OS film, the crystallinity of the region to which the impurities are added changes, resulting in a partial In some cases, regions of differing crystallinity may be formed.

[0063] In addition, InGaZnO 4 Out-of-plane crystallographic structure of CAAC-OS film In the analysis by the method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have the 2θ value of about 31°. It is preferable that the spectrum shows a peak at 2θ of about 36° and does not show a peak at 2θ of about 36°.

[0064] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. The oxide semiconductor film is preferably made of silicon or a transition metal element other than the main component of the oxide semiconductor film. The elements that bond to oxygen stronger than the metal elements that form the oxide semiconductor film, such as Zn, By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, and the crystallinity is reduced. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide are Since the diameter (or molecular radius) of the ions is large, when the ions are contained inside the oxide semiconductor film, the oxide semiconductor film The impurities contained in the oxide semiconductor film are disturbed, which causes a decrease in crystallinity. Pure materials may act as carrier traps or carrier generation sources.

[0065] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in semiconductor films act as carrier traps and trap hydrogen. This can become a carrier generation source.

[0066] The low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "high-purity intrinsic" refers to a substantially high-purity intrinsic oxide semiconductor. Since the film has a small number of carrier generation sources, the carrier density can be reduced. The transistor including the oxide semiconductor film has an electrical characteristic in which the threshold voltage is negative. (also called normally-on). An oxide semiconductor film having an intrinsic purity has few carrier traps. Transistors using conductor films have little fluctuation in electrical characteristics and are highly reliable. Note that it takes a certain amount of time for charges trapped in the carrier traps in the oxide semiconductor film to be released. The time it takes for the charge to reach the charge state is long, and it may behave as if it were a fixed charge. A transistor using an oxide semiconductor film having a high density of defect states has unstable electrical characteristics. This may be the case.

[0067] In addition, the electrical characteristics of transistors using CAAC-OS films are improved by irradiation with visible light or ultraviolet light. Gender variation is small.

[0068] Next, a microcrystalline oxide semiconductor film will be described.

[0069] In the TEM image of the microcrystalline oxide semiconductor film, crystal parts can be clearly seen. The crystal parts contained in the microcrystalline oxide semiconductor film may have a size of 1 nm or more and 100 nm or more. In particular, the size of the particles is between 1 nm and 10 nm. Nanocrystals (nc) are microcrystals with a diameter of 1 to 3 nm or less. The oxide semiconductor film having nc-OS (nanocrystalline O The nc-OS film is called a T In EM images, grain boundaries may not be clearly visible.

[0070] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or less). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed overall. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) is used to measure the nc-OS film using X-rays with a diameter larger than that of the crystals. When structural analysis was performed using the D instrument, the crystal plane In addition, the nc-OS film has a larger probe diameter ( Electron beam diffraction (also called selected area electron beam diffraction) using an electron beam of 50 nm or more When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. The probe diameter is close to or smaller than the size of the crystal part (for example, 1 nm to 30 nm). When electron beam diffraction (also called nanobeam electron beam diffraction) is performed using an electron beam of In addition, when nanobeam electron diffraction is performed on the nc-OS film, a circular pattern is observed. In addition, a bright area (ring-shaped) may be observed in the nc-OS film. When performing electron beam diffraction, multiple spots may be observed within a ring-shaped region. do.

[0071] The nc-OS film is an oxide semiconductor film that has higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, the crystal orientation is not regular between different crystal parts. The OS film has a higher density of defect states than the CAAC-OS film.

[0072] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a C The AAC-OS film may include two or more kinds of films.

[0073] The oxide semiconductor film 108a may be a stacked film of oxide semiconductor films. The semiconductor film 108a may have a two-layer structure or a three-layer structure.

[0074] For example, the case where the oxide semiconductor film 108a has a three-layer structure will be described. The oxide semiconductor film 108a includes the oxide semiconductor film 108a1, the oxide semiconductor film 108a2, and the oxide semiconductor film 108a3. 1 shows a case where the nitride semiconductor film 108a1 is a laminated film in which the nitride semiconductor film 108a2 is formed in order.

[0075] The oxide semiconductor film 108a2 (middle layer) is the same as the oxide semiconductor film 108a up to this point. The oxide semiconductor film 108a1 (lower layer) and the oxide semiconductor film 108a3 ( The upper layer is made of one or more elements other than oxygen that constitute the oxide semiconductor film 108a2. The oxide semiconductor film 108a2 is composed of oxide semiconductor films other than oxygen. The oxide semiconductor film 108a1 and the oxide semiconductor film 1 Since the oxide semiconductor film 108a1 and the oxide semiconductor film 108a2 are formed, At the interface between the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3, Interface states are unlikely to form.

[0076] When the oxide semiconductor film 108a1 is an In-M-Zn oxide, the The atomic ratio of In and M in the total is preferably less than 50 atomic % for In and less than 50 atomic % for M. atomic % or more, more preferably In is less than 25 atomic %, and M is 75 atomic % or more. When the oxide semiconductor film 108a2 is an In-M-Zn oxide, The atomic ratio of In and M, excluding Zn and O, is preferably 25 atomic percent of In. c% or more, M is less than 75 atomic %, and more preferably In is 34 atomic % or more. In addition, the oxide semiconductor film 108a3 is In-M- In the case of Zn oxide, the atomic ratio of In and M, excluding Zn and O, is preferably I n is less than 50 atomic %, M is 50 atomic % or more, and more preferably In is 2 5 atomic % or less, and M is 75 atomic % or more. The oxide semiconductor film 8a3 may be made of the same oxide as that of the oxide semiconductor film 108a1.

[0077] Here, an oxide semiconductor film is formed between the oxide semiconductor film 108a1 and the oxide semiconductor film 108a2. There may be a mixed region of the conductor film 108a1 and the oxide semiconductor film 108a2. Between the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3, the oxide semiconductor film 10 In some cases, the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3 may have a mixed region. Therefore, the state density of the oxide semiconductor film 108a1 and the oxide semiconductor film 108a2 is low. The stack of the oxide semiconductor film 108a1 and the oxide semiconductor film 108a2 has an energy This results in a band structure in which the band changes continuously (also called a continuous junction).

[0078] The oxide semiconductor film 108a2 is a semiconductor film including the oxide semiconductor film 108a1 and the oxide semiconductor film 108 For example, the oxide semiconductor film 108a2 is an oxide having a higher electron affinity than the oxide semiconductor film 108a3. Therefore, the oxide semiconductor film 108a has a smaller electron affinity than the oxide semiconductor film 108a1 and the oxide semiconductor film 108a3. 07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably In addition, the electron affinity is determined by the electron affinity of the oxide. It is the difference in energy between the level and the bottom of the conduction band.

[0079] At this time, when an electric field is applied to the gate electrode 114, the oxide semiconductor film 108a1 and the oxide Of the semiconductor film 108a2 and the oxide semiconductor film 108a3, the oxide semiconductor film having a larger electron affinity is A channel is formed in the body membrane 108a2.

[0080] In addition, in order to increase the on-state current of the transistor, the oxide semiconductor film 108a3 is required to be as thin as possible. For example, the oxide semiconductor film 108a3 has a thickness of less than 10 nm, preferably 5 nm or more. On the other hand, the oxide semiconductor film 108a3 has a channel thickness of 3 nm or less. The oxide semiconductor film 108a2 on which the gate insulating film 112 is formed is formed with an element other than oxygen. It has the function of blocking elements (such as silicon) from entering. The conductive film 108a3 preferably has a certain thickness. For example, the conductive film 108a3 may be an oxide semiconductor film. The thickness of 108a3 is 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more. That is all.

[0081] In order to improve reliability, the oxide semiconductor film 108a1 is thick and the oxide semiconductor film 1 Specifically, the oxide semiconductor film 108a1 is preferably 20 nm or more, preferably 30 nm or more, more preferably 40 nm or more, and even more preferably 6 The thickness of the oxide semiconductor film 108a1 is set to 20 nm or more, preferably 30 nm or more, more preferably 40 nm or more, and even more preferably 60 nm or more. An oxide semiconductor film 108a1 is formed at the interface between the interlayer insulating film 106 and the oxide semiconductor film 108a1. The semiconductor film 108a2 is 20 nm or more, preferably 30 nm or more, and more preferably 4 However, in the production of semiconductor devices, the distance between the electrodes can be set to 0 nm or more, and more preferably 60 nm or more. The thickness of the oxide semiconductor film 108a1 is preferably 200 nm or less. It is preferably 120 nm or less, and more preferably 80 nm or less.

[0082] For example, the silicon between the oxide semiconductor film 108a2 and the oxide semiconductor film 108a1 The ion concentration was measured by SIMS at 1×10 19 atoms / cm 3 Less than 5x1 0 18 atoms / cm 3 less than 2×10 18 atoms / cm 3 less than In addition, the shielding between the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3 is The recon concentration was 1×10 19 atoms / cm 3 Less than 5, preferably ×10 18 atoms / cm 3 less than 2×10 18 atoms / cm 3 Less than.

[0083] In order to reduce the hydrogen concentration in the oxide semiconductor film 108a2, It is preferable to reduce the hydrogen concentrations in the oxide semiconductor film a1 and the oxide semiconductor film 108a3. The hydrogen concentration in the oxide semiconductor film 108a1 and the oxide semiconductor film 108a3 was 2×10 2 0 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 The following is more preferred: Or 1×10 19 atoms / cm 3 Less than 5×10, more preferably 18 atoms / cm 3 In order to reduce the nitrogen concentration in the oxide semiconductor film 108a2, It is preferable to reduce the nitrogen concentration in the nitride semiconductor film 108a1 and the oxide semiconductor film 108a3. The nitrogen concentrations of the oxide semiconductor film 108a1 and the oxide semiconductor film 108a3 were measured by SIMS. In, 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5, more preferably ×10 17 atoms / cm 3 The following applies.

[0084] The above-described three-layer structure is an example. For example, the oxide semiconductor film 108a1 or the oxide semiconductor A two-layer structure without the film 108a3 may also be used.

[0085] The source electrode 110a and the drain electrode 110b are formed by extracting oxygen from the oxide semiconductor film. For example, a conductive film having a property of extracting oxygen from an oxide semiconductor film is preferably used. Conductive films with excellent properties include aluminum, titanium, chromium, nickel, molybdenum, Examples of the conductive film include a conductive film containing tantalum, tungsten, and the like.

[0086] The conductive film has a property of extracting oxygen from the oxide semiconductor film. In some cases, oxygen is extracted from the oxide semiconductor film, and oxygen vacancies are formed in the oxide semiconductor film. This phenomenon is more likely to occur when the temperature is high. The manufacturing process of transistors involves several processes. Because of the thermal process, the oxide semiconductor film in the vicinity of the contact with the source electrode or the drain electrode In this region, oxygen vacancies are likely to be formed. Hydrogen may enter the oxide semiconductor film and cause it to become n-type. The oxide semiconductor film and the source electrode or the drain electrode are connected to each other by the action of the drain electrode and the oxide semiconductor film. The resistance of the contacting region can be reduced, thereby reducing the on-resistance of the transistor.

[0087] In addition, transistors with small channel lengths (e.g., 200 nm or less, or 100 nm or less) When fabricating a transistor, the source and drain may be short-circuited due to the formation of an n-type region. Therefore, when forming a transistor with a small channel length, the source electrode and A conductive film that can adequately extract oxygen from the oxide semiconductor film is used for the drain electrode. Examples of conductive films that have the property of adequately extracting oxygen include nickel and molybdenum. Examples of conductive films include those containing butene or tungsten.

[0088] Also, transistors with very small channel lengths (e.g., 40 nm or less, or 30 nm or less) When fabricating a transistor, the source and drain electrodes are mostly made of oxide semiconductor films. In this case, a conductive film that does not extract oxygen from the oxide semiconductor film may be used. Examples of conductive films that are not pulled out include tantalum nitride, titanium nitride, and ruthenium nitride. A conductive film containing Zn may be used. Note that a plurality of types of conductive films may be stacked.

[0089] The gate insulating film 112 is made of aluminum oxide, magnesium oxide, silicon oxide, or nitride oxide. Silicon oxide, silicon nitride, silicon oxide, gallium oxide, germanium oxide, Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and The insulating film 112 may be made of one or more of the above-mentioned materials. The gate insulating film 112 may be a laminate of materials containing lanthanum, nitrogen, zirconium, etc. etc. may be contained as impurities.

[0090] The gate electrode 114 may be made of aluminum, titanium, chromium, cobalt, nickel, copper, or yttrium. Thorium, zirconium, molybdenum, ruthenium, silver, tantalum, tungsten, etc. A conductive film containing one or more selected from the above may be used.

[0091] The oxide insulating film 116 may be formed of aluminum oxide, magnesium oxide, silicon oxide, or nitride oxide. silicon oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, One or more selected from lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. An insulating film containing the same can be used.

[0092] Next, a method for manufacturing a transistor will be described with reference to FIGS.

[0093] First, a base insulating film 102 is formed on a substrate 100 (see FIG. 2(A)).

[0094] The base insulating film 102 is formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. vapor deposition) method, metal organic chemical deposition (MOCVD: Metal Organic CVD) method, Plasma-Enhanced Chemical Vapor Deposition (PECVD) assisted CVD method, molecular beam epitaxy (MBE) m Epitaxy) method, Atomic Layer Deposition (ALD) method ition method or Pulsed Laser Deposition (PLD) method To reduce damage caused by plasma, the MO The CVD method or the ALD method is preferred.

[0095] Next, a CMP process may be performed to flatten the surface of the base insulating film 102. By carrying out the P treatment, the average surface roughness (Ra) of the base insulating film 102 is set to 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less. Ra should be equal to or less than the above-mentioned value. This may result in high crystallinity of the oxide semiconductor film 108a. This can be measured using an AFM:Atomic Force Microscope.

[0096] Next, oxygen is added to the base insulating film 102 to form an insulating film containing excess oxygen. The addition of oxygen may be performed by a plasma treatment or an ion implantation method. When oxygen is added by ion implantation, for example, the acceleration voltage is set to 2 kV or more and 100 kV or less. The dose is 5×10 14 ions / cm 2 5×10 or more 16 ions / cm 2 Below and Just do that.

[0097] Next, a conductive film 104a, a conductive film 104b, and a conductive film 104c are formed on the base insulating film 102. The conductive film 104a, the conductive film 104b, and the conductive film 104c are formed (see FIG. 2B). Sputtering method, CVD method, MOCVD method, PECVD method, MBE method, ALD method or The film may be formed by a PLD method, and the same material as that of the gate electrode 114 may be used. To reduce damage caused by plasma, the MOCVD method or the ALD method is preferable.

[0098] Next, on the base insulating film 102, the conductive film 104a, the conductive film 104b, and the conductive film 104c An interlayer insulating film 105 is formed (see FIG. 2(C)). The interlayer insulating film 105 is formed by sputtering. The method is CVD, MOCVD, PECVD, MBE, ALD or PLD. To reduce damage caused by plasma, MOCVD or ALD can be used. In order to flatten the surface of the interlayer insulating film 105, a CMP process may be performed. By carrying out the CMP process, the average surface roughness (Ra) of the interlayer insulating film 105 is preferably 1 nm or less. The Ra value is preferably 0.3 nm or less, and more preferably 0.1 nm or less. In this case, the crystallinity of the oxide semiconductor film 108a may be increased in some cases.

[0099] Next, an opening 120a is formed in the interlayer insulating film 105, the opening 120a reaching the conductive film 104b, and the opening 120b is formed in the conductive film 104c. An opening 120b is formed so as to reach the insulating film 106 (see FIG. 3A).

[0100] Next, an oxide semiconductor film 108a, a blocking film 108b, and The blocking film 108c is formed by a sputtering method, a CVD method, an MOCVD method, a PECVD method, or the like. It is formed by using the MBE method, the ALD method or the PLD method (see FIG. 3(B)). In order to reduce the damage caused by the deposition, the MOCVD method or the ALD method is preferable. The insulating film 106 may be etched appropriately. As a result, the oxide semiconductor film 108a can be easily covered with the gate electrode 114 to be formed later. Note that in order to miniaturize the transistor, A hard mask may be used when processing the blocking film 108b and the blocking film 108c.

[0101] The oxide semiconductor film 108a includes an oxide semiconductor film 108a1 and an oxide semiconductor film 1 When a stacked film including the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3 is formed, each layer is heated in air. It is preferable to form the films continuously without contacting each other.

[0102] In order to reduce the inclusion of impurities and form an oxide semiconductor film with high crystallinity, The film 108a is formed by heating the substrate at a temperature of 100° C. or higher, preferably 150° C. or higher, and more preferably 2 The deposition gases, oxygen gas and argon gas, are used for deposition. The temperature is preferably -40°C or lower, more preferably -80°C or lower, and even more preferably -100°C or lower. The gas used is highly purified. The impurity concentration is low, and the defect level density is low (there is little oxygen vacancy). This is called high purity authentic or substantially high purity authentic.

[0103] Shapes of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c After the formation of the insulating film, a first heat treatment may be performed. The first heat treatment is performed at a temperature of 250° C. or higher and 650° C. or lower. Preferably, the temperature is 300° C. or higher and 500° C. or lower, and the atmosphere is an inert gas, an oxidizing gas, and the like for 10 minutes. The first heat treatment may be performed in an atmosphere containing 1 ppm or more, or under reduced pressure. After heat treatment in an inert gas atmosphere, oxidizing gas was introduced at 10p to replenish the desorbed oxygen. The first heat treatment may be performed in an atmosphere containing at least pm. The crystallinity of the oxide semiconductor film 108a, the base insulating film 102, and the interlayer insulating film 10 Impurities such as hydrogen and water can be removed from 6.

[0104] Note that the oxide semiconductor film and the blocking film were formed after the opening was formed in the interlayer insulating film. However, the present invention is not limited to this, and an opening may be formed in the interlayer insulating film after forming the oxide semiconductor film and the blocking film. may be formed.

[0105] Next, the conductive film 104b is electrically connected to the conductive film 104 via the opening 120a provided in the interlayer insulating film 106. and a source electrode on the oxide semiconductor film 108a and the blocking film 108b. 110a, and the conductive film 104c through an opening 120b provided in the interlayer insulating film 106. and a gate electrode on the oxide semiconductor film 108a and the blocking film 108c. The source electrode 110a and the drain electrode 110b are formed (see FIG. 3(C)). The electrode 110b is formed by a sputtering method, a CVD method, an MOCVD method, a PECVD method, or an MBE method. In order to reduce damage caused by plasma, the ALD method or PLD method can be used. The source electrode 110a and the drain electrode 110b are preferably formed by MOCVD or ALD. When etching the conductive film that will become the source electrode 110b, The upper end of the source electrode 110b may be rounded (curved). When etching the conductive film that will become the drain electrodes 110a and 110b, the interlayer insulating film 106 It may be moderately etched.

[0106] Next, on the oxide semiconductor film 108a, on the source electrode 110a and on the drain electrode 110b A gate insulating film 112 is formed on the silicon substrate 11 (see FIG. 4(A)). CVD, MOCVD, PECVD, MBE, ALD or PL To reduce damage caused by plasma, the MOCVD method can be used. The ALD method is preferred.

[0107] Next, a gate electrode 114 is formed on the gate insulating film 112 (see FIG. 4(B)).

[0108] Next, an oxide insulating film 116 is formed on the gate insulating film 112 and the gate electrode 114. (See FIG. 4C.) The oxide insulating film 116 is formed by a sputtering method, a CVD method, an MBE method, or the like. The film may be formed by the ALD method or the PLD method.

[0109] Next, a second heat treatment may be performed. The second heat treatment may be performed under the same conditions as the first heat treatment. The second heat treatment can be performed under the following conditions. It may be possible to reduce it.

[0110] Through the above steps, the transistors shown in FIGS. 1A and 1B can be manufactured. do.

[0111] <Modifications of Transistor Structure> Also, as in the transistor shown in FIG. 5(A), the source electrode 110a and the drain electrode 110b, and a conductive film 118a and a conductive film 118b functioning as wiring are formed. The conductive films 118a and 118b may be provided over the oxide insulating film 116. It may be electrically connected to elements such as transistors and capacitors.

[0112] In addition, as in the transistor illustrated in FIG. 5B, the oxide semiconductor film 108a has a three-layer structure. , an oxide semiconductor film 108a1, an oxide semiconductor film 108a2, and a blocking layer 108b are formed on the interlayer insulating film. The blocking film 108b1, the blocking film 108b2, the blocking film 108c1, and the blocking A gate insulating film 108c2 is provided on the source electrode and the drain electrode, and an oxide semiconductor film 108a3 is provided on the source electrode and the drain electrode. The oxide semiconductor film 108a3 and the gate insulating film may be formed of a The port electrodes may be etched into the mask.

[0113] <Modifications of Transistor Structure> In addition, as in the transistor shown in FIG. By providing the channel protective film 128, the oxide semiconductor film 108a The oxide semiconductor film 108a and the channel protective film 128 are not exposed to the etching gas. This reduces impurities, resulting in a current flow between the source and drain electrodes of the transistor. This can reduce the leakage current.

[0114] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0115] (Embodiment 2) In this embodiment mode, a semiconductor device different from that in the first embodiment mode will be described with reference to the drawings. .

[0116] 6A and 6B are a top view and a cross-sectional view of a transistor of one embodiment of the present invention. FIG. 6A is a top view, and the cross section taken along the dashed line B1-B2 shown in FIG. In the top view of FIG. 6(A), some elements are omitted for clarity. The dashed line B1-B2 direction is the channel length direction, and the dashed line B1-B The direction perpendicular to the two directions is sometimes called the channel width direction.

[0117] The transistor 250 shown in FIG. 6A and FIG. 6B is a transistor including a base insulating film on a substrate 100. 102, a gate electrode 114 on the insulating base 102, and a gate electrode A gate insulating film 112 on the electrode 114, a source electrode 110a on the gate insulating film 112, and A drain electrode 110b, a gate insulating film 112, a source electrode 110a, and a drain electrode The oxide semiconductor film 108a on the source electrode 110b and the blocking film 108 on the source electrode 110a. b, a blocking film 108c on the drain electrode 110b, a source electrode 110a, The blocking electrode 110b, the oxide semiconductor film 108a, the blocking film 108b, and the blocking The interlayer insulating film 106 on the insulating film 108c, the conductive film 104a on the interlayer insulating film 106, The insulating film 106 is electrically connected to the source electrode 110a through an opening 120a provided therein. In addition, the conductive film 104b on the interlayer insulating film 106 and the opening 1 provided in the interlayer insulating film 106 20b, and is electrically connected to the drain electrode 110b via the conductor 20b on the interlayer insulating film 106. and a conductive film 104c.

[0118] The blocking film 108b is closer to the oxide semiconductor film 108a than the opening 120a. The distance between the blocking film 108b and the oxide semiconductor film 108a is set to be equal to the distance between the opening 120a and the oxide semiconductor film 108a. The distance between the blocking film 108c and the opening 120b is shorter than the distance between the blocking film 108c and the opening 120b. That is, the blocking film 108c is closer to the oxide semiconductor film 108a. The distance between the opening 120b and the oxide semiconductor film 108a is shorter than the distance between the opening 120b and the oxide semiconductor film 108a.

[0119] By providing the blocking film as described above, hydrogen and the like that penetrate through the openings from other layers can be prevented. The impurities are absorbed by the blocking film, and the impurities penetrate into the oxide semiconductor film. Since the insulating film has a function of suppressing the generation of the electric field, it is possible to suppress defects in the electrical characteristics of the semiconductor device.

[0120] In addition, the blocking film is formed on the same surface as the oxide semiconductor film using the same material. Therefore, the blocking film can be formed without increasing the number of steps. The blocking film is not limited to this, and may be an oxide semiconductor film, a source electrode (or a drain electrode), etc. It may be made of a different material.

[0121] The blocking film adsorbs impurities such as hydrogen, and therefore has a higher impurity concentration than the oxide semiconductor film. Therefore, the blocking film has higher electrical conductivity than the oxide semiconductor film.

[0122] Next, a method for manufacturing a transistor will be described with reference to FIGS.

[0123] First, a base insulating film 102 is formed on a substrate 100 (see FIG. 7(A)). Embodiment 1 can be referred to for a material and a manufacturing method of 02.

[0124] Next, a gate electrode 114 is formed on the base insulating film 102 (see FIG. 7(B)). Embodiment 1 can be referred to for a material and a manufacturing method of the electrode 114.

[0125] Next, the gate insulating film 112 is formed on the base insulating film 102 and the gate electrode 114 ( (See FIG. 7C). The material and the manufacturing method of the gate insulating film 112 are described in Embodiment 1. It is possible.

[0126] Next, a source electrode 110a and a drain electrode 110b are formed on the gate insulating film 112. (See FIG. 8(A)). The material of the source electrode 110a and the drain electrode 110b and Embodiment 1 can be referred to for a manufacturing method.

[0127] Next, an oxide film is formed on the gate insulating film 112, the source electrode 110a, and the drain electrode 110b. The semiconductor film 108a, the blocking film 108b and the blocking film 108c are formed. (See FIG. 8B). Embodiment 1 can be referred to for a material and a formation method of the insulating film 108c.

[0128] The oxide semiconductor film 108a includes an oxide semiconductor film 108a1 and an oxide semiconductor film 1 When a stacked film including the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3 is formed, each layer is heated in air. It is preferable to form the films continuously without contacting each other.

[0129] Shapes of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c After the formation of the insulating film, a first heat treatment may be performed. For details of the first heat treatment, refer to Embodiment 1. It is possible.

[0130] Next, the oxide semiconductor film 108a, the blocking film 108b, the blocking film 108c, An interlayer insulating film 105 is formed on the source electrode 110a and the drain electrode 110b (FIG. 8 (C)). The material and manufacturing method of the interlayer insulating film 105 can be referred to in Embodiment 1. can.

[0131] Next, an opening 120a reaching the source electrode 110a and a drain electrode 120b are formed in the interlayer insulating film 105. An opening 120b reaching 110b is formed, and an interlayer insulating film 106 is formed (see FIG. 9(A)). (see).

[0132] Next, the conductive film 104a on the interlayer insulating film 106 and the opening provided in the interlayer insulating film 106 are The source electrode 110a is electrically connected to the conductive layer 120a through the insulating layer 106. The drain electrode 1 is connected to the insulating film 104b via an opening 120b provided in the interlayer insulating film 106. 10b and a conductive film 104c on the interlayer insulating film 106. 9B). The conductive film 104a, the conductive film 104b, and the conductive film 104c are Condition 1 may be taken into consideration.

[0133] Next, a second heat treatment may be performed. The second heat treatment may be performed under the same conditions as the first heat treatment. The second heat treatment can be performed under the following conditions. It may be possible to reduce it.

[0134] Through the above steps, the transistor shown in FIG. 6 can be manufactured.

[0135] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0136] (Embodiment 3) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention will be described with reference to FIG. This will be described with reference to the following.

[0137] [Cross-sectional structure] FIG. 11A shows a cross-sectional view of a semiconductor device of one embodiment of the present invention. The device has a transistor 2200 using a first semiconductor material on the bottom and a second The transistor 2100 is made of a semiconductor material. As the transistor 2100 using a dielectric material, the transistor exemplified in Embodiment 1 is used. An example of its use is shown.

[0138] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon, germanium, etc.). a second semiconductor, such as silicon germanium, silicon carbide, or gallium arsenide; The body material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can operate at high speed. The transistor has a low off-state current.

[0139] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either transistor or transistors may be used, and an appropriate transistor may be used depending on the circuit. In addition to using a transistor using an oxide semiconductor according to one embodiment of the present invention, the following materials and structures are used: For example, the specific configuration of the semiconductor device is not necessarily limited to that shown here.

[0140] In the structure shown in FIG. 11A, an insulating film 2201 and an insulating The transistor 2100 is provided through a film 2207. A plurality of wirings 2202 are provided between the transistor 2100 and the A plurality of plugs 2203 embedded in the insulating film are used to form wiring in the upper and lower layers. The lines and electrodes are electrically connected. Also, an insulating film 2204 covering the transistor 2100 A wiring 2205 and the same conductor as the pair of electrodes of the transistor 2100 are formed on the insulating film 2204. A wiring 2206 obtained by processing the conductive film is provided.

[0141] In this way, stacking two types of transistors reduces the area occupied by the circuit. , multiple circuits can be arranged at higher density.

[0142] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulating film provided near the semiconductor film of the transistor 2200 is converted into silicon dams. This has the effect of terminating the Gring bonds and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the upper layer, the transistor 2 Hydrogen in the insulating film provided near the semiconductor film of 100 generates carriers in the oxide semiconductor. This may be one of the factors that cause the transistor 2100 to become less reliable. Therefore, an oxide film is formed on the upper layer of the transistor 2200 using a silicon-based semiconductor material. When the transistor 2100 using a nitride semiconductor is stacked, hydrogen diffusion between the transistors can occur. It is particularly effective to provide the insulating film 2207 having the function of preventing diffusion. 07, the reliability of the transistor 2200 is improved by trapping hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, so that the transistor 2100 At the same time, the reliability of the system can be improved.

[0143] The insulating film 2207 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium oxynitride, yttria stabilized zirconia (YSZ), etc. can be used.

[0144] In addition, a transistor 2100 including an oxide semiconductor film is formed on the transistor 2100 so as to cover the transistor 2100. An insulating film 2208 having a function of preventing hydrogen diffusion can be formed on the transistor 2100. It is preferable that the insulating film 2208 be made of a material similar to that of the insulating film 2207. In particular, it is preferable to use aluminum oxide. The aluminum oxide film is resistant to hydrogen, moisture, etc. High blocking effect prevents impurities and oxygen from passing through the membrane Therefore, an aluminum oxide film is used as the insulating film 2208 covering the transistor 2100. By using the above, it is possible to prevent oxygen from being released from the oxide semiconductor film included in the transistor 2100. Furthermore, water and hydrogen can be prevented from entering the oxide semiconductor film.

[0145] [Circuit configuration example] In the above configuration, the connection configuration of the electrodes of the transistor 2100 and the transistor 2200 is By changing the number of the electrodes, various circuits can be configured. An example of a circuit configuration that can be realized by using the semiconductor device will be described.

[0146] [CMOS Circuits] The circuit diagram shown in FIG. 11B is a circuit diagram of a p-channel transistor 2200 and an n-channel transistor The transistors 2100 are connected in series and the gates of the transistors are connected together. 1 shows the configuration of the OS circuit.

[0147] [Analog Switch] In addition, the circuit diagram shown in FIG. 11C shows a transistor 2100 and a transistor 2200. The figure shows a configuration in which the source and drain of each are connected. , it can function as a so-called analog switch.

[0148] [Example of storage device] By using a transistor according to one embodiment of the present invention, the contents of the memory can be read even when power is not supplied. An example of a semiconductor device (memory device) that can hold data and has no limit on the number of times it can be written is shown in Figure 1. Shown in 2.

[0149] The semiconductor device shown in FIG. 12A includes a transistor 3200 using a first semiconductor material and A transistor 3300 using a second semiconductor material and a capacitor element 3400 are included. Note that the transistor described in the above embodiment is used as the transistor 3300. It is possible.

[0150] The transistor 3300 is a transistor in which a channel is formed in a semiconductor film having an oxide semiconductor. The off-state current of the transistor 3300 is small, so that the transistor 3300 can be used. It is possible to retain memory contents for a longer period of time, i.e., no refresh operation is required. To provide a semiconductor memory device that does not require a refresh operation or requires an extremely low frequency of refresh operations. This makes it possible to sufficiently reduce power consumption.

[0151] In FIG. 12A, a first wiring 3001 is connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode of the transistor 3300 or The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the The other of the source electrode and the drain electrode of the transistor 3300 is a capacitor 3400. The fifth wiring 3005 is electrically connected to one of the electrodes of the capacitor 3400. and is electrically connected to

[0152] In the semiconductor device shown in FIG. 12A, the potential of the gate electrode of the transistor 3200 is held. By taking advantage of this feature, it is possible to write, store, and read information as follows: be.

[0153] The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate electrode of the transistor 3200 is Then, a certain charge is applied (write). Here, two different potential levels are applied. Either a low-level charge or a high-level charge is applied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By setting the transistor 3300 in the off state, the The charge applied to the gate electrode is retained (retention).

[0154] Since the off-state current of the transistor 3300 is extremely small, the gate The charge on the electrodes is maintained for a long period of time.

[0155] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held in the gate electrode of the transistor 3200, the second wiring 3002 has different potentials. In general, if the transistor 3200 is an n-channel type, then the transistor 320 The apparent threshold voltage V when a high-level charge is applied to the gate electrode of th_ HThe figure shows the state when a low-level charge is applied to the gate electrode of the transistor 3200. Threshold V th_L The apparent threshold voltage is The potential of the fifth wiring 3005 required to turn on the transistor 3200 is Therefore, the potential of the fifth wiring 3005 is V th_H and V th_L Between potential V 0 By doing so, the charge applied to the gate electrode of the transistor 3200 can be determined. For example, if a high level charge is applied during writing, The potential of the fifth wiring 3005 is V 0 (>V th_H ), then transistor 3200 is When a low-level charge is applied, the fifth wiring 3005 is in the "ON state". The potential is V 0 ( <V th_L ), transistor 3200 remains in the "off state" Therefore, the stored data can be read by determining the potential of the second wiring 3002. It can be seen.

[0156] When memory cells are arranged in an array, it is possible to read only the information in a desired memory cell. In this way, if the information is not read out, the state of the gate electrode The potential at which transistor 3200 is in the "off state" regardless of th_ H A smaller potential may be applied to the fifth wiring 3005. The potential at which transistor 3200 remains "on," that is, V th_L Yo A potential larger than the potential at the fifth wiring 3005 may be applied to the fifth wiring 3005 .

[0157] The semiconductor device shown in FIG. 12B differs from the semiconductor device shown in FIG. 1 mainly in that the transistor 3200 is not provided. This is different from 2(A). In this case, the same operation as above is used to write and hold information. Operation is possible.

[0158] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in a floating state and the capacitor element 3400 are electrically connected to each other. As a result, the potential of the third wiring 3003 is The amount of change in the potential of the third wiring 3003 is the potential of one of the electrodes of the capacitor 3400. (or the charge stored in the capacitor 3400).

[0159] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, The capacitance component of the third wiring 3003 is denoted by CB, and the capacitance of the third wiring 3003 before the charge is redistributed is denoted by If the potential of the third wiring 3003 after the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0+C×V) / (CB+C). Therefore, the state of the memory cell is If the potential of one of the electrodes of the element 3400 has two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=( It can be seen that this is higher than (CB×VB0+C×V0) / (CB+C)).

[0160] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. This can be done.

[0161] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cells. A transistor in which a second semiconductor material is applied is used as the transistor 3300. The transistor may be laminated on the driver circuit.

[0162] In the semiconductor device described in this embodiment, an off-state current is generated by using an oxide semiconductor in a channel formation region. By using transistors with extremely low current, memory contents can be retained for an extremely long period of time. In other words, the refresh operation is unnecessary or the refresh operation is unnecessary. Since it is possible to reduce the frequency of operation extremely, power consumption can be reduced significantly. In addition, it is possible to operate the device without power supply (although it is preferable that the potential is fixed). Even if there is a problem, it is possible to retain the stored contents for a long period of time.

[0163] In addition, the semiconductor device described in this embodiment does not require a high voltage to write data. There is no problem with element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. In other words, the problem of deterioration of the gate insulating film does not occur at all. In a physical device, there is no limit to the number of times data can be rewritten, which is a problem with conventional non-volatile memory. This will dramatically improve reliability. Furthermore, the on and off states of transistors will determine the information Since the data is written in a single bit, high speed operation can be easily achieved.

[0164] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0165] (Embodiment 4) In this embodiment, the R The F tag will be described with reference to FIG.

[0166] The RF tag in this embodiment has a memory circuit inside and stores necessary information in the memory circuit. The information is stored in the memory, and information is exchanged with the outside world using a non-contact means, for example, wireless communication. Due to these characteristics, RF tags can identify items by reading their individual information. It can be used for individual authentication systems. Extremely high reliability is required.

[0167] The structure of an RF tag will be described with reference to Fig. 13. Fig. 13 shows an example of the structure of an RF tag. FIG.

[0168] As shown in FIG. 13, an RF tag 800 includes a communicator 801 (such as an interrogator or a reader / writer). An antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, and a The circuit 807, the modulation circuit 808, the logic circuit 809, the memory circuit 810, and the ROM 811. In addition, in order to sufficiently supply a reverse current to the transistor having a rectifying effect included in the demodulation circuit 807, A material capable of suppressing the above-mentioned phenomenon, for example, an oxide semiconductor, may be used. This suppresses the degradation of the rectification effect caused by the reverse current and prevents the output of the demodulation circuit from becoming saturated. In other words, the output of the demodulation circuit relative to the input of the demodulation circuit can be made closer to linear. The data transmission format is a pair of coils arranged facing each other and exchanged by mutual induction. The electromagnetic coupling method uses electromagnetic fields to communicate, the electromagnetic induction method uses radio waves to communicate, The RF tag 800 shown in this embodiment can be used with any of these three methods. It is also possible to use it in the method.

[0169] Next, the configuration of each circuit will be described. The antenna 804 is an antenna connected to the communication device 801. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 805 is a filter for adjusting an input AC signal generated by receiving a radio signal through the antenna 804. For example, the current is rectified by half-wave double voltage rectification, and the rectified signal is averaged by a capacitive element provided in the latter stage. The rectifier circuit 805 is a circuit for smoothing the input potential. A limiter circuit may be provided on the output side or the input side. When the internally generated voltage is large, power above a certain level is not input to the downstream circuit. This is a circuit for controlling the above.

[0170] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to reset the logic circuit 8. This is a circuit for generating the reset signal for 09.

[0171] The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation in response to the

[0172] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. , a circuit that holds input information, such as a row decoder, a column decoder, a memory area, etc. The ROM 811 stores a unique number (ID) and outputs the information according to the processing. This is a circuit for doing so.

[0173] It should be noted that the above-mentioned circuits can be appropriately selected or omitted as necessary.

[0174] Here, the memory device described in the above embodiment can be used for the memory circuit 810. The storage device according to one embodiment of the present invention can retain information even when the power supply is cut off. Furthermore, the storage device according to one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required for writing is significantly smaller than that of conventional non-volatile memory, It is also possible to eliminate the difference in maximum communication distance when reading and writing data. In addition, it is possible to prevent malfunctions or erroneous writing due to insufficient power when writing data. It is possible.

[0175] The storage device of one embodiment of the present invention can be used as a nonvolatile memory. Therefore, it can be applied to ROM811. In that case, the producer must A separate command is provided to write data, preventing users from freely rewriting it. It is preferable that the manufacturer writes the unique number on the product before shipping it. Therefore, instead of assigning a unique number to every RF tag produced, only good products are shipped. This means that the unique numbers of products will be assigned only to those that have been shipped. This makes it easier to manage customers' accounts after products are shipped.

[0176] This embodiment may be combined, at least in part, with other embodiments described in this specification. It can be implemented in combination.

[0177] (Embodiment 5) In this embodiment, at least the transistor described in the above embodiment is used. A CPU including the storage device described in the above embodiment will be described.

[0178] FIG. 14 shows a CPU using the transistors described in the above embodiments at least in part. FIG. 2 is a block diagram showing an example of a configuration.

[0179] The CPU shown in FIG. 14 includes an ALU 1191 (ALU: Arithmetic Unit) on a board 1190. tic logic unit, ALU controller 1192, instruction action decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface The substrate 1190 is a semiconductor substrate, an SOI Substrates, glass substrates, etc. are used. ROM 1199 and ROM interface 1189 Of course, the CPU shown in FIG. 14 can be simplified in its configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their applications. For example, the configuration including the CPU or arithmetic circuit shown in FIG. 14 is regarded as one core, and the core is divided into multiple The CPU may also be configured to include a processor core and each core may operate in parallel. The number of bits that can be handled by a computing circuit or a data bus is, for example, 8 bits, 16 bits, 32 bits, 6 It can be 4 bits, etc.

[0180] The instructions input to the CPU via the bus interface 1198 are The signal is input to the input decoder 1193, decoded, and then passed to the ALU controller 1192, the input The interrupt controller 1194, the register controller 1197, the timing controller It is entered into RA 1195.

[0181] ALU controller 1192, interrupt controller 1194, register controller The controller 1197 and timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to control the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it. It generates an address and reads and writes register 1196 depending on the CPU state.

[0182] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and and generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal CLK1. The internal clock generating unit generates the internal clock signal CLK2. It is supplied to the various circuits listed above.

[0183] In the CPU shown in FIG. 14, a memory cell is provided in the register 1196. The transistors shown in the above embodiments can be used as memory cells of the memory cell 1196. Cut.

[0184] In the CPU shown in FIG. 14, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or the capacity Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. When data retention in the capacitive element is selected, rewriting data to the capacitive element The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0185] FIG. 15 is a circuit diagram of an example of a memory element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A circuit 1202 in which memory data is not volatile, a switch 1203, a switch 1204, and a logic The circuit includes an element 1206, a capacitor 1207, and a circuit 1220 having a selection function. The circuit 1202 includes a capacitor element 1208, a transistor 1209, and a transistor 1210. The memory element 1200 may include a diode, a resistor, an inductor, etc., as necessary. It may further include other elements such as a converter.

[0186] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of the power supply voltage to the memory element 1200 is stopped, the transistor 12 The gate of 09 is supplied with ground potential (0V) or a potential that turns off transistor 1209. For example, the gate of the transistor 1209 is connected to the load such as a resistor. It is configured to be grounded.

[0187] The switch 1203 is a transistor 1213 of one conductivity type (for example, an n-channel type). The switch 1204 is configured with a conductivity type opposite to the one conductivity type (for example, a p-channel type). Here, the first transistor 1214 of the switch 1203 is used. The terminal corresponds to one of the source and drain of the transistor 1213, and the first terminal of the switch 1203. The terminal 2 corresponds to the other of the source and drain of the transistor 1213, and the terminal 2 corresponds to the other of the source and drain of the switch 1203. The first terminal and the second terminal are connected to each other by a control signal RD input to the gate of the transistor 1213. Conduction or non-conduction between the terminals of the transistor 1213 (i.e., the on or off state of the transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of a transistor 1214. The second terminal of the switch 1204 corresponds to one of the drains of the The switch 1204 is connected to the gate of the transistor 1214. A control signal RD is input to the first terminal and the second terminal to establish or break continuity (i.e., The on or off state of transistor 1214 is selected.

[0188] One of the source and drain of the transistor 1209 is connected to a pair of electrodes of the capacitor 1208. The other of the two is electrically connected to the gate of the transistor 1210. One of the source and drain of the transistor 1210 is connected to a low power supply voltage The other is electrically connected to a wiring (e.g., a GND line) that can supply a switch voltage. The first terminal of the transistor 1203 (one of the source and drain of the transistor 1213) is electrically connected to the The second terminal of the switch 1203 (the source and drain of the transistor 1213) is connected to the other terminal of the switch 1204 (the source and drain of the transistor 1214) The second terminal of the switch 1204 (the first terminal of the transistor 1214) is electrically connected to the The other of the source and drain is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (as well as the source and drain of the transistor 1213) a first terminal of the switch 1204 (one of the source and drain of the transistor 1214) one of a pair of electrodes of a capacitor 1207, and an input terminal of a logic element 1206. , are electrically connected. Here, the connection point is designated as node M1. The other electrode of the pair may be configured to have a constant potential input thereto. For example, It can be configured so that the power supply potential (GND, etc.) or high power supply potential (VDD, etc.) is input. The other of the pair of electrodes of the capacitor 1207 is connected to a power supply that can supply a low power potential. The pair of electrodes of the capacitor 1208 are electrically connected to a wiring (for example, a GND line). The other terminal may be configured to receive a constant potential. For example, a low power supply potential (GND A power supply potential (VDD, etc.) or a high power supply potential (VDD, etc.) can be input to the capacitance element 12. The other of the pair of electrodes of 08 is a wiring that can supply a low power supply potential (for example, GN D line).

[0189] The capacitors 1207 and 1208 are parasitic capacitances of transistors and wirings, etc. It is also possible to omit it by making active use of the above.

[0190] A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are connected to a control signal R, which is different from the control signal WE. D selects the conductive or non-conductive state between the first and second terminals, and When the first terminal and the second terminal of the switch are in a conductive state, the first terminal of the other switch There is no electrical continuity between the second terminals.

[0191] The other of the source and drain of the transistor 1209 is connected to a data terminal of the circuit 1201. In FIG. 15, the signal output from the circuit 1201 corresponds to the In the example shown, the other of the source and drain of the switch 1203 is connected to the source of the transistor 1209. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value of the inverted signal is inverted by the logic element 1206 and is output via the circuit 1220. The signal is then input to the circuit 1201.

[0192] In FIG. 15, the second terminal of the switch 1203 (the source of the transistor 1213) The signal output from the drain (the other drain) is passed through the logic element 1206 and the circuit 1220. The second terminal of the switch 1203 is connected to the first terminal of the circuit 1201. The signal output from the other terminal of the transistor 1213 (the other of the source and drain of the transistor 1213) is It may be input to the circuit 1201 without being inverted. For example, If there is a node that holds a signal whose logical value is the inverted value of the signal input from the input terminal, In this case, the second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) ) can be input to the node.

[0193] In addition, in FIG. 15, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed of a layer or a substrate 11 made of a semiconductor other than an oxide semiconductor. 90. For example, a silicon layer or The memory element may be a transistor in which a channel is formed in a silicon substrate. All the transistors used in the element 1200 are transistors whose channels are formed of oxide semiconductor films. Alternatively, the memory element 1200 may include a transistor 1209 or In addition, a transistor in which a channel is formed of an oxide semiconductor film may be included. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. Alternatively, the transistor may be formed by

[0194] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0195] In the semiconductor device according to one embodiment of the present invention, a power supply voltage is not supplied to the memory element 1200. During this period, data stored in the circuit 1201 is transferred to the capacitor 12 in the circuit 1202. It can be retained by 08.

[0196] In addition, a transistor in which a channel is formed in an oxide semiconductor film has an extremely low off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor film is The off-state current is significantly lower than that of a transistor having a channel formed in silicon. Therefore, by using the transistor as the transistor 1209, Even when the power supply voltage is not supplied to the capacitor 1200, the signal held in the capacitor 1208 remains constant for a long period of time. In this way, the memory element 1200 can maintain the stored contents ( It is possible to retain the data.

[0197] In addition, by providing the switches 1203 and 1204, the precharge Since the memory element is characterized by performing the following operations, after the power supply voltage is resumed, the circuit 1201 This can shorten the time it takes to restore the original data.

[0198] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is restarted. After the signal is released, the signal held by the capacitive element 1208 is transferred to the transistor 1210 in the state (on or off state) and can be read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitance element 1208 fluctuates slightly, the original signal It is possible to read out the number accurately.

[0199] Such a memory element 1200 may be a register or a cache memory of a processor. By using this in a storage device, it is possible to prevent data loss in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, or multiple logic circuits, the power can be stopped for a short period of time, reducing power consumption. can be suppressed.

[0200] In the present embodiment, the memory element 1200 is used as a CPU. The 1200 is equipped with a DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device) and other LSIs, It can also be applied to RF (Radio Frequency) devices.

[0201] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0202] (Embodiment 6) In this embodiment, a structure example of a display panel according to one embodiment of the present invention will be described.

[0203] [Configuration example] FIG. 19A is a top view of a display panel according to one embodiment of the present invention, and FIG. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. FIG. 19C is a circuit diagram illustrating a display panel according to one embodiment of the present invention. A circuit for explaining a pixel circuit that can be used when an organic EL element is applied to a pixel FIG.

[0204] The transistors disposed in the pixel portion can be formed according to the above-described embodiment. In addition, since the transistor can be easily made into an n-channel type, the n-channel A part of the driver circuit can be composed of a transistor of the same type as the transistor of the pixel part. In this manner, the transistor shown in the above embodiment is formed in the pixel portion and the driver circuit. By using the above-mentioned capacitor, a highly reliable display device can be provided.

[0205] An example of a block diagram of an active matrix display device is shown in FIG. On the substrate 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 703, and a The pixel portion 701 includes a signal line driver circuit 703 and a signal line driver circuit 704. A first scanning line driving circuit 702 and a second scanning line driving circuit 704 are arranged to extend from the first scanning line driving circuit 702 and a second scanning line driving circuit 704. The second scanning line driving circuit 703 is extended from the second scanning line driving circuit 703. In each region, pixels each having a display element are arranged in a matrix. The substrate 700 of the device is a flexible printed circuit (FPC) or the like. It is connected to a timing control circuit (also called a controller or control IC) via a connection part. do.

[0206] In FIG. 19A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal The line driver circuit 704 is formed on the same substrate 700 as the pixel section 701. The number of components such as the drive circuits to be provided is reduced, which contributes to cost reduction. 700 If a driving circuit is provided externally, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve reliability or yield.

[0207] [Liquid crystal panel] An example of the circuit configuration of a pixel is shown in FIG. 19(B). Here, a VA type liquid crystal display panel 4 shows a pixel circuit that can be applied to the pixel of

[0208] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels of the multi-domain design to be The signals applied to the electrode layers can be controlled independently.

[0209] A gate wiring 712 of a transistor 716 and a gate wiring 713 of a transistor 717 The data lines are separated so that different gate signals can be applied. The source electrode layer or drain electrode layer 714 functioning as a transistor 716 is Transistors 716 and 717 are used in common in the above embodiment. The transistor described in the above embodiment can be appropriately used. A liquid crystal display panel can be provided.

[0210] A first pixel electrode layer electrically connected to the transistor 716 and a second pixel electrode layer electrically connected to the transistor 717 The shape of the second pixel electrode layer that is electrically connected to the first pixel electrode layer will be described. The shape of the pixel electrode layer is separated by slits. The first pixel electrode layer spreads in a V shape. The second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0211] The gate electrode of the transistor 716 is connected to the gate wiring 712, and the transistor 717 The gate electrode of the gate electrode 712 is connected to the gate wiring 713. 3, different gate signals are applied to transistors 716 and 717. By varying the thickness, the alignment of the liquid crystal can be controlled.

[0212] In addition, the capacitance wiring 710, the gate insulating film functioning as a dielectric, and the first pixel electrode layer Alternatively, a storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0213] The multi-domain structure has a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. can be.

[0214] Note that the pixel circuit shown in FIG. 19B is not limited to this. A switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit may be newly added to the pixel shown in FIG. etc. may be added.

[0215] [Organic EL Panel] Another example of the circuit configuration of a pixel is shown in FIG. 1 shows the pixel structure of a display panel.

[0216] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of a pair of electrodes. and holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The electrons and holes recombine to form an excited state in the light-emitting organic compound, When the excited state returns to the ground state, light is emitted. The optical element is called a current-excited light-emitting element.

[0217] FIG. 19C is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. can be used for the channel formation region of an n-channel transistor. The pixel circuit can apply digital time gray scale driving.

[0218] Regarding the configuration of an applicable pixel circuit and the operation of a pixel when digital time gray scale driving is applied, I will explain it below.

[0219] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light emitting The switching transistor 721 has a gate element 724 and a capacitor element 723. The first electrode (one of the source and drain electrode layers) is connected to the scan line 726. The second electrode (the other of the source electrode layer and the drain electrode layer) is connected to a signal line 725. It is connected to the gate electrode layer of the driving transistor 722. The gate electrode layer is connected to a power supply line 727 through a capacitor element 723, and the first electrode is connected to the power supply line 727, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light emitting element 724 corresponds to a common electrode 728. It is electrically connected to a common potential line formed thereon.

[0220] The switching transistor 721 and the driving transistor 722 are the same as those in the above embodiment. This allows the transistors described in 2. to be used appropriately. A display panel can be provided.

[0221] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The low power supply potential is a potential lower than the high power supply potential set to the power supply line 727. For example, D, 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage of the light emitting element 72. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 24 refers to the voltage required to achieve the desired brightness, and should be at least 100%. Includes threshold voltage.

[0222] The capacitance element 723 is substituted for the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 can be omitted. A capacitance may be formed between the gate electrode layer and the gate electrode layer.

[0223] Next, a signal input to the driving transistor 722 will be described. In the case of the above method, the driving transistor 722 is in two states, that is, fully on or off. A video signal that satisfies the above requirement is input to the driving transistor 722. In order to operate the actuator 722 in a linear region, a voltage higher than the voltage of the power supply line 727 is applied to the drive A gate electrode layer of the transistor 722 is connected to a signal line 725. A voltage equal to or greater than the threshold voltage Vth of the driving transistor 722 is applied.

[0224] When analog gradation driving is performed, the gate electrode layer of the driving transistor 722 is connected to the light emitting element 7 A voltage equal to or greater than the sum of the forward voltage of the transistor 724 and the threshold voltage Vth of the driving transistor 722 is applied. In addition, a video signal is input so that the driving transistor 722 operates in the saturation region. This causes a current to flow through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is passed to the light emitting element 724. Moreover, analog gray scale driving can be performed.

[0225] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. 9(C) is connected to a pixel circuit having a switch, a resistor, a capacitor, a sensor, a transistor or a logic A logic circuit or the like may be added.

[0226] When the transistors illustrated in the above embodiments are applied to the circuit illustrated in FIG. The source electrode (first electrode) is on the low potential side, and the drain electrode (second electrode) is on the high potential side. The potential of the first gate electrode is controlled by a control circuit or the like. The second gate electrode is supplied with a potential lower than that applied to the source electrode by a wiring (not shown). Any of the above-mentioned potentials may be input.

[0227] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0228] (Embodiment 7) The semiconductor device according to one aspect of the present invention is used in a display device, a personal computer, a recording medium, Image playback device equipped with a DVD: Digital Versatile Disk c) a device having a display capable of reproducing a recording medium and displaying the image. In addition, an electronic device in which the semiconductor device according to one embodiment of the present invention can be used As such, mobile phones, handheld game consoles, portable data terminals, e-books, video cameras, Cameras such as digital still cameras, goggle-type displays (head-mounted displays) (car audio, digital audio player), navigation systems, audio playback devices Layers, etc.), copiers, facsimiles, printers, printer-combinations, automated teller machines Examples of electronic devices include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 16. .

[0229] FIG. 16A shows a portable game machine, which includes a housing 901, a housing 902, a display portion 903, and a display 904, microphone 905, speaker 906, operation keys 907, stylus 90 8. The portable game machine shown in FIG. 16(A) has two display units 903 and However, the number of display units that the portable game machine has is not limited to this. stomach.

[0230] FIG. 16B shows a portable data terminal, which includes a first housing 911, a second housing 912, and a first display unit. The first display unit 913, the second display unit 914, the connection unit 915, the operation keys 916, etc. 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connection part 915. The image on the first display unit 913 is transmitted between the first housing 911 and the second housing 912 at the connection unit 915. The first display unit 913 and the second display unit 914 may be switched according to the angle between the first display unit 913 and the second display unit 914. At least one of the first display unit 912 and the second display unit 914 is provided with a function as a position input device. The function of the position input device may be achieved by touching the display device. The position input function can be added by providing a panel. It can also be added by providing a photoelectric conversion element, also called a photo sensor, in the pixel section of the display device. This can be done.

[0231] FIG. 16C shows a notebook personal computer, which includes a housing 921, a display portion 922, It has a keyboard 923, a pointing device 924, and the like.

[0232] FIG. 16(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 933. 33 etc.

[0233] FIG. 16E shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943. The operation key 944, the lens 945, the connection part 946, etc. The lens 945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946. The angle between the first housing 941 and the second housing 942 can be changed by the connection part 946. The image on the display unit 943 is transmitted between the first housing 941 and the second housing 942 at the connection unit 946. 42.

[0234] FIG. 16(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953, Light 954 etc.

[0235] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0236] (Embodiment 8) In this embodiment, a usage example of an RF device according to one embodiment of the present invention will be described with reference to FIG. The applications of RF devices are wide-ranging, but for example, Bonds, bearer bonds, certificates (driver's licenses, resident's certificates, etc., see Figure 17(A)), recording media (D VDs and video tapes, see Fig. 17(B), packaging containers (wrapping paper, bottles, see Fig. 17 (C)), vehicles (bicycles, etc., see Figure 17 (D)), personal belongings (bags, glasses, etc.), Food, plants, animals, the human body, clothing, daily necessities, medicines and other medical products, or electrical appliances. Items such as child devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), Or it can be attached to a tag (see Figure 17(E) and Figure 17(F)) to be used. It is possible.

[0237] The RF device 4000 according to one embodiment of the present invention can be attached to or embedded in a surface. For example, in a book, the sensor is embedded in the paper and fixed to the packaging made of organic resin. If so, it is embedded in the organic resin and fixed to each article. The F Device 4000 is small, thin, and lightweight, so even after it is fixed to an article, it remains attached to the article. It does not impair the design of the product itself. It can also be used for banknotes, coins, securities, bearer bonds, Alternatively, the RF device 4000 according to one aspect of the present invention may be provided on a document or the like, By utilizing this authentication function, counterfeiting can be prevented. Also, packaging containers, recording media, personal belongings, food, clothing, daily necessities, or electronic devices. By attaching an RF device according to one aspect of the present invention to a system such as an inspection system, In addition, the R according to one aspect of the present invention can be used for vehicles as well. By installing the F device, you can increase security against theft, etc. Cut.

[0238] As described above, the RF device according to one aspect of the present invention can be used for each of the applications described in this embodiment. By using this technology, the power consumption during operation, including writing and reading information, can be reduced, enabling maximum It is possible to extend the transmission distance. In addition, information can be transmitted even when the power is cut off. Since the data can be stored for a long period of time, it is also suitable for applications where the frequency of writing and reading is low. It is possible.

[0239] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do. EXAMPLES

[0240] In this embodiment, a transistor having a similar structure to that shown in FIG. A transistor was fabricated and its electrical characteristics were evaluated.

[0241] First, a method for preparing the example samples will be described.

[0242] A 900 nm thick TEOS (Tetra Elastomer) film was placed on the silicon transistor as an interlayer insulating film. Silicon oxide film made from ethyl ortho silicate is produced by CVD. More formed.

[0243] Next, the silicon oxide film was subjected to a CMP process to flatten the surface of the silicon oxide film. The conditions were as follows: a polyurethane-based polishing cloth was used as the CMP polishing pad, and NP8 was used as the slurry. A stock solution of 020 (manufactured by Nitta Haas Corporation) (silica particle size 60 nm to 80 nm) was used. The slurry temperature was room temperature, the polishing pressure was 0.08 MPa, and the spindle on the side fixing the substrate was The rotation speed is 51 rpm, and the rotation speed of the table to which the polishing cloth is fixed is 50 rpm. Processed for 6 minutes.

[0244] Next, an opening reaching the electrode of the silicon transistor is etched in the silicon oxide film. The etching conditions were as follows: first, ICP (Inductively Coupled Plasma) etching was performed; The inductively coupled plasma (ICP) etching method Trifluoromethane and Helium (CHF 3 :He=50sccm:100sccm) mixture Under a combined atmosphere, power supply power 475 W, bias power 300 W, pressure 5.5 Pa for 3 seconds Then, as a second etch, trifluoromethane was removed by ICP etching. Tantalum and helium (CHF 3 :He=7.5sccm:142.5sccm) mixed atmosphere The etch was performed for 79 seconds under atmospheric pressure, with a power supply of 475 W, a bias power of 300 W, and a pressure of 5.5 Pa. The film is then etched again under the first etching conditions, and then etched under the second etching conditions. Switched.

[0245] Next, a 150 nm thick tungsten film that will become the relay wiring is formed by sputtering. The deposition conditions were as follows: a tungsten target was used, and the atmosphere was argon (Ar=80sccm). In the atmosphere, a pressure of 0.8 Pa and a power supply of 1 kW were applied, and the distance between the target and the substrate was The film was formed with a distance of 60 mm and a substrate temperature of 230°C.

[0246] Next, the tungsten film was etched to form relay wiring. The etching conditions were: The P etching method removes chlorine, carbon tetrafluoride, and oxygen (Cl 2 :CF 4 :O 2 =45s ccm: 55sccm: 55sccm) mixed atmosphere, power supply power 3000W, bias voltage Etching was carried out for 5 seconds at a power of 110 W and a pressure of 0.67 Pa.

[0247] Next, a silicon oxide film made of TEOS with a thickness of 500 nm, which will become the interlayer insulating film, is It was formed by method D.

[0248] Next, the silicon oxide film was subjected to CMP processing to expose the relay wiring. The polishing pad used was a polyurethane-based polishing cloth, and the slurry was NP8020 (Ni The slurry temperature was set at 100°C. The temperature was set to room temperature, the polishing pressure was 0.08 MPa, and the spindle rotation speed on the side fixing the substrate was 51 The rotation speed of the table to which the polishing cloth is fixed is 50 rpm, and the treatment is performed for 1.4 minutes. Ta.

[0249] Next, a 100 nm thick silicon oxide film made from TEOS, which will become the interlayer insulating film, A 50 nm thick silicon nitride film on a silicon film, a 300 nm thick oxide film on a silicon nitride film The silicon nitride film was formed by the CVD method.

[0250] Next, a first oxide semiconductor film having a thickness of 20 nm and a second oxide semiconductor film having a thickness of 15 nm were formed. The first oxide semiconductor film was formed by stacking layers of In:Ga:Zn=1:3:2. Argon and oxygen ( Ar:O2 = 30sccm:15sccm) mixed atmosphere, pressure 0.4Pa, voltage The source power was 0.5 kW, the distance between the target and the substrate was 60 mm, and the substrate temperature was 200°C. The second oxide semiconductor film was formed as an oxide semiconductor film having an atomic ratio of In:Ga:Zn=1:1:1. Argon and oxygen (Ar:O) were deposited by sputtering using a carbide target. 2 =30 sccm: 15sccm) mixed atmosphere, pressure 0.4Pa, power supply power 0.5kW The film was formed by applying a voltage of 100 V to the target, setting the distance between the target and the substrate at 60 mm and the substrate temperature at 300°C. Note that the first oxide semiconductor film and the second oxide semiconductor film were successively formed without exposure to air. went.

[0251] Next, a heat treatment was performed. The heat treatment was performed in a nitrogen atmosphere at 450°C for 1 hour, and then the sample was cooled to 100°C. The reaction was carried out in a nitrogen atmosphere at 450° C. for 1 hour.

[0252] Next, the first oxide semiconductor film and the second oxide semiconductor film are etched by an ICP etching method. Boron trichloride and chlorine (BCl 3 :Cl 2 =60sccm:20sccm) mixed atmosphere The experiment was performed for 89 seconds under atmospheric conditions with a power supply of 450 W, a bias power of 100 W, and a pressure of 1.9 Pa. The first oxide semiconductor film and the second oxide semiconductor film were then processed into island-shaped films by etching. At the same time, a first blocking island is formed from the first oxide semiconductor film and the second oxide semiconductor film. A blocking film and a second blocking film were then formed.

[0253] Next, a silicon oxide film made of TEOS with a thickness of 100 nm and a film on the silicon oxide film A 50 nm thick silicon nitride film and a 300 nm thick silicon oxide film on the silicon nitride film are An opening reaching the interconnection was formed by etching. The etching conditions were as follows: first, a first etch The etching was performed using trifluoromethane and helium (CHF 3 : He = 50sccm: 100sccm) mixed atmosphere, power supply power 475W, bias voltage Etching was performed for 3 seconds at a power of 300 W and a pressure of 5.5 Pa, and then as the second etching The ICP etching method uses trifluoromethane and helium (CHF 3 :He=7. 5sccm:142.5sccm) mixed atmosphere, power supply power 475W, bias power 30 The etching was performed for 69 seconds at 0 W and a pressure of 5.5 Pa, and then the etching was performed again under the first etching condition. After etching, the film was etched under the second etching conditions.

[0254] Next, a tungsten film having a thickness of 100 nm was formed to become the source and drain electrodes. The film was formed by sputtering using a tungsten target with argon (Ar =80sccm) atmosphere, pressure 0.8Pa, power supply power (power output) 1.0kW The distance between the substrate and the target was 60 mm, and the substrate temperature was 230°C. A film was formed.

[0255] Next, a resist mask was formed on the tungsten film, and etching was performed. The fluorine-containing gas was removed by ICP etching using carbon tetrafluoride, chlorine and oxygen (CF 4 :Cl 2 :O 2 = 55sccm: 45sccm: 55sccm) mixed atmosphere, power supply power 3000W, The first etching was performed for 13 seconds at a bias power of 110 W and a pressure of 0.67 Pa. Oxygen (O 2= 100sccm) atmosphere, power supply power 2000W, bias power 0W, pressure A second etching was performed at 3.0 Pa for 15 seconds, followed by etching with carbon tetrafluoride, chlorine and and oxygen (CF 4 :Cl 2 :O 2 =55sccm:45sccm:55sccm) mixed atmosphere The third etch was performed under atmospheric conditions with a power supply of 3000 W, a bias power of 110 W, and a pressure of 0.67 Pa. The etching was carried out for 14 seconds to form a source electrode and a drain electrode.

[0256] Next, a third oxide semiconductor film having a thickness of 5 nm was formed on the second oxide semiconductor film, the source electrode, and the drain electrode. An oxide semiconductor film was formed. The film formation conditions were In:Ga:Zn=1:3:2 (atomic ratio). Argon and oxygen (Ar:O) were deposited by sputtering using an oxide target. 2 =3 0sccm:15sccm) mixed atmosphere, pressure 0.4Pa, power supply power 0.5k W was applied, the distance between the target and the substrate was 60 mm, and the substrate temperature was 200°C.

[0257] Next, a 20 nm silicon oxynitride film, which will become the gate insulating film, is formed by the CVD method using silane and and nitrous oxide (SiH 4 :N 2 O = 1sccm: 800sccm) mixed atmosphere, pressure The applied pressure was 200 Pa, the power supply was 150 kW, and the distance between the target and the substrate was 28 mm. The film was formed at a substrate temperature of 350°C.

[0258] Next, a titanium nitride film having a thickness of 30 nm and a tungsten film having a thickness of 135 nm are sputtered. The titanium nitride film was formed by the deposition method. 2 =50sccm) atmosphere Under atmospheric conditions, a pressure of 0.2 Pa and a power supply of 12 kW were applied, and the gap between the target and the substrate was The distance was 400 mm, and the substrate temperature was 25°C. The deposition conditions for the tungsten film were argon (A In the atmosphere (r = 100sccm), a pressure of 2.0 Pa and a power supply of 4kW were applied. The distance between the target and the substrate was 60 mm, and the substrate temperature was 230°C.

[0259] Next, a titanium nitride film with a thickness of 30 nm and a SiO2 film with a thickness of 135 nm were formed by ICP etching. The tungsten film stack was etched under the following etching conditions: chlorine, carbon tetrafluoride and Oxygen (Cl 2 :CF 4 :O 2 =45sccm:55sccm:55sccm) mixed atmosphere The first edge was measured at a power supply of 3000 W, a bias power of 110 W, and a pressure of 0.67 Pa. After the first etching, chlorine and boron trichloride (Cl 2 :BCl 3 =5 0sccm:150sccm) mixed atmosphere, power supply power 1000W, bias power 50W A second etching was then performed at a pressure of 0.67 Pa to form a gate electrode.

[0260] Next, a gate insulating film and a third oxide semiconductor film are stacked using the gate electrode as a mask. The etching conditions were: boron trichloride (BCl 3 =80sccm) atmosphere, Etching was performed at a source power of 450 W, a bias power of 100 W, and a pressure of 1.0 Pa. .

[0261] Next, a 150 nm thick aluminum oxide film was formed on the gate electrode by sputtering. The deposition conditions were argon:oxygen (Ar:O 2 =25sccm:25sccm) mixed In the mixed atmosphere, a pressure of 0.4 Pa and a power supply of 2.5 kW were applied to the target and the substrate. The distance between the electrodes was 60 mm, and the substrate temperature was 250°C.

[0262] Through the above steps, a transistor having a channel length of 0.8 μm and a channel width of 10 μm is fabricated. As a comparative example, the first blocking film and the second blocking film of the above transistor were fabricated. A transistor was fabricated that did not have the blocking film.

[0263] Next, the drain voltage (V d :[V]) is 0.1 V or 2.7V, and the gate voltage (V g :[V]) from -3V to 3V , drain current (I d The measurement results are shown in FIG. The solid line indicates the drain voltage (V d : [V]) is 0.1V, and the dotted line indicates Drain voltage (V d :[V]) is 2.7V, and the horizontal axis is the gate voltage ( V g :[V]), and the vertical axis is the drain current (I d : [A]) Note that "drain voltage ( V d "Gate potential [V]" is the potential difference between the drain and source with respect to the source. Voltage (V g "V" is the potential difference between the gate and source with respect to the source. FIG. 18A shows the measurement results of the transistor of the comparative example, and FIG. 18B shows the measurement results of the transistor of the embodiment. The measurement results are shown in Fig.

[0264] In FIG. 18(A), it was confirmed that the characteristics vary widely. On the other hand, in FIG. 18(B), It was confirmed that the variation in characteristics was small. By providing a blocking film, It was suggested that the variation could be reduced. [Explanation of symbols]

[0265] 100 Substrates 102 Undercoat insulating film 104a Conductive film 104b Conductive film 104c Conductive film 105 Interlayer insulating film 106 Interlayer insulating film 108a Oxide semiconductor film 108a1 Oxide semiconductor film 108a2 Oxide semiconductor film 108a3 Oxide semiconductor film 108b Blocking membrane 108b1 Blocking membrane 108b2 Blocking membrane 108c Blocking membrane 108c1 Blocking membrane 108c2 Blocking membrane 110a source electrode 110b Drain electrode 112 Gate insulating film 114 Gate electrode 116 Oxide insulating film 118a Conductive film 118b Conductive film 120a opening 120b opening 128 Channel protection film 150 Transistors 250 Transistors 700 Substrates 701 Pixel section 702 Scanning line driver circuit 703 Scanning line driver circuit 704 Signal line driver circuit 710 Capacitance wiring 712 Gate wiring 713 Gate wiring 714 Drain electrode layer 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 pixels 721 Switching Transistors 722 Driving Transistor 723 Capacitive element 724 Light emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 800 RF Tags 801 Communication Device 802 Antenna 803 radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuit 810 Memory circuit 811 ROM 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 911 1st unit 912 2nd cabinet 913 Display section 914 Display section 915 Connection 916 Operation Key 921 Case 922 Display section 923 Keyboard 924 Pointing Device 931 Case 932 Refrigerator door 933 Freezer door 941 1st cabinet 942 2nd cabinet 943 Display section 944 Operation Key 945 Lens 946 Connection 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 Board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Registers 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic elements 1207 Capacitive element 1208 Capacitive element 1209 Transistor 1210 Transistor 1213 Transistor 1214 Transistor 1220 Circuit 2100 Transistor 2200 Transistor 2201 Insulating film 2202 Wiring 2203 Plug 2204 Insulating film 2205 Wiring 2206 Wiring 2207 Insulating film 2208 Insulating film 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 Transistors 3300 Transistors 3400 Capacitive element 4000 RF Devices

Claims

1. A first insulating film; a first conductive film having a region in contact with an upper surface of the first insulating film and functioning as a gate electrode; a second insulating film having a region in contact with an upper surface of the first conductive film and functioning as a gate insulating film; a second conductive film having a region in contact with an upper surface of the second insulating film and functioning as a source electrode; a third conductive film having a region in contact with an upper surface of the second insulating film and functioning as a drain electrode; a first oxide semiconductor film having a region in contact with an upper surface of the second insulating film, a region in contact with an upper surface of the second conductive film, and a region in contact with an upper surface of the third conductive film, the first oxide semiconductor film having a channel formation region; a second oxide semiconductor film having a region in contact with an upper surface of the second conductive film; a third insulating film having a region in contact with an upper surface of the second conductive film, a region in contact with an upper surface of the third conductive film, a region in contact with an upper surface of the first oxide semiconductor film, and a region in contact with an upper surface of the second oxide semiconductor film; a fourth conductive film having a region in contact with an upper surface of the third insulating film and a region in contact with an upper surface of the second conductive film through an opening provided in the third insulating film; the second oxide semiconductor film has a lower resistance than the first oxide semiconductor film; a distance between the second oxide semiconductor film and the first oxide semiconductor film is shorter than a distance between the opening and the first oxide semiconductor film; In a plan view, the second oxide semiconductor film intersects with the second conductive film.

2. A first insulating film; a first conductive film having a region in contact with an upper surface of the first insulating film and functioning as a gate electrode; a second insulating film having a region in contact with an upper surface of the first conductive film and functioning as a gate insulating film; a second conductive film having a region in contact with an upper surface of the second insulating film and functioning as a source electrode; a third conductive film having a region in contact with an upper surface of the second insulating film and functioning as a drain electrode; a first oxide semiconductor film having a region in contact with an upper surface of the second insulating film, a region in contact with an upper surface of the second conductive film, and a region in contact with an upper surface of the third conductive film, the first oxide semiconductor film having a channel formation region; a second oxide semiconductor film having a region in contact with an upper surface of the second conductive film; a third oxide semiconductor film having a region in contact with an upper surface of the third conductive film; a third insulating film having a region in contact with an upper surface of the second conductive film, a region in contact with an upper surface of the third conductive film, a region in contact with an upper surface of the first oxide semiconductor film, a region in contact with an upper surface of the second oxide semiconductor film, and a region in contact with an upper surface of the third oxide semiconductor film; a fourth conductive film having a region in contact with an upper surface of the third insulating film and a region in contact with an upper surface of the second conductive film through a first opening provided in the third insulating film; a fifth conductive film having a region in contact with an upper surface of the third insulating film and a region in contact with an upper surface of the third conductive film through a second opening provided in the third insulating film; the second oxide semiconductor film has a lower resistance than the first oxide semiconductor film; the third oxide semiconductor film has a lower resistance than the first oxide semiconductor film; a distance between the second oxide semiconductor film and the first oxide semiconductor film is shorter than a distance between the first opening and the first oxide semiconductor film; a distance between the third oxide semiconductor film and the first oxide semiconductor film is shorter than a distance between the second opening and the first oxide semiconductor film; the second oxide semiconductor film intersects with the second conductive film in a plan view; In a plan view, the third oxide semiconductor film intersects with the third conductive film.

Images