Multi-gate NOR flash thin-film transistor strings arranged in stacked horizontal active strips and having vertical control gates

Abstract

A multi-gate NOR flash thin film transistor (TFT) string array is provided. The TFTs in each stack are arranged as a stack of horizontal active strips that run parallel to the surface of a silicon substrate, with the TFTs in each stack controlled by vertical local word lines that run along one or both sidewalls of the stack of active strips. Each of the local word lines 208w is connected to one of the global word lines 208g-a, including word lines 208g-s that are routed to one or more layers above the active layers 202-6-202-7, or routed to one or more layers below the active layers between the global active layer 202-6 and the substrate 201.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 235,322, entitled "Multi-Gate NOR Flash Thin Film Transistor Strings Arranged in Stacked Horizontal Active Strips and Having Vertical Control Gates," filed on September 30, 2007. The provisional patent application is incorporated herein by reference in its entirety.

[0002] (Technical field) The present invention relates to high density memory structures, and more particularly to high density memory structures formed by interconnecting thin film storage elements such as thin film storage transistors. [Background technology]

[0003] In this disclosure, memory circuit structures are described herein. These structures can be fabricated on planar semiconductor substrates (e.g., silicon wafers) using conventional manufacturing processes. For ease of clarity herein, the term "vertical" refers to a direction perpendicular to the surface of the semiconductor substrate, and the term "horizontal" refers to any direction parallel to the surface of the semiconductor substrate.

[0004] Several high density non-volatile memory structures, sometimes referred to as "3D vertical NAND strings", are known in the prior art. Many of these high density memory structures are organized using thin film storage transistors formed from deposited thin films (e.g., polysilicon thin films) and arranged as an array of "memory strings". One type of memory string is called a NAND memory string or simply a "NAND string". A NAND string consists of a number of series connected memory transistors ("TFTs"). Reading or programming any of the series connected TFTs requires activation of all the series connected TFTs in the NAND string. Under this NAND configuration, activated TFTs that are not being read or programmed may experience undesirable program disturb or read disturb conditions. Furthermore, TFTs formed from polysilicon thin films - and therefore have high resistivity - have much lower channel mobility than conventional transistors formed on single crystal silicon substrates. In fact, the higher series resistance in a NAND string generally limits the number of TFTs in the string to 64 or 128 TFTs or less. The low read current that needs to be conducted through the long AND string results in high latency.

[0005] Another type of high density memory structure is called a NOR memory string or "NOR string." A NOR string includes multiple memory transistors each connected to a shared source region and a shared drain region. Thus, the NOR strings are connected in parallel such that the read current in the NOR string conducts with much less resistance than the read current through the NAND string. At present, the inventor is not aware of any conventional NOR strings formed with TFTs. To read or program a memory transistor in a NOR string, only that memory transistor needs to be activated (i.e., "on" or conducting), while all other memory transistors in the NOR string are placed in a quiescent state (i.e., off or non-conducting). As a result, the NOR string allows for more rapid sensing of the activated memory transistor to be read and avoids program disturb or read disturb conditions in other memory transistors of the NOR string that are not being read or programmed.

[0006] Three-dimensional memory structures have been disclosed in U.S. patents, such as U.S. Patent No. 8,878,278, filed January 30, 2013, and issued November 4, 2014, to Alsmeier et al., entitled "Compact 3D Vertical NAND and Method for Manufacturing Same." Alsmeier discloses various types of high density NAND memory structures, such as "Terabit Cell Array Transistor" (TCAT) NAND arrays (FIG. 1A), "Pipe-shaped Bit-Cost Scalable (P-BiCS) Flash Memory" (FIG. 1B), and "Vertical NAND" memory string structures. Similarly, U.S. Patent No. 7,005,350, filed December 31, 2002, and issued February 28, 2006, to Walker et al., entitled "Method for Manufacturing a Programmable Memory Array Structure Incorporating Series-Connected Transistor Strings," also discloses numerous three-dimensional high density NAND memory structures.

[0007] U.S. Patent No. 7,612,411, filed August 3, 2005, and published November 3, 2009, by Walker, entitled "Dual Gate Device and Method," discloses a "dual gate" memory structure in which a shared active area provides independently controlled storage elements in two NAND strings formed on opposite sides of the shared active area.

[0008] U.S. Patent No. 6,744,094 to Forbes, filed Aug. 24, 2001, and published Jun. 1, 2004, entitled "Floating Gate Transistor With Horizontal Gate Layer Adjacent to Vertical Body," discloses a memory structure having a body transistor with a vertically adjacent and parallel horizontal gate layer.

[0009] U.S. Pat. No. 6,580,124 to Cleaves et al., filed Aug. 14, 2000 and published June 17, 2003, entitled "Multi-Gate Semiconductor Device and Method of Fabrication Having Vertical Channel Current Flow," discloses a multi-bit memory transistor having two or four charge storage media formed along vertical surfaces of the transistor.

[0010] A three-dimensional memory structure including horizontal NAND strings controlled by vertical polysilicon gates is disclosed in a paper by W. Kim entitled "Stacked Vertical Gate NAND Flash Overcoming Stack Limits for Terabit Density Storage" (Non-Patent Document 1). Horizontal 3D NAND Strings with Vertical Poly Gates Another three-dimensional memory structure also including horizontal NAND strings with vertical polysilicon gates is disclosed in a paper by HT Liu et al. entitled "Highly Scalable 8-Layer 3D Vertical Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Devices" (2010 VLSI Symposium: Tech Digest of Technical Papers, pp. 131-132).

[0011] In the memory structures discussed herein, stored information is represented by stored charges, which are introduced using a variety of techniques. For example, U.S. Patent No. 5,768,192 to Eitan, entitled "Nonvolatile Semiconductor Memory Cell Utilizing Asymmetric Charge Trapping," filed July 23, 1996 and published June 16, 1998, discloses an NROM-type memory transistor operation based on "hot electron channel injection techniques." Other techniques include Fowler-Nordheim Tunneling, used in TFT NAND strings, and direct tunneling, both of which are known to those skilled in the art. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] U.S. Patent No. 8,878,278 [Patent Document 2] U.S. Patent No. 7,612,411 [Patent Document 3] U.S. Patent No. 6,744,094 [Patent Document 4] U.S. Patent No. 6,580,124 [Patent Document 5] U.S. Patent No. 5,768,192 [Non-patent literature]

[0013] [Non-Patent Document 1] "Multi-layered Vertical gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage" by W.Kim at al., 2009 Symposium on VLSI Tech.Dig.Of Technical Papers, pp188-189. [Non-Patent Document 2] "A Highly Scalable 8-Layer 3D Vertical-gate(VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device," by HT Lue et al.,2010 Symposium on VLSI:Tech.Dig.Of Technical Papers,pp.131-132. Summary of the Invention [Means for solving the problem]

[0014] According to one embodiment of the present invention, a multi-gate NOR flash thin film transistor (TFT) string array ("multi-gate NOR string array") is organized as a stack of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by a vertical local word line provided along one or both sidewalls of the stack of active strips. Each active strip includes at least one channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by a charge storage element provided between the active strip and a control gate provided by an adjacent local word line. Each active strip can provide TFTs belonging to one or two NOR strings, depending on whether one or both sides of the active strip are used.

[0015] In one embodiment, only one of the shared source or drain layers in an active strip is connected to a supply voltage, while the other source or drain layer is held at a voltage determined by the amount of charge deposited on the source or drain layer. Prior to a read, write or erase operation, a non-activated TFT acts as a strip capacitor, with one plate being the source or drain layer itself and the other plate being the control gate electrode of the NOR string referenced to ground. The charge on the strip capacitor is provided by one or more pre-charged TFTs, but the TFT is momentarily activated to transfer charge from the supply voltage connected to the contacted source or drain layer to the strip capacitor.

[0016] In one embodiment, TFTs are formed on both vertical side edges of each active strip such that vertical local word lines can be provided along both vertical side edges of the active strip. In that embodiment, double density is achieved by contacting the local word lines along one of the vertical edges of the active strip with horizontal global word lines provided above the active strip, while the local word lines of the active strip along the other vertical edge are contacted with horizontal global word lines provided below the active strip. All global word lines may run in a direction perpendicular to the orientation of the corresponding active strip. Even greater storage density can be achieved by storing more than one bit of data in each TFT.

[0017] Organizing the TFTs into NOR strings rather than conventional NAND results in (i) reduced read latency approaching that of dynamic random access memory (DRAM) arrays, (ii) reduced sensitivity to read disturb and program disturb conditions associated with NAND long strings, and (iii) lower power consumption and cost compared to planar NAND or 3D NAND arrays.

[0018] According to one embodiment of the present invention, threshold voltage variations within a block of NOR strings can be compensated for by providing an electrically programmable reference string within the block. The effect on the read operation of background leakage current inherent in multi-gate NOR strings can be substantially erased by comparing the sensing result of the TFT being read with the sensing result of a simultaneously read TFT on a reference NOR string. In another embodiment, the charge storage element of each TFT can have a modified structure to provide high write / erase cycle endurance despite a lower retention time requiring refresh. However, such refresh is required significantly less frequently than conventional dynamic random access memory (DRAM) circuits, making the NOR string array of the present invention operable in some DRAM applications. The use of such NOR strings allows for an inherently lower cost-per-bit figure of merit compared to conventional DRAMs, and an inherently reduced read delay time compared to conventional NAND string arrays.

[0019] The present invention is better understood in light of the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0020] [Figure 1A] FIG. 1A is a conceptual diagram of a memory configuration showing the configuration of a memory cell according to an embodiment of the present invention. [Figure 1B] FIG. 1B shows a basic circuit diagram of two stacks of NOR strings sharing a common vertical word line, according to one embodiment of the present invention. [Figure 1C] FIG. 1C shows a basic circuit diagram of a stack of four NOR strings in the YZ plane cross section of FIG. 1A. [Figure 2A] FIG. 2A illustrates a YZ cross-sectional view of a memory structure after active layers 202-0 through 202-7 have been formed on a semiconductor substrate, and prior to the formation of individual active strips, in accordance with one embodiment of the present invention. [Figure 2B-1] FIG. 2B-1 illustrates a structure 220a that can be used to implement any of the active layers 202-0 through 202-7 of FIG. 2A, according to one embodiment of the present invention. [Figure 2B-2] FIG. 2B-2 illustrates a structure 220c that includes an additional metal sublayer 224 adjacent to each layer 221 and 223 of structure 220a according to one embodiment of the present invention. [Figure 2B-3] FIG. 2B-3 illustrates a structure 220c that includes another metal sub-sublayer 224 adjacent to each layer 221 and 223 of structure 220a according to one embodiment of the present invention. [Figure 2C] FIG. 2C shows a cross-sectional view in the YZ plane through buried contacts 205-0 and 205-1 that connect the N+ sublayers 223 of active layers 202-0 and 202-1, respectively, to contacts 206-0 and 206-1 in semiconductor substrate 201. [Figure 2D] FIG. 2D is a cross-sectional view in the XY plane through active layer 202-7 of a portion of the memory structure illustrating the formation of trench 230 in memory structure 200 of FIG. 2A. [Figure 2E] FIG. 2E is a cross-sectional view in the XY plane through active layer 202-7 of a portion of memory structure 200 of FIG. 2A illustrating the deposition of charge trapping layers 231L and 231R on opposing sidewalls of the active strips along trench 230. [Figure 2F] FIG. 2F is a cross-sectional view showing the deposition of polysilicon or metal 208 to fill trench 230. [Figure 2G] FIG. 2G is a cross-sectional view showing that after photolithographic patterning and etching steps on the memory structure of FIG. 2F, local wordline 208w and precharge wordline 208-chg are formed by removing exposed portions of deposited polysilicon 208 to obtain insulating material 209 or shafts that provide air gap eye isolation. [Figure 2H]FIG. 2H shows a cross-sectional view in the XZ plane through row of local word line 208w of FIG. 2G, showing active strips of active layers 202-7 and 202-6. [Figure 2I] FIG. 2I is a cross-sectional view showing that each of the local word lines 208w of FIG. 2H is connected to one of the global word lines 208g-a and includes word lines 208g-s (see FIG. 4A) that are routed to one or more layers disposed above the active layers 202-0 to 202-7 or routed to one or more layers disposed below the active layers between the global active layer 202-0 and the substrate 201. [Figure 2J] FIG. 2J is a cross-sectional view showing an alternative embodiment to that shown in FIG. 2I according to one embodiment of the present invention, in which only top global word lines, i.e., no bottom global word lines, are provided, and in this embodiment, the local word lines along one edge of the active strip are staggered relative to the local word lines on the other edge of the active strip (see FIG. 4B). [Figure 2K] FIG. 2K is a cross-sectional view illustrating each of the local word lines 208w controlling TFTs formed from active strips on opposite sides of the local word line (see FIG. 4C) according to one embodiment of the present invention. [Diagram 3] FIG. 3 is a circuit diagram showing the method and circuit elements used to set the source voltage (Vss) on the source line in the N+ sublayer 221; specifically, it shows that the source line voltage can be set via a hardwire decoded source line connection 280 or using a precharge TFT 303 and bit line connection 270. [Figure 4A] FIG. 4A is a cross-sectional view in the XY plane showing contact 291 connecting local word line 208w to global word line 208g-a for the embodiment of the invention shown in FIG. 2I. [Figure 4B]FIG. 4B is a cross-sectional view in the XY plane showing contacts 291 connecting local word lines 208w to top global word lines 208g-a (or bottom global word lines 208g-s) in a staggered arrangement for the embodiment of the invention shown in FIG. 2J. [Figure 4C] FIG. 4C is a cross-sectional view in the XY plane showing contacts 291 connecting local word lines 208w to global word lines 208g-a and isolation 209 between adjacent active strip pairs for the embodiment of the invention shown in FIG. 2K. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] FIG. 1A illustrates a conceptualized memory structure 100 to facilitate illustration in this detailed description of an organization of memory cells according to an embodiment of the present invention. As shown in FIG. 1A, the memory structure 100 represents a three-dimensional block of memory cells formed into a thin film deposited on a surface of a substrate layer 101. The substrate layer 101 may be, for example, a conventional silicon wafer used to manufacture integrated circuits, which will be familiar to those skilled in the art. In this detailed description, a Cartesian coordinate system (e.g., as shown in FIG. 1A) is adopted merely for ease of discussion. Under this coordinate system, the surface of the substrate layer 101 is considered as a plane parallel to the XY plane. Thus, as used herein, the term "horizontal" refers to any direction parallel to the XY plane, and "vertical" refers to the Z direction.

[0022] In FIG. 1A, each vertical column represents a storage element (i.e., thin film memory transistor or TFT) that shares a vertical common control gate or word line in a stack of horizontal NOR strings, each NOR column extending along the Y direction. Each NOR string is formed from TFTs along an "active strip," described in more detail below. Unlike a NAND string, within a NOR string, writing, reading, or erasing one of the TFTs does not involve activation of other TFTs in the NOR string. As shown in FIG. 1A, memory structure 100 represents an array of four stacks of NOR strings, each stack having four NOR strings, each having four TFTs. It is important to note that, as a conceptualized structure, memory structure 100 is merely an abstraction of certain salient features of the memory structure of the present invention. Although shown in FIG. 1A as an array of 4×4 NOR strings, each having four TFTs, the memory structure of the present invention can have any number of TFTs along any of the X, Y, and Z directions. For example, there may be 2, 4, 8, 16, 32, 64... NOR type strings along the X and Z directions, respectively, and each NOR string may have 2, 4, 8, 16... 8192 or more TFTs. n , n is an integer), which follows customary practice in conventional memory design. It is customary to access each addressable memory unit by decoding the binary address. Thus, for example, a memory structure within the scope of the present invention may have M NOR strings along each of the X and Z directions, where M is not necessarily 2 for any integer n. nis not a number. If memory block 100 has 8192 stacks of 8 NOR strings, each NOR string having 8192 stacks of storage elements, memory block 100 has more than 500 million storage elements in the form of NOR type non-volatile TFTs. Since it is not uncommon today to store more than one bit in a storage element using multi-level cell (MLC) technology, memory block 100 can store more than 1 billion bits of information. A 1 terabit memory chip has more than 1000 blocks, plus spare blocks to replace defective or worn blocks.

[0023] As a conceptualized structure, memory structure 100 is not drawn to scale in any of the X, Y, or Z directions.

[0024] 1E shows a basic circuit representation of a stack of four NOR strings in a cross-section in the YZ plane of a conceptual diagram of memory structure 100. As shown in FIG. 1C, each NOR string extends along the Y direction and has a storage element connected between a source line 153-m and a bit line 154-m, where m is the index of the corresponding active strip, between 1 and 4. Corresponding storage elements in the four NOR strings are connected to corresponding vertical word lines 151-n, where n is the index of the word line along the active strip.

[0025] Figure 1B illustrates a basic circuit representation of two stacks of NOR strings sharing a common vertical word line, according to one embodiment of the present invention. The detailed structure of this configuration is described below in conjunction with Figure 2K. As shown in Figure 1B, this basic circuit configuration includes NOR strings (e.g., NOR strings 150L and 150R) in adjacent columns of memory structure 100 that share a common word line.

[0026] As shown in FIG. 1B, NOR strings 150L and 150R are NOR strings in two active strips located on opposite sides of common word line 151a. Memory transistors 152R-1 to 152R-4 and 152L-1 to 152L-4 are memory elements in the four active strips on the left side and the four active strips on the right side of vertical common word line 151a. In this embodiment, greater storage density can be achieved by having a common local word line that controls the TFTs of adjacent active strips, as will be described in more detail below in conjunction with FIG. 2K and FIG. 4C. For example, word line 15I controls the TFTs in the NOR strings of bit lines 153R-1, 153R-2, 153R-3, and 153R-4 and the TFTs in the NOR strings of bit lines 153L-1, 153L-2, 153L-3, and 153L-4. As described in more detail below, in one embodiment, a parasitic capacitance C inherent to each NOR string (e.g., the parasitic capacitance between the string's N+ diffusion and its many associated local word lines) is used to provide a virtual source under some operating conditions.

[0027] The TFTs in the NOR strings of the present invention can be programmed, program inhibited, erased, or read using conventional programming, inhibit, erase, and read voltages. In one or more embodiments of the present invention, the TFTs are implemented with thin film storage transistors that are programmed or erased using Fowler-Nordheim tunneling or direct tunneling mechanisms. In another embodiment, channel hot electron injection can be used for programming.

[0028] FIG. 2A illustrates a cross-section in the YZ plane of memory structure 200 after active layers 202-0 through 202-7 have been formed on semiconductor substrate 201, according to one embodiment of the present invention. As shown in FIG. 2A, memory structure 200 includes active layers 202-0 through 202-7. Semiconductor substrate 201 may represent, for example, a P-doped bulk silicon wafer in which support circuitry for memory structure 200 may be formed prior to forming the active layers. Such support circuitry may include both analog and digital circuitry. Some examples of such support circuitry include shift registers, latches, sense amplifiers, reference cells, source lines, bias and reference voltage generators, inverters, Nand, Nor, Exclusive-Or and other logic gates, input / output drivers, address decoders, bit line and word line decoders, other memory elements, sequencers and state machines. These support circuits may be formed from conventional device building blocks. For example, N-well, P-well, triple well, N-well, and other logic gates may be formed from conventional device building blocks, as known to those skilled in the art. + , P+ diffusion regions, isolation regions, low and high voltage transistors, capacitors, resistors, and wiring.

[0029] After support circuitry has been formed in and on the semiconductor substrate 201, an insulating layer 203-0 is provided, which may be, for example, a thick deposited or grown silicon oxide.

[0030] Next, in some embodiments, one or more interconnect layers including "global word lines" are formed, which are described below. Such metal wiring (e.g., global word line landing pads 264 in FIG. 2C, described below) may be provided as horizontal, elongated strips extending along a predetermined direction perpendicular to the active NOR strings formed in a later step. For ease of explanation in this detailed description, it is assumed that the global word lines extend along the X direction. The metal wiring may be formed by applying photolithographic patterning and etching steps on one or more deposited metal layers (alternatively, these metal wiring may be formed using a conventional damascene process, such as a copper damascene process). A thick oxide 203-0 is then deposited, followed by a planarization step using conventional chemical mechanical polishing (CMP).

[0031] Active layers 202-0 to 202-7 are then formed in sequence, with each active layer being insulated from the previous underlying active layer by a corresponding one 203-1 to 203-7. Although eight active layers are shown in FIG. 2A, any number of active layers may be provided. In practice, the number of active layers provided is limited by the process technology, e.g., the availability of a well-controlled anisotropic etching process that may cut through the active layers to reach the semiconductor substrate 201. Each active layer is etched in an etching step described below to form a number of parallel active strips, each extending along the Y direction.

[0032] FIG. 2B-1 illustrates a structure 220a that can be used to implement any of the active layers 202-0 through 202-7 of FIG. 2A, according to one embodiment of the present invention. As shown in FIG. 2B-1, the active layer 220a includes deposited polysilicon sublayers 221 through 223. The sublayers 221 through 223 can be deposited sequentially in the same process chamber without removal in between. The sublayer 223 includes 5-50 nm of in-situ doped N + Sublayers 222 and 221 can then be formed by depositing undoped or lightly doped polysilicon to a thickness in the range of 40-100 nm. Sublayer 221 (i.e., the top layer of deposited polysilicon) can then be formed by depositing N + This N + Doping is achieved by (i) low-energy shallow ion implantation of arsenic or antimony, 20–50 nm of N + (ii) formation of a doped top sublayer 221, or (iii) in situ doping of the deposited polysilicon, resulting in 20-50 nm of N + (Thermal diffusion should not be used since it exposes the previously formed lower active layers to greater diffusion than the upper active layers.) Low dose implantation of boron (P-) or phosphorus (N-) ions can also be used to remove implanted or in-situ N + It is performed with sufficient energy to penetrate the doped sublayer 221 and provide a modal threshold voltage for the sublayer 222 located between the top N+ doped sublayer 221 and the bottom N+ doped sublayer 223 .

[0033] Thermal activation of the N+ and P- implant species in sublayers 221 and 222 should preferably be performed after all active layers 202-0 through 202-7 are formed using conventional rapid thermal annealing techniques (e.g., 700° C. or higher), which ensures that all active layers receive approximately the same amount of high temperature processing. It should be noted that the total thermal budget should not be exceeded and that the N + Merging of sublayer 223 with N+ sublayer 221 should be avoided and P-sublayer 222 should not be lost. P-sublayer 222 is required to remain thick enough to avoid N+ P-N+ transistor punch-through at low voltages applied across N+ sublayers 221 and 223.

[0034] The final thickness of sublayer 222 represents the length of the TFT channel, which can be as little as 10 nm or less for long active strips. In one embodiment, it is possible to deposit an ultra-thin (approximately 1 nm) silicon nitride (e.g., SiN or Si3N4) or another suitable diffusion blocking film, followed by forming an N+ sublayer, and then depositing polysilicon of sublayer 222 to a thickness in the range of 5-30 nm before depositing N+ polysilicon sublayer 221 again, thereby controlling the TFT channel length to less than 10 nm. The ultra-thin silicon nitride layer can be deposited by chemical vapor deposition, atomic layer deposition, or any other means, such as high pressure nitridation at low temperature. Each ultra-thin silicon nitride layer acts as a diffusion barrier while the N + Sublayer 221 and N+Sublayer 223 +They prevent dopants from diffusing into the P-sublayer 222, yet are thin enough to only slightly interfere with MOS transistor operation in the region between the N+ sublayer 221 (acting as the source) and N+ sublayer 223 (acting as the drain) (electrons in the surface inversion layer of sublayer 222 easily tunnel directly through 1 nm of silicon nitride). These additional ultra-thin silicon nitride layers increase manufacturing costs, but help to significantly reduce leakage current in many TFTs along the active strip that are in the "off" state, while providing high read currents for TFTs that are accessed in the "on" state.

[0035] Optionally, N + To provide lower resistivity along the bit and source lines of sublayers 223 and 221, N +An additional conductive sublayer 224 may be provided adjacent to a corresponding one of the sublayers 221 and 223 (e.g., for FIG. 2B-2) or to both (e.g., for FIG. 2B-3). The sublayer 224 may be provided by one or more deposited metal layers. For example, the sublayer 224 may be provided by first depositing a 1-2 nm thick layer of TiN, followed by a 10-40 nm thick layer of tungsten or a similar refractory metal or its silicide or salicide. Reduction of wiring resistance is desirable to reduce the "RC delay" of signals across long conductive strips (i.e., the time delay due to the product of the wiring resistance R and the wiring capacitance C). It is used to minimize the "IR drop" across long, narrow active strips (i.e., the voltage drop due to the product of the current I and the wiring resistance R). However, the inclusion of metal sublayer 224 in each of active layers 202-0 through 202-7 can increase cost and complexity in the manufacturing process, including the complication that some of the metal materials are difficult to anisotropically etch compared to materials such as polysilicon or silicon oxide in the other sublayers. However, the use of metal sublayer 224 allows for the use of significantly longer active strips, which results in superior array efficiency, while shorter active strips may result in a larger number of active strips. + Sublayers 223 and N + It has better resistance to leakage to and from sublayer 221 and has lower intrinsic capacitance than longer strips. Integrated circuit designers can choose shorter active strips (with or without one or both metal layers) when low latency is most important. Alternatively, strip resistance can be reduced by providing buried contacts at both ends of each active strip, rather than just one end.

[0036] The block formation patterning and etching step defines separate blocks in the formed active layer, each of which defines an area in which a large number (e.g., thousands) of active strips extending in parallel along the Y direction will be formed, with each active strip forming a large number (e.g., thousands) of TFTs, as described below.

[0037] Each of the active layers 202-0 through 202-7 is formed sequentially, with each active layer being formed by repeating the above steps. In addition, in the block formation patterning that defines the blocks of each active layer, each upper active layer extends slightly beyond the previous active layer (e.g., layer 202-1 extends beyond layer 202-0 as shown in FIG. 2C described below), allowing the higher active layer to access its particular decoder and other circuitry within the semiconductor substrate 201 through certain buried contacts.

[0038] 2C shows a cross section in the YZ plane through buried contacts 205-0 and 205-1, which connect N+ sublayers 223 in active layers 202-0 and 202-1 to contacts 206-0 and 206-1 in semiconductor substrate 201. As shown in FIG. 2C, buried contacts 205-0 and 205-1 connect contacts 206-0 and 206-1 in semiconductor substrate 201, e.g., N+ sublayers 223 in active layers 202-0 and 202-2, respectively. + The contacts 206-0 to 206-7 are connected to local bit or source lines formed from sublayer 223. Buried contacts for active layers 202-2 to 202-7 (not shown) are similarly provided to connect active layers 202-2 to 202-7 to active layers 202-2 to 202-7 (not shown) on semiconductor substrate 201. A precharge voltage V blmay be applied to each bit line or source line, and may be connected to an input terminal of a sense amplifier or a latch during a read operation. The switch circuit connects each of the contacts 206-0 to 206-7 to a programming voltage (V program) , prohibited voltage (V inhibit ), erase voltage (V erase ), or any of several specific voltage sources, such as a voltage V bl Or V ss In one embodiment described below, a virtual ground can be formed in sublayer 221 of each active layer using the relatively large parasitic capacitance C along the bit or source lines. In this embodiment, buried contacts and separate interconnects are not required for the bit or source lines formed from sublayer 221 of each of active layers 202-0 through 202-7.

[0039] Also shown in FIG. 2C are buried contacts 261-0 to 261-n for connecting global word lines to be formed along the X direction to contacts 262-0 to 262-n in the semiconductor substrate 201. These global word lines are provided for connecting corresponding local word lines 208w to be formed (see, for example, FIG. 2G below). Landing pads 264 are provided to allow connection to local word lines 208w not yet formed perpendicular to the top surface of the global word lines 261-0 and 261-n. Through switch circuits and global word line decoders, each of the global word lines 262-0 to 262-n can selectively or individually apply multiple stepped programming voltages (V program ), read voltage (V read ) and erase voltage (V erase ) and other reference voltage sources are shared.

[0040] These buried contacts, global word lines and landing pads may be formed by conventional photolithographic patterning and etching steps, deposition of one or more conductors, or alloying (eg, tungsten metal or tungsten silicide).

[0041] After the top active layers (e.g., active layer 202-7) are formed, trenches are etched through the active layers down to the bottom global word lines (or semiconductor substrate 201) using a strip-forming mask. The strip-forming mask consists of a pattern of a photoresist layer of elongated strips that run along the Y direction (i.e., perpendicular to the global word line strips that run along the X direction). Sequential anisotropic etches etch active layer 202-7 down to 202-0, and dielectric isolation layer 203-7 down to 203-0. The number of active layers etched is 8 in the example of FIG. 2C (more typically there are 16 or more active layers). The photoresist mask itself is not strong enough to hold the strip pattern and survive the multiple etches required to etch the lowest active layers. Therefore, reinforcement with a hard mask material such as carbon may be required, as known to those skilled in the art. The etch ends with the dielectric isolation above the landing pads of the global word lines. It may be advantageous to provide an etch stop barrier film, such as aluminum oxide, to protect the landing pad during the trench etch sequence.

[0042] FIG. 2D is a cross-sectional view in the XY plane through active layer 202-7 of a portion of memory structure 200 of FIG. 2A showing the formation of trenches 230 in memory structure 200 of FIG. 2A. Between adjacent trenches 230 are stacks of elongated active strips with high aspect ratios. To obtain the best etch results, the etch chemistry may have to be changed when etching materials of different sublayers, especially when metal sublayer 224 is present. The anisotropy of the multi-step etch is important because undercutting of the lower layer must be avoided as much as possible, and the active strips of the lower active layer (e.g., active layers in active layer 202-0) have the same width and gap spacing in adjacent active strips as the corresponding width and gap spacing in the active strips of the top active layer (i.e., active strips in active layer 202-7). Naturally, the more active layers in the stack to be etched, the more difficult it is to design the subsequent etch. To alleviate the difficulties associated with etching through, for example, 32 active layers, the etching may be done in sections, for example, of 8 layers each, as discussed by Kim, supra, on pp. 188-189. As shown in FIG. 2D, trench 230 extends along the Y direction.

[0043] One or more layers of charge trapping material are then conformally deposited on the sidewalls of the active strips in the trenches 230. The charge trapping layer is formed by first depositing or growing a thin tunneling dielectric film, typically a silicon dioxide layer or a silicon oxide-silicon nitride-silicon oxide ("ONO") triple layer, 2-10 nm thick, followed by depositing a 4-10 nm thick layer of charge trapping material, typically silicon nitride or silicon rich nitride or oxide or nanocrystals or nanodots embedded in the thin dielectric film, which is then capped with a blocking dielectric. The blocking dielectric may be a 5-15 nm thick layer, for example an ONO layer, or may be aluminum oxide, hafnium oxide, or some combination thereof. The memory element may be SONOS, TANOS, nanodot memory, isolated floating gate, or any suitable charge trapping sandwich structure known to those skilled in the art. The trench 230 must be wide enough to accommodate the storage elements on two opposing sidewalls of adjacent active strips and the vertical local word line shared by the TFTs on those opposing sidewalls. Figure 2E is a cross-sectional view in the XY plane through the active layer 202-7 of a portion of the memory structure 200 of Figure 2, showing the charge trapping layers 231L and 231R deposited on opposing sidewalls of the active strips along the trench 230.

[0044] Bottom global wordline contact openings are photolithographically patterned on top of layer 202-7 and exposed by anisotropic etching through the charge trapping material at the bottom of trenches 230, stopping at bottom global wordline landing pads (e.g., global wordline landing pads 264 in FIG. 2C). In one embodiment described in connection with FIG. 2I below, only alternate rows of trenches 230 (e.g., rows with wordlines formed therein assigned to odd addresses) should be etched down to the bottom global wordlines. In some embodiments, a very thin layer of polysilicon (e.g., 2-5 nm thick) is deposited prior to etching to protect the vertical surfaces of the blocking dielectric on the sidewalls of trenches 230 during the anisotropic etching of the charge trapping material at the bottom of trenches 230.

[0045] Doped polysilicon (e.g., PT polysilicon) can then be deposited over the charge trapping layer to form control gates or vertical local word lines. + Doped polysilicon is preferred because it has a higher work function than N+ doped polysilicon. Alternatively, a metal with a high work function relative to SiO2 (e.g., tungsten, tantalum, chromium, or nickel) can be used to form the vertical local word lines. The trench 230 is formed of P +The trenches 230 may be filled with doped polysilicon or metal. In the embodiment of FIG. 2I described below, the doped polysilicon or metal in alternating columns of trenches 230 (i.e., rows hosting local word lines assigned to odd addresses) makes ohmic contact with the bottom global word lines. The polysilicon in the other trenches 230 (i.e., rows hosting local word lines assigned to even addresses) is isolated from the bottom global word lines (these local word lines will be contacted by the top global word lines routed over the top active layer). The photoresist and hard mask can now be removed. A CMP step can then be used to remove the doped polysilicon from the top surface of each block. FIG. 2F shows the deposition of polysilicon 208 filling the trenches 230.

[0046] FIG. 2G shows that after photolithographic patterning and etching steps on the memory structure of FIG. 2, the local word lines 208w are created by removing the exposed portions of the deposited polysilicon 208 and filling the resulting shaft with insulating material 209. Since the removal of the doped polysilicon in this case is a high aspect ratio etch in a fairly narrow space, a hard mask may be required using the techniques described above. The resulting shaft may be filled with insulating material 209 or left as an air gap. The mask pattern exposing the doped polysilicon for drilling is parallel strips extending along the X direction, so that they may coincide with the global word lines that are required to be formed to contact the local word lines 208w in one embodiment.

[0047] In FIG. 2G, the portions of the charge trapping layers 231L and 231R adjacent to the insulating material 209 remained after removal of the corresponding portions of the deposited polysilicon 208. In some embodiments, these portions of the charge trapping layers 231L and 231R can be removed by a conventional etching process before filling the shaft with the insulating material 209. Etching of the charge trapping material in the shaft can be performed simultaneously with or after removing the doped polysilicon. The subsequent etch also removes the fine polysilicon stringers left by the anisotropic etch. Such polysilicon stringers cause undesirable charge leakage and act as resistive leakage paths between adjacent vertical local word lines. Removal of such charge trapping material also eliminates lateral diffusion of trapped charge between one TFT and other TFTs immediately to the left and right along the same string.

[0048] FIG. 2H shows a cross-sectional view in the XZ plane through a row of local vertical word lines 208w (also shown in FIG. 2G in the XY plane) showing active strips in active layers 202-7 and 202-6. As shown in FIG. 2H, each active layer has N + Sublayer 221, P-Sublayer 222, N +2H. In one embodiment, the N+ sublayer 221 (e.g., source line) is connected to a ground reference voltage Vss (not shown) and the N+ sublayer 223 (e.g., bit line) is connected to a contact of the substrate 201 in the manner shown in FIG. 2C. Thus, the local word line 208w, that portion of the active layer 202-7 or 202-6 facing the word line 208w, and the charge trapping layer 231L between the word line 208w and the portion of the active layer 202-7 or 202-6 form a storage element or memory TFT, as indicated by references 281 and 282 in FIG. 2H. Opposite the TFTs 281 and 282 on the opposite side of the word line 208W are TFTs 283 and 284, respectively, incorporating the charge trapping layer 231R. On the other side of the active strips 202-6 and 202-7 that provide the TFTs 283 and 284 are TFTs 285 and 286. Thus, the configuration shown in FIG. 2H is the highest density TFT configuration, with each vertical word line shared by two active strips along its side, and each active strip shared by two word lines along its side, resulting in N + Sublayer 223 is connected to the appropriate voltage required for operation of the current memory transistor (e.g., program voltage V prog , prohibited voltage V inhibit , erase voltage V erasc or read reference voltage V bl ) as shown in FIG. 2H. The additional metal sublayer 224 increases the conductivity of the bit lines to facilitate operation of the memory device. In another embodiment, N of any of the active layers 202-0 to 202-7 may be used. + Sublayer 221 may be left floating. In each active layer, one or more local vertical word lines (called "precharge word lines": e.g., precharge word line 208-chg in FIG. 2G) may be used as non-memory TFTs. When the appropriate voltage is applied (i.e., turning the precharge TFT to the "on" state), each precharge word line instantaneously flips sublayer 222, causing N+ Sublayer 221 is N + On sublayer 223, voltage V ss When the precharged word line is voltage-reduced (i.e., returned to the "off" state) and all other word lines on either side of the strip are also "off," operation of the device proceeds and N + Sublayer 221 is connected to a precharge voltage V ss remains electrically charged as a virtual reference at + This is because the parasitic capacitance of the strip capacitor of sublayer 221 is large enough to hold charge long enough to support program and read operations (see below).

[0049] Each local word line 208w can be used to read, write or erase charges stored in a designated one of the TFTs formed in each of the active layers 202-0 to 202-7, either in the charge trapping portion 231L or 231R, provided that an appropriate voltage is applied to the local word line 208w. Alternatively, in an alternative embodiment, described in connection with FIG. 2K below, each local word line 208w can be used to read, write or erase charges stored in a designated one of the TFTs formed in each of the active layers 202-0 to 202-7, either in the charge trapping portion 231L or 231R, provided that an appropriate voltage is applied to the local word line 208w. However, as shown in FIG. 2K, only one of the two sides of the active layers 202-0 to 202-7 is formed as an accumulation TFT, thereby eliminating the need for global word lines on both the bottom and top sides in this embodiment.

[0050] An insulating dielectric or oxide may then be deposited and its surface planarized. Contacts to the semiconductor substrate 201 and the local word lines 208w may be patterned and etched by photolithography. In one embodiment described in connection with FIG. 2I and corresponding FIG. 4A, contacts to the local word lines 208w are provided to the local word lines assigned to even addresses (local word lines assigned to odd addresses are arrayed with the lowest global word lines). For the embodiment shown in FIG. 2J, contacts are provided to all local word lines, but the local word lines are staggered with respect to the opposing word lines, as shown in FIG. 4B. A deposited metal layer provides the top metal layer and contacts. Such a metal layer may be provided by first forming a thin TiN layer, followed by a low resistivity metal layer (e.g., tungsten). The metal layer is then patterned by photolithography to form the top global word lines. Alternatively, these global word lines may be provided by a copper damascene process. In one embodiment, these global word lines are horizontal, running along the X direction, and electrically connect with contacts formed in the isolation oxide (i.e., contacting local word lines 208w) and contacting the semiconductor substrate 201 (not shown). Of course, other mask and etch process flow possibilities known to those skilled in the art can be used to form even and odd addressed local word lines and appropriately connect them to the global word lines, with some embodiments running from the top of the array through the top global word line or from the bottom of the array through the bottom global word line, and both global word lines.

[0051] FIG. 2I includes word lines 208g-s, each of which is connected to one of the global word lines 208g-a in FIG. 2H and routed to one or more layers above the active layers 202-0 to 202-7, or routed to one or more layers below the active layers between the global active layer 202-0 and the substrate 201. The local word lines 208w coupled to the bottom global word lines may be assigned odd addresses, and the local word lines 208w coupled to the top global word lines may be assigned even addresses. FIG. 4A is a cross-sectional view in the XY plane showing contacts 291 connecting the local word lines 208w to the global word lines 208g-a. (In contrast, in the embodiment of FIG. 2K and corresponding FIG. 4C, the local word lines 208w control each active strip on only one of the sides of the active strip.)

[0052] FIG. 2J illustrates an alternative embodiment to that of FIG. 2I, illustrating an embodiment of the invention in which only top global wordlines are provided (or alternatively, only bottom global wordlines are provided). In this embodiment, the local wordlines along one edge of the active strip are staggered relative to the local wordlines on the other edge of the active strip. This is as shown in FIG. 4B, and the corresponding cross-sectional view in the XY plane showing contacts 291 connecting local wordlines 208w to top global wordlines 208g-a (or bottom global wordlines 208g-s) in a staggered configuration. This embodiment simplifies the process flow by omitting process steps required to form the bottom global wordlines (or possibly the top global wordlines). In the embodiment of FIG. 2I and corresponding embodiment of FIG. 4A, both top and bottom global word lines are provided, and two TFTs can be provided in each active layer of each active strip within one pitch of the global word lines: one TFT is formed using one sidewall of the active strip and controlled from the bottom global word line, and the other TFT is formed using the other sidewall of the active strip and controlled from the top global word line (pitch is one minimum line width plus the minimum required spacing between adjacent lines). In contrast, as shown in FIG. 2J and corresponding FIG. 4B, only one TFT can be provided within one global word line pitch in each active layer. The two local word lines 208w on the two sides of each strip may be staggered relative to each other, and two global word line pitches require both contacts. The penalty for the staggered embodiment is giving up the inherent double density TFTs, where both ends of each active strip provide a TFT within one pitch of each global word line.

[0053] FIG. 2K shows each of the local word lines 208w controlling a TFT formed from active strips on opposite sides of the local word line according to one embodiment of the present invention. FIG. 4C is a corresponding cross section in the XY plane showing the contacts 291 connecting the local word lines 208w to the global word lines 208g-a and the separations 209 between adjacent pairs of active strips. As shown in FIG. 2K, each TFT is formed from one of a double pair of active strips on opposite sides of a common local word line, and each double pair of active strips includes an oxide or void 209 from the adjacent double pair of active strips formed in a similar manner. The separation trenches between adjacent pairs of active strips contain charge trapping material 231 or polysilicon 208. After the local word lines 208w are defined by etching, the protected separation trenches are filled with oxide or dielectric material 209 or left as voids.

[0054] FIG. 3 shows that sublayer 221 of each active strip (see, for example, FIG. 2B-1) is connected by hardwire 280 (dotted line) to a source reference voltage Vss by a metal or N+ doped polysilicon conductor. Each of hardwires 280 may be connected independently, so that the source voltages of different layers do not need to be the same. Because sublayer 221 is formed only after sublayer 223 is formed, the metal or N+ doped polysilicon conductor for connecting sublayer 221 to the reference voltage Vss requires one or two additional patterning and etching steps for each of active layers 202-0 to 202-7, thus increasing processing costs. To avoid this additional cost, a large intrinsic parasitic capacitance C of each active NOR string is used. By utilizing the inherent parasitic capacitance C, no hard wires 280 are required and the sublayer 221 of each active strip is left floating after being temporarily precharged to voltage Vss by the action of a local vertical precharge TFT controlled by the precharge wordline 208-chg from the bitline sublayer 223. In a long horizontal NOR string (e.g., with more than 1,024 memory TFTs), several precharge TFTs can be provided on either side of the active strip (e.g., one for every 512 TFTs). Assuming a local capacitor between each local wordline as one plate and the N+ / P- / N+ active layer as the other plate, each such TFT typically has a capacitance of about 3×10 -18 Since there are about 2,000 TFTs contributing capacitance from each side of the strip, the total capacitance C of the string approaches 0.01 picofarads, which is enough to maintain the precharge voltage for well over the milliseconds required to perform a read operation immediately following a write, erase or precharge operation. The capacitance C can be increased by lengthening the NOR string to accommodate several thousand TFTs along each side of the string, correspondingly increasing the capacitance C by 0.01 picofarads. +It increases the retention time of the precharge voltage Vss on the sublayer 221. However, a longer NOR string increases the + Sublayers 221 and N - This can result in increased leakage current between the sublayer 223 and the TFTs, which can disrupt the detected current when reading the single TFT being addressed. Also, the potentially longer time it takes to precharge a large capacitor during a read operation can conflict with low read latency (i.e., fast read access time) requirements. Speeding up the precharging of the capacitance C of a long NOR string typically requires the provision of multiple precharge TFTs, which may be distributed throughout the entire length of the NOR string.

[0055] 3 also shows an optional connection 290 to the P-sublayer 222 for accessing a back bias voltage Vbb from the substrate 201. A common technique is to use a negative Vbb voltage to modulate the threshold voltage of the TFTs along each active strip, thereby reducing the leakage current subthreshold between the N+ source sublayer 221 and the N+ drain sublayer 223. A high positive voltage Vbb may be applied during an erase operation to tunnel erase TFTs whose control gates are held at ground potential.

[0056] Since the TFTs in a NOR string are connected in parallel, the read operating conditions of the NOR string of the present invention should preferably ensure that all TFTs along both ends of an active strip are operated in enhancement mode, i.e., they have a positive threshold voltage between their control gates 151n and their source 221 voltage Vss, and leakage current between the N+ sublayers 221 and 223 of an active strip is suppressed when the control gates on both sides of the strip are all held at or below the voltage Vss. This enhancement threshold voltage is determined by the presence of a P-dopant concentration (typically 1×10 16 ~1×10 17 / cm 3 A concentration of boron (N) may be doped into the active string, resulting in a native TFT threshold voltage of about 1 volt, which may be achieved by holding all unaddressed local word lines on either side of the active strip at 0 volts. Alternatively, if any of the TFTs along the active string have a negative threshold voltage (i.e., a depletion mode threshold voltage), then the N + The Vss voltage on sublayer 221 is set to about 1.5 volts, and N + V on sublayer 223 bl Leakage suppression can be achieved by raising the voltage from about 1.5 volts to about 0.5 volts while keeping all local wordlines at 0 volts. This has the same effect as holding the wordline voltage at -1.5 volts with respect to the source, thereby suppressing leakage through TFTs that are at slightly depleted threshold voltages. Also, after erasing the NOR string, the erase operation should preferably include a soft programming operation to shift all TFTs that have been over-erased to their depletion mode threshold voltages back to their enhancement mode threshold voltages.

[0057] The charge trapping materials mentioned above (e.g., ONO stacks) have long data retention times (typically measured in years) but low endurance. Endurance is a measure of the degradation of a memory transistor after a number of write-erase cycles, and is usually considered low if it is less than 10,000 cycles. However, changing the charge trapping material to reduce retention time can significantly increase endurance (e.g., increasing endurance to tens of millions of write / erase cycles while reducing retention time to a few hours). For example, in an ONO film or a similar combination of charge trapping layers, the typically 6-8 nm silicon oxide tunnel dielectric can be thinned to 2 nm silicon oxide or less, or replaced entirely by a different dielectric (e.g., silicon nitride or SiN). Under a moderate positive control gate voltage, electrons are attracted by direct tunneling (different from Fowler-Nordheim tunneling) into the silicon nitride charge trapping layer, where they are temporarily trapped for minutes to hours or days. The charge trapping silicon nitride layer and the blocking layer of silicon oxide or aluminum oxide prevent these electrons from escaping to the control gate word line, but eventually back leak into the active sublayer (the electrons are negatively charged and repel each other). Even if the tunnel dielectric of 2 nm or less breaks down locally after overcycling, the trapped electrons are slow to leave the traps in the silicon nitride layer. Other combinations of charge storage materials can result in high durability but low retention ("semi-volatile") TFTs. Such TFTs may require periodic write refresh to replenish lost charge. Because such TFTs provide relatively fast read access times with low latency, the NOR string arrays of the present invention with such TFTs can be useful in applications currently obtainable with relatively slow DRAM.

[0058] The advantages of such a NOR string array over DRAM include lower cost per bit, since DRAM cannot be organized in 3D blocks, and much lower power consumption, requiring refresh cycles on the order of minutes or even hours, compared to the short refresh cycles of milliseconds for current DRAM technology. The NOR string array of the present invention incorporates periodic data refresh by modifying the composition of the charge trapping material (e.g., charge trapping layers 231L and 231R in FIG. 2E) and appropriately configuring the program / read / erase conditions.

[0059] According to another embodiment of the invention, the NOR string array can also be programmed using a channel hot electron injection method similar to that used in NROM / mirror bit transistors known to those skilled in the art. In NROM / mirror bit transistors, a charge representing one bit is stored at one end of the channel region adjacent to the junction with the drain region, and by reversing the polarity of the source and drain, a charge representing a second bit is programmed and stored at the opposite end of the channel region adjacent to the source junction. Typical programming voltages are 5 volts on the drain, 0 volts on the source, and 8 volts on the control gate. Reading both bits requires the opposite reading of the source and drain, as is well known to those skilled in the art. However, channel hot electron programming is much less efficient than tunnel programming, and therefore does not lend itself to the massively parallel programming possible with tunneling. However, the channel hot electron injection approach doubles the bit density, making it attractive for applications such as archival memory.

[0060] Next, an exemplary operation of the NOR string of the present invention will be described. (Read operation)

[0061] To read a TFT among many TFTs on an active strip, the TFTs on both sides of the active strip are first set to the "off" state, so that all global and local word lines in the selected block are held at 0 volts. In FIG. 3, the addressed NOR string either shares the sense circuitry among several NOR strings through a decoding circuit, or connects each NOR string directly to a dedicated sense circuit, so that many other addressed NOR strings sharing the same plane can be sensed in parallel. Each addressed NOR string is connected to a source (N + sublayer 221) is set to Vss~0V, which is also set to 0V with precharge wordline 208-chg either through hardwire 280 or through bitline connection 270 (in this case V bl are initially held at 0 volts during the precharge phase. After the precharge phase, the bit lines (i.e., N + Sublayer 223) is then coupled to V bl It is set to about 2 volts. V bl The voltage is the sense voltage at the sense amplifier for the addressed NOR string. An addressed global word line and all its associated vertical local word lines are raised from zero volts, typically to about 2 volts, while all other global word lines in the block are in the off state. When the addressed TFT is in the erased state (i.e., Vth ~ 1 volt), the bit line voltage V bl starts discharging towards the source voltage Vss. This voltage drop is detected by the respective sense amplifier. However, if the addressed TFT is in the programmed state (e.g., Vth, ~3 volts), the voltage drop is not detected.

[0062] When MLC is used (i.e., when more than one bit of information is stored in each TFT), the addressed TFT is driven to several threshold voltages (e.g., 1 volt (for erased state), 2.5 volts, 4 volts or 5.5 volts representing four states representing two bits of data). The addressed global word line and its local word lines can be raised in incremental voltage steps until continuity is detected in the addressed TFT by the respective sense amplifiers. Or, alternatively, a single word line voltage V bl can be applied (for example, V bl = 6 volts), voltage V bl The discharge rate of the can be compared to the discharge rate of each of several programmable reference voltages representing four voltage states representing the bit stored in the TFT. This approach can be extended to store eight states (for 3-bit MLC TFTs) or a succession of states, thereby effectively providing analog storage. The programmable reference voltages are stored in a dedicated NOR string in the same block as the reference NOR string, the block preferably being located in the same plane as the addressed NOR string. When MLC is used, more than one programmable reference NOR string may be provided to detect each of the programmed states. For example, if 3-bit MLC is used, there would be at least seven reference NOR strings. Preferably, a full set of reference NOR strings should be provided for each active layer and each block. The programmable reference NOR strings closely track the characteristics of the NOR operating strings in the same block due to read, program, and background leakage. Only TFTs on one of the two sides of the active strip can participate in the read operation, and each TFT on the other side of the active strip must be set to the "off" state. Other methods of reading the correct state of a multi-state TFT are known to those skilled in the art.

[0063] Reading is faster because in a NOR string, only the TFT being read needs to be "on" compared to a NAND string, where the TFT in series with the one being read must be "on". In embodiments where metal sublayer 224 is not provided in the active layer (see, e.g., 220a in FIG. 2B-1), for a string with 1,024 TFTs on each side, a typical resistance R is ∼100,000 ohms and a typical capacitance C ∼10 -14 Farads, resulting in an RC time delay on the order of 1 nanosecond. Even with 4,098 TFTs in each NOR string on either side of the active strip, the RC delay time is less than 20 nanoseconds. If a metal sublayer 224 is provided to reduce the resistance R of the active strip, the time delay could be significantly reduced. To further reduce the read latency, some or all planes with selected active blocks can have their read voltages Vss and V bl The TFTs in the array are always precharged to 0 V, making them ready to sense the addressed TFT immediately (i.e., eliminating the need for a precharge step just before a read operation). Such a ready standby also requires very little standby power, since only a very small current is needed to periodically recharge the capacitor C to compensate for charge leakage. Within each block, all strings, all 8 or more planes, can be precharged to allow fast reading; for example, after reading all strings in plane 207-0 (FIG. 2A), plane 207-1 can be precharged to its Vss and V bl is already set for the previous read and can therefore be read quickly.

[0064] In memory block 100, only one TFT per NOR string can be read in one operation. In a plane with 8000 NOR strings, if each NOR string is connected to its own sense amplifier, all 8000 TFTs sharing a common global word line can be read simultaneously. If each sense amplifier is shared, for example, if one string decoding circuit is used between four NOR strings in the same plane, four read operations need to be performed in four successive steps, with each read operation involving 2000 TFTs. Each plane can provide its own dedicated set of sense amplifiers, or alternatively, a set of sense amplifiers can be shared between the NOR strings of eight or more planes by the plane decoding selector. Providing separate sense amplifiers for each plane allows simultaneous read operations of the NOR strings of all planes, with a corresponding increase in read throughput. However, such throughput comes at the cost of the extra chip area required for the additional sense amplifiers, and can also result in ground voltage bounce when a large number of TFTs are read at once. In this regard, the embodiment is particularly advantageous because it sets a virtual Vss voltage via a precharged capacitor C, and because the source voltages Vss of all NOR strings are not connected to the chip's Vss ground line, such ground voltage bounce is eliminated.

[0065] (Program (write) and program inhibit operations)

[0066] There are several ways to program an addressed TFT to its intended threshold voltage. The most common method is by tunneling, i.e., direct tunneling or Fowler-Nordheim tunneling. Either of these tunneling and charge trapping mechanisms are so efficient that only a small current is required to program the TFT, allowing concurrent programming of tens of thousands of TFTs with minimal power consumption. To illustrate, programming by tunneling requires a 20 volt pulse of 100 microseconds (μs) duration applied to the addressed word line (control gate) and 0 volts applied to the active strip (see, e.g., 202-0 in FIG. 2A). Under these conditions, the N+ source and drain of the TFT (see sublayers 221, 223 in FIG. 2B-1) and the P-channel of the TFT (sublayer 222) are inverted at the surface and electrons tunnel to the charge trapping layer. TFT programming can be inhibited by applying a half-select voltage (e.g., 10 volts in this example). Program inhibition can be accomplished, for example, by either lowering the word line voltage to 10 volts while keeping the word line voltage at 0 volts, or by raising the active strip voltage to 10 volts while maintaining the word line voltage at 20, or by some combination of the two. Only one TFT on an addressed active strip can be programmed at a time, but the TFTs on other strips can be programmed in the same programming cycle. When programming one of many TFTs of an addressed active strip on one side (e.g., an even addressed NOR string), all other TFTs of that NOR string are program inhibited, as are the active strips on the other side (e.g., all TFTs in an odd addressed NOR string).Once an addressed TFT is programmed to its designated state's target voltage threshold, programming inhibition of that TFT is necessary because overshooting the target voltage would cause unnecessary stress on the TFT. If an MFC is used, overshooting the target voltage could cause an overstep or merging at the threshold voltage of the next higher target threshold voltage state. It should be noted that all TFTs in adjacent active strips in the same plane that share the same global word line and associated local word line are therefore exposed to the 20 volt programming voltage and need to be programmed inhibited. Similarly, all TFTs on other planes that are in the same block and share the same global word line and associated local word line are therefore exposed to the 20 volt programming voltage and need to be programmed inhibited. All of these program and program inhibit conditions are satisfyable under the present invention because the even and odd sides of each active strip are controlled by different global word lines and their associated local word lines, and the voltage of each active strip, no matter which plane it is in, can be set independently of all other active strips or other planes.

[0067] In one example, all TFTs in a block are first erased to a threshold voltage of about 1 volt. Then the voltage on the active strip of each addressed TFT is set to 0 volts (through connection 270 with precharge word line 208-chg, or through connection 280, as shown in FIG. 3) if the addressed TFT is to be programmed. Otherwise, the voltage on the active strip of the addressed TFT is set to 10 volts if it is to remain in the erased state (i.e., program inhibited). Next, the global word line associated with the addressed TFT is raised to 20 volts in one step, or in short-term incremental voltage steps, starting from about 14 volts. Such incremental voltage increase steps reduce electrical stress on the TFTs and avoid overshooting the target threshold voltage. All other global word lines in the block are set to half-select 10 volts. All active strips in all non-addressed planes in the block, and all non-individually addressed active strips in the addressed plane, are also set to 10 volts or may be floating. These active strips are strongly capacitively coupled to the 10 volt local word lines and are therefore floating close to 10 volts. Incrementally higher voltage programming pulses are applied following the read cycle to determine whether the addressed TFT has reached its target threshold voltage. Once the target threshold voltage is reached, the active strip voltage is raised to 10 volts (or alternatively raised close to 10 volts when the strips are floating and all but one addressed global word line in the block have been raised to 10 volts), and further programming is inhibited while the global word lines continue to program other addressed strips in the same plane that have not yet achieved their target threshold voltage. The programming sequence ends when all addressed TFTs are read verified to be correctly programmed. When MLC is used, programming of the correct one of the multiple threshold voltage states can be accelerated by first precharging the capacitors C of all addressed active strips to one of several voltages (e.g., 0, 1.5, 3.0, or 4.5 volts if two bits of information are stored in each TFT) (e.g., connection 270 and precharge word line 208-chg, see FIG. 3). A 20 volt pulse is then applied to the addressed global word line, exposing the TFTs to different effective tunneling voltages (i.e., 20, 18.5, 17, or 15.5 volts, respectively), which then settle to the voltage that results in the correct one of the four thresholds programmed in a single course programming step. Fine programming pulses can then be applied at the individual TFT level.

[0068] Due to the intrinsic capacitance C of all active strips in a block, all active strips on all planes in the block can be successfully set to a precharge voltage state before applying a high voltage pulse to the addressed global word line. As a result, concurrent programming of a large number of TFTs is achievable. Individual read verify and, if necessary, reset of properly programmed active strips to a program inhibit mode can then be performed. Precharging is advantageous because programming times are relatively long (e.g., about 100 microseconds), and precharging all capacitors C or read verifying the addressed TFTs can be performed over a 1.000 times shorter time window. It is therefore advantageous to program as many TFTs as possible in a single global word line programming sequence.

[0069] (Erase operation)

[0070] In some charge trapping layers, erasure is achieved by reverse tunneling of trapped charge, which can be quite slow (e.g., requiring an erase pulse of tens of milliseconds). Erase operations are therefore performed frequently at the block level, often in the background. A typical block would have 8,000 active strips with 4,000 TFTs on each side, for 8 planes, resulting in a total of 5 billion TFTs in a block, so that a 1 terabit chip would contain about 1,000 such blocks if each TFT stores 2 bits of information. Ideally, block erase is performed by applying about 20 volts to the P-sublayer 222 (see, e.g., FIG. 2B-1) of each active strip via connection 290, while keeping all global wordlines in the block at 0 volts. The duration of the erase pulse should be such that most TFTs are erased to a slight enhancement mode threshold voltage between 0 and 1 volt. Some TFTs may overshoot and be erased to depletion mode (i.e., have a slightly negative threshold voltage). Such TFTs are required, as part of the erase command, to be programmed to a small enhancement mode threshold voltage following the end of the erase pulse.

[0071] Alternatively, instead of applying Vbb to the P-sublayer, sublayers 221 and 223 on all active strips are raised to about 20 volts while all global wordlines are held at zero volts for the duration of the erase pulse. This scheme requires the strip selection decoders (206-0, 206-1 in FIG. 2C) to use transistors that can withstand 20 volts at their junctions. Alternatively, hold all but the addressed global wordline at 0 volts, pulse the addressed global wordline to -20 volts, and hold all active strips on planes 202-0 to 202-7 at zero volts. This method erases only the XZ slices of all TFTs touched by one addressed global bitline.

[0072] Implementing erase for an NROM TFT can be accomplished using the conventional NROM erase mechanism of band-to-band tunneling induced hot hole injection. To neutralize the charge of the trapped electrons, apply -5 volts to the word line, zero volts to the source sublayer 221, and 5 volts to the drain sublayer 223.

[0073] The above detailed description is provided to illustrate specific embodiments of the present invention and is not intended to be limiting. Many variations and modifications are possible within the scope of the present invention, which is set forth in the appended claims.

Claims

1. 1. A memory structure comprising: a semiconductor substrate having a planar surface, the semiconductor substrate having circuitry formed on or within the planar surface; an insulating layer disposed on the semiconductor substrate over the circuitry; a first active strip and a second active strip formed on the insulating layer, each of the first and second active strips extending along a first direction parallel to the planar surface and separated from each other by a predetermined distance along a second direction also parallel to the planar surface, each of the first and second active strips having (i) a channel material for providing a respective channel region for a plurality of thin film field effect transistors in a NOR memory string, and (ii) a source material and a drain material for forming a common source region and a common drain region, respectively, of the plurality of thin film field effect transistors in the NOR memory string, the plurality of thin film field effect transistors being supported in operation by the circuit; a storage material disposed on both side walls of each of the first and second active strips; a plurality of local word line conductors, each of which extends lengthwise along a third direction perpendicular to the planar surface, each local word line conductor being spaced from either the first active strip or the second active strip by the storage material; the plurality of thin film field effect transistors of the NOR memory strings in each of the first and second active strips are storage transistors whose operation is supported by the circuit; the plurality of thin film field effect transistors are formed from the channel region, the common drain region, the common source region, the storage material in the active strip, and the plurality of local word line conductors along sides of the active strip; A memory structure comprising: a first insulating layer and a second insulating layer, the first insulating layer being electrically connected to the first insulating layer and the second insulating layer being electrically connected to the first insulating layer and the second insulating layer being electrically connected to the second insulating layer.

2. 2. The memory structure of claim 1, 11. A memory structure, wherein each of the first and second active strips further comprises a dielectric material selected from the group consisting of silicon oxide, silicon nitride, and air gaps.

3. 2. The memory structure of claim 1, further comprising an interconnect; said common source region and said common drain region being connected by an interconnect to said circuitry on or within said semiconductor substrate.

4. 2. The memory structure of claim 1, further comprising two or more buried contacts formed on the planar surface of the semiconductor substrate; At least one of said common source region and said common drain region is connected to said circuitry on or within said semiconductor substrate by said buried contact.

5. 2. The memory structure of claim 1, the channel region of each of the first and second active strips, the common drain region, the common source region, the storage material, and the local word line conductors along sides of each active strip form a plurality of storage transistors.

6. 6. A memory structure as claimed in claim 5, comprising: The memory structure, wherein the plurality of storage transistors form a plurality of NOR memory strings.

7. 6. A memory structure as claimed in claim 5, comprising: further comprising a plurality of precharge devices each associated with one of the first and second active strips; A memory structure characterized in that each precharge device precharges the common source region of the active strip to a predetermined voltage prior to a read, program, erase, or inhibit operation of the plurality of storage transistors on the active strip associated with the precharge device.

8. 8. The memory structure of claim 7, 11. A memory structure comprising: a first region having a first common source region and a second common source region, the first region having a first predetermined voltage, the second region having a first predetermined voltage, the first region having a first predetermined voltage, the second region having a first predetermined voltage, the third region having a first predetermined voltage, the

9. 9. The memory structure of claim 8, The memory structure, wherein the predetermined voltage has a magnitude that is determined depending on whether a read, program, erase, or inhibit operation is being performed.

10. 8. The memory structure of claim 7, A memory structure, wherein each precharge device includes one or more precharge transistors having a different configuration than the storage transistors.

11. 8. The memory structure of claim 7, the plurality of storage transistors form a plurality of NOR memory strings; 11. A memory structure comprising: in each NOR memory string, the common source region serves as a shared virtual ground reference and the common drain region serves as a common bit line for the plurality of storage transistors.

12. 6. A memory structure as claimed in claim 5, comprising: A memory structure, wherein charge stored in the storage material of each storage transistor represents data stored in the storage transistor.

13. 13. The memory structure of claim 12, The circuitry includes a voltage source for selectively applying a predetermined configuration of voltages to each storage transistor to read, program, inhibit, or erase data stored in the storage transistor.

14. 14. The memory structure of claim 13, A memory structure in which the data represents two or more bits of binary information stored in charge-trapping sandwich structures that are storage elements.

15. 14. The memory structure of claim 13, A memory structure, wherein the data represents a sequence of states stored in an analog memory.

16. 6. A memory structure as claimed in claim 5, comprising: the plurality of storage transistors form a plurality of NOR memory strings; 11. A memory structure comprising: a memory cell including: a first NOR string having a first gate voltage and a second gate voltage; a second NOR string having a second gate voltage and a third gate voltage; a memory cell including a first gate voltage and a second gate voltage; a memory cell including a first gate voltage and a second gate voltage;

17. 17. The memory structure of claim 16, 1. A memory structure comprising: a common source region or a common drain region of said second active strip being floated or precharged to an inhibit voltage while any storage transistor is addressed for programming or erasing in said first active strip.

18. 17. The memory structure of claim 16, 11. A memory structure comprising: storage transistors associated with said first and second active strips, said storage transistors being programmed in a single, concurrent program operation.

19. 20. The memory structure of claim 18, During the parallel program operation, the common source regions of each of the first and second active strips are appropriately precharged to a predetermined voltage associated with a program or inhibit operation, and then a pulse of a programming voltage is applied to one or more addressed local word line conductors, and the parallel program operation is terminated after all storage transistors associated with the addressed local word line conductors are read and verified to have reached their intended programmed states.

20. 20. The memory structure of claim 19, A memory structure, wherein the programming voltage is one of several programming voltages in a programming sequence, the programming voltages representing different data values.

21. 13. The memory structure of claim 12, The memory structure wherein the circuitry further comprises one or more sense amplifiers for sensing data stored in the storage transistors.

Images