Display device

Abstract

To enhance device characteristic as well as reliability of a device even when arranging a semiconductor layer on a gate electrode layer, a source electrode layer, and a drain electrode layer.SOLUTION: In a structure comprising a gate electrode layer; a gate insulation layer arranged on the gate electrode layer; a source electrode layer and a drain electrode layer arranged so as to overlap a part of the gate electrode layer via the gate insulation layer; and a semiconductor layer arranged on the gate insulation layer, the source electrode layer, and the drain electrode layer, film thickness of the gate insulation layer positioned in a region between the source electrode layer and the drain electrode layer is set to be smaller than film thickness of the gate insulation layer arranged between the gate electrode layer and the source electrode layer, and of the gate insulation layer arranged between the gate electrode layer and the drain electrode layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. [Background technology]

[0002] In recent years, thin film transistors (also called TFTs) have been fabricated using oxide semiconductors, and electronic devices For example, Patent Documents 1 and 2 describe the technology for applying oxide semiconductors. The conductive layer is made of zinc oxide or In-Ga-Zn-O oxide semiconductors, and is used to develop image display devices. The document discloses a technique for manufacturing a switching element for a semiconductor device.

[0003] In addition, various structures have been proposed as a structure of a transistor using an oxide semiconductor layer. For example, in the above-mentioned Patent Document 2 and Patent Document 3, a source is provided on a gate insulating layer. A bottom gate / bottom contact structure that forms an oxide semiconductor layer on the electrode layer and the drain electrode layer. The structure of the tetrahydrofuran type is shown. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2007-305658 A Summary of the Invention [Problem to be solved by the invention]

[0005] Generally, in order to reduce the driving voltage of a transistor and achieve high-speed operation, the gate insulating layer It is effective to reduce the film thickness. However, the bottom gate / bottom contact structure A gate electrode layer, a source electrode layer, and a drain electrode layer are connected via a gate insulating layer. In the case of partial overlap, as the thickness of the gate insulating layer becomes smaller, the gate electrode layer and the source There is a risk that a parasitic capacitance will be formed between the source electrode layer and the drain electrode layer, which may affect the device characteristics. As a result, there is a risk that the element characteristics will vary and the reliability of the element will decrease.

[0006] In addition, a source electrode layer and a drain electrode layer are formed so as to cover the end of the gate electrode layer via a gate insulating layer. When the electrode layer is provided, the thickness of the gate insulating layer covering the end of the gate electrode layer is small. This can lead to leakage between the gate electrode layer and the source electrode layer or the drain electrode layer. This occurs.

[0007] In view of the above problem, a semiconductor layer is provided over a gate electrode layer, a source electrode layer, and a drain electrode layer. Even in such a case, the objective is to improve the element characteristics and reliability. It shall be one. [Means for solving the problem]

[0008] A gate electrode layer, a gate insulating layer provided on the gate electrode layer, and a gate insulating layer a source electrode layer and a drain electrode layer provided so as to overlap a part of the gate electrode layer; In a structure having a semiconductor layer provided on a gate insulating layer, a source electrode layer, and a drain electrode layer, The thickness of the gate insulating layer located between the source electrode layer and the drain electrode layer is set to be equal to the thickness of the gate insulating layer. A gate insulating layer or a gate electrode layer and a drain electrode layer are provided between the gate electrode layer and the source electrode layer. The thickness of the gate insulating layer is set to be smaller than the thickness of the gate insulating layer provided between the electrode layers. The parasitic capacitance between the source electrode layer and the drain electrode layer and the gate electrode layer is reduced, and As a result, the device characteristics can be improved.

[0009] Another embodiment of the disclosed invention is a gate electrode layer provided over a substrate; A gate insulating layer is provided so as to overlap a part of the gate electrode layer via the gate insulating layer. A source electrode layer and a drain electrode layer are formed on the gate electrode layer. a gate insulating layer disposed in a region between the drain electrode layers and the source electrode layer; an oxide semiconductor layer provided on the gate electrode layer and the drain electrode layer; The thickness of the gate insulating layer located in the region between the gate electrode layer and the drain electrode layer is A gate insulating layer provided between the source electrode layer or between the gate electrode layer and the drain electrode layer. The thickness of the gate insulating layer is smaller than the thickness of the gate insulating layer.

[0010] Another embodiment of the disclosed invention is a gate electrode layer provided over a substrate; a first insulating layer provided on the first insulating layer so as to overlap a part of the gate electrode layer; a second insulating layer provided on the first insulating layer and a gate electrode layer provided on the second insulating layer; A source electrode layer and a drain electrode layer provided so as to overlap with the gate electrode layer. and is provided in contact with the first insulating layer located in a region between the source electrode layer and the drain electrode layer, and further comprising an oxide semiconductor layer provided over the source electrode layer and the drain electrode layer. In addition, in the region between the source electrode layer and the drain electrode layer on the gate electrode layer, The thickness of the first insulating layer located between the gate electrode layer and the source electrode layer is set to be equal to the thickness of the first insulating layer located between the gate electrode layer and the source electrode layer. The thickness of the first insulating layer provided between the gate electrode layer and the drain electrode layer is smaller than the thickness of the first insulating layer. It may be possible to do so.

[0011] Another embodiment of the disclosed invention is a gate electrode layer provided over a substrate; A first insulating layer and a second insulating layer are laminated in this order, and a source electrode layer and a drain electrode layer provided to overlap with a part of the gate electrode layer with an insulating layer therebetween; and a second electrode layer located on the gate electrode layer and between the source electrode layer and the drain electrode layer. An oxide semiconductor provided in contact with the insulating layer and on the source electrode layer and the drain electrode layer. A conductive layer is provided on the gate electrode layer and is located in a region between the source electrode layer and the drain electrode layer. The thickness of the second insulating layer provided between the gate electrode layer and the source electrode layer is set to be equal to the thickness of the second insulating layer provided between the gate electrode layer and the source electrode layer. and the thickness of the second insulating layer provided between the gate electrode layer and the drain electrode layer is smaller than the thickness of the second insulating layer. It is characterized by:

[0012] In one embodiment of the disclosed invention, a gate electrode layer is formed over a substrate, and a gate a source electrode layer and a drain electrode layer are formed on the gate insulating layer; An upper portion of the gate insulating layer provided in a region between the electrode layer and the drain electrode layer is etched. By this, the thickness of the gate insulating layer located in the region between the source electrode layer and the drain electrode layer is reduced. A gate insulating layer provided between the gate electrode layer and the source electrode layer or a gate insulating layer between the gate electrode layer and the drain electrode layer The thickness of the gate insulating layer provided between the gate electrode layer and the source electrode layer is set to be smaller than that of the gate insulating layer. The present invention is characterized in that an oxide semiconductor layer is formed over the electrode layer and the drain electrode layer.

[0013] In one embodiment of the disclosed invention, a gate electrode layer is formed over a substrate, and a first forming a second insulating layer on the first insulating layer; and forming a source potential on the second insulating layer. a source electrode layer and a drain electrode layer, and a region between the source electrode layer and the drain electrode layer is provided The second insulating layer is etched to expose the first insulating layer, and the first insulating layer, The present invention is characterized in that an oxide semiconductor layer is formed over a source electrode layer and a drain electrode layer.

[0014] Note that an example of an oxide semiconductor that can be used in this specification is InMO 3 (Zn O) m (m>0, m is not necessarily an integer.) Here, M is the number of Lithium (Ga), Iron (Fe), Nickel (Ni), Manganese (Mn) and Cobalt (Co For example, M is Ga, and In addition to the case of Ga alone, the above-mentioned metals other than Ga, such as Ga and Ni, Ga and Fe, are also used. In addition, in the oxide semiconductor, a metal element contained as M may be selected. In addition to the group elements, impurity elements include Fe, Ni, and other transition metal elements, or oxides of the transition metals. In this specification, among the above oxide semiconductors, M is Those that contain at least gallium are called In-Ga-Zn-O oxide semiconductors, and Thin films using this material are called In-Ga-Zn-O non-single crystal films.

[0015] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to electro-optical devices, semiconductor circuits, and electronic devices, all of which are included in the category of semiconductor devices. In this specification, the term "display device" includes a light-emitting device and a liquid crystal display device. The light emitting element changes its brightness depending on a current or a voltage. The category includes elements that are controlled by inorganic EL (Electro Lu These include photoluminescence elements, organic electroluminescence elements, etc. Effect of the Invention

[0016] A gate electrode layer, a gate insulating layer provided on the gate electrode layer, and a gate insulating layer a source electrode layer and a drain electrode layer provided so as to overlap a part of the gate electrode layer; In a structure having a semiconductor layer provided on a gate insulating layer, a source electrode layer, and a drain electrode layer, The thickness of the gate insulating layer located between the source electrode layer and the drain electrode layer is set to be equal to the thickness of the gate insulating layer. A gate insulating layer or a gate electrode layer and a drain electrode layer are provided between the gate electrode layer and the source electrode layer. The thickness of the gate insulating layer provided between the electrode layers is set to be smaller than the thickness of the gate insulating layer. The parasitic capacitance between the source electrode layer and the drain electrode layer and the gate electrode layer is reduced, and As a result, the device characteristics can be improved. [Brief description of the drawings]

[0017] [Figure 1] 1A to 1C illustrate an example of a semiconductor device according to Embodiment 1 or 2. [Diagram 2] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to Embodiment 1. [Diagram 3] 1A to 1C illustrate an example of a method for manufacturing a semiconductor device according to Embodiment 2. [Figure 4] FIG. 13 illustrates an example of an apparatus used for plasma treatment in accordance with a second embodiment. [Diagram 5] 10A to 10C illustrate an example of a semiconductor device according to Embodiment 3. [Figure 6] 10A to 10C illustrate an example of a method for manufacturing a semiconductor device according to Embodiment 3. [Figure 7] 10A to 10C illustrate an example of a semiconductor device according to Embodiment 4. [Figure 8] 10A to 10C illustrate an example of a manufacturing method of a semiconductor device according to Embodiment 4. [Figure 9] 13A to 13C illustrate an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 10] 13A to 13C illustrate an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 11] 13A to 13C illustrate an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 12] 13A to 13C illustrate an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 13] 13A to 13C illustrate an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 14] 13A to 13C illustrate an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 15] 13A to 13C illustrate an example of a method for manufacturing a semiconductor device according to Embodiment 5. [Figure 16] 13A to 13C illustrate an example of a semiconductor device according to Embodiment 6. [Figure 17] 13A to 13C illustrate an example of a semiconductor device according to Embodiment 6. [Figure 18] 13A to 13C illustrate an example of a semiconductor device according to Embodiment 7. [Figure 19] FIG. 13 illustrates an example of a pixel equivalent circuit of a semiconductor device according to Embodiment 8. [Figure 20] 13 illustrates an example of a semiconductor device according to Embodiment 8. [Figure 21] 13 illustrates an example of a semiconductor device according to Embodiment 8. [Figure 22] FIG. 1 is a diagram illustrating an example of a usage pattern of electronic paper. [Diagram 23] FIG. 1 is an external view showing an example of an electronic book. [Figure 24] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Diagram 25] FIG. 1 is an external view showing an example of a gaming machine. [Figure 26] FIG. 1 is an external view showing an example of a mobile phone. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the described embodiment, and various changes in form and details are possible without departing from the spirit of the invention. It is obvious to those skilled in the art that the configurations according to the different embodiments can be combined as appropriate. In the configuration of the invention described below, the same parts Alternatively, the same reference numerals are used for parts having similar functions, and repeated explanations thereof will be omitted.

[0019] (Embodiment 1) First, a structure of a thin film transistor shown in this embodiment mode will be described with reference to FIG. Reveal.

[0020] The thin film transistor 250 shown in this embodiment has a gate electrode layer 210 formed over a substrate 200. 202, a gate insulating layer 204 provided on the gate electrode layer 202 and the substrate 200, and a gate a source electrode layer 206a and a drain electrode layer 206b provided over the source insulating layer 204; The source electrode layer 206a and the drain electrode layer 206b are provided on the source electrode layer 206 a and the drain electrode layer 206b. Further, the source electrode layer 206a and the drain electrode layer 2 The gate electrode layer 202 is provided so as to overlap with a part of the gate electrode layer 202 via the gate insulating layer 204. and a gate insulating layer located in the region between the source electrode layer 206a and the drain electrode layer 206b. 204 film thickness t2 The gate electrode layer 202 and the source electrode layer 206a are connected to each other. The gate insulating layer 204 and the gate electrode layer 202 and the drain electrode layer 206b are connected to each other. The thickness t of the insulating layer 204 1 It is designed to be smaller than the above (see FIG. 1(A)).

[0021] That is, a recess (a depression (hereinafter, The gate insulating layer 204 has a recess 207 therein. The semiconductor layer 210 is provided. When observed from a cross-sectional direction connecting the source electrode layer and the drain electrode layer, the gate insulating layer 20 This refers to the depression formed in 4.

[0022] In this manner, by using the structure shown in FIG. 1A, a gate electrode layer 202 is formed on the gate electrode layer 202. The source electrode layer 206a and the drain electrode layer 206b are connected to the gate electrode 206 via the insulating layer 204. The source electrode layer 206a and the drain electrode layer 202 are provided so as to partially overlap with each other. Even when the oxide semiconductor layer 210 is provided on the source electrode layer 206a and the drain electrode layer 206b, The parasitic capacitance between the gate electrode layer 206b and the gate electrode layer 202 is reduced, and The driving voltage of the transistor can be reduced and the element characteristics can be improved.

[0023] In FIG. 1A, both the source electrode layer 206a and the drain electrode layer 206b are gate electrodes. Although the case where the insulating layer 204 overlaps with a part of the gate electrode layer 202 is shown, in this embodiment However, the present invention is not limited to this. Either the source electrode layer 206a or the drain electrode layer 206b When the gate electrode layer 202 overlaps with the gate insulating layer 204 interposed therebetween, the overlapping electrode layer The thickness t of the gate insulating layer 204 provided between the gate electrode layers 202 1 , source electrode layer 2 The thickness t of the gate insulating layer 204 located in the region between the drain electrode layer 206a and the drain electrode layer 206b 2 Yo It is sufficient to provide the thickness of the insulating layer 11 so that the insulating layer 11 is thicker than the insulating layer 1

[0024] Next, referring to FIG. 2, a method for manufacturing the thin film transistor 250 shown in FIG. This article explains the following.

[0025] First, a gate electrode layer 202 is formed on a substrate 200. A gate insulating layer 204 is formed (see FIG. 2A).

[0026] The substrate 200 may be any substrate having an insulating surface, for example, a glass substrate. The glass substrate is preferably a non-alkali glass substrate. Examples of the glass substrate include aluminosilicate glass, aluminoborosilicate glass, and bar glass. The substrate 200 is made of a glass material such as borosilicate glass. Ceramic substrates, insulating substrates made of insulators such as quartz substrates and sapphire substrates, silicon substrates, etc. The surface of a semiconductor substrate made of semiconductor material is covered with an insulating material, and conductive materials such as metal and stainless steel are used. A conductive substrate made of a conductive material and having its surface covered with an insulating material can be used. A plastic substrate can also be used if it can withstand the heat treatment in the manufacturing process.

[0027] The gate electrode layer 202 is formed by forming a conductive layer on the entire surface of the substrate 200 and then forming a gate electrode layer 202 by photolithography. The gate electrode layer 202 can be formed by etching the conductive layer using a SiO 2 film. The term "electrodes" includes electrodes and wirings, such as gate wirings, formed by the conductive layer.

[0028] The gate electrode layer 202 may be made of aluminum (Al), copper (Cu), molybdenum (Mo), tungsten (Ti), or the like. It is preferable to form the wiring from conductive materials such as tungsten (W) or titanium (Ti). When aluminum is used as an electrode, aluminum alone has low heat resistance and is prone to corrosion. Therefore, it is preferable to form the material in combination with a heat-resistant conductive material. .

[0029] Heat-resistant conductive materials include titanium (Ti), tantalum (Ta), tungsten (W), and molybdenum (Mo). Mo, Cr, Nd, and Sc were selected. An element, an alloy containing the above-mentioned element, an alloy of a combination of the above-mentioned elements, or The film made of these heat-resistant conductive materials can be formed of nitrides containing the elements. Then, layers of aluminum (or copper) can be laminated to form wiring and electrodes.

[0030] The gate electrode layer 202 is formed on the substrate 200 by using a droplet discharge method, a screen printing method, or the like. It may also be selectively formed.

[0031] The gate insulating layer 204 may be a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a nitride oxide film. The insulating film can be formed of a silicon oxide film, an aluminum oxide film, a tantalum oxide film, or the like. These films may be laminated to a thickness of 5 mm or more by using a sputtering method or the like. For example, the gate insulating layer 204 may be formed to a thickness of 0 nm or more and 250 nm or less. A silicon oxide film can be formed to a thickness of 200 nm by sputtering.

[0032] In this specification, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. The content is high, and preferably, it is measured by Rutherford backscattering spectrometry (RBS). rford Backscattering Spectrometry) and hydrogen forward Scattering method (HFS: Hydrogen Forwardscattering Spect When measured using a rheometry, the concentration range is 50 to 70 atomic percent oxygen and 50 to 70 atomic percent nitrogen. The atomic percentage of hydrogen is 0.5 to 15%, the atomic percentage of silicon is 25 to 35%, and the atomic percentage of hydrogen is 0.1 to 10%. Silicon nitride oxide is a material that contains more nitrogen than oxygen as a component. The material has a high content of fluorine, preferably as measured by RBS and HFS. The concentration ranges are 5 to 30 atomic percent oxygen, 20 to 55 atomic percent nitrogen, and 25 to 3 5 atomic % and hydrogen in the range of 10 to 30 atomic %. When the total of atoms constituting silicon or silicon nitride oxide is 100 atomic %, nitrogen, oxygen The silicon and hydrogen content is within the above range.

[0033] Next, the source electrode layer 206a and the drain electrode layer 206b are formed over the gate insulating layer 204. (See Figure 2(B)).

[0034] The source electrode layer 206a and the drain electrode layer 206b are formed by forming a conductive layer over the gate insulating layer 204. After the formation, the conductive layer is etched using a photolithography method. Here, as an example, a source electrode layer 206a and a drain electrode layer 206b can be formed. A part of the gate electrode layer 202 is formed so as to overlap with the gate insulating layer 204. This shows the case where

[0035] The source electrode layer 206a and the drain electrode layer 206b are formed by using a sputtering method, a vacuum deposition method, or the like. Aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (Tb) Tennen (W), Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Scandium ( Sc), an alloy containing the above elements, or the above elements It can be formed from a material such as a nitride containing the above-mentioned elements.

[0036] For example, the source electrode layer 206a and the drain electrode layer 206b are formed of a molybdenum film or a titanium film. The source electrode layer 206a and the drain electrode layer 206b can be formed as a single layer. For example, the insulating film 06b may be formed as a laminated structure of an aluminum film and a titanium film. In addition, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated in this order can be used. Alternatively, a molybdenum film, an aluminum film, and a molybdenum film may be laminated in this order. The aluminum film used in these laminated structures may be a three-layer structure. Alternatively, an aluminum film containing niobium (Al-Nd) may be used. The drain electrode layer 206a and the drain electrode layer 206b may have a single-layer structure of an aluminum film containing silicon. good.

[0037] The source electrode layer 206a and the drain electrode layer 206b are formed by a droplet discharge method or a screen printing method. It is also possible to selectively form it on the substrate 200 using a printing method or the like.

[0038] The source electrode layer 206a formed in FIG. 2B functions as the source of the transistor. The drain electrode layer 206b functions as a drain of the transistor. Depending on the driving method of the transistor, the source electrode layer 206a functions as a drain, and the drain voltage In some cases, the pole layer 206b may function as the source.

[0039] Next, a gate insulating film is formed in the region between the source electrode layer 206a and the drain electrode layer 206b. By performing an etching process on the upper layer of the edge layer 204 (exposed gate insulating layer 204), A recess 207 is formed in the gate insulating layer 204 (see FIG. 2(C)).

[0040] By performing etching treatment, the source electrode layer 206a and the drain electrode layer 206b are The thickness t of the gate insulating layer 204 located in the region between 2 However, the gate electrode layer 202 and the source electrode The gate insulating layer 204 and the gate electrode layer 202 are disposed between the electrode layer 206a and the drain electrode layer 206b. The thickness t of the gate insulating layer 204 provided between the electrode layers 206b 1 Can be made smaller Preferably, the thickness t of the gate insulating layer 204 is 2 t 1 1 / 5~4 / 5 of the film thickness (t 2 =t 1 / 5~4t 1 / 5).

[0041] The etching process includes plasma treatment using inert gas and / or reactive gas, A hot etching process or the like can be used.

[0042] In addition, in the etching treatment, the source electrode layer 206a and the drain electrode layer 206b are In addition, the source electrode layer 206a and the drain electrode layer 20 The etching of the gate insulating layer 204 was performed using the photomask used in forming the gate insulating layer 6b (FIG. 2(B)). In this case, the source electrode layer 206a and the drain electrode layer 206 The gate insulating layer 204 that does not overlap with b is etched.

[0043] By performing an etching process, the thickness of the gate insulating layer 204 is made to have different values ​​in each region. At the same time, impurities attached to the exposed surface of the gate insulating layer 204 and impurity elements are taken in. The damaged surface layer can then be removed (see FIG. 2(C)).

[0044] Next, a layer is formed on the gate insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206b. The oxide semiconductor layer 209 is formed as shown in FIG.

[0045] The oxide semiconductor layer 209 can be formed using an In-Ga-Zn-O based non-single crystal film. For example, an oxide semiconductor target containing In, Ga, and Zn (In 2 O 3 :Ga 2 O 3 The oxide semiconductor layer 209 can be formed by a sputtering method using a ZnO film (ZnO=1:1:1). The sputtering conditions are, for example, a distance between the substrate 200 and the target of 30 mm. ~500mm, pressure 0.1Pa~2.0Pa, direct current (DC) power supply 0.25kW~5. 0kW, temperature 20℃~100℃, atmosphere argon, oxygen, or argon The atmosphere may be a mixture of oxygen and nitrogen.

[0046] In addition, if a pulsed direct current (DC) power supply is used, dust can be reduced and the film thickness distribution becomes uniform. After the above-described plasma treatment, the oxide semiconductor layer is preferably By forming the oxide semiconductor layer 209, dust particles are prevented from being generated at the interface between the gate insulating layer 204 and the oxide semiconductor layer 209. In addition, the thickness of the oxide semiconductor layer 209 can be reduced. It is sufficient to set the thickness to about 5 nm to 200 nm.

[0047] The sputtering method is RF sputtering, which uses a high-frequency power source for the sputtering power source, or direct sputtering. DC sputtering method using a current power source, and pulsed DC sputtering method applying a pulsed DC bias etc. can be used.

[0048] In addition, when plasma treatment is used as the etching treatment, the oxide semiconductor layer It is preferable to perform the formation of the GaN film 209 in the same chamber in succession. The surfaces of the source electrode layer 206a and the drain electrode layer 206b are exposed to the atmosphere. By forming the oxide semiconductor layer 209 without Impurities may adhere to the surfaces of the electrode layer 206a and the drain electrode layer 206b, and oxide films or the like may be formed. This can prevent the data from being used for other purposes.

[0049] In this embodiment, the semiconductor layer that becomes the channel formation region of the thin film transistor 250 is However, the semiconductor layer to which the present invention can be applied is not limited to this. In addition, a semiconductor layer using an organic semiconductor material can be used as the semiconductor layer. In addition to the In-Ga-Zn-O-based non-single crystal film, at least In is used as the semiconductor layer. Oxide semiconductors containing one of the following: sulphur, gallium, or zinc, such as ZnO, IZO, and ITO. Alternatively, an oxide semiconductor such as SnO, or a compound semiconductor such as SiGe or GaAs may be used. .

[0050] Next, the oxide semiconductor layer 209 is etched to form an island-shaped oxide semiconductor layer 210 ( See Figure 2(E)).

[0051] Through the above steps, a thin-film transistor using the oxide semiconductor layer 210 as a channel formation region is obtained. A star 250 can be formed.

[0052] After the oxide semiconductor layer 210 is formed, it is heated at 100° C. to 600° C., typically 200° C. to It is recommended to perform heat treatment at 400°C. For example, heat treatment at 350°C for 1 hour in a nitrogen atmosphere. By this heat treatment, the In-Ga- The atomic level rearrangement of the Zn-O oxide semiconductor occurs. This heat treatment (including photo-annealing) The above-mentioned structure (including the above-mentioned structure) relieves distortion that inhibits carrier movement in the island-shaped oxide semiconductor layer 210. Note that the timing of the heat treatment is important in that the oxide semiconductor layer 209 There is no particular limitation as long as it is after the formation of

[0053] Further, the island-shaped oxide semiconductor layer 210 may be subjected to oxygen radical treatment. By carrying out the calcination process, a thin-film transistor having the oxide semiconductor layer 210 as a channel formation region is formed. The star can be normally off. Also, by performing radical treatment, island-like The oxide semiconductor layer 210 can be repaired from damage caused by etching. Processing is O 2 , N 2 O, N containing oxygen 2 The reaction can be carried out under an atmosphere of He, Ar, etc. In addition, Cl is added to the above atmosphere. 2 , C.F. 4 The reaction may be carried out in an atmosphere containing a radical. The treatment is preferably carried out without applying a bias voltage to the substrate 200 side.

[0054] The oxide semiconductor layer 210, the source electrode layer 206a, the drain electrode layer 206b, and the like are included. A protective insulating layer may be formed to cover the thin film transistor 250. For this purpose, silicon oxide film, silicon nitride film, silicon oxynitride film, etc. are prepared by using CVD method, sputtering method, etc. Silicon film, silicon oxynitride film, aluminum oxide film, aluminum nitride film, aluminum oxynitride film The insulating film 11 may be formed of a single layer or a multilayer of an aluminum film or an aluminum nitride oxide film.

[0055] After that, various electrodes and wiring are formed to complete a semiconductor device having a thin film transistor 250. Completed.

[0056] As described above, after the source electrode layer 206a and the drain electrode layer 206b are formed, The source electrode layer 206a and the gate insulating layer 204 are etched. The thickness t of the gate insulating layer 204 located between the drain electrode layer 206b and the 2 The gate electrode A gate insulating layer 204 and a gate electrode layer 206a are provided between the layer 202 and the source electrode layer 206a. The thickness t of the gate insulating layer 204 provided between the drain electrode layer 202 and the drain electrode layer 206b 1 Less than As a result, the source electrode layer, the drain electrode layer, and the gate electrode layer can be formed. This can reduce the parasitic capacitance occurring between the first and second gate electrodes and improve the element characteristics.

[0057] (Embodiment 2) In this embodiment mode, a transistor configuration different from that in the above embodiment mode will be described with reference to FIG. This article explains the following.

[0058] The thin film transistor 260 shown in FIG. 1B is a thin film transistor 250 shown in FIG. In the embodiment, the source electrode layer 206a and the drain electrode layer 206b are tapered. In the case where the source electrode layer 206a and the drain electrode layer 206b are provided so as to have curved upper ends, The other structures (gate electrode layer 202, gate insulating layer 204, source The positional relationship between the electrode layer 206a, the drain electrode layer 206b, and the oxide semiconductor layer 210 is shown in FIG. It can be set up in the same manner as (A).

[0059] The source electrode layer 206a and the drain electrode layer 206b are tapered. By providing the upper end portions of the drain electrode layer 206a and the drain electrode layer 206b to have curved surfaces, Oxides for the gate insulating layer 204, the source electrode layer 206a and the drain electrode layer 206b The coverage of the semiconductor layer 210 can be improved, and discontinuity can be suppressed. The thickness t of the gate insulating layer 204 located in the region between the drain electrode layer 206a and the drain electrode layer 206b 2 The gate insulating layer 206 is disposed below the source electrode layer 206a and the drain electrode layer 206b. The film thickness t 1 Even if the thickness is made sufficiently small with respect to the thickness of the oxide semiconductor layer 210, the step It can be effectively suppressed.

[0060] An example of a method for manufacturing the thin film transistor 260 shown in FIG. 1B will be described below with reference to FIG. Note that the manufacturing process in FIG. 3 is common to that in FIG. Therefore, in the following description, the overlapping parts will be omitted and only the differences will be explained. 3, the gate insulating layer 204 is etched using a plasma. This shows the case where processing is used.

[0061] First, a gate electrode layer 202 is formed on a substrate 200 having an insulating surface, and then the gate A gate insulating layer 204 is formed over the electrode layer 202 (see FIG. 3A). When the layer 202 is formed, the covering property of the gate insulating layer 204 to be formed later is improved and a step is prevented. In order to prevent this, the end of the gate electrode layer 202 is etched to have a tapered shape. For example, the taper angle θ 1 is 20° or more and less than 90°, preferably 30° or more It is preferable that the taper angle is 80° or less. 1 " is a A layer having a perforated shape (here, the gate electrode layer 202) is formed in a cross-sectional direction (the surface of the substrate 200). When observed from the side of the layer (a plane perpendicular to the side of the layer), the inclination angle between the side and bottom of the layer on the inside of the layer is That is, when observed from the cross-sectional direction, the lower end of the gate electrode layer 202 in contact with the substrate 200 is This corresponds to the angle of the part.

[0062] The materials and manufacturing methods of the gate electrode layer 202 and the gate insulating layer 204 are described in detail in the embodiment. Please refer to State 1.

[0063] Next, the source electrode layer 206a and the drain electrode layer 206b are formed over the gate insulating layer 204. (see FIG. 3B). Note that the materials of the source electrode layer 206a and the drain electrode layer 206b are For the materials and a manufacturing method, refer to Embodiment Mode 1.

[0064] Next, the gate insulating layer 204 is etched. Plasma is generated in the chamber to expose the gate insulating layer 204 and the source electrode layer 206. The gate insulator layer 206a and the drain electrode layer 206b are exposed to the plasma 208. This shows the case where a recess 207 is formed in the edge layer 204 (see FIG. 3(C)).

[0065] In the plasma treatment, for example, an inert gas such as argon (Ar) gas is introduced into a vacuum chamber. A bias voltage is applied to the workpiece (here, the substrate 200) to create a plasma state. When Ar gas is introduced into the chamber, the plasma contains electrons and A. There are positive ions of Ar, and the positive ions of Ar are accelerated toward the cathode (toward the substrate 200). The Ar cations are deposited on the substrate 200 to form a gate insulating layer 204 and a source electrode layer 205. The surfaces of the drain electrode layer 206a and the drain electrode layer 206b are sputtered by the collision. The gate insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206 are etched. The surface of b can be etched. This type of plasma treatment is called "reverse sputtering." "It is also sometimes called ".

[0066] A bias voltage is applied to the substrate 200 to perform plasma processing, thereby forming a gate insulating layer. 204, sputter etching of the surfaces of the source electrode layer 206a and the drain electrode layer 206b This can be done effectively.

[0067] In addition, when the surface of the gate insulating layer 204 is uneven, a plasma treatment is performed. As a result, the protruding portions of the gate insulating layer 204 are preferentially sputter-etched, and the gate The flatness of the surface of the insulating layer 204 can be improved.

[0068] In addition, helium gas is used instead of argon gas as the gas used in the plasma treatment. Alternatively, the treatment may be performed in an atmosphere in which oxygen, hydrogen, nitrogen, etc. are added to an argon atmosphere. Also, Cl was added to the argon atmosphere.2 , C.F. 4 The above may be added to the atmosphere.

[0069] For example, in this embodiment, the plasma processing is performed using a sputtering apparatus as shown in FIG. It is possible.

[0070] The sputtering apparatus shown in FIG. 4 has a chamber 190 and a workpiece 195 (here, a substrate 2 00) and an opposing second electrode 192. The first electrode 191 is connected to an RF power source (high frequency power source) 197, and the second electrode 192 is connected to an The first electrode 191 and the RF power supply 192 are connected to an RF power supply 198 and a DC power supply 199. 7 and between the second electrode 192 and the RF power supply 198 for impedance matching. For this purpose, matching box 193 and matching box 194 are provided.

[0071] Using the sputtering apparatus shown in FIG. 4, a plasma treatment (also called reverse sputtering) is performed on a processing object 195. When performing the above-mentioned step, an inert gas such as argon gas is introduced from the inlet 196 to the first electrode. A high frequency voltage is applied to the first electrode 191 to generate a plasma of inert gas between the first electrode 191 and the second electrode 192. A negative self-bias is generated on the side of the workpiece 195 provided on the first electrode 191. By generating a positive ion in the plasma (with a bias voltage applied), The electrons are accelerated and collide with the object to be processed 195. At this time, the surface of the gate insulating layer 204 is uneven. If formed, the protruding portion is preferentially sputter-etched, and the gate insulating layer 204 The surface of the substrate can be flattened.

[0072] The sputtering apparatus shown in FIG. 4 is used to form a film on the workpiece 195 (sputtering film formation). In this case, a target made of the material to be deposited is placed on the second electrode 192 side. Then, a DC voltage or a high-frequency voltage is applied to the second electrode 192 to connect the first electrode 191 and the second electrode A plasma is generated between the electrodes 192, and positive ions in the plasma are accelerated to collide with the target. Just do that.

[0073] Therefore, when a film is formed on the object to be treated 195 after the plasma treatment, After the plasma treatment, the treated object 195 is continuously treated by sputtering without being exposed to the atmosphere. A membrane can be formed on the substrate 95.

[0074] In this embodiment, when a bias voltage is applied to the substrate 200 side during plasma processing, However, if the recess 207 can be formed in the gate insulating layer 204, The plasma treatment may be performed without applying an asphalt voltage.

[0075] In addition, a plasma treatment is performed to remove the oxide from the surface of the gate insulating layer 204 and the source electrode layer 206. a and the drain electrode layer 206b. There are.

[0076] In addition, in FIG. 3, not only the gate insulating layer 204 but also the source electrode layer 206a and the drain electrode The source electrode layer 206a and the drain electrode layer 206b are subjected to a plasma treatment. The end of the layer 206b is tapered. For example, the taper angle θ 2 2 The angle is preferably 0° or more and less than 90°, and more preferably 30° or more and 80° or less. It is preferable to use a taper angle of θ 2 " refers to a layer having a tapered shape (here, the source The electrode layer 206a or the drain electrode layer 206b is When observing from the side of the layer, the inclination angle of the tip part inside the layer formed by the side and bottom of the layer is That is, when observed from the cross-sectional direction, the source electrode layer 204 in contact with the gate insulating layer 204 is The angle corresponds to the angle of the bottom end of the source electrode layer 206a or the drain electrode layer 206b. The end of the drain electrode layer 206b is tapered to prevent the oxidation of the oxide layer 206b. This improves the coverage of the compound semiconductor layer and suppresses discontinuities.

[0077] In addition, in FIG. 3, not only the gate insulating layer 204 but also the source electrode layer 206a and the drain electrode The source electrode layer 206a and the drain electrode layer 206b are subjected to a plasma treatment. This shows a case where the upper end of layer 206b is formed to have a curved surface (a curved shape). For example, the radius of curvature of the upper end portions of the source electrode layer 206a and the drain electrode layer 206b is R is 1 / 1 of the thickness of the source electrode layer 206a and the drain electrode layer 206b after the plasma treatment. The ratio of the source electrode layer 206a and the drain electrode layer 206b to each other is preferably 100 to 1 / 2. It is formed so that it is between 3 / 100 and 1 / 5 of the thickness.

[0078] For example, the thickness of the source electrode layer 206a and the drain electrode layer 206b after the plasma treatment is 1 When the thickness of the source electrode layer 206a and the drain electrode layer 206b is 0.00 nm, The radius of curvature R is set to 1 nm or more and 50 nm or less, preferably 3 nm or more and 20 nm or less. In addition, the radius of curvature R of the upper end portions of the source electrode layer 206a and the drain electrode layer 206b is within this range. The source electrode layer 206a and the drain electrode layer 206 may have a shape that changes continuously. By providing the upper end portion of b to have a curved surface, it is possible to cover the oxide semiconductor layer to be formed later. In particular, the thickness of the oxide semiconductor layer is increased when the source potential is increased. The total length of the thickness of the electrode layer 206a or the drain electrode layer 206b and the depth of the recess (step When the thickness is thinner than the thickness difference (difference), the effect of suppressing step discontinuity becomes significant.

[0079] In addition, when the end portions of the source electrode layer 206a and the drain electrode layer 206b are tapered, In both cases, it is preferable to form the recess 207 of the gate insulating layer 204 in a tapered shape. In this case, the gate insulating layer 204 and the source electrode layer 206a or the drain electrode layer 206 Improves the coverage of the oxide semiconductor layer formed at the contact area with b, effectively preventing discontinuities The recess 207 of the gate insulating layer 204 is formed in a tapered shape. The inclination angle θ of the recessed portion side between the side surface and the bottom surface of the recessed portion of the gate insulating layer 204 3 (or hollow The inclination angle of the recessed portion between the side surface of the recessed portion and the surface of the substrate 200 is set to 90° or more. say.

[0080] In this manner, not only the gate insulating layer 204 but also the source electrode layer 206a and the drain electrode layer A plasma treatment is also performed on 206b to form a recess 207 in the gate insulating layer 204. At the same time, the source electrode layer 206a and the drain electrode layer 206b are tapered. The source electrode layer 206a and the drain electrode layer 206b are provided so that their upper ends have curved surfaces. This can be done.

[0081] Next, a layer is formed on the gate insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206b. After the oxide semiconductor layer is formed as described above, the oxide semiconductor layer is selectively etched. In this manner, the oxide semiconductor layer 210 is formed (see FIG. 3D). Regarding the material and the manufacturing method, Embodiment 1 can be referred to.

[0082] According to this embodiment, a semiconductor device including transistors having high characteristics is provided. Note that this embodiment mode can be used in appropriate combination with other embodiment modes. can be done.

[0083] (Embodiment 3) In this embodiment mode, a transistor configuration different from that in the above embodiment mode will be described with reference to FIG. explain.

[0084] The thin film transistor 270 shown in FIG. 5A includes a first insulating layer 2 provided on a substrate 200. 51, a second insulating layer 252 provided on the first insulating layer 251, and a second insulating layer 252 provided on the first insulating layer 251. and a solenoid 252 provided to overlap a part of the gate electrode layer 202 with the second insulating layer 252 interposed therebetween. A source electrode layer 206a and a drain electrode layer 206b, and a source electrode layer 206a and a drain electrode layer 206b are formed. A conductive layer is provided over the source electrode layer 206a and between the drain electrode layer 206b. The oxide semiconductor layer 210 is provided in contact with the first insulating layer 251 located in the region. There are.

[0085] That is, in the region where the second insulating layer 252 overlaps with the gate electrode layer 202, The layer 206a is removed in a region where it does not overlap with the drain electrode layer 206b. In this case, the insulating layer located between the source electrode layer 206a and the drain electrode layer 206b is The insulating layer 251 is disposed between the gate electrode layer 202 and the source electrode layer 206a. and an insulating layer provided between the gate electrode layer 202 and the drain electrode layer 206b. The insulating layer 251 is made up of a laminated structure of a first insulating layer 251 and a second insulating layer 252 .

[0086] In addition, the thickness t of the insulating layer located between the source electrode layer 206a and the drain electrode layer 206b 2 However, the insulating layer and the gate electrode layer are provided between the gate electrode layer 202 and the source electrode layer 206a. The thickness t of the insulating layer provided between the electrode layer 202 and the drain electrode layer 206b 1 Become smaller In FIG. 5(A), the film thickness t 1 is the sum of the thicknesses of the first insulating layer 251 and the second insulating layer 252. corresponds to the film thickness t 2 corresponds to the film thickness of the first insulating layer 251.

[0087] In this manner, by using the structure shown in FIG. 5A, the first The source electrode layer 206a and the drain electrode layer 206b are formed with the insulating layer 251 and the second insulating layer 252 interposed therebetween. The source electrode layer 206a and the drain electrode layer 206b are provided with an oxide semiconductor layer. Even when the dielectric layer 210 is provided, the source electrode layer 206a and the drain electrode layer 206b The parasitic capacitance between the gate electrode layer 202 and the gate electrode layer 203 is reduced, and the driving current of the transistor is reduced. This reduces the pressure and improves the device characteristics.

[0088] In the structure shown in FIG. 5A, the first insulating layer 251 and the second insulating layer 252 are It is preferable to use different materials for the first insulating layer 251. The dielectric constant of the material used for the first insulating layer 251 is made higher than the dielectric constant of the material used for the second insulating layer 252. By making the dielectric constant higher than that of the second insulating layer 252, the driving voltage of the transistor can be Therefore, the source electrode layer 206a, the drain electrode layer 206b and the gate The influence of the parasitic capacitance occurring between the electrode layer 202 can be effectively reduced.

[0089] By using different materials for the first insulating layer 251 and the second insulating layer 252, This makes it easier to obtain an etching selectivity when etching the insulating layer 252. In addition, the etching selectivity can be obtained when, for example, etching layers A and B, This means that there is a sufficient difference between the etching rate of layer A and the etching rate of layer B. The "etching rate" refers to the amount of etching per unit time (amount of etching Therefore, "high etching rate" means that the material is more easily etched. A "small etching rate" means that the material is more resistant to etching. means...

[0090] The thickness of the first insulating layer 251 and the thickness of the second insulating layer 252 are appropriately determined depending on the material used. For example, the first insulating layer 251 may be a silicon nitride film, an aluminum oxide film, or the like. The insulating layer is made of a 5nm to 20nm thick aluminum film, hafnium oxide film, or a combination of these films. The second insulating layer 252 is formed with a thickness of 0 nm, and an aluminum oxide film, a polyimide film, or the like is used. By combining these films, an insulating layer or the like can be formed with a film thickness of 5 nm to 200 nm. In addition, the driving voltage is further reduced, and the source electrode layer 206a and the drain electrode layer 206b and the gate electrode In order to reduce the parasitic capacitance generated between the first insulating layer 251 and the electrode layer 202, the thickness of the first insulating layer 251 is set to It is preferable that the thickness of the second insulating layer 252 be smaller than that of the second insulating layer 252.

[0091] Note that the structure of the transistor described in this embodiment is not limited to that shown in FIG. 5(B) and 5(C) may also be used.

[0092] The thin film transistor 271 shown in FIG. 5B is a thin film transistor including a first insulating layer 2 51, a second insulating layer 252 provided on the first insulating layer 251, and a second insulating layer 252 provided on the first insulating layer 251. and a solenoid 252 provided to overlap a part of the gate electrode layer 202 with the second insulating layer 252 interposed therebetween. A source electrode layer 206a and a drain electrode layer 206b, and a source electrode layer 206a and a drain electrode layer 206b are formed. A conductive layer is provided on the source electrode layer 206b and between the source electrode layer 206a and the drain electrode layer 206b. The oxide semiconductor layer 210 is provided in contact with the second insulating layer 252 located in the SOI region. A second insulating layer 252 located in the region between the source electrode layer 206a and the drain electrode layer 206b. The upper layer has been removed.

[0093] That is, the second insulating layer 252 has a recess 207 in the area where it overlaps with the gate electrode layer 202. An oxide semiconductor layer 210 is provided in the recess 207 of the second insulating layer 252 .

[0094] The transistor 272 shown in FIG. 5C has the structure shown in FIG. 5A, but has a second insulating layer. 252 is a region overlapping the gate electrode layer 202, and the source electrode layer 206a and the drain electrode In the region located between the pole layers 206b, the first insulating layer 251 has a recess 207. An oxide semiconductor layer 210 is provided in the recess 207 of the first insulating layer 251 .

[0095] Even in the case of the configuration shown in FIG. 5B or FIG. 5C, the source electrode layer 206a and The thickness t of the insulating layer located between the drain electrode layers 206b 2The gate electrode layer 202 and the source The insulating layer and the gate electrode layer 202 and the drain electrode layer 206a are provided between the gate electrode layer 202 and the drain electrode layer 206b. The thickness t of the insulating layer provided between 1 It can be made smaller.

[0096] 5, the gate electrode layer 202, the source electrode layer 206a, and the drain electrode layer 20 6b, a two-layer structure of a first insulating layer 251 and a second insulating layer 252 is used. However, this embodiment is not limited to a two-layer structure, and may have a three-layer structure.

[0097] Next, with reference to FIG. 6, an example of a method for manufacturing the transistor 270 shown in FIG. Note that the manufacturing process in FIG. 6 is largely the same as that in FIG. 1. In the following description, the description of the overlapping parts will be omitted, and the differences will be described in detail. do.

[0098] First, a gate electrode layer 202 is formed on a substrate 200 having an insulating surface, and then the gate A first insulating layer 251 and a second insulating layer 252 are formed by laminating them in this order on the electrode layer 202 (FIG. 6(A)).

[0099] The first insulating layer 251 and the second insulating layer 252 are made of a silicon oxide film, a silicon oxynitride film, a nitride film, or the like. Silicon nitride film, silicon oxide nitride film, aluminum oxide film, tantalum oxide film, hafnium oxide film The insulating film can be formed using a silicon film or the like.

[0100] In addition, the first insulating layer 251 and the second insulating layer 252 may be formed using different materials. In particular, it is preferable to set the dielectric constant of the first insulating layer 251 higher than the dielectric constant of the second insulating layer 252. For example, the first insulating layer 251 may be made of A film made by stacking a silicon oxide film and a silicon nitride film in order is formed to a thickness of 5 nm to 200 nm. As the second insulating layer 252, a silicon oxide film is formed to a thickness of 5 nm to 200 nm. It is possible.

[0101] As described above, the first insulating layer 251 may be a silicon nitride film or an aluminum oxide film. The insulating layer is a hafnium oxide film or a combination of these films with a thickness of 5 nm to 200 nm. The second insulating layer 252 is formed of an aluminum oxide film, a polyimide film, or a film of these. An insulating layer or the like made by combining these can be formed to a thickness of 5 nm to 200 nm.

[0102] Note that for a material and a manufacturing method of the gate electrode layer 202, Embodiment 1 can be referred to. can.

[0103] Next, the source electrode layer 206a and the drain electrode layer 206b are formed over the second insulating layer 252. (see FIG. 6B). Note that the materials of the source electrode layer 206a and the drain electrode layer 206b are For the materials and a manufacturing method, refer to Embodiment Mode 1.

[0104] Next, the second insulating layer 2 formed between the source electrode layer 206a and the drain electrode layer 206b is The second insulating layer 52 (exposed second insulating layer 252) is etched. 252 is removed to expose the first insulating layer 251 (see FIG. 6(C)).

[0105] By performing an etching process, the source electrode layer 206a and the drain electrode layer 206b are The thickness t of the insulating layer (here, the first insulating layer 251) located in the region between the 2 But the gate electrode An insulating layer provided between the layer 202 and the source electrode layer 206a and a gate electrode layer 202 and a drain electrode layer 206b are provided. An insulating layer (here, a first insulating layer 251 and a second insulating layer 252) is provided between the first electrode layer 206b and the second electrode layer 206b. The thickness t of the edge layer 252 1 It becomes smaller.

[0106] The etching process may be dry etching or wet etching. For example, the etching process is 4 F 8 Dry etching using a mixture of Ar and By performing etching, the etching selectivity between the silicon oxide film and the silicon nitride film is obtained, The second insulating layer 252 can be effectively removed.

[0107] By controlling the etching conditions, the source electrode layer 206a and the drain electrode A part of the second insulating layer 252 formed between the pole layers 206b may be left as it is (FIG. 5( B)), a second electrode layer formed between the source electrode layer 206a and the drain electrode layer 206b The insulating layer 252 is removed and the upper layer of the first insulating layer 251 is etched to form the first insulating layer. A recess may be formed in the layer 251 (corresponding to FIG. 5(C)).

[0108] In addition, in the etching treatment, the source electrode layer 206a and the drain electrode layer 206b are In addition, the source electrode layer 206a and the drain electrode layer 20 The second insulating layer 252 is etched using the photomask used in forming 6b (FIG. 6(B)). Ching can also be performed.

[0109] Next, the first insulating layer 251, the second insulating layer 252, the source electrode layer 206a and the drain electrode After forming the oxide semiconductor layer 209 so as to cover the electrode layer 206b (see FIG. 6D), The oxide semiconductor layer 210 is formed by selectively etching the oxide semiconductor layer 209. (see FIG. 6E). Note that the material of the oxide semiconductor layer 209 (the oxide semiconductor layer 210) For details of the configuration and manufacturing method, refer to Embodiment 1.

[0110] According to this embodiment, a semiconductor device including transistors having high characteristics is provided. Note that this embodiment mode can be used in appropriate combination with other embodiment modes. can be done.

[0111] (Embodiment 4) In this embodiment mode, a transistor configuration different from that in the above embodiment mode will be described with reference to FIG. explain.

[0112] The thin film transistor 280 shown in FIG. 7A includes a gate insulating layer 2 provided on a substrate 200. 04 and a part of the gate electrode layer 202 are provided so as to overlap with each other via a gate insulating layer 204. The source electrode layer 206a and the drain electrode layer 206b are A source electrode 217 is provided on the source electrode layer 206b via the buffer layers 217a and 217b. The drain electrode layer 206b is disposed between the gate insulating layer 204 and the drain electrode layer 206a. Further, the source electrode layer 206a and the drain electrode layer 206b are The thickness t of the gate insulating layer 204 located in the region between the electrode layers 206b 2 However, the gate electrode layer 20 The gate insulating layer 204 and the gate electrode layer 202 are provided between the source electrode layer 206a and the gate electrode layer 202. The thickness t of the gate insulating layer 204 provided between the drain electrode layer 206b and the 1 Smaller (See FIG. 7(A)).

[0113] That is, the transistor shown in FIG. 7A is the same as the transistor shown in FIG. It is configured by adding 217a and 217b.

[0114] The buffer layers 217a and 217b are formed in the source electrode layer 206a and the drain electrode layer 206b in the manufacturing process. The surface of the electrode layer 206b is prevented from being oxidized and functions as a channel forming region. The oxide semiconductor layer 210 is connected to the source electrode layer 206a and the drain electrode layer 206b. It acts as a layer for achieving good electrical connection.

[0115] The buffer layers 217a and 217b have a conductivity equal to or greater than that of the oxide semiconductor layer 210. For example, the buffer layer can be formed using an oxide semiconductor layer having a higher electrical conductivity than the buffer layer. 217a and 217b are formed of In-Ga-Zn-O-based non-single crystal films, and the oxide semiconductor layer 2 10 is an In-Ga-Zn-O based non-single crystal having a lower electrical conductivity than the buffer layers 217a and 217b. It can be formed of a membrane.

[0116] In this manner, the source electrode layer 206a, the drain electrode layer 206b, and the oxide semiconductor layer 21 0, buffer layers 217a and 217b are provided between the As a result, the element characteristics of the transistor can be improved.

[0117] Next, referring to FIG. 8, an example of a method for manufacturing the thin film transistor 280 shown in FIG. The fabrication process in FIG. 8 is largely the same as that in FIG. 1. Therefore, in the following description, the description of the overlapping parts will be omitted, and the differences will be described in detail. Reveal.

[0118] First, a gate electrode layer 202 is formed on a substrate 200 having an insulating surface, and then the gate A gate insulating layer 204 is formed over the electrode layer 202 (see FIG. 8A). For the materials and manufacturing methods of the gate insulating layer 202 and the gate insulating layer 204, refer to Embodiment 1. This can be done.

[0119] Next, a conductive layer 206 is formed on the gate insulating layer 204, and then an oxide semiconductor is formed on the conductive layer 206. Then, a body layer 217 is formed (see FIG. 8(B)).

[0120] The conductive layer 206 is formed by depositing aluminum (Al), copper (Cu) ), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), Metals containing elements selected from chromium (Cr), neodymium (Nd), and scandium (Sc), An alloy containing the above elements, or a material made of a nitride containing the above elements, etc. It can be formed.

[0121] For example, the conductive layer 206 can be formed to have a single-layer structure of a molybdenum film or a titanium film. The conductive layer 206 may be formed in a laminated structure, for example, an aluminum film and a titanium film. A laminate structure of a titanium film, an aluminum film, and a titanium film may be formed in this order. Alternatively, a three-layer structure may be formed by laminating a molybdenum film, an aluminum film, and a molybdenum film. In addition, the aluminum used in these laminated structures may be The film may be an aluminum film containing neodymium (Al-Nd). Layer 206 may be a single layer of aluminum film containing silicon.

[0122] The oxide semiconductor layer 217 can be formed of an In-Ga-Zn-O based non-single crystal film. For example, an oxide semiconductor target containing In, Ga, and Zn (In 2 O 3 :Ga 2 O 3 : The oxide semiconductor layer 217 is formed on the conductive layer 206 by a sputtering method using ZnO (ZnO=1:1:1). The sputtering conditions are, for example, the substrate 200 and the target. Distance: 30mm~500mm, pressure: 0.1Pa~2.0Pa, direct current (DC) power: 0. 25kW~5.0kW, temperature 20℃~100℃, atmosphere argon, oxygen , or a mixture of argon and oxygen.

[0123] The oxide semiconductor layer 217 is formed by oxidizing the surfaces of the source electrode layer and the drain electrode layer to be formed later. The oxide semiconductor layer serves as a channel forming region to be formed later. A buffer layer is provided to improve electrical connection between the conductor layer and the source and drain electrode layers. It functions as a layer.

[0124] In the step of FIG. 8B, after the conductive layer 206 is formed, the conductive layer 206 is exposed to the atmosphere. It is preferable to form the oxide semiconductor layer 217 in succession without exposing the conductive layer 206 to heat. By forming the oxide semiconductor layer 217 without exposing the oxide semiconductor layer 217 to the air, The conductive layer 206 and the oxide semiconductor layer 21 are prevented from being attached with impurities or from being formed with an oxide film. This is because the contact resistance of 7 can be reduced.

[0125] In addition, the surface of the conductive layer 206 is oxidized by using a gas for forming the oxide semiconductor layer 217. For example, the oxide semiconductor layer 217 is formed under the following conditions: , the ratio of the flow rate of argon gas to the flow rate of oxygen gas is increased (preferably, the ratio of the flow rate of oxygen gas to the flow rate of argon gas is increased). Specifically, the oxide semiconductor layer 217 is formed under an atmosphere of argon, helium, or the like. or in an atmosphere of 10% or less oxygen gas and 90% or more rare gas. This can be achieved by reducing the ratio of the oxygen gas flow rate to the argon gas flow rate. This makes it possible to prevent an oxide film from being formed on the surface of the conductive layer 206. In this way, the contact resistance between the conductive layer 206 and the oxide semiconductor layer 217 can be reduced.

[0126] In addition, by reducing the ratio of the flow rate of oxygen gas to the flow rate of argon gas, In this case, the conductivity of the oxide semiconductor layer formed later can be increased. The oxide semiconductor layer which functions as a formation region and the source electrode layer and the drain electrode layer are electrically connected to each other. This allows for good connection.

[0127] Next, the conductive layer 206 and the oxide semiconductor layer 217 are etched by photolithography. By this, the source electrode layer 206a, the drain electrode layer 206b, and the buffer layer 2 17a and a buffer layer 217b are formed.

[0128] Next, a gate insulating layer 2 provided between the source electrode layer 206a and the drain electrode layer 206b is 04 (exposed gate insulating layer 204) is etched to form a gate insulating layer A recess 207 is formed in 204 (see FIG. 8(C)).

[0129] Next, the gate insulating layer 204, the source electrode layer 206a, the drain electrode layer 206b, and the buffer layer 206 are After forming the oxide semiconductor layer 209 so as to cover the anode layer 217a and the buffer layer 217b ( As shown in FIG. 8D, the oxide semiconductor layer 209 is selectively etched to form an oxide semiconductor layer. The compound semiconductor layer 210 is then formed (see FIG. 8(E)). The oxide semiconductor layer 209 (oxide semiconductor Regarding the material and manufacturing method of the layer 210, Embodiment Mode 1 can be referred to.

[0130] In FIG. 7A, the transistor shown in FIG. However, the present invention is not limited to this. For example, as shown in FIG. The transistor shown in FIG. 1A may be provided with buffer layers 217a and 217b. (B), buffer layers 217a and 217b are provided in the configurations shown in FIG. 5(B) and FIG. 5(C). It is also possible.

[0131] According to this embodiment, a semiconductor device including transistors having high characteristics is provided. Note that this embodiment mode can be used in appropriate combination with other embodiment modes. can be done.

[0132] (Embodiment 5) In this embodiment, a display device, which is an example of a usage form of a semiconductor device including a transistor, is used. The manufacturing process of the semiconductor device will be described with reference to the drawings. The above-mentioned parts are common to the first embodiment. Therefore, in the following, the overlapping parts will be explained. In the following description, the differences will be described in detail with reference to FIGS. FIG. 0 shows a cross-sectional view, and FIG. 11 to FIG. 14 show top views.

[0133] First, wiring and electrodes (gate electrodes including a gate electrode layer 202) are formed on a substrate 200 having an insulating surface. The port wiring, the capacitance wiring 308, and the first terminal 321 are formed (see FIG. 9(A) and FIG. 11). .

[0134] The capacitance wiring 308 and the first terminal 321 are formed at the same time as the gate electrode layer 202 using the same material. The material and manufacturing method of the gate electrode layer 202 are described in the embodiment. Please refer to State 1.

[0135] Next, a gate insulating layer 204 is formed on the gate electrode layer 202, and then the gate insulating layer 204 A conductive layer 206 is formed thereover (see FIG. 9B).

[0136] The conductive layer 206 is formed by depositing aluminum (Al), copper (Cu) ), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), Metals containing elements selected from chromium (Cr), neodymium (Nd), and scandium (Sc), An alloy containing the above elements, or a material made of a nitride containing the above elements, etc. It can be formed.

[0137] For example, the conductive layer 206 can be formed of a single layer structure of a titanium film. The insulating film 06 may be formed in a laminated structure, for example, a laminated structure of an aluminum film and a titanium film. In addition, a titanium film and an aluminum film containing neodymium (Al-Nd) can be used. The conductive layer 206 may be a three-layer structure of an aluminum film containing silicon. Alternatively, the film may have a single layer structure.

[0138] In FIG. 9B, after the gate insulating layer 204 is formed, After the contact hole 213 is formed, the conductive layer 206 is formed, so that the first terminal 3 21 and the conductive layer 206 are electrically connected.

[0139] Next, the conductive layer 206 is etched to form a source electrode layer 206a, a drain electrode The layer 206b, the connection electrode 320, and the second terminal 322 are formed (see FIG. 9(C) and FIG. 12). .

[0140] The second terminal 322 is electrically connected to the source wiring (the source wiring including the source electrode layer 206a). The connection electrode 320 can be formed on the gate insulating layer 204. The first terminal 321 is directly connected to the second terminal 322 through the contact hole 213. can be done.

[0141] Next, a gate insulating layer 2 provided between the source electrode layer 206a and the drain electrode layer 206b is 04 (exposed gate insulating layer 204) is etched to form a gate insulating layer A recess 207 is formed in 204 (see FIG. 9(D)).

[0142] By performing an etching process, the source electrode layer 206a and the drain electrode layer 206b are The thickness t of the gate insulating layer 204 located in the region between 2 However, the gate electrode layer 202 and the source electrode The gate insulating layer 204 and the gate electrode layer 202 and the drain electrode layer 206a are disposed between the gate insulating layer 204 and the gate electrode layer 202. The thickness t of the gate insulating layer 204 provided between the layers 206b 1 It becomes smaller.

[0143] The etching process includes plasma treatment using inert gas and / or reactive gas, A hot etching process or the like can be used.

[0144] Here, the etching process is performed on the gate insulating layer 204, the source electrode layer 206a, the drain When plasma treatment is performed on the surfaces of the electrode layer 206b, the connection electrode 320, and the second terminal 322, In this case, the source electrode layer 206a, the drain electrode layer 206b, and the connection electrode 3 20. The end of the second terminal 322 is tapered and the upper end is formed to have a curved surface. As for the method of plasma processing, reference can be made to the above-mentioned embodiment mode 2. This can be done.

[0145] In addition, by reducing the thickness of the gate insulating layer 204 formed on the capacitance wiring 308, Therefore, the capacitance of the capacitive element to be formed later can be increased.

[0146] Next, the gate insulating layer 204, the source electrode layer 206a, the drain electrode layer 206b, and the connection electrode 320, an oxide semiconductor layer 209 is formed so as to cover the second terminal 322 (FIG. 10(A) reference).

[0147] The plasma treatment and the formation of the oxide semiconductor layer 209 can be performed successively in the same chamber. It is preferable that the plasma treatment and the formation of the oxide semiconductor layer 209 are performed in succession. Impurities on the surfaces of the source insulating layer 204, the source electrode layer 206a, and the drain electrode layer 206b Adhesion, oxide films, etc. are formed on the surfaces of the source electrode layer 206a and the drain electrode layer 206b. Note that the material and the formation method of the oxide semiconductor layer 209 are Please refer to embodiment 1.

[0148] Next, the oxide semiconductor layer 209 is selectively etched to form an island-shaped oxide semiconductor layer 210. Thus, a thin film transistor 290 is formed (see FIG. 10B and FIG. 13).

[0149] Next, it is preferable to carry out a heat treatment at 100°C to 600°C, typically 200°C to 400°C. For example, heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. Atomic level rearrangement of the In-Ga-Zn-O based non-single crystal film constituting the oxide semiconductor layer 210 This heat treatment releases the distortion that inhibits carrier movement, The heat treatment (including photo-annealing) is effective. There is no particular limitation as long as it is performed after the deposition of the organic semiconductor layer 209. For example, it may be performed after the formation of the pixel electrode. good.

[0150] Further, the exposed island-shaped oxide semiconductor layer 210 may be subjected to oxygen radical treatment. By performing oxygen radical treatment, the island-shaped oxide semiconductor layer 210 is made into a channel formation region. The thin film transistor can be normally off by performing radical treatment. As a result, damage to the island-shaped oxide semiconductor layer 210 caused by etching can be repaired. Radical processing is O 2 , N 2 O, preferably N containing oxygen 2 , He, Ar atmosphere It is preferable to carry out the above-mentioned process without adding Cl 2 , C.F. 4 It may be carried out in an atmosphere containing stomach.

[0151] Next, a protective insulating layer 340 is formed to cover the thin film transistor 290. A contact hole 325 reaching the drain electrode layer 206b is selectively etched. A contact hole 326 reaching the connecting electrode 320 and a contact hole 326 reaching the second terminal 322 A hole 327 is formed (see FIG. 10(C)).

[0152] Next, a transparent conductive layer 310 electrically connected to the drain electrode layer 206b and a connection electrode 320 are A transparent conductive layer 328 electrically connected to the second terminal 322 329 is formed (see FIG. 10(D) and FIG. 14).

[0153] The transparent conductive layer 310 functions as a pixel electrode, and the transparent conductive layers 328 and 329 are connected to the FPC. More specifically, the transparent conductive layer formed on the connection electrode 320 is an electrode or wiring used for the connection electrode 320. The transparent conductive layer 328 is used as a terminal electrode for connection that functions as an input terminal of the gate wiring. The transparent conductive layer 329 formed on the terminal 322 of the second electrode serves as an input terminal of the source wiring. It can be used as a terminal electrode for connection.

[0154] In addition, the capacitance wiring 308, the gate insulating layer 204, the protective insulating layer 340, and the transparent conductive layer 310 In this case, the capacitance wiring 308 and the transparent conductive layer 310 are It serves as an electrode, and the gate insulating layer 204 and the protective insulating layer 340 serve as dielectrics.

[0155] The transparent conductive layers 310, 328, and 329 are made of indium oxide (In 2 O 3 ), indium oxide Tin oxide alloy (In 2 O 3 - SnO 2 Indium oxide zinc oxide (ITO) Gold 2 O 3 -ZnO) can be formed using sputtering or vacuum deposition. For example, after forming a transparent conductive layer, a resist mask is formed on the transparent conductive layer, and an etching process is performed. Transparent conductive layers 310, 328, and 329 are formed by removing unnecessary portions by etching. It is possible.

[0156] Through the above process, elements such as bottom-gate n-channel thin-film transistors and storage capacitors can be fabricated. These elements are then arranged in a matrix to correspond to the individual pixels. One substrate for fabricating an active matrix display device by disposing the For the sake of convenience, this type of substrate is referred to as an active matrix substrate in this specification. Call.

[0157] When manufacturing an active matrix type liquid crystal display device, an active matrix substrate A liquid crystal layer is provided between the active matrix substrate and a counter substrate having a counter electrode. The opposing substrate may be fixed.

[0158] The configuration shown in this embodiment is not limited to the pixel configuration shown in FIG. FIG. 15 shows a transparent conductive layer 31 functioning as a pixel electrode without a capacitance wiring 308. 0 and the gate wiring 302 of the adjacent pixel are used as electrodes, and the protective insulating layer 340 and the gate insulating layer The layer 204 serves as a dielectric to form a storage capacitor.

[0159] Note that this embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0160] (Embodiment 6) In this embodiment mode, a thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further In the case of manufacturing a semiconductor device (also called a display device) having a display function by using the device in a driver circuit, In addition, a part or the whole of a driver circuit made of thin film transistors is used as a pixel region. A system-on-panel can be formed by integrally forming the display and the display device on the same substrate.

[0161] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0162] The display device includes a panel in which a display element is sealed, and a controller for the panel. The display device further includes a module in which an IC or the like including the display device is mounted. In the process of manufacturing the display device, the element substrate corresponds to a form before the display device is completed. The element substrate includes a means for supplying a current to each of the plurality of pixels. Specifically, only the pixel electrodes of the display element may be formed, or the pixel electrodes and The conductive layer is formed and the pixel electrode is not yet formed by etching. is fine, and all forms apply.

[0163] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0164] In this embodiment, a liquid crystal display device will be described as an example of a semiconductor device which is one embodiment of the present invention. First, the appearance and cross section of a liquid crystal display panel, which corresponds to one embodiment of a semiconductor device, will be described with reference to FIG. 16(A1) and 16(A2) show an In-GaAs thin film formed on a first substrate 4001. Highly reliable thin film transistors containing a-Zn-O based non-single crystal film as a semiconductor layer 4010 The liquid crystal element 4013 is disposed between the second substrate 4006 and a sealing material 4005. FIG. 16(B) is a top view of the panel sealed by the above method. Equivalent to the cross-sectional view at -N.

[0165] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealant 4005, and a second substrate 4006. The liquid crystal layer 4008 is sealed together with the first substrate 4001. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0166] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, A wire bonding method, a TAB method, or the like can be used. FIG. 16A shows an example of mounting a signal line driver circuit 4003 by the COG method. This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0167] In addition, a pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 16B, the thin film transistor included in the pixel portion 4002 is A thin film transistor 4010 and a thin film transistor 401 included in a scanning line driver circuit 4004 The insulating layers 4020 and 4011 are formed on the thin film transistors 4010 and 4011. 21 is provided.

[0168] The thin film transistors 4010 and 4011 are made of In-Ga-Zn-O non-single crystal films as semiconductor layers. In this embodiment, a highly reliable thin film transistor including the above-mentioned The thin film transistors 4010 and 4011 are n-channel thin film transistors.

[0169] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0170] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Alternatively, you can use aluminum foil with a PVF film or polyester film. A sheet having a structure sandwiched between films can also be used.

[0171] Also, 4035 is a columnar spacer obtained by selectively etching the insulating layer. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031, A spherical spacer may be used. 1 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the counter electrode layer 4 to the conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 4 to the common potential line. Included in 005.

[0172] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs to It is short at 100μs, has optical isotropy so no alignment treatment is required, and has small viewing angle dependency. stomach.

[0173] Note that the liquid crystal display device shown in this embodiment is an example of a transmission type liquid crystal display device. The device can be applied to both a reflective liquid crystal display device and a semi-transmissive liquid crystal display device.

[0174] In the liquid crystal display device shown in this embodiment mode, a polarizing plate is provided on the outer side (the viewing side) of the substrate. In this example, a colored layer and an electrode layer for use in a display element are provided on the side of the substrate in this order. The laminated structure of the polarizing plate and the colored layer is not limited to the embodiment, and the polarizing plate may be provided in the same manner. The thickness may be appropriately set depending on the material of the colored layer and the manufacturing process conditions. A light-shielding film that functions as a light shielding film may be provided.

[0175] In this embodiment, in order to reduce the surface unevenness of the thin film transistor, It acts as a protective layer and a planarizing insulating layer for thin-film transistors to improve the reliability of the transistors. The insulating layer 4020 and the insulating layer 4021 are formed to cover the insulating layer 4020 and the insulating layer 4021. is intended to prevent the intrusion of polluting impurities such as organic matter, metals, and water vapor suspended in the air. The protective layer is preferably a silicon oxide film or a silicon nitride film formed by sputtering. Silicon film, silicon oxynitride film, silicon oxynitride film, aluminum oxide film, aluminum nitride film Aluminum oxide film, aluminum oxynitride film, or aluminum oxide nitride film, or a single layer or a multilayer structure. In this embodiment mode, an example in which the protective layer is formed by a sputtering method is shown; however, the method is not particularly limited. The insulating layer 11 may be formed by various methods.

[0176] Here, an insulating layer 4020 having a laminated structure is formed as a protective layer. A silicon oxide film is formed as the first layer of the 0 by sputtering. By using a silicon film, the hysteresis of the aluminum film used as the source electrode layer and the drain electrode layer can be improved. It is effective in preventing lockup.

[0177] In addition, an insulating layer is formed as the second layer of the protective layer. A silicon nitride film is formed by sputtering. A silicon nitride film is used as a protective layer. When this happens, mobile ions such as sodium penetrate into the semiconductor region and change the electrical properties of the TFT. This can prevent the deterioration of the image.

[0178] After forming the protective layer, the semiconductor layer may be annealed (at 300° C. to 400° C.). stomach.

[0179] In addition, an insulating layer 4021 is formed as a planarizing insulating layer. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. are used. In addition, by laminating multiple insulating layers made of these materials, 4021 may be formed.

[0180] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, the organic group may have a fluoro group. That's fine.

[0181] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife When the insulating layer 4021 is formed using a material liquid, In the step of bonding, the semiconductor layer may be annealed (at 300° C. to 400° C.) at the same time. By combining the firing process of the edge layer 4021 with the annealing process of the semiconductor layer, a semiconductor device can be efficiently manufactured. It becomes possible to do so.

[0182] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0183] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The formed pixel electrode preferably has a light transmittance of 70% or more at a wavelength of 550 nm. In addition, the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. preferable.

[0184] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0185] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials are applied to 002 via FPC4018.

[0186] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the same conductive layer as the thin film transistors 4010 and 30. The source electrode layer and the drain electrode layer 11 are formed of the same conductive layer.

[0187] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0188] In FIG. 16, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. However, the present embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0189] FIG. 17 shows a liquid crystal display module, which corresponds to one form of a semiconductor device, using a TFT substrate 2600. An example of the configuration is shown in FIG.

[0190] FIG. 17 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is necessary for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. A wiring board 2609 is connected to the wiring circuit section 2608 of the TFT board 2600, and the controller The LCD has external circuits such as a filter circuit and a power supply circuit. The layers may be laminated with a retardation plate interposed therebetween.

[0191] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0192] Through the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device. .

[0193] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0194] (Embodiment 7) In this embodiment, electronic paper will be described as an example of a semiconductor device which is one embodiment of the present invention.

[0195] FIG. 18 shows an active matrix type electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the body device may be the thin film transistor shown in any one of the first to third embodiments. It can be fabricated in the same way as a transistor.

[0196] The electronic paper in FIG. 18 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method for controlling the orientation of spherical particles and displaying information by generating a light-emitting diode.

[0197] A thin film transistor 581 provided on a substrate 580 is a thin film transistor of a bottom gate structure. The source electrode layer or the drain electrode layer is a first electrode layer 587 and an insulating layer 583, The first electrode is electrically connected to the second electrode through contact holes formed in the first electrode 84 and the second electrode 585. Between the layer 587 and the second electrode layer 588, there are black areas 590a and white areas 590b. and a spherical particle 589 having a cavity 594 therearound that is filled with liquid. The spherical particles 589 are surrounded by a filler 595 such as resin (see FIG. 18). In FIG. 18, the first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is provided over the same substrate as the thin film transistor 581. The common connection portion shown in the above embodiment is used to electrically connect a pair of A second electrode layer 588 provided on the substrate 596 is connected to the second electrode layer 588 via conductive particles disposed between the substrates. It is possible to electrically connect to a common potential line.

[0198] Also, instead of the twist ball, an electrophoretic element can be used. In that case, A transparent liquid is enclosed in a 10 cm diameter tube containing positively charged white particles and negatively charged black particles. Microcapsules of about 200 μm in size are used. Between the first electrode layer and the second electrode layer The microcapsules provided on the substrate are subjected to an electric field by the first electrode layer and the second electrode layer. When the light is turned on, the white particles and black particles move in opposite directions, allowing the display to be white or black. A display element that applies this principle is an electrophoretic display element, and is generally called electronic paper. Since electrophoretic display elements have a higher reflectivity than liquid crystal display elements, the auxiliary light It does not require a battery, consumes little power, and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display unit, the image once displayed can be retained. Therefore, it is possible to transmit the signal from the radio wave source to the semiconductor device with a display function (simply a display device, or a display The displayed image is preserved even if the device (also called a semiconductor device having the device) is moved away. It will be possible to keep

[0199] In this manner, electronic paper with high reliability as a semiconductor device can be manufactured.

[0200] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0201] (Embodiment 8) In this embodiment, an example of a light-emitting display device will be described as a semiconductor device which is one embodiment of the present invention. The display element of the display device is a light-emitting element that uses electroluminescence. The light-emitting element that utilizes electroluminescence is an organic compound that is used as the light-emitting material. Generally, the former are organic EL elements, the latter are inorganic compounds. These are called inorganic EL elements.

[0202] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into layers containing light-emitting organic compounds, causing a current to flow. The rears (electrons and holes) recombine to form an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. Such a light-emitting element is called a current-excitation type light-emitting element.

[0203] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0204] FIG. 19 shows a semiconductor device to which digital time gray scale driving can be applied as an example of the semiconductor device according to one embodiment of the present invention. FIG. 1 is a diagram showing an example of a pixel configuration that can be used.

[0205] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. The channel formation region is made of an oxide semiconductor layer (In-Ga-Zn-O non-single crystal film). 1 shows an example in which two L-channel transistors are used in one pixel.

[0206] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, The switching transistor 64 has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408 .

[0207] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0208] The capacitor 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. It is also possible to set the gate capacitance of the driving transistor 6402 as follows: A capacitance may be formed between the gate electrode and the second electrode.

[0209] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is The driving transistor 6402 is in two states, either fully on or fully off. A video signal is inputted, that is, the driving transistor 6402 is operated in a linear region. In order to operate the driving transistor 6402 in a linear region, the voltage of the power supply line 6407 must be higher than that of the driving transistor 6402. A high voltage is applied to the gate of the driving transistor 6402. A voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied.

[0210] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 19 can be used.

[0211] In the case of performing analog gradation driving, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or higher than the forward voltage of the light emitting element 6401 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and should be at least 100% forward voltage. In addition, the video transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The gate potential of the light emitting element 6402 is set higher than that of the light emitting element 6403. Analog gradation drive can be performed by passing a current corresponding to a video signal through 6404.

[0212] Note that the pixel configuration shown in FIG. 19 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0213] Next, the configuration of the light-emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be described using the example of the type shown in Figures 20(A), (B), and (C). The driving TFTs used in the semiconductor device are TFTs 7001, 7011, and 7021. It can be manufactured in the same manner as the thin film transistor shown in the embodiment, and is an In-Ga-Zn-O system non-single crystal. The thin film transistor is highly reliable and contains a crystal film as a semiconductor layer.

[0214] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and side emission. There are light-emitting elements with a double-sided emission structure that emits light from the side of the substrate. The present invention can also be applied to optical elements.

[0215] A light emitting element having a top emission structure will be described with reference to FIG.

[0216] In FIG. 20A, a TFT 7001 which is a driving TFT is an n-type TFT, and a light emitting element 7002 emits light. FIG. 20(A) shows a cross-sectional view of a pixel when the light incident on the pixel exits the anode 7005 side. A cathode 7003 of a light emitting element 7002 and a TFT 7001 which is a driving TFT are electrically connected. A light-emitting layer 7004 and an anode 7005 are laminated in this order on a cathode 7003. 7003 uses various materials as long as they have a small work function and are conductive films that reflect light. For example, Ca, Al, MgAg, AlLi, etc. are preferable. 004 may be composed of a single layer or may be composed of multiple layers stacked together. In the case where the cathode 7003 is composed of multiple layers, an electron injection layer, an electron transport layer, and a The light-transmitting layer, the light-emitting layer, the hole-transporting layer, and the hole-injecting layer are laminated in this order. The anode 7005 is formed using a light-transmitting conductive material. For example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide Lead oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide, Indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, and silicon oxide are added. A light-transmitting conductive layer such as doped indium tin oxide may also be used.

[0217] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 constitutes the light-emitting element 7002. In the case of the pixel shown in FIG. 20(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as indicated by the mark.

[0218] Next, a light emitting element having a bottom emission structure will be described with reference to FIG. When 011 is an n-type light emitting element and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side, FIG. 20B shows a cross-sectional view of a pixel. A cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive layer 7017. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. When the anode 15 has a light-transmitting property, a shielding layer for reflecting or blocking light is provided so as to cover the anode. The cathode 7013 may have a film 7016 formed thereon, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, a 20 nm film An aluminum film having a thickness of 700 nm can be used as the cathode 7013. 014 may be composed of a single layer, as in FIG. 20(A), or may be composed of multiple layers. The anode 7015 does not need to transmit light, but as shown in FIG. As in the case of 20(A), the insulating film 20 can be formed using a conductive material having light-transmitting properties. The shielding film 7016 may be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin containing a black pigment may be used.

[0219] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 20B, the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0220] Next, a light emitting element having a dual emission structure will be described with reference to FIG. Then, on a conductive layer 7027 having a light transmitting property and electrically connected to a driving TFT 7021, A cathode 7023 of the light-emitting element 7022 is formed, and a light-emitting layer 7024 is formed on the cathode 7023. The anode 7025 is laminated in order. The cathode 7023 is, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be For example, the cathode 7023 is made of Al having a thickness of 20 nm. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be configured as a single layer or as a laminate of multiple layers. 25 is formed using a conductive material having a light transmitting property, similar to FIG. It is possible.

[0221] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 20C, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0222] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0223] In this embodiment, a thin film transistor (driving TFT) that controls driving of a light emitting element is Although an example in which the light-emitting element is electrically connected has been shown, the current between the driving TFT and the light-emitting element is A control TFT may be connected.

[0224] Note that the semiconductor device described in this embodiment mode is not limited to the configuration shown in FIG. Many variations are possible.

[0225] Next, the appearance and structure of a light-emitting display panel (also called a light-emitting panel) which corresponds to one embodiment of a semiconductor device will be described. The cross section will be described with reference to FIG. 21. FIG. 21(A) shows a cross section of a semiconductor device formed on a first substrate 4501. A highly reliable thin film transistor containing a non-single crystal In-Ga-Zn-O-based semiconductor layer The resistors 4509 and 4510 and the light emitting element 4511 are sealed between the second substrate 4506. FIG. 21(B) is a top view of the panel sealed with a material 4505. This corresponds to the cross-sectional view in HI.

[0226] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. The filling material 4507 is sealed with the sealing material 4507. Highly sealed protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the package in a material such as a film or a cover material.

[0227] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 21B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0228] The thin film transistors 4509 and 4510 are made of In-Ga-Zn-O non-single crystal films as semiconductor layers. In this embodiment, a highly reliable thin film transistor including the above-mentioned The thin film transistors 4509 and 4510 are n-channel thin film transistors.

[0229] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured as a first electrode layer 4517, an electroluminescent layer The first electrode layer 4512 and the second electrode layer 4513 are stacked in a stacked structure. The light emitting element 4511 is not rotated in accordance with the direction of the light to be extracted from the light emitting element 4511. The configuration can be changed as appropriate.

[0230] The partition 4520 is formed using an organic resin layer, an inorganic insulating layer, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0231] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0232] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective layer may be formed on the partition wall 4513 and the partition wall 4520. The protective layer may be formed of silicon nitride. It is possible to form a silicon oxide nitride film, a DLC film, etc.

[0233] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0234] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 of the light emitting element 4511. The terminal electrode 4516 is formed from the same conductive layer as the thin film transistors 4509 and 517. The source electrode layer and the drain electrode layer 510 are formed from the same conductive layer.

[0235] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0236] The second substrate 4506 located in the direction in which light is extracted from the light emitting element 4511 must be transparent. In this case, a glass plate, a plastic plate, a polyester film or A light-transmitting material such as an acrylic film is used.

[0237] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of oil or thermosetting resin, and can be made of PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. In this embodiment, filler 4507 Nitrogen was used as the gas.

[0238] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0239] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0240] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0241] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0242] (Embodiment 9) The semiconductor device according to one embodiment of the present invention can be used as electronic paper. The LCD can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, and train rides. It can be used for in-vehicle advertising, display on various cards such as credit cards, etc. An example of the electronic device is shown in FIG. 22 and FIG.

[0243] FIG. 22(A) shows a poster 2631 made of electronic paper. When the advertisements are printed on paper, they are replaced manually. You can change the display of your ad in a short time. Also, the display is stable and the image does not collapse. The poster may be configured to transmit and receive information wirelessly.

[0244] FIG. 22(B) shows an advertisement 2632 on a train or other vehicle. When using printed paper, advertisements are replaced manually, but with electronic paper, This allows you to change the display of your ads in a short time without a lot of manual labor. The in-car advertisement system is structured to transmit and receive information wirelessly. It is also possible to use the following.

[0245] FIG. 23 also shows an example of an electronic book 2700. For example, the electronic book 2700 is The device is made up of two housings, a housing 2701 and a housing 2703. The body 2703 is integrated with a shaft portion 2711, and the opening and closing movement is performed around the shaft portion 2711. This configuration allows the device to operate like a paper book. It becomes.

[0246] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 23) and An image can be displayed on the display unit 2707 in FIG.

[0247] FIG. 23 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a touch panel, a touch screen, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. This is also fine.

[0248] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0249] (Embodiment 10) A semiconductor device according to one embodiment of the present invention can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras, etc. digital photo frames, mobile phones (also called mobile phones or mobile phone devices), These include large game machines such as small game machines, portable information terminals, audio playback devices, and pachinko machines. can be.

[0250] FIG. 24A shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In addition, the stand 9605 supports the housing 9601. This shows a configuration in which the above is supported.

[0251] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0252] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0253] FIG. 24B shows an example of a digital photo frame 9700. The photo frame 9700 includes a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example images captured by a digital camera. By displaying the image data, it can function like a normal photo frame.

[0254] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The captured image data can be displayed on the display portion 9703 .

[0255] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0256] FIG. 25(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 25(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and at least the semiconductor device It is sufficient that the device is provided with the equipment, and other auxiliary equipment may be provided as appropriate. The portable gaming machine shown in FIG. 25(A) uses a program or data recorded on a recording medium. It also has the function of reading the information and displaying it on the display, and sharing information with other portable gaming machines via wireless communication. However, the functions of the portable gaming machine shown in FIG. 25(A) are not limited to these. It can have a variety of functions.

[0257] FIG. 25(B) shows an example of a slot machine 9900, which is a large-scale gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. The Machine 9900 also includes other operating means such as a start lever and stop switch, coin The slot machine 9900 is equipped with a slot slot, a speaker, etc. However, the present invention is not limited to the above, and any configuration including at least a semiconductor device according to one embodiment of the present invention is possible. Other auxiliary equipment may be provided as appropriate.

[0258] FIG. 26A shows an example of a mobile phone 1000. The mobile phone 1000 has a housing. In addition to the display unit 1002 incorporated in the 1001, the operation buttons 1003 and the external connection port 10 04, a speaker 1005, a microphone 1006, etc.

[0259] The mobile phone 1000 shown in FIG. 26A displays information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a phone call or sending an e-mail can be performed without using the display. This can be done by touching the display unit 1002 with a finger or the like.

[0260] The screen of the display unit 1002 has three main modes. The first is a display mode that is mainly used for displaying images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. This is a display + input mode that combines the display mode and the input mode.

[0261] For example, when making a call or composing an e-mail, the display unit 1002 is used for inputting characters. The main character input mode is to input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0262] In addition, a sensor for detecting tilt, such as a gyro or an acceleration sensor, is installed inside the mobile phone 1000. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0263] The screen mode can be changed by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, the image signal to be displayed on the display unit is a moving image. If it is data, the mode is switched to display mode, and if it is text data, the mode is switched to input mode.

[0264] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0265] The display unit 1002 can also function as an image sensor. By touching the palm or fingers to the sensor 02, the palm print, fingerprint, etc. can be captured and identity authentication can be performed. In addition, the display unit may be equipped with a backlight that emits near-infrared light or a sensor that emits near-infrared light. By using a scanning light source, it is also possible to image finger veins, palm veins, etc.

[0266] FIG. 26B is also an example of a mobile phone. The mobile phone in FIG. 26B has a housing 9411. A display device 9410 including a display portion 9412 and an operation button 9413 and a housing 9401 An operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and The communication device 9400 includes a light emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 can be attached to and detached from the communication device 9400 having a telephone function in the two directions shown by the arrows. Therefore, the display device 9410 and the communication device 9400 can be attached to each other with their short axes facing each other. The display device 9410 and the communication device 9400 can be attached to each other with their long axes facing each other. When only the function is required, the display device 9410 is removed from the communication device 9400, and the display device The communication device 9400 and the display device 9410 may be used alone. Images or input information can be sent and received via wireless or wired communication, and each can be recharged with a rechargeable battery. Has Terry. [Explanation of symbols]

[0267] 190 Chamber 191 Electrode 192 Electrode 193 Matching Box 194 Matching Box 195 Processing object 196 Introduction 197 RF power supply 198 RF power supply 199 DC power supply 200 boards 202 Gate electrode layer 204 Gate insulating layer 206 Conductive Layer 207 Recess 208 Plasma 209 Oxide semiconductor layer 210 Oxide semiconductor layer 213 Contact Hole 217 Oxide Semiconductor Layer 250 Thin Film Transistors 251 Insulating Layer 252 Insulating layer 260 Thin Film Transistor 270 Thin-film transistor 271 Thin-film transistor 272 Thin-film transistor 280 Thin Film Transistor 290 Thin Film Transistor 302 Gate wiring 308 Capacitance wiring 310 Transparent conductive layer 320 Connection electrode 321 Terminal 322 Terminal 325 Contact Hole 326 Contact Hole 327 Contact Hole 328 Transparent conductive layer 329 Transparent conductive layer 340 Protective insulation layer 580 Substrate 581 Thin Film Transistor 583 Insulating Layer 584 Insulating Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 594 Cavity 595 Filling material 596 Board 1000 Mobile Phones 1001 Case 1002 Display section 1003 Operation button 1004 External connection port 1005 Speaker 1006 Mike 206a Source electrode layer 206b Drain electrode layer 217a Buffer layer 217b Buffer layer 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2631 Poster 2632 In-car advertising 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4033 Insulation layer 4501 Board 4502 Pixel section 4505 Sealing material 4506 Board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4519 Anisotropic conductive film 4520 Bulkhead 590a black area 590b White area 6400 pixels 6401 Switching transistor 6402 Driving transistor 6403 Capacitor 6404 Light emitting element 6405 Signal Line 6406 scan lines 6407 Power line 6408 Common electrode 7001 TFT 7002 Light emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7011 Driving TFT 7012 Light emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding membrane 7017 Conductive layer 7021 Driving TFT 7022 Light emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive layer 9400 Communication Equipment 9401 Case 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light emitting part 9410 Display device 9411 Housing 9412 Display section 9413 Operation button 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 Slot Machine 9901 Case 9903 Display section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4518a FPC 4518b FPC

Claims

[Claim 1] a first conductive layer having a region in contact with an upper surface of the substrate and a region functioning as a gate electrode; a first insulating layer having a region in contact with an upper surface of the first conductive layer and a region functioning as a gate insulating layer; a second conductive layer having a region in contact with an upper surface of the first insulating layer and a region functioning as a source electrode layer; a third conductive layer having a region in contact with an upper surface of the first insulating layer and a region functioning as a drain electrode layer; an oxide semiconductor layer having a channel formation region, the oxide semiconductor layer having a region in contact with a top surface of the first insulating layer, a region in contact with a top surface of the second conductive layer, and a region in contact with a top surface of the third conductive layer; a second insulating layer having a region in contact with an upper surface of the second conductive layer, a region in contact with an upper surface of the third conductive layer, and a region in contact with an upper surface of the oxide semiconductor layer; a third insulating layer having a region in contact with an upper surface of the second insulating layer; a fourth conductive layer having a region in contact with an upper surface of the third insulating layer, and a region in contact with an upper surface of the second conductive layer or a region in contact with an upper surface of the third conductive layer, and having a region that functions as a pixel electrode; a first region in which the first conductive layer, the first insulating layer, and the second conductive layer overlap one another; a second region in which the first conductive layer, the first insulating layer, and the third conductive layer overlap one another; a third region in which the first insulating layer and the channel formation region overlap; a thickness of the first insulating layer in the third region is smaller than a thickness of the first insulating layer in the first region; a thickness of the first insulating layer in the third region is smaller than a thickness of the first insulating layer in the second region; an upper end portion of the second conductive layer and an upper end portion of the third conductive layer have a curved surface; the oxide semiconductor layer contains In, Ga, and Zn; the second insulating layer includes a first film and a second film above the first film; the first film comprises oxygen and silicon; the second film comprises nitrogen and silicon; The third insulating layer comprises an organic material.

Images