Monolithically integrated top-gate thin film transistors and light emitting diodes and methods of manufacture - Patents.com

Abstract

Pixels and subpixels suitable for high density displays are disclosed. High density is achieved by forming top-gate thin film transistors (TFTs) directly on light emitting diodes (LEDs), thereby reducing the required packaging area. To enable a stacked structure, a planarization layer is formed such that its upper surface is flush with the upper surface of the LED's upper electrode. The source and drain of the TFT are then formed on the planarization layer and the electrodes, such that electrical contact is made between the LED and the TFT. In some embodiments, the fabrication includes deposition of an additional planarization layer, whose upper surface is flush with the upper surface of the TFT's gate. This allows for the formation of a parallel plate capacitor on the TFT / LED stack, thereby further reducing the pixel's footprint.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This case claims priority to U.S. Provisional Patent Application No. 63 / 215,776 (Attorney Docket No. 6494-236PR1), entitled "Monolithically Integrated Top-Gate Thin-Film Transistor and LED," filed June 28, 2021, which is incorporated herein by reference in its entirety. If there is any conflict or inconsistency between this application and one or more of the cases incorporated by reference that may affect the interpretation of the claims of this case, the claims in this case shall be construed consistent with the language in this case.

[0002] The present disclosure relates to image display technology, and more particularly to LED-based microdisplays. [Background technology]

[0003] Inorganic light emitting diodes (LEDs) are robust, have long lifetimes, and can emit brighter light than other types of LEDs, such as organic light emitting diodes (OLEDs). As a result, inorganic light emitting diodes are attractive for use as pixel elements in emissive displays and microdisplays.

[0004] However, historically, it has been difficult to integrate inorganic LEDs with pixel driving circuitry in a display backplane. Inorganic LEDs are typically made of compound semiconductor materials, including III-V or II-VI materials, such as gallium nitride (GaN). Compound semiconductor materials require very high temperatures to process (>700C). Drivers made using compound semiconductor technology exhibit significantly higher voltages compared to standard silicon technologies, such as complementary metal-oxide semiconductors (CMOS) with single crystal silicon or thin film transistors (TFTs) using amorphous silicon (aSi) or polycrystalline silicon (poly-Si). As a result, it has been difficult to fabricate practical display devices using only GaN.

[0005] There have been attempts to monolithically combine inorganic LEDs with standard silicon-based transistor technology to achieve displays, but they have been largely unsuccessful. For example, Hartensveld disclosed heteroepitaxial integration of GaN-based microLEDs on silicon substrates in “Fully Monolithic GaN μLED Display System,” Proceedings of Display Week 2021, Paper 61-5, published by the Society for Information Display, conducted online May 17-21, 2021, which is incorporated herein by reference. Unfortunately, the cost and complexity of such monolithic integration techniques make their use out of the question for many applications.

[0006] Heterogeneous integration of inorganic LEDs and silicon-based electronics offers an alternative approach to monolithic integration. Such approaches employ pick-and-place techniques to transfer an array of fully formed LEDs from a bulk LED substrate to a receiving substrate containing previously formed silicon transistor circuitry, where solder bump bonding or a thermoset resin containing conductive particles is used to operatively bond the LEDs and circuitry. Unfortunately, long-term reliability and production yield issues remain difficult to overcome.

[0007] More recently, inorganic LEDs have been demonstrated that are monolithically integrated with TFT circuitry. For example, successful integration of inorganic LEDs with bottom-gate TFT circuitry was disclosed by Gosh in U.S. Patent No. 9,793,252, issued October 17, 2017, which is incorporated herein by reference. Unfortunately, the complex layer stack structure of such structures poses challenging manufacturing problems that continue to prevent many applications from adopting this technology.

[0008] Inorganic LED and TFT transistor-based circuitry monolithically integrated in a practical and cost-effective manner would represent a significant advancement over the prior art. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] U.S. Pat. No. 9,793,252 [Non-patent literature]

[0010] [Non-Patent Document 1] Published by the Society for Information Display, "Fully Monolithic GaN μLED Display System," Proceedings of Display Week 2021, Document 61-5 Summary of the Invention [Problem to be solved by the invention]

[0011] The present disclosure is directed to monolithic integration of top-gate TFT circuitry and inorganic LEDs.Embodiments according to the present disclosure are particularly suitable for use in displays, microdisplays, augmented reality systems, and virtual reality systems. [Means for solving the problem]

[0012] Advances over the prior art are realized by forming displays whose pixels include TFTs with a top-gate architecture disposed directly over LEDs and combined device layers, resulting in a significantly simplified combined circuit and LED layer structure that is easier to manufacture, thereby reducing manufacturing costs and improving yields.

[0013] An exemplary embodiment comprises a top-gate TFT formed directly on top of an inorganic LED structure. The TFT and LED are monolithically integrated on a sapphire substrate. To enable the formation of the TFT on top of the LED, the topography of the LED is adjusted by the encapsulation of a planarization layer comprising a dielectric material. The planarization layer is formed over the LED structure and polished so that its top surface is flush with the top surface of the anode of the LED, which is simultaneously exposed. Once the planarization layer is formed and the top surface of the anode is exposed, the source and drain of the TFT are formed such that the drain is on the anode and they are in electrical communication. The transistor structure is then completed by the deposition of conformal layers of semiconductor and dielectric materials that define the channel region and gate dielectric of the TFT. A gate electrode is then formed on top of the gate dielectric to complete the monolithically integrated structure of the TFT and LED.

[0014] The TFT is formed with its drain disposed over and in physical contact with the anode of the underlying LED, allowing pixels and subpixels according to the present disclosure to be scaled down to sizes not previously possible using prior art approaches. By scaling the pixels and subpixels to extremely small dimensions, they can be used in large format, standard resolution, or near-eye displays.

[0015] In some embodiments, the anode of the LED and one of the drain or source of the TFT are formed from the same layer, hi some embodiments, the anode of the LED functions as the drain or source of the TFT.

[0016] In some embodiments, the storage capacitor is also monolithically integrated with the TFT and LED structure by forming it directly on the gate of the TFT, hi some embodiments, the gate of the TFT serves as one plate of the storage capacitor.

[0017] An embodiment according to the present disclosure is a display including a first pixel, the first pixel including a first light emitting diode (LED) including a first cathode and a first anode, and a first thin film transistor (TFT) disposed on the first LED, the first TFT including a first source, a first drain, and a first gate distal to a substrate, the first LED and the first TFT being monolithically integrated on the substrate such that one of the first cathode and the first anode is electrically coupled to one of the first source and the first drain.

[0018] Another embodiment according to the present disclosure is a display comprising a plurality of pixels, each pixel of the plurality of pixels comprising: a light emitting diode (LED) including a cathode and an anode, the LED having a first surface disposed on a substrate, one of the cathode and the anode being distal to the substrate; a planarization layer having a second surface coplanar with the first surface, the planarization layer comprising a dielectric material; and a thin film transistor (TFT) disposed on the LED and the planarization layer, the TFT including a source, a drain, and a gate distal to the substrate, one of the source and drain electrically coupled to one of the anode and the cathode, the other of the source and drain being disposed on the planarization layer, wherein the plurality of LEDs and the plurality of TFTs are monolithically integrated on the substrate.

[0019] Yet another embodiment according to the present disclosure is a method for forming a display including a plurality of pixels, the method including the steps of: forming a plurality of light emitting diodes (LEDs) on a substrate, each LED of the plurality of LEDs including a cathode and an anode, one of the cathode and the anode having a first surface distal to the substrate; forming a planarization layer including a dielectric material, the planarization layer having a second surface coplanar with the plurality of first surfaces; and forming a plurality of thin film transistors (TFTs) such that each TFT of the plurality of TFTs is disposed on a different LED of the plurality of LEDs, each TFT of the plurality of TFTs including a source, a drain, and a gate distal to the substrate, each TFT being formed such that (1) one of a first source and a first drain is disposed on and electrically connected to one of the first anode and the first cathode of its respective LED, and (2) the other of the source and drain is disposed on the second surface. [Brief description of the drawings]

[0020] [Figure 1A] 1 is a schematic perspective view of a portion of a pixel suitable for use in a light-emitting display according to the present disclosure; [Figure 1B] 1 is a schematic cross-sectional view of a portion of a pixel suitable for use in a light-emitting display according to the present disclosure. [Diagram 2] 1 illustrates an operation of a method suitable for forming a sub-pixel of a pixel of a display according to the present disclosure. [Figure 3A] 1 is a schematic cross-sectional view of an initial subpixel 100' after completion of an LED 102. FIG. [Figure 3B] 1 is a schematic cross-sectional view of an initial subpixel 100' after completion of a planarization layer 120. FIG. [Figure 3C] 1 is a schematic cross-sectional view of an initial sub-pixel 100' after completion of a TFT 104. FIG. [Figure 4A] 1 is a schematic diagram of the electrical layout of a pixel of a display, the pixel including red, green, and blue sub-pixels, in accordance with the present disclosure; [Figure 4B] 1 is a schematic cross-sectional view of the layer structure of the electrical bus regions of subpixels 100R, 100G, and 100B. [Diagram 5] 2 is a schematic perspective view showing a more detailed layer structure of the circuit section 400. FIG. [Figure 6] FIG. 2 is a schematic diagram of a sub-pixel including a monolithically integrated storage capacitor according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The following merely illustrates the principles of the present disclosure, and it will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the present disclosure and are within its spirit and scope.

[0022] Furthermore, all examples and proviso language referred to in this specification are expressly intended to be primarily for educational purposes only to aid the reader in understanding the principles of the present disclosure and concepts brought about by the inventors to improve their techniques, and should be considered as being without limitation to the examples and proviso language so specifically referred to.

[0023] Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. In addition, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.

[0024] Thus, for example, it will be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the present disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudocode, or the like are substantially represented in a computer-readable medium and represent various processes that such computers or processors may so execute, whether or not a computer or processor is explicitly depicted.

[0025] The functions of the various elements shown in the figures, including any functional block that may be labeled "processor," may be realized through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When realized by a processor, the functions may be realized by a single dedicated processor, a single shared processor, or multiple individual processors that may share portions thereof. Furthermore, explicit use of the terms "processor" or "controller" should not be construed to refer solely to hardware capable of executing software, but may implicitly include, without limitation, digital signal processor (DSP) hardware, network processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), read only memory (ROM) for storing software, random access memory (RAM), non-volatile storage devices, and other hardware, conventional and / or custom, may also be included.

[0026] A software module, or simply a module that is implied to be software, may be represented herein as any combination of flowchart elements or other elements illustrating the performance and / or textual description of process steps. Such modules may be executed by hardware that is explicitly or implicitly shown.

[0027] Unless otherwise specified herein, the drawings, including the figures, are not to scale.

[0028] As discussed above, the monolithic integration of top-gate TFT circuitry and inorganic LEDs for use in display and microdisplay applications provides embodiments of the present disclosure with significant advantages over the prior art. First, the combined circuitry and LED layer structure is significantly simplified. Second, such designs are significantly easier to manufacture, resulting in reduced manufacturing costs and improved system yields. Third, the TFT and LED layer stacks are largely independent of each other. As a result, neither needs to compromise processing due to the inclusion of the other.

[0029] 1A-1B depict perspective and cross-sectional schematic diagrams of a portion of a pixel suitable for use in an emissive display according to the present disclosure. The subpixel 100 includes an LED 102 and a TFT 104 monolithically integrated on a substrate 106.

[0030] For purposes of this specification, including the appended claims, the term "monolithic integration" is defined as either formed in the body of a substrate, typically by etching into the substrate, or on the surface of the substrate, typically by patterning a layer disposed on the surface. The term monolithic integration explicitly excludes systems / devices integrated using hybrid integration methods, such as joining fully formed devices using processes such as adhesion, solder bump bonding, etc.

[0031] 2 depicts method acts suitable for forming subpixels of a pixel of a display according to the present disclosure. The method 200 begins at act 201, where an LED 102 is formed on a substrate 106.

[0032] Substrate 106 is a substrate suitable for use in a planar process manufacturing method. Preferably, substrate 106 is substantially transparent to the light emitted by LED 102. In the depicted example, substrate 106 is a sapphire substrate, although other substrates suitable for use in accordance with the present disclosure will be apparent to those of skill in the art after reading this specification.

[0033] The LED 102 is an inorganic LED structure that is epitaxially grown on a substrate 106. The LED 102 includes, among other layers, a semiconductor (SC) layer 108, a gain layer 110, an SC layer 112, a cathode 116, and an anode 118. Typically, the semiconductor and gain layers of the LED 102 are epitaxially grown using metalorganic chemical vapor deposition (MOCVD), although any suitable growth method can be used to form the layers of the LED 102, including atomic layer epitaxy (ALE), molecular beam epitaxy (MBE), etc.

[0034] Formation of the LED 102 begins with the epitaxial growth of an n-type semiconductor (SC) layer 108 on a substrate 106. The SC layer 108 functions as a conductive layer that allows electrical connection to a cathode 116. The SC layer 108 also functions as a lower light confinement layer for a gain layer 110. In the depicted example, the SC layer 108 is a layer of n-type doped gallium nitride (GaN) having a thickness of about 2 microns, although in some embodiments the SC layer 108 comprises a different compound semiconductor material and / or thickness.

[0035] A gain layer 110 is then grown on the SC layer 108. The gain layer 110 comprises one or more layers of a compound semiconductor material suitable for achieving optical gain within the structure of the LED 102. In the depicted example, the gain layer 110 is a multiple quantum well (MQW) layer comprising alternating layers of indium gallium nitride (InGaN) and gallium nitride (GaN) having an overall thickness of about 150 nm, although in some embodiments the gain layer 110 comprises at least one different compound semiconductor material and / or has a different thickness.

[0036] Formation of the LED 102 then continues with epitaxial growth of an SC layer 112 on the gain layer 110. The SC layer 112 serves as a top contact for the LED 102 and as an upper light confinement layer for the gain layer. In the depicted example, the SC layer 112 is a layer of p-type doped GaN having a thickness of about 250 nm, although in some embodiments the SC layer 112 comprises a different compound semiconductor and / or has a different thickness.

[0037] The gain layer 110 and the SC layer 112 are then patterned to define a mesa 114 , which exposes areas of the SC layer 108 in preparation for the formation of a cathode 116 .

[0038] The cathode 116 is formed on the SC layer 108 such that the cathode is electrically coupled to the gain layer 110 through the SC layer 108. In the depicted example, the cathode 116 is a layer of molybdenum (Mo) having a thickness of about 50 nm. Typically, the cathode 116 is formed by direct patterning by sputtering through a shadow mask, although any suitable deposition and / or deposition and patterning method can be used to form the cathode 116.

[0039] In a similar manner, an anode 118 is then formed on the SC layer 112 such that the anode is electrically coupled to the gain layer 110 through the SC layer 112. In the depicted example, the anode 118 is a layer of molybdenum (Mo) having a thickness of about 20 nm.

[0040] FIG. 3A illustrates a schematic cross-sectional view of an initial subpixel 100 ′ after completion of the LED 102 .

[0041] Once the LED 102 is completed, the method 200 continues with operation 202, where a planarization layer 120 is formed over the LED structure. The planarization layer 120 is a layer of dielectric material that fills the area surrounding the mesa 114. In the depicted example, the planarization layer 120 comprises silicon dioxide that is vapor deposited over the topography of the LED 102. In some embodiments, the planarization layer 120 is deposited in a manner other than vapor deposition, such as spin coating, spray coating, or the like.

[0042] In operation 203, planarization layer 120 is thinned to expose a top surface (i.e., surface S1) of anode 118. As a result, surface S2 (i.e., top surface of planarization layer 120) is approximately coplanar with surface S1, defining a plane suitable for formation of the layers of TFT 104 using planar processing techniques. In the depicted example, planarization layer 120 is thinned and planarized via chemical mechanical polishing (CMP), although any suitable method may be used without departing from the scope of this disclosure.

[0043] FIG. 3B depicts a schematic cross-sectional view of an initial subpixel 100 ′ after completion of the planarization layer 120 .

[0044] In operation 204 , the TFT 104 is formed on the substrate 106 .

[0045] The TFT 104 is a FET transistor structure configured such that its gate is distal to the LED 102. The TFT 104 includes a gate 122, a drain 124, a source 126, a semiconductor layer 128, and a gate dielectric 130.

[0046] Formation of the TFT 104 begins with the formation of a drain 124 on the anode 118 and a source 126 on the top surface of the planarization layer 120. Typically, the drain 124 and the source 126 are formed in the same operation using methods similar to those described above for the formation of the cathode 116. In the illustrated example, the drain 124 and the source 126 are each a layer of molybdenum having a thickness of about 20 nm.

[0047] After definition of the drain 124 and source 126, an SC layer 128 is deposited over them using a conformal deposition method such that the material is between the source and drain. In the illustrated example, the SC layer 128 is a layer of indium gallium zinc oxide (IGZO) having a thickness of about 40 nm.

[0048] A gate dielectric 130 is then formed over the SC layer 128. In the example depicted, the gate dielectric 130 is a layer of silicon dioxide having a thickness of about 150 nm.

[0049] The formation of the TFT 104 is completed with the definition of a gate 122 on the top surface of the gate dielectric 130. In the example depicted, the gate 122 comprises a layer of molybdenum having a thickness of about 20 nm.

[0050] However, as will be apparent to one of ordinary skill in the art after reading this specification, any suitable thicknesses and / or materials can be used for any of the component layers / structures of TFT 104 without departing from the scope of the present disclosure.

[0051] As will also be apparent to one of ordinary skill in the art, in some embodiments, subpixel 100 will typically include additional semiconductor layers (e.g., buffer layers, contact extension layers, etc.) as well as additional features such as vias, bond pads, and electrical traces that enable its electrical connection to other subpixels, control circuitry, drive circuitry, etc. For clarity, these layers / features are not shown in the depicted example.

[0052] FIG. 3C depicts a schematic diagram of a cross section of the initial subpixel 100 ′ after completion of the TFT 104 .

[0053] In operation 205 , a passivation layer 132 is formed to electrically passivate the LED 102 and the TFT 104 , thereby completing the subpixel 100 .

[0054] When the subpixel 100 is completed, the TFT 104 and LED 102 are electrically coupled through the drain 124 and anode 118, which are formed such that the drain is in physical contact with the anode. In some embodiments, the anode 118 and drain 124 are defined by a single element within the structure of the TFT 104.

[0055] 4A shows a schematic diagram of an electrical layout of a pixel of a display according to the present disclosure, the pixel including red, green, and blue subpixels. Display portion 400 illustrates pixel P1, one pixel of a display comprising a plurality of substantially identical pixels. Pixel P1 includes three subpixels 100R, 100G, and 100B, a bus 402, and a bus 404.

[0056] 4B shows a schematic cross-sectional view of the layer structure of the electrical bus regions of subpixels 100R, 100G, and 100B. Layer structure 406 simply depicts bus 402 and bus 404, as well as the interlayer dielectric therebetween that provides electrical isolation.

[0057] Each of subpixels 100R, 100G, and 100B includes, among other circuit elements, an LED 102 configured to emit a desired color for that subpixel, and a TFT 104 electrically connected as discussed above and with respect to Figures 1A-1B. In other words, subpixels 100R, 100G, and 100B include LEDs 102R, 104G, and 104B, respectively, where LED 102R emits red light, LED 102G emits green light, and LED 102B emits blue light.

[0058] In each of subpixels 100R, 100G, and 100B, the LED cathode 116 is electrically connected to an electrical bus 402 that is held at a common VSS voltage level. In a similar manner, in each subpixel, the source of its respective drive transistor 104 is electrically connected to an electrical bus 404 that is held at a common ELVDD voltage level.

[0059] In the depicted example, the buss 402 is formed at the same time as the cathode 116, however, the buss 402 may be formed in a separate process without departing from the scope of this disclosure.

[0060] In a similar manner, in the depicted example, the buss 404 is formed simultaneously with the drain 124 and the source 126, although the buss 404 may be formed in a separate process without departing from the scope of the present disclosure.

[0061] Bus 402 is electrically isolated from bus 404 by a portion of planarization layer 120 that acts as an interlevel dielectric. In some embodiments, different dielectric layers are included to electrically isolate bus 402 and bus 404.

[0062] 5 shows a more detailed perspective schematic diagram of the layer structure of circuitry 400. As is common to most LED-based displays, data lines DataR, DataG, and DataB are common to all of the pixels in the same row of the display. Typically, the data lines and gates of each subpixel are separated by a thick layer of electrical insulator (i.e., insulator 504). In some embodiments, insulator 504 comprises passivation layer 132.

[0063] In the prior art, each pixel (or subpixel) typically includes a storage capacitor positioned adjacent to a transistor and an LED. In other words, the circuit elements included in the pixel drive circuit are arranged horizontally. As a result, each circuit element requires a significant amount of chip real estate, which places a lower limit (and a commensurate upper limit for pixel density) on how small each pixel can be made.

[0064] However, it is an aspect of this disclosure that the storage capacitor can be formed on top of the TFT, allowing for vertical placement of the elements, thereby reducing the footprint required for a given pixel drive circuitry.

[0065] 6 depicts a schematic diagram of a subpixel including a monolithically integrated storage capacitor according to the present disclosure. Subpixel 600 comprises subpixel 100 and a capacitor 602.

[0066] Capacitor 602 is a parallel plate capacitor that includes capacitor plates C1 and C2 positioned on either side of a dielectric 604. Capacitor 602 is formed over subpixel 100 such that plate C1 is in physical and electrical contact with gate 122.

[0067] Each of the capacitor plates C1 and C2 is similar to the above-described cathode 116. In the example depicted, each capacitor plate is a layer of molybdenum having a thickness of about 50 nm.

[0068] Dielectric 604 is similar to the above-described gate dielectric 130. In the example depicted, dielectric 604 is a layer of silicon dioxide having a thickness of about 150 nm.

[0069] Although not depicted, a planarization layer similar to planarization layer 120 is typically formed over subpixel 100 prior to the formation of plate C1.

[0070] By forming the sub-pixel 600 such that the capacitor 602 is disposed on top of the TFT 104, embodiments according to the present disclosure provide significant advantages over the prior art, including the following: i. Reducing the pixel area required for the circuitry, or ii. Increased pixel density, or iii. Increased circuit complexity without sacrificing pixel density, or iv. A larger capacitor for better storage performance, or v. Any combination of i, ii, iii, and iv

[0071] This disclosure teaches several examples of illustrative embodiments, and it should be understood that those skilled in the art will be able to readily conceive numerous variations of the invention after reading this disclosure. [Explanation of symbols]

[0072] 100 subpixels 100' Initial Subpixel 100B Blue subpixel 100G Green subpixel, 2nd subpixel 100R Red subpixel 102 Light emitting diode, LED 102G 2nd LED 102R First Light Emitting Diode, LED 104 TFT 104G 2nd TFT 104R First thin film transistor, TFT 106 Substrate 108 n-type SC layer, semiconductor layer 110 Gain Layer 112 p-type SC layer 114 Mesa 116 First cathode, second cathode 118 First anode, second anode 120 Planarization layer Gate 122 122G 2nd Gate 122R 1st Gate 124 Drain 124G Second Drain 124R First Drain 126 Source 126G Second Source 126R First Source 128 SC layer, semiconductor layer 130 Gate Dielectric 132 Passivation Layer 400 Display section, circuit section 402 Bus 404 Bus 406 layer structure 504 Insulators 600 subpixels 602 Parallel Plate Capacitor 604 Dielectric C1 First plate C2 Second Plate P1 First pixel S1 surface, top surface S2 Surface, first surface

Claims

1. A display comprising a first pixel (P1), said first pixel (P1) having a first light emitting diode (LED) (102R) including a first cathode (116) and a first anode (118); a first thin film transistor (TFT) (104R) disposed on the first LED, the first TFT (104R) including a first source (126R), a first drain (124R), and a first gate (122R) distal to a substrate (106); Including, the first LED and the first TFT are monolithically integrated on the substrate such that one of the first cathode and the first anode is electrically coupled to one of the first source and the first drain; A display wherein the first anode and the first drain are in direct physical contact.

2. 2. The display of claim 1, wherein the first anode has a top surface (S1), the first pixel includes a planarization layer (120) comprising a dielectric material, the planarization layer (120) having a first surface (S2) that is coplanar with the top surface, and further wherein one of the first source and the first drain is disposed on the first surface.

3. 2. The display of claim 1, wherein the first anode is the first drain.

4. 2. The display of claim 1, wherein the first pixel further comprises a parallel plate capacitor (602) having a first plate (C1), a second plate (C2), and a dielectric layer (604) disposed between the first plate and the second plate, the first plate being electrically coupled to the first gate and the first plate being disposed on and in physical contact with the first gate.

5. 5. The display of claim 4, wherein the first plate is the first gate.

6. The first pixel is a second LED (102G) including a second cathode (116) and a second anode (118); a second TFT (104G) disposed on the second LED, the second TFT (104G) including a second source (126G), a second drain (124G), and a second gate (122G) distal to the substrate; and further comprising a second subpixel (100G) comprising:

2. The display of claim 1, wherein the second LED and the second TFT are monolithically integrated on the substrate such that one of the second cathode and the second anode is electrically coupled to one of the second source and the second drain.

7. A method for forming a display comprising a plurality of pixels (P1), comprising the steps of: forming a plurality of light emitting diodes (LEDs) (102) on a substrate, each LED of the plurality of LEDs including a cathode (116) and an anode (118), one of the cathode and the anode having a first surface (S1) distal to the substrate; forming a planarization layer (120) comprising a dielectric material, said planarization layer having a second surface (S2) coplanar with said first surfaces; forming a plurality of thin film transistors (TFTs) (104) such that each TFT of the plurality of TFTs is disposed over a different LED of the plurality of LEDs, each TFT of the plurality of TFTs including a source (126), a drain (124), and a gate (122) distal to the substrate; Including, Each TFT is formed such that (1) one of the source and the drain is disposed on and electrically connected to one of the anode and the cathode of its respective LED, and (2) the other of the source and the drain is disposed on the second surface; wherein in each pixel of the plurality of pixels, the anode and the drain are formed such that the anode and the drain are in direct physical contact and electrically connected.

8. The method of claim 7 , wherein in each pixel of the plurality of pixels, the anode is formed such that the anode is the drain.

9. 8. The method of claim 7, further comprising forming a plurality of parallel plate capacitors (602), each capacitor having a first plate (C1), a second plate (C2), and a dielectric layer (604) disposed between the first plate and the second plate, and in each pixel of the plurality of pixels, the first plate is electrically coupled to the gate of its respective TFT, and the first plate is disposed on and in physical contact with the gate.

10. The method of claim 9 , wherein the first plate is the gate.

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