Semiconductor Device

Abstract

To provide a semiconductor device including a transistor with an oxide semiconductor, whose electric characteristics vary less, reliability is high, and on-state current is large.SOLUTION: An insulating layer that releases a large amount of oxygen is used as an insulating layer in contact with a channel region of an oxide semiconductor layer. An insulating layer that releases a small amount of oxygen is used as an insulating layer in contact with a source region and a drain region of the oxide semiconductor layer. Using the insulating layer that releases a large amount of oxygen and releasing a large amount of oxygen can reduce the oxygen deficiency in the channel region and the interface state density of the insulating layer and the channel region. Thus, the semiconductor device whose electric characteristics vary less and reliability is high can be manufactured. The increase in resistance of the source region and the drain region is suppressed by providing the source region and the drain region in contact with the insulating layer that releases a small amount of oxygen.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] A technology for constructing transistors using a semiconductor thin film formed on a substrate with an insulating surface. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in such electronic devices. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention as other materials. is.

[0004] For example, a semiconductor with an electron carrier concentration of 10 18 / cm 3 Less than The amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) is used. A transistor having such a structure is disclosed in Patent Document 1.

[0005] Transistors using oxide semiconductors have higher performance than transistors using amorphous silicon. Although they are faster and easier to manufacture than polysilicon transistors, It is known that the electrical characteristics are easily fluctuated and the reliability is low. For example, bias - After the thermal stress test (BT test), the threshold voltage of the transistor changes. In this specification, the threshold voltage is the voltage required to turn a transistor on. The gate voltage is the gate potential with respect to the source potential. This refers to the potential difference between a given potential and an electric potential. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2006-165528 A Summary of the Invention [Problem to be solved by the invention]

[0007] The change in threshold voltage of a transistor using an oxide semiconductor due to a BT test is In one embodiment of the present invention, the reliability of a transistor using an oxide semiconductor is significantly reduced. The present invention aims to improve the reliability of a semiconductor device using such a body. [Means for solving the problem]

[0008] One embodiment of the present invention is an insulating layer in contact with a channel region of an oxide semiconductor layer, The insulating layer which releases oxygen is used, and the insulating layer which contacts the source region and the drain region of the oxide semiconductor layer is As the edge layer, an insulating layer which releases less oxygen than the insulating layer in contact with the channel region is used. The present invention relates to a semiconductor device or a method for manufacturing a semiconductor device having the above technical concept.

[0009] One aspect of the present invention is a method for manufacturing an insulating layer having a first region and a second region, and a method for manufacturing an insulating layer having a first region and a second region. a channel region, a source region, and a drain region; a conductive layer, a channel region of the oxide semiconductor layer being provided in contact with the first region, The source region and the drain region of the nitride semiconductor layer are provided in contact with the second region, and the first region The first region is an insulating layer that releases oxygen when heated, and the second region is an insulating layer that releases oxygen in an amount smaller than that of the first region. The present invention relates to a semiconductor device having fewer insulating layers or a method for manufacturing the semiconductor device.

[0010] "Oxygen is released by heating" refers to TDS (Thermal Desorption Spectroscopy: Thermal Desorption Spectroscopy) analysis, oxygen converted to oxygen atoms The amount of emission is 1×10 18 atoms / cm 3 More than 3×10 20 atoms / cm 3 This means that the above is the case.

[0011] Oxygen is supplied to the channel region from the first region, which is an insulating layer in contact with the channel region. As a result, the interface state density between the channel region and the first region can be reduced. Charges that may be generated due to the operation of the first region are captured at the interface between the first region and the channel region. This can adequately prevent the leakage of the liquid.

[0012] In addition, charges may occur due to oxygen vacancies in the channel region. Some of the oxygen vacancies in the region become donors and generate electrons as carriers. The threshold voltage of the transistor is shifted in the negative direction. The oxygen is sufficiently released from the first region, which is the layer, to the channel region, so that the threshold voltage This can compensate for the oxygen vacancies in the channel region that cause the pressure to shift in the negative direction. .

[0013] That is, when oxygen vacancies occur in the channel region, the first insulating layer in contact with the channel region It becomes difficult to suppress the trapping of charges at the interface between the first region and the channel region. By providing an insulating layer that releases oxygen when heated as a channel region and a first region, The interface state density between the first region and the channel region and the oxygen vacancies in the channel region are reduced, and the channel region and the first region are This can reduce the effect of charge trapping at the interface with the substrate.

[0014] In addition, the source and drain regions are formed in a second region in which the amount of oxygen released is smaller than that in the first region. By providing the source region and the drain region in contact with the region of FIG. This is because some of the oxygen vacancies in the oxide semiconductor layer are electron carriers. This is a configuration that focuses on the fact that oxygen is the source of oxygen. This is a technical advantage in that defects are reduced and the source and drain regions are prevented from becoming highly resistive. For example, the TDS is a second region adjacent to the source and drain regions. Analysis revealed that the amount of oxygen released was 1 x 10 18 atoms / cm 3 Using an insulating layer that is less than can be done.

[0015] Thus, the effect of one aspect of the present invention is that the insulating layer which releases oxygen when heated and the oxygen release layer This is due to the insulating layer having a smaller protrusion amount than the insulating layer in question.

[0016] The present invention is directed to suppressing the trapping of charges at the interface of the channel region of the oxide semiconductor layer and providing a source This suppresses the increase in the resistance of the source and drain regions. The resistance of the source and drain regions is increased, which reduces the current flowing through the source and drain regions. This can suppress problems such as a decrease in the on-state current of the transistor. Suppresses problems such as an increase in the off-state current of transistors using semiconductors and fluctuations in threshold voltage. In addition, the reliability of the semiconductor device can be improved.

[0017] The insulating layer that releases oxygen by heating has a sufficient thickness relative to the oxide semiconductor layer. It is preferable that the insulating layer which releases oxygen by heating is thinner than the oxide semiconductor layer. In such a case, oxygen supply to the oxide semiconductor layer may be insufficient.

[0018] One aspect of the present invention is a method for manufacturing an insulating layer having a first region and a second region, and a method for manufacturing an insulating layer having a first region and a second region. a channel region, a source region, and a drain region; A conductive layer, a gate insulating layer provided in contact with the oxide semiconductor layer, and a gate insulating layer provided in contact with the gate insulating layer. a gate electrode formed on the first region, and a channel region of the oxide semiconductor layer is in contact with the first region. a source region and a drain region of the oxide semiconductor layer are provided in contact with the second region. The first region is an insulating layer that releases oxygen when heated, and the second region is a The present invention relates to a semiconductor device or a method for manufacturing a semiconductor device, in which the insulating layer in the first region is smaller than that in the second region. The first region and the second region are made of the same material or have two or more of the same constituent elements. Materials having different constituent elements may be used.

[0019] In the above structure, the insulating layer that releases oxygen when heated is made of silicon oxide ( SiO X (X>2)) or silicon oxide (SiO X (X>2) ) is a material that contains more than twice as many oxygen atoms per unit volume as silicon atoms. The number of silicon atoms and oxygen atoms per unit volume was measured by the Rutherford backscattering method. This is the value.

[0020] In the above structure, the insulating layer that releases oxygen when heated is made of silicon oxide, silicon oxynitride, or the like. Silicon or aluminum oxide may be used. Also, the insulating layer may be made of an insulating material which releases less oxygen than the first region. The edge layer may be silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, or alumina oxide. Aluminum, aluminum nitride or aluminum oxynitride may be used. The first region and the second region may be made of materials having different constituent elements. For example, The insulating layer that releases oxygen is made of silicon oxide, and the amount of oxygen released is smaller than that of the first region. The edge layer may be silicon nitride, silicon oxide nitride, silicon oxide nitride, aluminum oxide, or nitride. For example, the first region may be made of aluminum oxide or aluminum oxynitride. When silicon oxide is used, the second region is a region that is thicker than silicon oxide at any temperature. It is preferable to use aluminum oxide, which has a low oxygen diffusion coefficient. By providing a second region with a low diffusion coefficient, the oxygen released in the first region is absorbed into the second region. This can reduce the amount of radiation diffusing into the area.

[0021] Here, silicon oxynitride is a material whose composition contains more oxygen than nitrogen. For example, oxygen is 50 atomic % or more and 70 atomic % or less, and nitrogen is 0.5 atomic % or more and 15 atomic % or less. % or less, silicon is 25 atomic % to 35 atomic %, hydrogen is 0 atomic % to 10 atomic % The following range is included. Silicon nitride oxide is a material that does not contain any oxide in its composition. For example, oxygen is between 5 atomic % and 30 atomic %. Nitrogen is 20 atomic % or more and 55 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen The content of 10 atomic % or more and 25 atomic % or less is defined as the range of the above. Rutherford Backscattering (RBS) Spectrometry and Hydrogen Forward Scattering (HFS) The results are based on measurements using Scattering. The total content does not exceed 100 atomic percent. Aluminum oxynitride is It refers to a composition in which the oxygen content is greater than the nitrogen content.

[0022] In the above configuration, the surface of the first region and the surface of the second region are aligned. In other words, it is preferable that the first region and the second region have the same thickness. Alternatively, in the vicinity of the boundary between the first region and the second region, the surface of the first region and the surface of the second region It is preferred that the surface of the region is formed continuously.

[0023] In the above configuration, it is also possible to adopt a configuration in which the second region is not provided. In this case, a first insulating layer is selectively provided on a substrate, and the first insulating layer is heated to release oxygen. Alternatively, a second insulating layer may be provided on the substrate, and a second insulating layer may be provided on the second insulating layer. A first insulating layer is selectively provided, and the first insulating layer is configured as an insulating layer that releases oxygen when heated. Just use it as is.

[0024] That is, one aspect of the present invention is a method for selectively providing a semiconductor device on a substrate or a second insulating layer provided on the substrate. A first insulating layer formed on the substrate, a substrate or a second insulating layer, and a second insulating layer provided in contact with the first insulating layer. an oxide semiconductor layer having a channel region, a source region, and a drain region; a gate insulating layer provided in contact with the conductor layer; and a gate electrode provided in contact with the gate insulating layer. a channel region of the oxide semiconductor layer being in contact with the first insulating layer; the source region and the drain region of the semiconductor layer are provided in contact with the substrate or the second insulating layer; The first insulating layer is an insulating layer that releases oxygen when heated. This is the method of production.

[0025] In the above structure, the insulating layer that releases oxygen when heated is made of silicon oxide ( SiO X (X>2)) or silicon oxide (SiO X (X>2) ) is a material that contains more than twice as many oxygen atoms per unit volume as silicon atoms. The number of silicon atoms and oxygen atoms per unit volume was measured by the Rutherford backscattering method. This is the value.

[0026] In the above structure, the insulating layer that releases oxygen when heated is made of silicon oxide, silicon oxynitride, or the like. Silicon and aluminum oxide may also be used.

[0027] In the above configuration, the substrate or the second insulating layer releases less oxygen than the first insulating layer. It is preferred.

[0028] In the above structure, the second insulating layer is made of silicon oxide, silicon nitride, silicon oxynitride, or the like. silicon oxynitride, aluminum oxide, aluminum nitride or aluminum oxynitride A program may also be used.

[0029] In the above structure, an insulating layer that releases oxygen when heated is used as a gate insulating layer. Alternatively, an acid containing more than twice as many oxygen atoms as silicon atoms per unit volume is preferred. It is preferred to use silicon carbide as the gate insulating layer.

[0030] In the above-mentioned structure, an interlayer insulating layer is provided on the gate electrode, and a wiring provided in the interlayer insulating layer and in contact with the oxide semiconductor layer through an opening provided in the interlayer insulating layer; You may do so.

[0031] In the above structure, the source region and the drain region are formed by forming the oxide semiconductor layer into a region having a low resistance. That is, the source region and the drain region are regions in which a resistance reducing treatment is applied to a part of the oxide semiconductor layer. At the same time, a channel region is formed in the oxide semiconductor layer. .

[0032] In the above structure, the insulating layer which releases oxygen when heated is formed by a sputtering method. Alternatively, the insulating layer that releases oxygen upon heating is preferably made of oxygen or It is preferable that the SiO 2 layer is formed by a sputtering method using a mixed gas of SiO 2 and argon.

[0033] In the above structure, the oxide semiconductor layer is preferably formed by a sputtering method. It is nice.

[0034] In the above structure, after the oxide semiconductor layer is formed, a heat treatment is performed at 100° C. or more and 650° C. or less. It is preferable to do so.

[0035] In the above structure, the source region and the drain region are formed by oxidizing the gate electrode as a mask. Alternatively, the oxide semiconductor layer may be partially subjected to a resistance reducing treatment. A channel region is formed in the conductor layer in a portion masked by the gate electrode.

[0036] In the above structure, the channel length L of the transistor is 10 nm or more and 10 μm or less. Of course, the channel length L can be set to 1 The channel width W may be 10 μm or more. This can be done. Effect of the Invention

[0037] According to one embodiment of the present invention, a thermally insulating layer is formed in contact with a channel region of an oxide semiconductor layer. An insulating layer that releases oxygen is provided in contact with a source region and a drain region of the oxide semiconductor layer. By providing an insulating layer in which the amount of oxygen released is less than that of the insulating layer in contact with the channel region, , low off-current, small threshold voltage variation, large on-current, stable current A transistor having dielectric properties is provided.

[0038] According to one embodiment of the present invention, a transistor having favorable electrical characteristics and high reliability is provided. A semiconductor device is provided. [Brief description of the drawings]

[0039] [Figure 1] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 2] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Diagram 3] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Diagram 5] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 6] 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 7] 1A to 1C illustrate one embodiment of a semiconductor device. [Figure 8] 1A to 1C are diagrams illustrating electronic devices as semiconductor devices. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0040] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and it is understood by those skilled in the art that various modifications may be made to the modes and details. The present invention is not limited to the description of the following embodiments. In addition, when explaining the configuration of the invention using the drawings, The reference numbers are used in common between different drawings. Note that the hatch pattern is used to refer to the same objects. In some cases, the same symbols are used and no particular symbols are used.

[0041] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. In addition, the present specification does not indicate the order of the invention. It does not indicate the name.

[0042] (Embodiment 1) In this embodiment mode, one embodiment of a semiconductor device and a manufacturing method thereof will be described with reference to FIGS. I will use this to explain.

[0043] FIG. 1 shows a top-gate type semiconductor device as an example of a semiconductor device according to one embodiment of the present invention. A cross-sectional view of a planar transistor 155 is shown.

[0044] The transistor 155 shown in FIG. 1A includes an insulating layer 103, an oxide semiconductor The gate electrode 114 is formed by a gate insulating layer 112 and a gate electrode 114. The insulating layer 103 is a first region. The transistor 155 includes a first region 101 and a second region 102. The semiconductor device has a channel region 126, a source region 122a, and a drain region 122b. The source region 122a and the drain region 122b are provided in the same layer. There are.

[0045] The oxide semiconductor layer 106 is provided in contact with the first region 101 and the second region 102. A channel region 126 of the oxide semiconductor layer 106 is provided in contact with the first region 101. The source region 122a and the drain region 122b of the oxide semiconductor layer 106 are the second region 1. The gate insulating layer 112 is provided in contact with the oxide semiconductor layer 106. The gate electrode 114 is provided in contact with the gate insulating layer 112. An interlayer insulating layer 124 is provided on the source region 122a and the drain region 122b. In the region 122b, the wiring 108a and the wiring 108b are provided via the interlayer insulating layer 124. The wiring 108a and the wiring 108b are electrically connected to a source electrode and a drain electrode. In FIG. 1A, the gate insulating layer 112 and the gate electrode 114 are The widths of the electrodes are described as being similar, but are not limited to this. As shown in FIG. 1, the gate insulating layer 113 is formed instead of the gate insulating layer 112, and the insulating layer 103 and the oxide The gate insulating layer 113 may be provided on the gate semiconductor layer 106. The insulating film 112 may be formed by the same method and using the same material as the insulating film 112. 112 can be replaced with a gate insulating film 113 as appropriate.

[0046] The material of the first region 101 may be silicon oxide, silicon oxynitride, aluminum oxide or the like. The first region 101 is a region that releases oxygen when heated. The term "releasing oxygen when heated" refers to the TDS (Thermal Dosage Formation) By thermal desorption spectroscopy, oxygen The amount of oxygen released in atoms is 1×10 18 atoms / cm 3 More than 3x, preferably 10 20 atoms / cm 3 Or, the material of the first region 101 is is a silicon oxide (SiO X (X>2)) may be used. Silicon carbide (SiO X (X>2) means that the number of oxygen atoms in a unit is more than twice the number of silicon atoms. The number of silicon atoms and oxygen atoms per unit volume is calculated by laser. The values ​​were measured using the Ford backscattering method.

[0047] The material of the second region 102 may be silicon oxide, silicon nitride, silicon oxynitride, or oxide. Silicon nitride, aluminum oxide, aluminum nitride or aluminum oxynitride is used. The second region 102 is an insulating layer that releases less oxygen than the first region 101. The first region 101 and the second region 102 are made of the same material. Alternatively, materials having two or more of the same constituent elements may be used, or materials having different constituent elements may be used. The first region 101 and the second region 102 may be made of the same material or of the same constituent elements. When two or more of the materials are the same, the material of the second region 102 is A material having a smaller number of oxygen atoms than that of the first region 101 may be used. For example, The material in question is silicon oxide, which contains more than twice as many oxygen atoms as silicon atoms per unit volume. Con (SiOX (X>2) is used, and the material of the second region 102 is an acid per unit volume. The number of atomic atoms in the first region 101 is smaller than that in the second region 102. X (X≦2) Alternatively, the material of the second region 102 may have a number of oxygen atoms per unit volume that is smaller than that of the first region. The second region 102 may be made of silicon oxynitride, which is less than that of the first region 101. Acrylic resin, polyimide, benzocyclobutene resin, polyamide, epoxy resin, etc. Organic insulating materials that can be formed by a wet method may also be used. low-k materials, siloxane resins, PSG (phosphorus glass), BPSG (phosphorus Alternatively, inorganic insulating materials that can be formed by a wet process, such as boron glass, may be used. The second region 102 has a temperature (for example, in the range of 100° C. to 650° C.) higher than the first region 101. It is preferable that the diffusion coefficient of oxygen in the first region 10 is low. This can reduce the amount of oxygen released in the first region 101 diffusing into the second region 102.

[0048] The insulating layer 103 having the first region 101 and the second region 102 is made of the above-mentioned material. and silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide Aluminum, aluminum nitride, aluminum oxide nitride, or a mixture of these materials is laminated. In the case where the insulating layer 103 has a stacked structure, The above-mentioned materials for the first region 101 and the second region 102 may be used. The border layer 103 serves as an underlayer for the transistor 155 .

[0049] The material used for the oxide semiconductor layer 106 is a quaternary metal oxide, In-Sn-G a-Zn-O based materials, In-Ga-Zn-O based materials, which are ternary metal oxides, In -Sn-Zn-O based materials, In-Al-Zn-O based materials, Sn-Ga-Zn-O based materials Materials, Al-Ga-Zn-O materials, Sn-Al-Zn-O materials, and binary metal oxides In-Zn-O based materials, Sn-Zn-O based materials, and Al-Zn-O based materials are oxides. , Zn-Mg-O based materials, Sn-Mg-O based materials, In-Mg-O based materials, In- Ga-O, In-O, Sn-O, and Zn-O materials are used. The above materials may contain silicon oxide. In-Ga-Zn-O-based materials are made of indium (In), gallium (Ga), and zinc ( The composition ratio is not particularly important. Elements other than Ga and Zn may be included.

[0050] When an In-Zn-O based material is used for the oxide semiconductor layer 106, the atomic ratio is In / Zn=0.5 to 50, preferably In / Zn=1 to 20, more preferably The atomic ratio of In / Zn is 1.5 or more and 15 or less. By setting the atomic ratio of Zn in the above range, The field effect mobility of the transistor can be improved. When In:Zn:O=X:Y:Z, it is preferable that Z>1.5X+Y.

[0051] The oxide semiconductor layer 106 is formed of a compound represented by the chemical formula InMO 3 (ZnO) m (m>0) The thin film can be formed using a material selected from the group consisting of Ga, Al, Mn, and Co. For example, M is Ga, Ga, and A. For example, Ga and Mn or Ga and Co can be used.

[0052] The channel region 126 and the first region 101 are in contact with each other, so that the first region 101 and the channel The interface state density with the channel region 126 and the oxygen vacancies in the channel region 126 can be reduced. Cut. As a result, charges that may be generated due to the operation of the semiconductor device are transferred between the first region 101 and the Therefore, the trapping at the interface with the channel region 126 can be sufficiently suppressed.

[0053] Furthermore, charges may occur due to oxygen vacancies in the channel region 126. Some of the oxygen vacancies in the channel region become donors, generating electrons that act as carriers. As a result, the threshold voltage of the transistor is shifted in the negative direction. Sufficient oxygen is released from the first region 101, which is an insulating layer in contact with the channel region 126. This causes the threshold voltage to shift in the negative direction, which is the channel region 126 This can compensate for the oxygen deficiency in the

[0054] That is, when oxygen vacancies occur in the channel region 126, the insulating layer in contact with the channel region 126 In order to suppress the trapping of charges at the interface between the first region 101 and the channel region 126, However, it is possible to provide an insulating layer that releases oxygen when heated as the first region 101. As a result, the interface state density between the channel region 126 and the first region 101 and the 26, and the charge at the interface between the channel region 126 and the first region 101 is reduced. This can reduce the impact of capture.

[0055] In addition, the source region 122a and the drain region 122b, and the amount of oxygen released from the first region 10 The source region 122a and the drain region 122b are in contact with less than one second region 102. The supply of oxygen to the oxide semiconductor layer 122b is prevented. Part of the electron deficiency is due to the fact that oxygen is the source of electron carriers. As a result, oxygen vacancies are reduced, and the source region 122a and the drain region 122b For example, the source region 122a and the The second region 102 in contact with the drain region 122b is determined by TDS analysis to determine the amount of oxygen released. is 1×10 18 atoms / cm 3 An insulating layer having a thickness of less than 100 .mu.m can be used.

[0056] The above-mentioned trapping of charges at the interface of the channel region 126 of the oxide semiconductor layer is suppressed, and In addition, due to the effect of suppressing the increase in resistance of the source region 122a and the drain region 122b, if The source region 122a and the drain region 122b become highly resistive, The on-state current of the transistor 155 is reduced by the reduction in the current flowing through the drain region 122b and the drain region 122c. In addition, the oxide semiconductor can be used to suppress problems such as a decrease in current. To suppress problems such as an increase in the off-state current of the transistor 155 and a change in the threshold voltage. In addition, the reliability of the semiconductor device can be improved.

[0057] The gate insulating layer 112 may be of the same composition (e.g., the same material) as the first region 101. That is, the gate insulating layer 112 may be an insulating layer that releases oxygen when heated. In addition, hafnium oxide or oxide is used in consideration of its function as a gate insulating layer for transistors. Materials with high relative dielectric constants, such as aluminum oxide, may also be used. Considering the interface with the semiconductor, silicon oxide, silicon oxynitride, silicon nitride, and oxide are A material with a high relative dielectric constant, such as hafnium oxide or aluminum oxide, may be laminated.

[0058] The gate electrode 114 may be made of any of molybdenum, titanium, tantalum, tungsten, aluminum, Metallic materials such as copper, neodymium, and scandium, their nitrides, or materials that contain these as the main components The gate electrode 114 can be formed using an alloy material having a single layer structure. Alternatively, a laminated structure may be used.

[0059] An interlayer insulating layer 124 may be further provided on the transistor 155. The edge layer 124 may be of a similar construction (e.g., of a similar material) as the second region 102. In order to electrically connect the wiring 108a and the wiring 108b, an opening is formed in the interlayer insulating layer 124. A portion may be formed.

[0060] The conductive layer used for the wiring 108a and the wiring 108b may be, for example, Al, Cr, Cu, A metal layer containing an element selected from Ta, Ti, Mo, and W, or a metal layer containing the above elements as components. Metal nitride layers (titanium nitride layer, molybdenum nitride layer, tungsten nitride layer, etc.) are used. In addition, Ti, M, etc. can be added to the underside or top side or both sides of the metal layer such as Al or Cu. A layer of a high melting point metal such as titanium or W, or a layer of a nitride of these metals (titanium nitride layer, molybdenum nitride layer, etc.) A laminated structure of a tungsten nitride layer and a tungsten nitride layer may be used.

[0061] The transistor 155 has a second gate electrode under the oxide semiconductor layer 106. Note that the oxide semiconductor layer 106 is preferably processed into an island shape; It is not necessary to process it into an island shape.

[0062] An example of a manufacturing process of the transistor 155 shown in FIG. 1A will be described below with reference to FIGS. We will explain about this.

[0063] First, referring to Figs. 2(A) to 2(D) and Figs. 3(A) to 3(D), An example of a manufacturing process of the transistor 155 shown in FIG.

[0064] A first insulating layer 131 is formed on a substrate 100 (see FIG. 2(A)). 1 is processed by a method such as photolithography to form an island-shaped first region 101. (See FIG. 2B.) The photomask used in forming the first region 101 is a gate electrode The same photomask as that used in forming the first region 101 can be used. Alternatively, the material of the first region 101 may contain oxygen. Excess silicon oxide (SiO X (X>2) may also be used.

[0065] There is no particular restriction on the material of the substrate 100, but it should be strong enough to withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, quartz substrates, and sa A substrate such as a ferroelectric substrate can be used as the substrate 100. In addition, silicon or silicon carbide can be used. Single crystal semiconductor substrates such as silicon, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium It is also possible to apply a conductor substrate, SOI substrate, etc., and semiconductor elements are formed on these substrates. The provided one may be used as the substrate 100 .

[0066] A flexible substrate may be used as the substrate 100. When providing the transistor, the transistor may be directly formed on the flexible substrate, or the transistor may be formed on another substrate. After the transistor is formed, it may be peeled off and transferred to a flexible substrate, which is the substrate 100. In order to peel off the transistor and transfer it to a flexible substrate, the transistor and the other substrate are A release layer may be formed between the substrate and the heater.

[0067] The method for forming the first insulating layer 131 that becomes the first region 101 is, for example, a plasma CVD method. The insulating layer that releases oxygen when heated can be formed by a method such as sputtering. It is preferable to use a sputtering method for the deposition.

[0068] To form an insulating layer that releases oxygen when heated using the sputtering method, When oxygen or a mixture of oxygen and rare gas (such as argon) is used as the gas, It is advisable to increase the ratio of oxygen in the mixture of rare gases. For example, the concentration of oxygen in the total gas is It is recommended that the level be between 6% and less than 100%.

[0069] The material of the first insulating layer 131 that becomes the first region 101 is silicon oxide, silicon oxynitride, etc. For example, aluminum oxide, a mixture of these materials, or the like may be used.

[0070] For example, the first insulating layer 131 is formed by using quartz (preferably synthetic quartz) as a target. The substrate temperature is 30° C. or more and 450° C. or less (preferably 70° C. or more and 200° C. or less), and the deposition gas is Oxygen or oxygen and argon are used as the deposition gas. 2 / (O 2 +Ar) ratio 1 % or more and 100% or less (preferably 6% or more and 100% or less), and RF sputtering method Silicon oxide is formed by the above.

[0071] The thickness of the first insulating layer 131 and the first region 101 is preferably 50 nm or more, and more preferably The thickness is preferably 200 nm or more. This makes it possible to increase the amount of oxygen released from the first region 101 .

[0072] Next, a second insulating layer 132 is formed on the substrate 100 and the first region 101 (FIG. 2( Then, the second insulating layer 132 is heated until the surface of the first region 101 is exposed. The insulating layer 103 having the second region 102 in contact with the first region 101 is formed by the process. See FIG. 2(D). The second region 102 is an insulating region that releases less oxygen than the first region 101. When the second insulating layer 132 is processed, the first region is also processed. The surface of the region 101 may be processed to remove a portion of the first region 101 .

[0073] The second insulating layer 132 is formed by, for example, a plasma CVD method or a sputtering method. can be used.

[0074] The material of the second insulating layer 132 may be silicon oxide, silicon nitride, silicon nitride oxide, or oxide. Silicon oxide nitride, aluminum oxide, aluminum nitride or aluminum oxide nitride is used. That's good.

[0075] For example, silicon nitride is formed as the second insulating layer 132 by a plasma CVD method. Alternatively, the second insulating layer 132 may be formed of silicon oxide by plasma CVD. Good too.

[0076] After the above steps, the surface of the first region 101 and the surface of the second region 102 are aligned. For example, it is preferable to remove the second insulating layer 13 until the surface of the first region 101 is exposed. 2 is polished by chemical mechanical polishing (CMP) or etched to form a The second region 102 is in contact with the first region 101, and the surface of the first region 101 and the second region 102 are The insulating layer 103 can be formed with a uniform surface of the first region 101. By aligning the surface of the second region 102, the step of the oxide semiconductor layer to be formed thereon can be formed. This effect is remarkable when the oxide semiconductor layer is thin. By preventing step discontinuity in the semiconductor layer, step discontinuity in the source and drain regions is also prevented. In addition, the oxide semiconductor layer can be formed on the upper surface of the oxide semiconductor layer. It is possible to prevent the gate insulating layer formed on the substrate from being broken. This makes it possible to suppress an increase in leakage current and a decrease in breakdown voltage.

[0077] The thickness of the second region 102, i.e., the thickness of the insulating layer 103, is the same as that of the first insulating layer 131 and The thickness of the second region 102 is the same as that of the first region 101. The thickness of the layer 103 is preferably 50 nm or more, and more preferably 200 nm or more. However, by performing polishing or etching, the thickness of the first insulating layer 131 is In some cases, the film thickness may be thinner than it was at the time of deposition.

[0078] The insulating layer 103 having the first region 101 and the second region 102 is made of the above-mentioned material. and silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide Aluminum, aluminum nitride, aluminum oxide nitride, or a mixture of these materials is laminated. In the case where the insulating layer 103 has a stacked structure, The above-mentioned materials for the first region 101 and the second region 102 may be used. The border layer 103 serves as an underlayer for the transistor 155 .

[0079] In this example, the first region 101 is formed, and then the second region 102 is formed. However, the order of forming the first region 101 and the second region 102 was reversed, and the second region 102 was The first region 101 may be formed after the formation of the second region 102. After forming the second region 102, a first insulating layer 131 is formed on the entire surface, and the surface of the second region 102 is exposed. The first insulating layer 131 is polished or etched until the first region 1 An insulating layer 103 can be formed having a second region 102 in contact with the first region 101 .

[0080] Next, an oxide semiconductor layer is formed over the insulating layer 103, and the oxide semiconductor layer is processed to form an island. The oxide semiconductor layer 106 is formed in a shape similar to that of the oxide semiconductor layer 106 shown in FIG. It is formed in contact with the first region 101 and the second region 102 .

[0081] The oxide semiconductor layer 106 is formed by, for example, sputtering, vacuum evaporation, pulsed laser deposition, or the like. The oxide semiconductor layer 106 can be formed by a method such as a CVD method. The thickness of the oxide semiconductor layer 106 is preferably greater than or equal to 3 nm and less than or equal to 50 nm. When the thickness is increased (for example, to 100 nm or more), the short channel effect becomes more significant and the size becomes smaller. This is because there is a risk that a small transistor will be normally on. "On" means that the channel exists even when no voltage is applied to the gate electrode, and the transistor is electrically This refers to a state in which the flow of water is allowed to flow.

[0082] In this embodiment, the oxide semiconductor layer 106 is an In—Ga—Zn—O-based oxide target. The film is formed by sputtering using a sputter.

[0083] The In-Ga-Zn-O oxide target may have a composition ratio of, for example, In 2 O 3 :Ga 2 O 3 Use an oxide target with a molar ratio of ZnO = 1:1:1. It is not necessary to limit the material and composition of the target to those described above. Ba, In 2 O 3 :Ga 2 O 3 :ZnO=1:1:2 [molar ratio] oxide ternary A get can also be used.

[0084] The relative density of the oxide target is 90% or more and 100% or less, preferably 95% or more and 10 0% or less. By using a metal oxide target with a high relative density, the oxide film formed This is because the compound semiconductor layer can be made dense.

[0085] The film formation atmosphere is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. In addition, hydrogen, water, a hydroxyl group, or the like may be added to the oxide semiconductor layer. In order to prevent the inclusion of hydrides, impurities such as hydrogen, water, hydroxyl groups, and hydrides are thoroughly removed. It is preferable to use a high purity gas that has been removed.

[0086] For example, the oxide semiconductor layer 106 can be formed as follows.

[0087] As an example of the deposition conditions, the distance between the substrate and the target is 60 mm, and the pressure is 0.4 Pa. The direct current (DC) power supply was 0.5 kW, and the deposition atmosphere was a mixture of argon and oxygen (oxygen flow rate The ratio can be 33%). By using the pulse DC sputtering method, the film formation This reduces the amount of powdery material (also called particles or dust) that is generated during cleaning, and the thickness distribution is uniform. This is preferable.

[0088] At this time, the substrate temperature is set to 100° C. or higher and 450° C. or lower, preferably 150° C. or higher and 250° C. or lower. By this, oxygen is released from the first region 101, and the first region of the oxide semiconductor layer 106 In this way, oxygen vacancies are reduced in the portion in contact with the region 101 (the portion that becomes the channel region 126). In addition, the interface state density between the oxide semiconductor layer 106 and the first region 101 can be reduced. It is possible.

[0089] In addition, the portion of the oxide semiconductor layer 106 that is not in contact with the first region 101 (the source region 122a and the drain region 122b), the amount of oxygen released is greater than that of the first region 101. The second region 102 having a small amount of the oxide semiconductor layer 106 is in contact with the second region 102, and the resistance of the second region 102 is increased. It can be suppressed.

[0090] Note that before the oxide semiconductor layer 106 is formed by a sputtering method, an argon gas A reverse sputtering process is performed by introducing a gas to generate plasma, and the surface of the formation layer (for example, the surface of the insulating layer 103) is Here, the reverse sputtering is the same as in normal sputtering. In this method, instead of bombarding the sputtering target with ions, the ions are bombarded on the treatment surface. This refers to a method of modifying a surface by bombarding it with ions. The method of applying the heat is to apply a high-frequency voltage to the surface to be treated in a rare gas atmosphere. In addition, nitrogen or oxygen, etc. can be used instead of the rare gas atmosphere. The atmosphere may be applied.

[0091] The oxide semiconductor layer 106 is processed by forming a mask having a desired shape on the oxide semiconductor layer. The above-mentioned mask can be used for the etching of the oxide semiconductor layer. The insulating layer 11 can be formed by a method such as photolithography. The mask may be formed using a method such as a photolithography method.

[0092] Note that the etching of the oxide semiconductor layer may be either dry etching or wet etching. Of course, these may be used in combination.

[0093] After that, the oxide semiconductor layer 106 is preferably subjected to heat treatment (first heat treatment). The first heat treatment removes excess hydrogen (including water and a hydroxyl group) from the oxide semiconductor layer 106. The temperature of the first heat treatment is 100° C. or higher and 650° C. or lower, or The temperature is set to be lower than the distortion point of the substrate, preferably 250° C. or higher and 600° C. or lower. The heating is performed in an oxidizing gas atmosphere or an inert gas atmosphere.

[0094] In addition, inert gases are mainly composed of nitrogen or rare gases (helium, neon, argon, etc.). It is preferable that the gas does not contain water, hydrogen, etc. For example, the nitrogen or The purity of rare gases such as helium, neon, and argon is 6N (99.9999%) or higher. Preferably, the concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, The concentration of inert gas in the atmosphere is 0.1 ppm or less. An atmosphere in which the reactive gases are less than 10 ppm.

[0095] The oxidizing gas is oxygen, ozone, nitrogen dioxide, or the like, and does not contain water, hydrogen, or the like. For example, the pure oxygen, ozone, and nitrogen dioxide introduced into the heat treatment device should not be The degree of contamination should be 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. That is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less. In the present invention, an oxidizing gas may be mixed with an inert gas, and the oxidizing gas is preferably at least 10 ppm or more.

[0096] This first heat treatment causes oxygen to be released from the first region 101, and a portion of the oxide semiconductor layer 106 that is in contact with the first region 101 (a portion that becomes the channel region 126). The interface state density with the first region 101 can be reduced, and the oxide in the portion in contact with the first region 101 can be reduced. The oxygen vacancies in the oxide semiconductor layer 106 can be reduced. This makes it possible to reduce the threshold voltage fluctuation after the BT test. It is known that some of the oxygen vacancies in the conductor layer act as donors and generate electrons, which are carriers. When electrons are generated in the oxide semiconductor layer 106, the threshold voltage of the transistor 155 is lowered. The low voltage is shifted in the negative direction, and the device is likely to be normally on. By filling the oxygen vacancies in 6, the amount of negative shift in threshold voltage is reduced. can.

[0097] In addition, the portion of the oxide semiconductor layer 106 that is not in contact with the first region 101 (the source region 122a and the drain region 122b), the amount of oxygen released is greater than that of the first region 101. The second region 102 having a small amount of the oxide semiconductor layer 106 is in contact with the second region 102, and the resistance of the second region 102 is increased. It can be suppressed.

[0098] The heat treatment is carried out, for example, by placing the workpiece in an electric furnace using a resistance heating element and heating the workpiece in a nitrogen atmosphere. The process can be carried out at 350°C for 1 hour. During this time, the oxide semiconductor layer is not exposed to the air. This prevents water and hydrogen from getting mixed in.

[0099] The heat treatment device is not limited to an electric furnace, but may be a device that uses heat conduction or heat radiation from a medium such as a heated gas. For example, a GRTA (Gas Rap id Thermal Anneal) equipment, LRTA (Lamp Rapid The RTA (Rapid Thermal Anneal) equipment l) Equipment can be used. LRTA equipment includes halogen lamps, metal halide lamps, etc. xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp It is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a The GRTA device is a device that performs heat treatment using high-temperature gas. Inert gases such as rare gases such as fluorine or nitrogen that do not react with the workpiece during heat treatment are used. Used.

[0100] For example, in the first heat treatment, the workpiece is placed in a heated inert gas atmosphere and heated for several minutes. After heating for 10 minutes, the workpiece may be removed from the inert gas atmosphere and subjected to GRTA treatment. GRTA treatment enables high-temperature heat treatment in a short time. The method can be applied even under temperature conditions exceeding the above temperature. The first atmosphere may be switched to an atmosphere containing an oxidizing gas. By performing the heat treatment, oxygen vacancies in the oxide semiconductor layer 106 can be filled and In addition, it is possible to reduce the defect level in the energy gap caused by oxygen vacancies. be.

[0101] By the way, the above-mentioned heat treatment (first heat treatment) has the effect of removing hydrogen, water, etc. This heat treatment can also be called dehydration treatment, dehydrogenation treatment, or the like. Since this method has the effect of supplying oxygen from the heat treatment atmosphere, it is also called oxygen addition treatment. The dehydration treatment, the dehydrogenation treatment, and the oxygen addition treatment can be performed, for example, by forming the oxide semiconductor layer into islands. It is possible to carry out the dehydration at a timing such as after processing. The treatment, dehydrogenation treatment, and oxygen addition treatment may be carried out not only once but also multiple times.

[0102] Note that in this embodiment, the first heat treatment is performed after the oxide semiconductor layer 106 is processed into an island shape. However, the present invention is not limited to this structure. After the first heat treatment, the oxide semiconductor layer 106 may be processed.

[0103] Next, an insulating layer is formed in contact with the oxide semiconductor layer 106, and a conductive layer is formed in contact with the insulating layer. The insulating layer and the conductive layer are patterned in the same way by photolithography to form the gate insulating layer. An edge layer 112 and a gate electrode 114 are formed (see FIG. 3(B)). 14 and the gate insulating layer 112 can be processed using the same mask. The gate electrode 114 is processed, and then the gate insulating layer 11 is formed by using the gate electrode 114 as a mask. 2 may be processed.

[0104] The gate insulating layer 112 may be of the same composition (e.g., the same material) as the first region 101. Alternatively, hafnium oxide is used in consideration of its function as a gate insulating layer for transistors. Materials with high relative dielectric constants, such as aluminum or aluminum oxide, may also be used. Considering the interface state with the oxide semiconductor, silicon oxide, silicon oxynitride, and silicon nitride were used. A material with a high relative dielectric constant, such as hafnium oxide or aluminum oxide, may be laminated on the capacitor. The total thickness of the gate insulating layer 112 is preferably 1 nm or more and 300 nm or less, and more preferably The thickness is generally 5 nm to 50 nm. The thicker the gate insulating layer, the more pronounced the short channel effect becomes. The threshold voltage tends to shift to the negative side. It is known that leakage due to tunnel current increases when the capacitance is less than m.

[0105] After the gate insulating layer 112 is formed, a second heat treatment is preferably performed. The temperature is 100° C. or higher and 650° C. or lower than the strain point of the substrate, preferably 250° C. or higher and 6 00°C or below the distortion point of the substrate.

[0106] The second heat treatment may be performed in an oxidizing gas atmosphere or an inert gas atmosphere. It is preferable that the gas does not contain water, hydrogen, etc. In addition, the purity of the gas introduced into the heat treatment device is The degree of the ion exchange is set to 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. It is preferable to keep the impurity concentration at 1 ppm or less, and preferably at 0.1 ppm or less.

[0107] In the second heat treatment, the oxide semiconductor layer 106, the first region 101, and the gate insulating film 104 are removed. The layer 112 is heated in contact with the oxide semiconductor. The oxygen, which is one of the oxides, is converted from the first region 101 containing oxygen and the gate insulating layer 112 into an oxide semiconductor. This can supply oxygen to the oxide semiconductor layer 106. The interface state density between the first region 101 and the oxide semiconductor layer 106 and the oxide semiconductor layer and the gate The interface state density with the insulating layer 112 can be reduced. The defects in 2 can also be reduced.

[0108] The timing of the second heat treatment is not particularly limited as long as it is performed after the gate insulating layer 112 is formed. In addition, the second heat treatment may be carried out multiple times.

[0109] The gate electrode 114 may be made of any of molybdenum, titanium, tantalum, tungsten, aluminum, Metallic materials such as copper, neodymium, and scandium, their nitrides, or materials that contain these as the main components The gate electrode 114 can be formed using an alloy material having a single layer structure. Alternatively, a laminated structure may be used.

[0110] Next, the resistance of the oxide semiconductor layer 106 is reduced by using the gate electrode 114 as a mask. The region 122a and the drain region 122b are formed. The gate electrode 114 is not made to have a low resistance. The lower region becomes the channel region 126 (see FIG. 3(C)). The method for reducing the resistance is as follows: Examples of the treatment include argon plasma treatment, hydrogen plasma treatment, and ammonia plasma treatment. At this time, the channel length L of the transistor is determined by the width of the gate electrode 114. In this way, by patterning using the gate electrode 114 as a mask, The gate electrode 114 does not overlap with the source region 122a and the drain region 122b. The absence of parasitic capacitance in the region allows faster transistor operation.

[0111] Next, an interlayer insulating layer 124 is formed to overlap the source region 122a and the drain region 122b. An opening is provided in the interlayer insulating layer 124 in the portion to be folded. Then, a conductive layer is formed. The wiring 108a and the wiring 108b are formed by processing the insulating film 106 (see FIG. 3D).

[0112] The conductive layer used for the wiring 108a and the wiring 108b may be, for example, Al, Cr, Cu, A metal layer containing an element selected from Ta, Ti, Mo, and W, or a metal layer containing the above elements as components. Metal nitride layers (titanium nitride layer, molybdenum nitride layer, tungsten nitride layer, etc.) are used. In addition, Ti, M, etc. can be added to the underside or top side or both sides of the metal layer such as Al or Cu. A layer of a high melting point metal such as titanium or W, or a layer of a nitride of these metals (titanium nitride layer, molybdenum nitride layer, etc.) A laminated structure of a tungsten nitride layer and a tungsten nitride layer may be used.

[0113] The conductive layer used for the wiring 108a and the wiring 108b is formed of a conductive metal oxide. As the conductive metal oxide, indium oxide (In 2 O 3 etc.), tin oxide (S nO 2 etc.), zinc oxide (ZnO etc.), indium oxide tin oxide (In 2 O 3 - SnO 2 etc. , abbreviated as ITO), indium zinc oxide (In 2 O 3 -ZnO, etc.) or these A metal oxide material containing silicon oxide can be used.

[0114] The conductive layer can be processed by etching using a resist mask. The exposure to light used in forming the resist mask used in etching is ultraviolet light, KrF laser light, or ArF A laser beam or the like may be used.

[0115] Through the above steps, the transistor 155 is manufactured.

[0116] Next, an example of a manufacturing process of the insulating layer 103 will be described with reference to FIGS. First, a first region is formed on a substrate 100 by the same steps as those shown in FIG. forming a second insulating layer 132 on the substrate 100 and the first region 101; (See FIG. 4(A)). Next, a third insulating layer 133 is formed on the second insulating layer 132 ( (See FIG. 4B.) The third insulating layer 133 can be a planarizing insulating layer. For example, the material of the third insulating layer 133 may be acrylic resin, polyimide, or benzocyclobutene resin. Organic insulating materials that can be formed by wet methods, such as grease, polyamide, and epoxy resin, can be used. In addition to the above organic insulating materials, low-k materials and siloxane resins are also available. Inorganic materials that can be formed by wet methods such as polysilicon, polysilicon glass (PSG), and boron phosphorus glass (BPSG) Mechanically insulating materials can be used.

[0117] The method for forming the third insulating layer 133 may be a spin coating method, a dipping method, or the like, depending on the material. , spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc. ), roll coating, curtain coating, knife coating, etc. can be done.

[0118] Next, the third insulating layer 133 and the second insulating layer 132 are subjected to an etching process. The etchant used in the process is a material that can etch the third insulating layer 133 and the second insulating layer 132. The selection ratio is 1:1 or close to 1. This allows the third insulating layer 133 and the second The etching rate of the insulating layer 132 can be made almost the same as that of the insulating layer 132 (see FIG. 4(C)). The third insulating layer 133 and the second insulating layer 132 are etched by dry etching. The etching may be performed by either drying or wet etching.

[0119] Then, the third insulating layer 133 and the second insulating layer 134 are removed until the surface of the first region 101 is exposed. By etching 132, a second region 102 is formed in contact with the first region 101. The insulating layer 103 is formed so that the surface of the first region 101 and the surface of the second region 102 are aligned. (See FIG. 4(D)). By aligning the surfaces of the two, it is possible to prevent the oxide semiconductor layer formed thereon from being cut off. This effect is remarkable when the oxide semiconductor layer 106 is thin. By preventing the step disconnection of 106, the source region 122a and the drain region 122b It is possible to prevent a step disconnection and suppress a decrease in the on-current. This can prevent the gate insulating layer 112 formed on the semiconductor layer 106 from being cut off. By preventing the step disconnection of the gate insulating layer 112, an increase in leakage current and a decrease in breakdown voltage are prevented. It can be suppressed.

[0120] In this example, the first region 101 is formed, and then the second region 102 is formed. However, the order of forming the first region 101 and the second region 102 was reversed, and the second region 102 was The first region 101 may be formed after the formation of the second region 102. After forming the insulating film 02, a first insulating layer 131 is formed on the entire surface, and a third insulating layer 132 is formed on the first insulating layer 131. Then, the third insulating layer 133 is formed until the surface of the second region 102 is exposed. The layer 133 and the first insulating layer 131 are etched to form a region adjacent to the first region 101. The surface of the first region 101 and the surface of the second region 102 are In this case, the third insulating layer 133 and the insulating layer 103 having the same structure can be formed. The etching of the first insulating layer 131 may be either dry etching or wet etching.

[0121] In addition, although an example in which the second insulating layer 132 and the third insulating layer 133 are formed has been shown here, The second insulating layer 132 is formed using the same material and the same method as the third insulating layer 133. The second insulating layer 132 may be formed with a flat surface by using the above-mentioned method. That is, as shown in FIG. 5(A), The third insulating layer 133 is formed on the substrate 100 and the first region 101 using the same material and method as the third insulating layer 133. The second insulating layer 132 may be formed with a flat surface. The second insulating layer 132, which has a flat surface, is etched until the surface of the first region 101 is exposed. By carrying out the etching treatment, the second region 102 can be formed as shown in FIG. 5(B). As a result, an insulating layer 103 having a uniform surface of the first region 101 and the second region 102 is formed. In this case, the material used for the second region 102 is selected from those having a high oxygen release rate. The insulating layer is smaller than that in the first region 101. In comparison with the manufacturing method shown in FIG. 4, the number of film formations required to form the insulating layer 103 is reduced, and processing is also simplified. It becomes easier.

[0122] The subsequent steps can be similar to those shown in FIGS.

[0123] According to the present embodiment, the insulating layer in contact with the channel region 126 of the oxide semiconductor layer 106 is The first region 101 which releases oxygen by heating is provided, and the source region of the oxide semiconductor layer 106 is The insulating layer in contact with the drain region 122a and the drain region 122b has an oxygen release amount of the first region 10 By providing the second region 102, which is less than one, the off-current is small and the variation in the threshold voltage is small. A transistor having stable electrical characteristics with low adhesion and large on-current is provided. .

[0124] Alternatively, according to this embodiment, a semiconductor device having a transistor with favorable electrical characteristics and high reliability can be provided. A conductor device is provided.

[0125] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0126] (Embodiment 2) In this embodiment, one mode of a semiconductor device will be described with reference to FIG. 1 shows a cross-sectional structure of a transistor 156 having a different structure from the transistor 155 shown in A). The transistor 156 illustrated in FIG. 6 is the same as the transistor 155 illustrated in FIG. In this configuration, the area 102 is not provided.

[0127] The transistor 156 shown in FIG. 6 is formed of a first insulating layer 104, an oxide semiconductor layer 106, and a The transistor 156 includes an oxide semiconductor layer 106, a gate insulating layer 112, and a gate electrode 114. In the nitride semiconductor layer 106, a channel region 126, a source region 122a and a drain region 12 The channel region 126, the source region 122a, and the drain region 122b are They are provided in the same layer.

[0128] A second insulating layer 105 may be provided under the transistor 156. Layer 105 serves as an underlayer for transistor 156 .

[0129] A first insulating layer is formed on the substrate 100 or on a second insulating layer 105 formed on the substrate 100. An oxide semiconductor layer 106 is provided on the first insulating layer 104. The oxide semiconductor layer 106 is formed on the substrate 100 or a The oxide semiconductor layer is provided in contact with the second insulating layer 105 and the first insulating layer 104. The channel region 126 of the oxide semiconductor layer 106 is provided in contact with the first insulating layer 104. The source region 122a and the drain region 122b of the semiconductor substrate 106 are formed on the substrate 100 or the substrate 100. It is provided in contact with the second insulating layer 105 provided thereon.

[0130] The gate insulating layer 112 is provided in contact with the oxide semiconductor layer 106. An interlayer insulating layer 124 is provided on the gate electrode 114. The source region 122a and the drain region 122b are provided with an interlayer insulating film. The wiring 108a and the wiring 108b are electrically connected to each other via the layer 124. The wiring 108a and the wiring 108b function as a source electrode and a drain electrode.

[0131] The material of the first insulating layer 104 is the same as the material of the first region 101 shown in the first embodiment. That is, the material of the first insulating layer 104 may be silicon oxide, oxynitride, or the like. Silicon oxide, aluminum oxide, or a mixture of these materials may be used. Layer 104 is characterized by releasing oxygen when heated. TDS (Thermal Desorption Spectroscopy) The amount of oxygen released, calculated as oxygen atoms, was 1 x 10 18 atoms / cm 3 More than 3×10 20 atoms / cm 3 It also means that The material of the first insulating layer 104 is silicon oxide (SiO X (X>2) Silicon oxide (SiO X (X>2) is a silicon atom It contains more than twice the number of oxygen atoms per unit volume. The numbers of nitrogen atoms and oxygen atoms are values ​​measured by the Rutherford backscattering method.

[0132] In the case where the second insulating layer 105 is provided, the material of the second insulating layer 105 is the same as that in the first embodiment. The second insulating layer 102 may be made of the same material as that of the second region 102 shown in FIG. 05 materials include silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, Aluminum oxide, aluminum nitride, aluminum oxynitride, or the like may be used. The second insulating layer 105 is an insulating layer that releases less oxygen than the first insulating layer 104. It is a sign.

[0133] The first insulating layer 104 and / or the second insulating layer 105 may be made of the above-mentioned material and an oxide silicon. Silicon, silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, nitride Aluminum, aluminum oxynitride, or a mixture of these materials may be laminated. When the first insulating layer 104 and / or the second insulating layer 105 are formed in a laminated structure, The side in contact with the oxide semiconductor layer 106 is covered with the first insulating layer 104 or the second insulating layer 105. It is recommended to use this as material.

[0134] The channel region 126 and the first insulating layer 104 are in contact with each other, so that the first insulating layer 104 and the To reduce the interface state density with the channel region 126 and the oxygen vacancies in the channel region 126. The reduction in the interface state density mentioned above reduces the threshold voltage in the negative direction after the BT test. Alternatively, the generation of carriers can be suppressed, so the normally OFF characteristics are obtained.

[0135] In addition, the source region 122a and the drain region 122b are connected to the substrate 100 or the second insulating layer. The contact with the layer 105 increases the resistance of the source region 122a and the drain region 122b. To provide a semiconductor device having a transistor 156 having excellent electrical characteristics and high reliability. It is possible.

[0136] There is no particular restriction on the material of the substrate 100, but it should be strong enough to withstand the subsequent heat treatment. For example, glass substrates, ceramic substrates, quartz substrates, and sa A substrate such as a ferroelectric substrate can be used as the substrate 100. In addition, silicon or silicon carbide can be used. Single crystal semiconductor substrates such as silicon, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium It is also possible to apply a conductor substrate, SOI substrate, etc., and semiconductor elements are formed on these substrates. The provided one may be used as the substrate 100 .

[0137] A flexible substrate may be used as the substrate 100. When providing the transistor, the transistor may be directly formed on the flexible substrate, or the transistor may be formed on another substrate. After the transistor is formed, it may be peeled off and transferred to a flexible substrate, which is the substrate 100. In order to peel off the transistor and transfer it to a flexible substrate, the transistor and the other substrate are A release layer may be formed between the substrate and the heater.

[0138] In addition, when the second insulating layer 105 is not provided, the amount of oxygen released from the substrate 100 is smaller than that of the first insulating layer 105. It is preferable to use a substrate that is made of less material than the insulating layer 104. For example, In the case where the layer 105 is not provided, the substrate 100 may be a glass substrate, a ceramic substrate, or a quartz substrate. It is preferable to use a sapphire substrate, an SOI substrate, or the like.

[0139] A manufacturing process of the transistor 156 will be described. A first insulating layer 104 is selectively formed on the second insulating layer 105. The insulating layer 104 is characterized in that it releases oxygen when heated. The material in 04 is silicon oxide (SiO X (X>2) may also be used. In order to improve the coverage of the oxide semiconductor layer 106 to be formed later, the first insulating layer 10 It is preferable that the end of the first insulating layer 104 is formed to have a slope. The photomask used in the formation of the gate electrode 114 is the same as that used in the formation of the gate electrode 114. can be used.

[0140] The subsequent manufacturing steps can be similar to those described in Embodiment Mode 1.

[0141] The transistor 156 described in this embodiment can omit a step of leveling the surface of an insulating layer. Therefore, it is possible to provide a transistor 156 with high throughput at low cost and in a simple manner. can.

[0142] According to the present embodiment, the insulating layer in contact with the channel region 126 of the oxide semiconductor layer 106 is The first insulating layer 104 which releases oxygen by heating is provided, and the source of the oxide semiconductor layer 106 is The amount of oxygen released from the substrate or insulating layer in contact with the drain region 122a and the drain region 122b is the largest. By providing a substrate 100 or a second insulating layer 105 that is less than the first insulating layer 104, Small current, small variation in threshold voltage, large on-current, stable electrical characteristics A transistor having a

[0143] Alternatively, according to this embodiment, a semiconductor device having a transistor with favorable electrical characteristics and high reliability can be provided. A conductor device is provided.

[0144] The structures, methods, etc. described in this embodiment may be combined as appropriate with the structures, methods, etc. described in other embodiments. They can be used in combination.

[0145] (Embodiment 3) In this embodiment, one mode of a semiconductor device will be described with reference to FIG. FIG. 9B shows a top view of a transistor. The cross-sectional structure is shown.

[0146] The transistor shown in FIG. 9B includes an insulating layer 103, an oxide semiconductor layer 1, and a 36, gate insulating layer 112, gate electrode 114, sidewall insulating layer 130, source electrode 116a , and drain electrode 116b. The insulating layer 103 is formed in the first region 101 and the second region 102. The transistor illustrated in FIG. 9B has a channel region 1 26, source region 122a, drain region 122b, offset region 123a and off The channel region 126, the source region 122a, the drain region 123b, The offset regions 122b, 123a and 123b are provided in the same layer. It is being done.

[0147] The offset region 123a and the offset region 123b have a higher resistance than the channel region 126. The source region 122a and the drain region 122b have a low resistance and are higher in resistance than the source region 122a and the drain region 122b. The width of the offset region 123a or the offset region 123b is also called Loff, and is shown in FIG. The width is shown in A). By having Loff, the short channel effect of the transistor is reduced. Therefore, when using miniaturized transistors where the short channel effect is prominent, The structure shown in FIG. 9(B) (also called the Loff structure) is preferable. This also reduces degradation of the transistors, such as hot carrier degradation.

[0148] The oxide semiconductor layer 136 is provided in contact with the first region 101 and the second region 102. The channel region 126 of the oxide semiconductor layer 136 is provided in contact with the first region 101. , the source region 122 a, the drain region 122 b, and the offset region of the oxide semiconductor layer 136 The offset region 123a and the offset region 123b are provided adjacent to the second region 102. The offset region 123a and the offset region 123b are It is located closer to the channel region 126 than the in-region 122b.

[0149] The gate insulating layer 112 includes a channel region 126, an offset region 123a, and an offset region 123b. The sidewall insulating layer 130 is provided around the gate electrode 114. A gate electrode 114 and a sidewall insulating layer 130 are provided in contact with the gate insulating layer 112. An interlayer insulating layer 124 is provided on the gate electrode 114 and the sidewall insulating layer 130. In addition, the source electrode 116a and the drain electrode 122b are in contact with the source region 122a and the drain region 122b. and drain electrodes 116b are provided, respectively, and a source electrode 116a and a drain electrode The wiring 108a and the wiring 108b are electrically connected to the wiring 116b via an interlayer insulating layer 124. are actively connected.

[0150] The conductive layer used for the source electrode 116a and the drain electrode 116b is, for example, A metal layer containing an element selected from the group consisting of I, Cr, Cu, Ta, Ti, Mo, and W, or the above-mentioned elements. Metal nitride layers containing titanium nitride as a component (titanium nitride layer, molybdenum nitride layer, tungsten nitride layer) In addition, the lower or upper side of a metal layer such as Al or Cu may be used. Both have a high melting point metal layer such as Ti, Mo, W, etc., or a layer of these metal nitrides (titanium nitride layer A laminated structure of a thin film transistor (a metal nitride layer, a molybdenum nitride layer, and a tungsten nitride layer) may be used.

[0151] In addition, the offset region 123a and the offset region 123b are arranged so that the amount of oxygen released is the first The offset region 123a and the second region 102, which is smaller than the region 101, are in contact with each other. The offset region 123b is prevented from being supplied with oxygen.

[0152] The offset region 123a and the offset region 123b are particularly low-resistance regions. The region where the insulating layer 103 contacts is distinguished from the channel region 126. The set region 123a and the offset region 123b are made of an insulating layer that releases oxygen when heated. 11 is a region of the oxide semiconductor layer 136 that is not in contact with the

[0153] The transistor described in this embodiment has an offset region, which allows for better current flow. It is possible to provide a transistor having excellent thermal properties and high reliability.

[0154] However, it is not always necessary to provide an offset region. For example, The transistor shown in FIG. 9C differs from that shown in FIG. 9B in that no offset region is provided. It has a structure.

[0155] Alternatively, according to this embodiment, a semiconductor device having a transistor with favorable electrical characteristics and high reliability can be provided. A conductor device is provided.

[0156] The structures, methods, etc. described in this embodiment may be combined as appropriate with the structures, methods, etc. described in other embodiments. They can be used in combination.

[0157] (Embodiment 4) Display using the transistor exemplified in the first, second or third embodiment It is possible to manufacture a semiconductor device (also called a display device) having a transistor function. A part or the whole of the driver circuit including the pixel unit is formed on the same substrate as the system A panel can be formed.

[0158] In FIG. 7A, a pixel portion 202 provided on a first substrate 201 is surrounded by a A sealant 205 is provided, and the substrate is sealed with a second substrate 206. In the above, a region different from the region surrounded by the sealant 205 on the first substrate 201 is A scanning line formed of a single crystal semiconductor layer or a polycrystalline semiconductor layer on a separately prepared substrate is provided in the region. A driver circuit 204 and a signal line driver circuit 203 are mounted on the board. A driving circuit 203 and a scanning line driving circuit 204 or various signals and voltages provided to the pixel portion 202 are The second place is FPC (Flexible printed circuit) 218a, 218 It is supplied by b.

[0159] In FIG. 7B and FIG. 7C, a pixel portion 202 provided on a first substrate 201 and A sealant 205 is provided so as to surround the scanning line driver circuit 204. A second substrate 206 is provided on the element portion 202 and the scanning line driving circuit 204. The pixel portion 202 and the scanning line driver circuit 204 are formed by a first substrate 201, a sealant 205, and a second substrate 202. The display element is sealed with the substrate 206. In the above, a region different from the region surrounded by the sealant 205 on the first substrate 201 is A signal line formed of a single crystal semiconductor layer or a polycrystalline semiconductor layer on a separately prepared substrate is provided in the region. In FIG. 7B and FIG. 7C, a driving circuit 203 is mounted. A signal line driver circuit 203 and a scanning line driver circuit 204 or various signals provided to the pixel portion 202 Signals and potentials are supplied from the FPC 218 .

[0160] In addition, in FIG. 7B and FIG. 7C, the signal line driver circuit 203 is formed separately. However, the present invention is not limited to this configuration. The circuit may be formed separately and mounted, or may be mounted as part of a signal line driver circuit or a scanning line driver circuit. Alternatively, the first and second electrodes may be separately formed and mounted.

[0161] The method of connecting the separately formed drive circuit is not particularly limited, and may be any method such as COG ( hip on glass method, wire bonding method, or TAB (Tape The Automated Bonding method can be used. This is an example of mounting a signal line driver circuit 203 and a scanning line driver circuit 204 by the COG method. FIG. 7(B) shows an example in which the signal line driver circuit 203 is mounted by the COG method, and FIG. 13 is an example in which the signal line driver circuit 203 is mounted by the TAB method.

[0162] The display device includes a panel in which a display element is sealed, and a controller for the panel. and modules in which ICs including lasers are mounted.

[0163] In this specification, the term "display device" refers to an image display device, a display device, or Refers to light sources (including lighting devices). Also refers to connectors, such as FPC or TAB tape. or a module with TCP attached, a printed wiring board on the tip of TAB tape or TCP The IC (integrated circuit) is directly mounted on the module or display element using the COG method. The display device includes all of the modules installed in the display device.

[0164] In addition, the pixel portion and the scanning line driver circuit provided on the first substrate 201 have a plurality of transistors. The transistors shown in the first, second or third embodiment have a number of transistors. A stamp can be applied.

[0165] Examples of display elements provided in the display device include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, and the like. A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also includes electronic inks and other electrically-operated A display medium whose contrast changes depending on use can also be applied.

[0166] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. Liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials can be in a cholesteric phase, a smectic phase, a cubic phase, or It exhibits chiral nematic phase, isotropic phase, etc.

[0167] Also, liquid crystals exhibiting a blue phase, which can eliminate the need for an alignment layer, may be used. is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, the cholesteric phase changes to the equilibrium phase. This is the phase that appears just before the transition to the lattice phase. The blue phase appears only in a narrow temperature range. In order to improve the temperature range, a liquid crystal composition containing a chiral agent is used in the liquid crystal layer. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec or less. Since the film is short and optically isotropic, no alignment treatment is required, and the viewing angle dependency is small. Since no layer is required, rubbing treatment is also unnecessary. This prevents electrostatic damage that may occur during the manufacturing process, reducing defects and damage to liquid crystal display devices. Therefore, the productivity of the liquid crystal display device can be improved.

[0168] The specific resistivity of the liquid crystal material is 1×10 9 Ω cm or more, preferably 1×10 11 Ω cm or more, and more preferably 1×10 12 Ω·cm or more. The resistivity values ​​in the specification are values ​​measured at 20°C.

[0169] The size of the storage capacitor provided in the liquid crystal display device is determined by the capacitance of the transistor arranged in the pixel portion. It is set so that the charge can be held for a certain period of time, taking into account the break current, etc. By using a transistor having an oxide semiconductor layer, the liquid crystal capacitance in each pixel can be reduced. It is sufficient to provide a storage capacity having a capacity of 1 / 3 or less, preferably 1 / 5 or less. It is.

[0170] The transistor including an oxide semiconductor layer used in this embodiment has a current in an off state. Therefore, the retention time of electrical signals such as image signals can be reduced. The write interval can be set longer when the power is on. Since the frequency of the refresh operation can be reduced, this has the effect of reducing power consumption.

[0171] In addition, the transistor including an oxide semiconductor layer used in this embodiment has a relatively high electric field Therefore, it is possible to achieve high-speed driving because of the high effective mobility. By using the transistor, a high quality image can be provided. The transistor can be separately manufactured for the driver circuit section and the pixel section on the same substrate. Therefore, the number of parts in the liquid crystal display device can be reduced.

[0172] There are two types of LCD displays: TN (Twisted Nematic) mode, IPS (In- Plane-Switching mode, FFS (Fringe Field Switching) mode tching) mode, ASM(Axially Symmetric aligned) Micro-cell) mode, OCB(Optical Compensated) Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal mode etc. can be used.

[0173] In addition, normally black type liquid crystal display devices, for example, those using a vertical alignment (VA) mode Here, the vertical alignment mode is a mode in which the liquid crystal display panel is This is a method for controlling the arrangement of liquid crystal molecules, and is used to display the liquid crystal on the panel surface when no voltage is applied. In this method, the liquid crystal molecules are oriented vertically. There are several types of vertical alignment modes: For example, MVA (Multi-Domain Vertical Alignment) ent) mode, PVA (Patterned Vertical Alignment ) mode, ASV mode, etc. can be used. The molecules are divided into sub-pixels, each of which is designed to tilt in a different direction. A method known as multi-domain or multi-domain design can be used.

[0174] In addition, in display devices, black matrices (light-shielding layers), polarizing members, phase difference members, reflectors, Optical members (optical substrates) such as anti-reflection members are provided as appropriate. For example, a polarizing substrate and a retardation Circular polarization by the substrate may be used. Also, backlight, sidelight, etc. may be used as the light source. It may be used.

[0175] In addition, multiple light-emitting diodes (LEDs) are used as backlights to display the image in a time-division format. It is also possible to use the field sequential driving method. By applying the Shar driving method, color display is achieved without using color filters. It is possible.

[0176] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB ( R stands for red, G for green, and B for blue). For example, RGBW (W stands for white) or RGB plus one or more colors such as yellow, cyan, or magenta The size of the display area may be different for each dot of the color element. The present invention is not limited to color display devices, but may be applied to monochrome display devices. It is also possible.

[0177] In addition, a light-emitting device using electroluminescence is used as a display element included in the display device. The light-emitting element that utilizes electroluminescence can be applied to a light-emitting material They are classified according to whether the material is an organic compound or an inorganic compound. The latter is called an inorganic EL element.

[0178] In an organic EL element, when a voltage is applied to the light-emitting element, electrons and holes are emitted from a pair of electrodes. are injected into layers containing light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. When the excited state returns to the ground state, light is emitted. The light-emitting element is called a current-excited light-emitting element.

[0179] Inorganic EL elements are classified into dispersion type inorganic EL elements and thin film type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-based ion exchange reaction that utilizes the donor and acceptor levels. This is an acceptor recombination type emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner shell electron transition of metal ions. This is a localized light emission that utilizes organic EL elements. do.

[0180] The light emitting element only needs to have at least one of the pair of electrodes transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. The top emission is from the top surface, the bottom emission is from the surface on the substrate side, and the bottom emission is from the surface on the substrate side and the opposite side to the substrate. There are light emitting devices with a double-sided emission structure that emits light from both sides, and light emitting devices of any emission structure can be used. It is possible.

[0181] It is also possible to provide electronic paper that drives electronic ink as a display device. Electronic paper is also called an electrophoretic display device (electrophoretic display). It has the same readability as paper, consumes less power than other display devices, and can be made thin and light. This has the advantage that:

[0182] The electrophoretic display device may have various configurations, but the first particles have a positive charge. and a second particle having a negative charge are mixed into a solvent or solute. By applying an electric field to the microcapsules, By moving the particles in a capsule in opposite directions, only the color of the particles that have gathered on one side is displayed. In addition, the first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (including colorless). (Mm).

[0183] In this way, electrophoretic displays are devices in which materials with high dielectric constants move to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0184] The microcapsules dispersed in a solvent are called electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. In addition, a color display is possible by using a color filter or particles having a pigment.

[0185] The first particles and the second particles in the microcapsules are made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of trochromic material, magnetophoretic material, and a composite material thereof is used. That's good.

[0186] In addition, display devices using the twist ball display method can also be used as electronic paper. The twist ball display method uses black and white spherical particles as display elements. The electrode layer is disposed between the first electrode layer and the second electrode layer, which are the electrode layers to be used. This method creates a potential difference between the electrode layers to control the orientation of the spherical particles, thereby displaying information. be.

[0187] A display device transmits light from a light source or a display element to display an image. The thin films such as the substrate, insulating layer, and conductive layer provided in the pixel area are all sensitive to light in the visible light wavelength range. This makes it translucent.

[0188] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, In the case of the counter electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmitting property or the reflecting property can be selected depending on the pattern structure of the electrode layer.

[0189] As described above, the transistor illustrated in the first, second or third embodiment By applying the above, a highly reliable semiconductor device can be provided. 1. The transistor exemplified in the second or third embodiment has the above-mentioned display function. Not only semiconductor devices, but also power devices mounted on power circuits, semiconductor integrated circuits such as LSIs, etc. Various functions such as semiconductor devices with circuits and image sensor functions that read information from objects The present invention can be applied to a semiconductor device having a

[0190] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0191] (Embodiment 5) The semiconductor device according to one embodiment of the present invention can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras, etc. Cameras such as digital cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices) (hereinafter referred to as "computer games"), portable game machines, personal digital assistants, audio playback devices, large game machines such as pachinko machines Examples of electronic devices including the semiconductor device described in the above embodiment include He explains.

[0192] FIG. 8A shows a notebook personal computer, which includes a main body 301, a housing 302, The display unit 303 and the keyboard 304 are included. By applying the semiconductor device shown in any one of the above, a highly reliable notebook type personal computer can be manufactured. The input signal may be a computer.

[0193] FIG. 8B shows a portable digital assistant (PDA), which has a main body 311 including a display unit 313 and an external An interface 315 and an operation button 314 are provided. The semiconductor device shown in any one of the first to third embodiments is a stylus 312. By applying this technology, a more reliable personal digital assistant (PDA) can be achieved.

[0194] FIG. 8C shows an example of an electronic book. For example, an electronic book 320 has a housing 321 The housing 321 and the housing 322 are connected to the shaft portion 32 5, and opening and closing operations can be performed with the shaft portion 325 as an axis. Such a configuration makes it possible to operate like a paper book.

[0195] A display unit 323 is incorporated in the housing 321, and a display unit 324 is incorporated in the housing 322. The display unit 323 and the display unit 324 may be configured to display a continuous screen, or may be configured to display different screens. By configuring to display different screens, for example, A text is displayed on the right display unit (display unit 323 in FIG. 8C) and a text is displayed on the left display unit ( In the case of the embodiment 1 to 4, an image can be displayed on the display unit 324. By applying the semiconductor device shown in the drawings, a highly reliable e-book reader can be obtained.

[0196] FIG. 8C shows an example in which an operation unit and the like are provided on the housing 321. The body 321 includes a power source 326, operation keys 327, a speaker 328, and the like. The operation keys 327 can be used to turn pages. The configuration may include a keyboard, a pointing device, etc. , external connection terminals (earphone terminal, USB terminal, etc.), a recording medium insertion section, etc. Furthermore, the electronic book 320 may be configured to have a function as an electronic dictionary. Good too.

[0197] The electronic book 320 may also be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0198] FIG. 8D shows a portable information terminal, which is composed of two housings, a housing 330 and a housing 331. The housing 331 includes a display panel 332, a speaker 333, and a microphone 334. 34, pointing device 336, camera lens 337, external connection terminal 338, etc. The housing 330 also includes a solar cell 340 for charging the portable information terminal. , an external memory slot 341, etc. Also, the antenna is built inside the housing 331. By applying the semiconductor device described in any one of the first to fourth embodiments, It is possible to provide a highly reliable portable information terminal.

[0199] The display panel 332 is equipped with a touch panel, and in FIG. The multiple operation keys 335 are indicated by dotted lines. A boost circuit is also implemented to boost the voltage to the voltage required for each circuit.

[0200] The display direction of the display panel 332 changes appropriately depending on the usage mode. A camera lens 337 is provided on the same surface as 332, making video telephony possible. The speaker 333 and microphone 334 are not limited to voice calls, but also video calls, recording, playback, etc. Furthermore, the housing 330 and the housing 331 can be slid to each other as shown in FIG. It can be folded from the unfolded state to the overlapping state, making it compact and suitable for carrying. It is Noh.

[0201] The external connection terminal 338 can be connected to various cables such as an AC adapter and a USB cable. It is possible to charge the battery and to communicate data with a personal computer, etc. A recording medium can be inserted into the memory slot 341 to accommodate the storage and transfer of larger amounts of data. .

[0202] In addition to the above functions, it also has infrared communication function, TV reception function, etc. Good too.

[0203] FIG. 8E shows a digital video camera, which includes a main body 351, a display unit (A) 357, and an eyepiece. The device is constituted by a display unit 353, an operation switch 354, a display unit (B) 355, a battery 356, etc. By applying the semiconductor device described in any one of the first to fourth embodiments, Therefore, it can be a highly reliable digital video camera.

[0204] FIG. 8(F) shows an example of a television device. The television device 360 ​​is A display unit 363 is built into the body 361. The display unit 363 can display images. In addition, a configuration in which the housing 361 is supported by a stand 365 is shown here. By applying the semiconductor device described in any one of the first to fourth embodiments, reliability can be improved. This makes the television device 360 ​​highly user-friendly.

[0205] The television device 360 ​​can be operated using an operation switch provided on the housing 361 or a separate remote control. In addition, the remote control device can be operated by a remote control device. A display unit for displaying input information may be provided.

[0206] The television device 360 ​​is configured to include a receiver, a modem, and the like. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0207] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination. [Explanation of symbols]

[0208] 100 Substrates 101 First Area 102 Second Area 103 Insulating layer 104 First insulating layer 105 Second insulating layer 106 Oxide semiconductor layer 108a Wiring 108b Wiring 112 Gate insulating layer 113 Gate Insulation Layer 114 Gate electrode 116a Source electrode 116b Drain electrode 122a Source Region 122b Drain region 123a Offset Area 123b Offset Area 124 Interlayer insulation layer 126 Channel Area 130 Sidewall insulating layer 131 First insulating layer 132 Second insulating layer 133 Third Insulating Layer 136 Oxide Semiconductor Layer 155 Transistor 156 Transistor 201 Substrate 202 Pixel section 203 Signal line driver circuit 204 Scanning line driving circuit 205 Sealing material 206 Substrate 218 FPC 218a FPC 218b FPC 301 Main unit 302 Case 303 Display section 304 Keyboard 311 Main unit 312 Stylus 313 Display section 314 Operation button 315 External Interface 320 e-books 321 Case 322 Case 323 Display section 324 Display section 325 Shaft 326 Power supply 327 Operation Key 328 Speakers 330 Case 331 Case 332 Display Panel 333 Speaker 334 Microphone 335 Operation Key 336 Pointing Device 337 Camera Lenses 338 External connection terminal 340 Solar Cells 341 External memory slot 351 Main unit 353 Eyepiece 354 Operation switch 355 Display section (B) 356 Battery 357 Display section (A) 360 Television Equipment 361 Case 363 Display section 365 Stand

Claims

1. an insulating layer having a first region and a second region; an oxide semiconductor layer provided in contact with an upper surface of the insulating layer in the first region and the second region; a gate insulating layer provided in contact with the oxide semiconductor layer; a gate electrode provided in contact with the gate insulating layer, the oxide semiconductor layer has a channel region, a source region, and a drain region; the channel region is provided in contact with the first region, the gate insulating layer is provided in contact with the second region, the source region and the drain region are provided in contact with the second region, The second region releases less oxygen than the first region.

2. an insulating layer having a first region and a second region; an oxide semiconductor layer provided in contact with an upper surface of the insulating layer in the first region and the second region; a gate insulating layer provided in contact with the oxide semiconductor layer; a gate electrode provided in contact with the gate insulating layer, the oxide semiconductor layer has a channel region, a source region, and a drain region; the channel region is provided in contact with the first region, the gate insulating layer is provided in contact with the second region, the source region and the drain region are provided in contact with the second region, The second region releases less oxygen than the first region, The semiconductor device, wherein the oxide semiconductor layer is In—O.

3. In claim 1 or 2, the first region has silicon oxide; The semiconductor device, wherein the second region has silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

Images