Nanowire and method for manufacturing the same

Abstract

According to the present invention, after having fine metal particles, which are configured from Ga, penetrate through a silicon oxide layer (102) by means of heating and bringing the fine metal particles into contact with the surface of an Si substrate (101), an In source is supplied thereto so as to form fine alloy particles (104), which are formed of an alloy of Ga and In, and the In source and a P source are subsequently supplied thereto so as to form nanowires (105), which contain In, Ga and P as constituent elements, by means of crystal growth (VLS growth) of a compound semiconductor, while using the fine alloy particles (104) as a catalyst.

Description

Technical Field

[0001] The present invention relates to nanowires and a method for manufacturing the same.

Background Art

[0002] Si is widely used as a material for electronic devices such as CMOS and optical devices such as light receivers and solar cells because of its stability as a material and the ease of increasing the diameter of the substrate. On the other hand, there are problems caused by the material properties that it is difficult to emit light from Si itself or to obtain a large electron mobility. In order to solve these problems, studies have been underway for a long time to integrate light-emitting devices using III-V semiconductors or electronic devices with large mobility on a Si substrate or a Si-based structure. When a structure using a III-V semiconductor is directly fabricated and integrated on Si, there are the following three problems.

[0003] First, when a III-V semiconductor having polarity is epitaxially grown on a non-polar substrate such as Si, a phase change of the atomic arrangement easily occurs on the same plane. Specifically, the surface locally becomes a group III plane or a group V plane. The boundary where this phase changes is called an antiphase boundary. When there is such a phase change, crystal defects are caused thereby.

[0004] Second, the thermal expansion coefficient of the III-V semiconductor is nearly twice that of Si. This means that the difference in lattice spacing between the III-V semiconductor and Si varies depending on the temperature. Therefore, when a III-V semiconductor is grown on Si, when the substrate temperature is returned from a high temperature to room temperature, tensile stress is applied to both the grown film and the Si substrate, and cracks are likely to occur or the grown film is likely to peel off.

[0005] Third, compared with Si, the lattice constant of the III-V semiconductor is about 4% larger in GaAs and about 8% larger in InP, so misfit dislocations easily occur due to lattice mismatch.

[0006] Among the above, regarding the first and second problems, it is possible to solve them by adopting an off-substrate, procedures for heating and cooling the substrate temperature, devising the layer structure, etc. On the other hand, regarding the third one, it is an essential problem caused by material parameters and is difficult to solve. In a device structure using a general III-V semiconductor, a wafer with a two-dimensional epitaxial thin film grown is often used.

[0007] In this case, lattice deformation in the epitaxial film is only allowed in the growth direction (vertical direction), and in a state where crystal defects do not occur, the lattice spacing in the growth plane (horizontal direction) is almost equal to that of the substrate. That is, in an epitaxial film by two-dimensional growth, it is necessary to absorb the stress caused by lattice mismatch only by lattice deformation in the growth direction. However, when the lattice mismatch between the substrate and the epitaxial film is large or when the film thickness of the epitaxial film is large, it is difficult to absorb the stress only by lattice deformation in this growth direction. When this stress cannot be absorbed, crystal defects such as misfit dislocations occur.

[0008] On the other hand, a nanowire structure with a diameter on the nanometer scale can be lattice-deformed not only in the growth direction but also to some extent in the growth plane, which is different from the case of two-dimensional growth. For this reason, in a nanowire structure using a III-V semiconductor on Si, it is easier to fabricate while suppressing the occurrence of crystal defects due to misfit dislocations compared to the case of two-dimensional growth. Also, the direction in which the transition propagates can be made different from the growth direction, and the influence of crystal defects on the growth layer can be reduced. Due to these characteristics, research and development on fabricating optical devices and electronic devices using III-V semiconductor nanowires on Si are actively underway.

Prior Art Documents

Non-Patent Documents

[0009]

Non-Patent Document 1

[0010] The problems in fabricating III-V semiconductors on Si described above can be mitigated by using a nanowire structure. In the growth of nanowires, a growth mode called VLS (Vapor-Liquid-Solid) growth using liquid metal fine particles as a catalyst is generally used.

[0011] In VLS growth, although not in thermal equilibrium, semiconductors grow on the semiconductor surface in contact with metal droplets (metal fine particles in the case of nanowires) in the same way as liquid phase epitaxy (LPE), and III-V semiconductor nanowires are formed bottom-up. The metal fine particles used as this catalyst can be roughly classified into cases where they are composed only of the metal of the group III element of the III-V semiconductor to be grown, and cases where they are composed of an alloy of Au and the metal of the group III element. The former has the advantage that there is no mixing of Au, which is a problem in the Si process, compared to the latter, and furthermore, the process of forming Au fine particles when producing the metal fine particles serving as the catalyst becomes unnecessary.

[0012] In any case of using the above metal fine particles, the growth direction of the nanowire greatly depends on the plane orientation of the underlying Si. Therefore, in order to fabricate nanowires with aligned growth directions, it is necessary to transfer the information on the plane orientation of Si to the III-V semiconductor. For this purpose, basically, it is necessary to directly contact Si and the III-V semiconductor. In order to directly contact Si and the III-V semiconductor, it is necessary to remove the silicon oxide film (SiO x ) formed on Si.

[0013] However, it is known that the silicon oxide film is formed immediately upon exposure to the atmosphere and is very stable. Generally, when trying to remove the silicon oxide film only by heat treatment, it is difficult without heating the substrate temperature to 800 °C or higher. On the other hand, in devices such as CMOS, light receivers, solar cells, and optical waveguides using Si, the concentration profiles of dopants and constituent elements are likely to change due to high-temperature heat treatment, which becomes a factor in changing the characteristics of the device. Therefore, when fabricating nanowires using a III-V semiconductor on Si, it is desirable to use a method that can reduce the influence of the silicon oxide film at a relatively low substrate temperature.

[0014] In the fabrication of GaAs nanowires on a Si substrate, when Ga metal fine particles are formed on a silicon oxide film and heated at a relatively low substrate temperature, these Ga metal fine particles can penetrate the silicon oxide film and reach the Si surface. Thus, it is known that GaAs nanowires with aligned crystal orientations can be fabricated on Si (see, for example, Non-Patent Document 1 and Non-Patent Document 2).

[0015] As an example, the fabrication process of producing GaAs nanowires on a Si substrate will be described with reference to FIGS. 6, 7A, 7B, and 7C. Note that in the flowchart of FIG. 6, the steps in parentheses are not essential.

[0016] For example, the pretreatment of the Si substrate 301 generally involves removing the silicon oxide film by wet treatment using hydrofluoric acid or the like, but it is also possible to load it into the apparatus and use it without wet treatment (see, for example, Non-Patent Document 3). In this fabrication process, Ga metal fine particles 303 are formed on the Si substrate 301 (strictly speaking, on the silicon oxide film 302). The density and size of the Ga metal fine particles 303 can be controlled by the supply amount and supply rate of the Ga raw material, the substrate temperature, and the like.

[0017] At this point, since there is a silicon oxide film 302 on the surface of the Si substrate 301, as shown in FIG. 7B, the Ga metal fine particles 303 are formed on the silicon oxide film 302 rather than on the Si. It is known that when the substrate temperature is increased with Ga in contact with the silicon oxide film 302, Ga reacts with the silicon oxide film 302 to form another compound (see, for example, Non-Patent Document 4 and Non-Patent Document 5).

[0018] The compound generated by the reaction between Ga and the silicon oxide film 302 is incorporated into the Ga metal fine particles 303. Therefore, the Ga metal fine particles 303 can penetrate the silicon oxide film 302, and as shown in FIG. 7C, the metal fine particles 303 reach the Si surface. The silicon oxide film 302 naturally formed on the Si substrate 301 can also serve as a mask for selective growth when fabricating nanowires.

[0019] Therefore, when it is desired to increase the thickness of the silicon oxide film 302, as shown in the flowchart of FIG. 6, the substrate may be temporarily taken out of the apparatus, exposed to the atmosphere to form an additional oxide film, and then re-introduced into the apparatus (see, for example, Non-Patent Document 6). After that, if the substrate is heated to a desired temperature and Ga raw material and As raw material are supplied, GaAs nanowires 304 can be fabricated on the Si substrate 301.

[0020] In the fabrication of the nanowires described with reference to FIGS. 6, 7A, 7B, and 7C, the key point is to react the Ga metal fine particles 303 with the silicon oxide film 302 and penetrate it. The temperature required to penetrate the silicon oxide film 302 is considerably lower than the temperature required to remove the silicon oxide film 302 by heat treatment alone (generally 800° C. or higher), and is about 610° C. to 760° C. (see, for example, Non-Patent Documents 1, 2, 3, and 5).

[0021] In other words, if the temperature is raised to a level at which the Ga metal fine particles 303 formed on the Si substrate 301 can react with the silicon oxide film 302, nanowires can be fabricated on the Si substrate 301 without high-temperature heat treatment. Generally, in this nanowire fabrication process, the highest substrate temperature occurs in the step where the Ga metal fine particles 303 penetrate the silicon oxide film 302. The temperature of about 610° C. to 760° C. mentioned above is not much different from the substrate temperature used in the thin film growth of general GaAs-based and InP-based semiconductors, and there is little possibility of a significant change in the concentration profile of dopants and constituent elements.

[0022] GaAs nanowires on Si can be fabricated without the high-temperature heat treatment for removing the silicon oxide film by using the method described above. On the other hand, it is difficult to fabricate a light-emitting device corresponding to the wavelength band (1.26 to 1.675 μm) used in optical fiber communication by using a structure utilizing GaAs nanowires because of the large lattice constant difference between the material forming the light-emitting layer and GaAs nanowires. This problem can be solved by using InP nanowires instead of GaAs nanowires and adopting a structure having a well layer that becomes the light-emitting layer therein (see Non-Patent Document 7).

[0023] In the case of fabricating InP nanowires, VLS growth using metal fine particles as a catalyst is also used. As described above, in VLS growth, group III raw materials are supplied to the growth surface via metal fine particles. Therefore, in the case of InP nanowires, it is common to use elemental In or an alloy of In and Au for the metal fine particles. When trying to use the same method as the GaAs nanowires described above, it is necessary to form elemental In or an alloy of In and Au on the silicon oxide film and then react with and penetrate the silicon oxide film.

[0024] In and Ga belong to the same group 13 in the periodic table, but generally, In with a larger atomic number is less reactive than Ga. Therefore, it is considered that a higher heating temperature is required for the metal fine particles of In to penetrate the silicon oxide film than in the case of using Ga metal fine particles. However, when the temperature is increased, In evaporates more easily than Ga.

[0025] Figure 8 shows the change in vapor pressure with the temperature of In and Ga. The vapor pressure of In at 600 °C to 700 °C is nearly two orders of magnitude higher than that of Ga. That is, although it is considered that a high heating temperature is required to penetrate the silicon oxide film using metal fine particles that are In or an alloy of In and Au, desorption from the surface of In itself occurs when the temperature becomes high. Therefore, when forming InP nanowires on Si, there is a problem that it cannot be easily fabricated as in the case of GaAs nanowires using Ga metal fine particles on the silicon oxide film.

[0026] The present invention has been made to solve the above problems, and an object thereof is to enable the formation of nanowires composed of In and P on a Si layer.

Means for Solving the Problems

[0027] The method for manufacturing a nanowire according to the present invention includes: a first step of forming metal fine particles composed of Ga on a Si layer via a silicon oxide layer; a second step of heating to cause the metal fine particles to penetrate the silicon oxide layer and contact the surface of the Si layer; a third step of supplying a raw material of In to make the metal fine particles into alloy fine particles composed of an alloy of Ga and In; and a fourth step of supplying a raw material of In and a raw material of P to form a nanowire composed of In, Ga, and P as constituent elements using the alloy fine particles as a catalyst.

[0028] The nanowire according to the present invention is a nanowire composed of In, Ga, and P formed on a Si layer via a silicon oxide layer, and the composition ratio of Ga decreases as the distance from the Si layer increases.

Effects of the Invention

[0029] As described above, according to the present invention, since a raw material of In is supplied to metal fine particles composed of Ga and used as alloy fine particles composed of an alloy of Ga and In, nanowires composed of In and P as constituent elements can be formed on the Si layer.

Brief Description of the Drawings

[0030]

Figure 1A

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Figure 1C

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Figure 8

Embodiments for Carrying Out the Invention

[0031] Hereinafter, a method for manufacturing a nanowire according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1E.

[0032] First, as shown in FIG. 1A, a Si substrate (Si layer) 101 is prepared. For example, the main surface of the Si substrate 101 is oriented in the (111) plane direction. Further, a silicon oxide layer 102 is formed on the surface of the Si substrate 101. Next, as shown in FIG. 1B, metal fine particles 103 composed of Ga are formed on the Si substrate 101 via the silicon oxide layer 102 (first step).

[0033] For example, after etching the Si substrate 101 by a known method using hydrofluoric acid and pure water, it is carried into the introduction chamber of an organometallic molecular beam epitaxy (MOMBE) apparatus and evacuated. Even if it is carried into the introduction chamber of the MOMBE apparatus within 5 minutes after the treatment using hydrofluoric acid and pure water, a silicon oxide layer 102 is formed on the surface of the Si substrate 101 due to exposure to the atmosphere. When the exposure to the atmosphere is short, it is known that the thickness of the formed silicon oxide layer 102 is about 0.3 to 0.6 nm (see, for example, Non-Patent Document 2).

[0034] As described above, after transporting the Si substrate 101 having the silicon oxide layer 102 formed on its surface from the introduction chamber to the growth chamber, it is heated under the conditions of a substrate temperature of 660° C. for 5 minutes to remove surface impurities. After lowering the substrate temperature to 550° C., trimethylgallium (TEGa), which is a raw material of Ga, is supplied into the growth chamber for 30 seconds. Thereby, Ga metal fine particles 103 are formed on the silicon oxide layer 102.

[0035] Next, as shown in FIG. 1C, by heating, the metal fine particles 103 are made to penetrate the silicon oxide layer 102 and contact the surface of the Si substrate 101 (second step). For example, following the formation of the metal fine particles 103 described above, in the same growth chamber, by raising the substrate temperature to 630° C. and performing a heat treatment for 20 minutes, the metal fine particles 103 penetrate the silicon oxide layer 102 and reach the surface of the Si substrate 101.

[0036] Next, an In raw material is supplied to convert the metal fine particles 103 into alloy fine particles 104 made of an alloy of Ga and In as shown in FIG. 1D (third step). For example, following the heat treatment described above, in the same growth chamber, the substrate temperature is lowered to 460° C., and trimethylindium (TMIn), which is the In raw material, is supplied into the growth chamber for 60 seconds. Thereafter, the supply of TMIn is stopped and the chamber is held for 2 minutes. By this treatment, the metal fine particles 103 are converted into alloy fine particles 104 of In and Ga.

[0037] Next, as shown in FIG. 1E, an In raw material and a P raw material are supplied to form a nanowire 105 having In, Ga, and P as constituent elements using the alloy fine particles 104 as a catalyst (fourth step). For example, as described above, after forming the alloy fine particles 104, the Si substrate 101, whose temperature has been once lowered, is transferred from the growth chamber to the introduction chamber in the growth chamber, further taken out from the introduction chamber and exposed to the atmosphere, and then the Si substrate 101 is again transferred into the introduction chamber and evacuated.

[0038] Next, the Si substrate 101 is transferred from the introduction chamber to the growth chamber, and impurities adhering to the substrate surface are removed under the condition of a substrate temperature of 500° C. Next, the substrate temperature is lowered to 430° C. In this state, TMIn, which is the In raw material, and PH 3 which is the P raw material, are introduced into the growth chamber, and In and P (P 2 ) generated by the decomposition of these raw materials are supplied to the substrate surface. By these operations, a nanowire 105 having In, Ga, and P as constituent elements grows by crystal growth (VLS growth) of a compound semiconductor using the alloy fine particles 104 as a catalyst. As a result, the nanowire 105 is formed in contact with the alloy fine particles 104.

[0039] Incidentally, in the growth of the nanowire 105 using the alloy fine particles 104 as a catalyst as described above, the diameter of the nanowire 105 is determined by the diameter of the alloy fine particles 104. Therefore, when manufacturing the nanowire 105, the supply amount of TMIn is adjusted so that the diameter of the alloy fine particles 104 does not change significantly. Here, in the formation (growth) of the nanowire 105, since no Ga raw material is supplied, as the nanowire 105 grows, the Ga content in the alloy fine particles 104 decreases. As a result, the Ga composition ratio of the nanowire 105 becomes smaller as it moves away from the Si substrate 101, and the lattice constant of the nanowire 105 is small in the region close to the Si substrate 101 and increases as it moves away, and finally approaches the lattice constant of InP. As a result, according to this manufacturing method, as will be described later, a structure having an emission wavelength corresponding to the wavelength band used in optical fiber communication can be fabricated.

[0040] Next, the concept of the method for manufacturing a nanowire according to an embodiment of the present invention will be described with reference to FIG. 2. The method for manufacturing a nanowire according to the present invention includes, in step S101, performing wet processing such as cleaning of a Si substrate, in step S102, forming Ga metal fine particles on a silicon substrate on which an oxide film (oxide layer) is formed, in step S103, causing the metal fine particles to penetrate the oxide film and contact the Si substrate, in step S104, supplying In to form the metal fine particles into alloy fine particles made of an alloy of Ga and In, in step S105, carrying out the loading and reloading of the Si substrate to increase the thickness of the oxide layer, in step S106, heating to a predetermined temperature, and in step S107, forming a nanowire having In, Ga, and P as constituent elements. The steps of step S101, step S105, and step S106 are not necessary.

[0041] As shown in FIG. 2, a significant difference from the conventional manufacturing process described with reference to FIG. 6 is that in step S103, after contacting metal fine particles of Ga on the Si substrate, there is a step S104 of supplying In to form alloy fine particles of In and Ga. In the present invention, these alloy fine particles are used as a catalyst to fabricate nanowires. In step S104, when In is supplied onto a substrate having metal fine particles, the phenomenon that In is incorporated into these metal fine particles is utilized. Note that metallic Ga has the characteristic of easily alloying with other metals, and both In and Ga have low melting points (the melting point of In is about 157° C. and the melting point of Ga is about 30° C.), so it is easy to obtain the above-mentioned alloy of In and Ga.

[0042] On the other hand, since the reactivity of In is lower than that of Ga, it is possible to perform surface diffusion at a relatively low substrate temperature. Therefore, when there are metal fine particles on the substrate surface, it is easy to incorporate In into the metal fine particles.

[0043] FIGS. 3A and 3B are photographs showing the state of experimental results indicating how In is incorporated into metal fine particles. FIG. 3A shows an atomic force microscope (AFM) image of the surface of the substrate on which metal fine particles are arranged before supplying In. FIG. 3B shows an AFM image of the substrate surface after supplying a raw material of In at a substrate temperature of 460° C. and holding at this temperature for 2 minutes. The metal fine particles (alloy fine particles) in FIG. 3B are larger in size (area and height) than those in FIG. 3A, but the density has hardly changed. This indicates that the supplied In has been incorporated into the metal fine particles present on the substrate surface.

[0044] When using alloy fine particles that become an alloy of In and Ga, the semiconductor grown by VLS is composed of In, Ga, and P (InGaP). The molar composition ratio of Ga in this InGaP increases as the Ga content in the alloy fine particles increases. This is because the group III elements in the group III-V semiconductor nanowires are supplied in such a way that the group III elements contained therein move through the alloy fine particles (metal fine particles).

[0045] On the one hand, in order to fabricate nanowires with a uniform diameter along the growth direction, it is necessary to continuously supply group III raw materials (In raw materials) so that the alloy nanoparticles do not become smaller. When growing nanowires using alloy nanoparticles composed of an alloy of In and Ga, if only the In raw material is supplied, the molar composition ratio of Ga in the InGaP nanowires can be changed in the growth direction.

[0046] FIG. 4 schematically shows the change in the growth direction of the Ga content in the nanowire 105 composed of In, Ga, and P as constituent elements. The molar composition ratio of Ga in the nanowire 105 decreases as the growth of the nanowire 105 progresses due to the change in the Ga content during the growth process in the alloy nanoparticles 104. In this case, the lattice constant of InGaP becomes smaller as it gets closer to the Si substrate 101. As described above, in the nanowire 105, it is less affected by the misfit transition than the epitaxial film by two-dimensional growth, but it is still preferable that the lattice mismatch is smaller.

[0047] The nanowire 105 made of InGaP has a structure that can reduce the lattice mismatch with Si compared to InP nanowires, and this feature becomes more prominent as it gets closer to the Si substrate 101. On the other hand, since the Ga molar composition ratio of the nanowire 105 decreases as the growth progresses, if a layer that becomes the light-emitting layer is grown when the lattice constant of the nanowire 105 approaches that of InP, an optical device in the wavelength band used for optical fibers can be fabricated.

[0048] Note that the Ga molar composition ratio of the nanowire 105 made of InGaP can be controlled not only by the Ga content of the alloy nanoparticles 104 but also by the substrate temperature and the supply rates of group III and group V raw materials. Therefore, it is also possible to adjust the change in the Ga molar composition ratio in the nanowire 105 according to the purpose.

[0049] Using alloy fine particles composed of an alloy of In and Ga as a catalyst during the production of nanowires is considered effective not only in reducing the lattice mismatch with Si as described above but also in improving the film quality. When Ga metal fine particles react with a silicon oxide layer, it is known that oxygen is incorporated into the metal fine particles (Non-Patent Document 5). Although it is preferable that the oxygen concentration in the film (layer) of the III-V semiconductor is low, it is not easy to remove oxygen because the bond between Ga and oxygen is strong.

[0050] On the other hand, it is known that the bond between In and oxygen is weaker than that between Ga (reference document). Therefore, in terms of desorbing oxygen from the metal fine particles, it is considered more advantageous to use alloy fine particles of In and Ga as the metal fine particles than to use only Ga metal fine particles.

[0051] In the flowchart shown in FIG. 2, although not essential, in order to increase the thickness of the silicon oxide layer that serves as a mask for selective growth, in step S105, the substrate is once taken out of the apparatus, exposed to the atmosphere, and then re-introduced into the apparatus. As described above, since In is less reactive than Ga, generally, In is less likely to be oxidized than Ga. Therefore, when including the step of exposing the substrate to the atmosphere, it is considered effective to use metal fine particles composed of an alloy of In and Ga.

[0052] According to the above-described embodiment, nanowires can be fabricated without removing the silicon oxide layer. Therefore, nanowires can be fabricated at a lower temperature compared to the conventional method that required removing the silicon oxide layer (silicon oxide film) before fabricating the nanowires. In the above-described embodiment, the case of fabricating a nanowire structure on a Si substrate has been described, but it goes without saying that it is also effective for fabricating a nanowire structure on the Si layer of an Si-based optical device or electronic device.

[0053] In the above-described embodiment, the case where metalorganic molecular beam epitaxy is used as the crystal growth method has been described. However, the production of metal fine particles and nanowires themselves can be carried out using other growth methods such as metalorganic vapor phase epitaxy and molecular beam epitaxy. Therefore, it goes without saying that the nanowires and the method for manufacturing the same according to the embodiment are also effective when other growth methods other than metalorganic molecular beam epitaxy are used.

[0054] Further, in the above-described embodiment, after forming metal fine particles made of an alloy of In and Ga, the thickness of the silicon oxide layer serving as a mask for selective growth is increased by once exposing it to the atmosphere. On the other hand, in the growth of nanowires, selective growth is often possible even when the thickness of the silicon oxide layer is small. Therefore, in the nanowires and the method for manufacturing the same according to the present invention, the step of once exposing to the atmosphere after forming the metal fine particles is not essential.

[0055] Next, an application example of the nanowire to an optical device will be described with reference to FIG. 5. In this optical device, the basic steps regarding the production of the nanowire are not much different from those described above, but the details are different. The production of the optical device will be described below.

[0056] First, a Si substrate 111 having a (111) plane orientation is carried into the introduction chamber of a metalorganic vapor phase epitaxy (MOVPE) apparatus and evacuated. A silicon oxide layer 112 is formed on the surface of the Si substrate 111. After transporting the Si substrate 111 from the transport chamber to the growth chamber, heat treatment is performed at a substrate temperature of 670° C. for 20 minutes. After lowering the substrate temperature to 450° C., TEGa, which is a raw material of Ga, is supplied for 30 seconds to form Ga metal fine particles (not shown) on the silicon oxide layer 112.

[0057] Thereafter, the substrate temperature is raised to 650° C. and heat treatment is performed for 20 minutes to penetrate the silicon oxide layer 112 into the metal fine particles. After lowering the substrate temperature to 360° C., TMIn, which is a raw material of In, is supplied for 10 minutes to make the metal fine particles into alloy fine particles of In and Ga (not shown).

[0058] Furthermore, after reducing the substrate temperature to 350 °C, trimethylindium (TMIn), which is a raw material of In, and tertiary butylphosphine (TBP), which is a raw material of P, are supplied to the surface of the Si substrate 111. By using metal microparticles, which are an alloy of In and Ga, as a catalyst, nanowires 115 made of InGaP are fabricated. The length of the nanowires 115 is approximately 2 μm. At the end of the growth of the nanowires 115, the Ga content in the alloy microparticles approaches 0, so the molar composition ratio of Ga in the nanowires 115 at this point is less than 1%.

[0059] Subsequently, by intermittently supplying tertiary butylarsine (TBA), which is a raw material of As, to the surface of the Si substrate 111, a multiple quantum disk structure 116 is fabricated in which well layers made of InGaAsP with a length (thickness) of approximately 10 nm and barrier layers made of InGaP with a length (thickness) of approximately 20 nm are alternately stacked. In the multiple quantum disk structure 116, the number of well layers is 100. When fabricating this multiple quantum disk structure 116, the Ga content in the alloy microparticles becomes even smaller, so the molar composition ratios of Ga in both the well layers and the barrier layers are less than 1%.

[0060] Subsequently, nanowires 117 made of InGaP with a length of approximately 0.5 μm are fabricated on the multiple quantum disk structure 116. By supplying only TBP to the surface of the Si substrate 111 with the supply of TMIn stopped, the alloy microparticles present at the tip disappear. In this state, the supply amount of TBP is adjusted, and by supplying TMIn, InP is grown on the outer peripheral portions of the nanowires 115, the multiple quantum disk structure 116, and the nanowires 117 to cover the nanowires 115, the multiple quantum disk structure 116, and the nanowires 117 with a cladding layer 118 made of InP.

[0061] As described above, an optical device with a core-shell nanowire structure having the multiple quantum disk structure 116 as a core (active part) is completed. The emission peak wavelength in the photoluminescence measurement of this optical device at room temperature is approximately 1.3 μm, which is a wavelength used in optical communication.

[0062] In and Ga in the alloy fine particles used as a catalyst are incorporated from the alloy fine particles into the nanowire, but the incorporated amount is supplemented by supplying In, and the diameter of the alloy fine particles is adjusted so as not to change significantly. Therefore, as the growth of the nanowire progresses, the composition of Ga in the alloy fine particles decreases, and finally only In metal fine particles are left, and as a result, the nanowire also does not contain Ga.

[0063] For this reason, in the above description, a multiple quantum disk structure using InGaAsP for the well layer and InGaP for the barrier layer has been described. However, even when InAsP or InAs that does not contain Ga is used for the well layer and InP that does not contain Ga is used for the barrier layer, it goes without saying that it is the same as described above.

[0064] As described above, according to the present invention, since a raw material of In is supplied to metal fine particles composed of Ga and used as alloy fine particles composed of an alloy of Ga and In, a nanowire having In and P as constituent elements can be formed on the Si layer.

[0065] Note that the present invention is not limited to the embodiments described above, and it is obvious that many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention.

[0066] [References] B. Brennan et al., "Identification and thermal stability of native oxides on InGaAs using synchrotron radiation based photoemission", Journal of Applied Physics, vol. 108, No. 5, 053516, 2010.

Explanation of symbols

[0067] 101... Si substrate (Si layer), 102... silicon oxide layer, 103... metal fine particles, 104... alloy fine particles, 105... nanowire.

Claims

1. A first step of forming metal fine particles composed of Ga via a silicon oxide layer on an Si layer; A second step of causing the metal fine particles to penetrate the silicon oxide layer by heating and contact the surface of the Si layer; A third step of supplying a raw material of In to make the metal fine particles into alloy fine particles composed of an alloy of Ga and In; A fourth step of supplying a raw material of In and a raw material of P and forming a nanowire having In, Ga, and P as constituent elements using the alloy fine particles as a catalyst A method for manufacturing a nanowire comprising the above steps.

2. In the method for manufacturing a nanowire according to Claim 1, The composition ratio of Ga in the nanowire decreases as the distance from the Si layer increases A method for manufacturing a nanowire, characterized by this.

3. A nanowire having In, Ga, and P as constituent elements formed via a silicon oxide layer on an Si layer, The composition ratio of Ga decreases as the distance from the Si layer increases A nanowire, characterized by this.

4. In the nanowire according to Claim 3, It includes alloy fine particles composed of an alloy of Ga and In formed on the Si layer, The nanowire is characterized by being formed in contact with the alloy fine particles.

5. In the nanowire according to Claim 3 or 4, It has a quantum disk structure composed of a well layer and a barrier layer, The well layer is composed of any one of InGaAsP, InAsP, and InAs, The barrier layer is composed of any one of InGaP and InP A nanowire, characterized by this.

6. In the nanowire according to any one of Claims 3 to 5, The nanowire further includes a coating layer made of InP formed to cover the periphery of the nanowire.

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