Semiconductor substrate, semiconductor device, and method for manufacturing the same

Abstract

This semiconductor substrate (10) includes: a drift layer (11), which is a first layer and formed of a single crystal SiC semiconductor; a buffer layer (12a) and a substrate layer (12b) which are a second layer (12) and formed of a SiC semiconductor including polycrystals on the surface of the first layer, wherein the second layer (12) is formed, through CVD growth, on the surface of the drift layer (11) of the first layer, and the drift layer (11) of the first layer is formed by epitaxial growth. The present invention suppresses the occurrence of defects at a bonding interface of a semiconductor substrate including a single crystal SiC layer and a polycrystalline SiC layer, and also reduces manufacturing costs.

Description

Technical Field

[0001] The present invention relates to a semiconductor substrate and a semiconductor device using SiC, and a method for manufacturing them. The present invention also relates to a polycrystalline silicon carbide substrate, a polycrystalline silicon carbide ingot, a method for manufacturing a polycrystalline silicon carbide substrate, a semiconductor substrate structure, and a power semiconductor device.

Background Art

[0002] Conventionally, devices made of SiC such as Schottky barrier diodes (SBD), MOSFETs, and IGBTs (insulated gate bipolar transistors) have been provided for power control applications. The SiC semiconductor substrate on which such SiC devices are formed may be manufactured by bonding a single-crystalline SiC semiconductor substrate to a polycrystalline SiC semiconductor substrate in order to reduce manufacturing costs and provide desired physical properties.

[0003] Patent Document 1 discloses a technique in which a single-crystalline SiC semiconductor substrate produced by sublimation is attached to a polycrystalline SiC semiconductor substrate produced by chemical vapor deposition (CVD), and an epitaxial layer is grown on the single-crystalline SiC semiconductor substrate by CVD.

[0004] Patent Documents 2 and 3 disclose a technique called remote epitaxy in which a graphene film is formed on a seed single-crystalline SiC semiconductor substrate, a SiC epitaxial layer is grown on the seed single-crystalline SiC semiconductor substrate through the graphene film, only the SiC epitaxial layer is peeled off and transferred, and bonded to a SiC semiconductor substrate at the transfer destination. Since graphene and SiC form a van der Waals bond, the SiC epitaxial layer can be easily peeled off from the seed single-crystalline SiC semiconductor substrate.

[0005] An n-channel IGBT (insulated gate bipolar transistor) made of SiC is provided for power control applications. In an n-channel IGBT, a single-crystalline n-type drift layer is formed on a single-crystalline p-type substrate layer. The p-type substrate layer is required to have high crystal quality for epitaxially growing the n-type drift layer on its surface. As methods for manufacturing a p-type SiC single crystal, a sublimation method and a solution method are known (see Patent Documents 4 and 5).

[0006] FIG. 1 is a flowchart for fabricating a p-type substrate layer by another manufacturing method (Non-Patent Document 1). As shown in FIG. 1(a), an n-type substrate layer 101 is prepared, and an n-type drift layer 102 and a p-type layer 103 are sequentially formed on the n-type substrate layer 101 by CVD (chemical vapor deposition) as shown in FIGS. 1(b) and 1(c). Then, as shown in FIG. 1(d), the stacked n-type substrate layer 101, n-type drift layer 102, and p-type layer 103 are inverted up and down, and a portion from the surface of the n-type substrate layer 101 and the n-type drift layer 102 to a predetermined depth is removed from the upper side. Thereby, a structure for an n-channel IGBT in which an n-type drift layer 102 is stacked on a p-type layer 103 corresponding to the p-type substrate is obtained.

[0007] Patent Document 6 describes a technique for providing a silicon carbide substrate that is a sintered body with a high relative density.

[0008] When using a polycrystalline silicon carbide substrate such as a sintered body in the manufacture of various silicon carbide semiconductor devices, there are advantages such as cost reduction compared to using a single-crystalline silicon carbide substrate. However, when using a silicon carbide substrate in the manufacture of various SiC semiconductor devices, a lower resistivity of the silicon carbide substrate is required.

[0009] To reduce the resistivity of a polycrystalline silicon carbide substrate, a method of doping the silicon carbide substrate with a high concentration of dopant can be considered.

[0010] Patent Document 7 discloses a technique of using a single-crystal substrate made of a single crystal as a substrate for semiconductor devices such as next-generation LED devices, power devices, and high-frequency devices.

Prior Art Documents

Patent Documents

[0011]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Non-Patent Documents

[0012]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0013] In the technology described in Patent Document 1, in order to grow an epitaxial layer on a single-crystalline SiC semiconductor substrate attached to a polycrystalline SiC semiconductor substrate, it was necessary to attach a high-quality single-crystalline SiC semiconductor substrate to the polycrystalline SiC semiconductor substrate without defects. However, the polishing process for ensuring the surface roughness required for attaching a single-crystalline SiC semiconductor substrate to a polycrystalline SiC semiconductor substrate by room-temperature bonding or diffusion bonding was costly, and the yield might decrease due to defects generated at the bonding interface.

[0014] In SiC single crystals produced by the sublimation method or the solution method, due to an increase in the doping amount of impurities required for reducing the resistance of the p-type substrate layer, the mobility decreased and the crystallinity also decreased, making it difficult to grow an epitaxial layer having high crystallinity for the n-type drift layer on the p-type substrate layer. Also, another manufacturing method in which the n-type substrate layer 101, n-type drift layer 102, and p-type layer 103 shown in the flowchart of FIG. 1 are laminated, reversed top and bottom, and a part is removed from the upper side had a complicated manufacturing procedure, low throughput, and high cost.

[0015] For example, when N (nitrogen) is added as a dopant, during the recrystallization process of silicon carbide during sintering, the C (carbon) sites in the single crystal grains are substituted by N, causing lattice constant mismatch and making it likely to generate vacancy defects within the crystal grains. Furthermore, substitution of C sites in the single crystal grains by N may lead to unnecessary microcrystallization or amorphization. Especially when the dopant concentration is increased, these phenomena become prominent and may reduce the density of the entire sintered body.

[0016] When growing an epitaxial growth layer on a single-crystal substrate, the material of the single-crystal substrate is subject to constraints such as having a lattice constant close to that of the epitaxial growth layer and a thermal expansion coefficient close to that of the epitaxial growth layer. Therefore, it was difficult to select a combination of a single-crystal substrate having desired characteristics and an epitaxial growth layer.

[0017] Furthermore, when using a single crystal substrate as a substrate for semiconductor devices, there has been a problem that a single crystal substrate with good crystal quality becomes costly due to complications in the manufacturing method and the like. Also, when using a polycrystalline substrate for cost reduction, there is a risk that recesses exist on the polished surface and the breakdown voltage of the devices formed at locations around the recesses decreases.

[0018] This invention is proposed in view of the above circumstances, and aims to provide a semiconductor substrate including a single crystal SiC semiconductor layer and a polycrystalline SiC semiconductor layer, which suppresses defects generated at the bonding interface and also reduces the manufacturing cost, a semiconductor device manufactured using such a semiconductor substrate, and manufacturing methods thereof.

[0019] Also, a semiconductor substrate in which an n-type SiC semiconductor layer is laminated on a p-type SiC semiconductor layer applicable to an IGBT, including an n-type SiC semiconductor layer having high crystallinity, and aims to provide a semiconductor substrate, a semiconductor device using such a semiconductor substrate, and manufacturing methods thereof, which ensure throughput and reduce costs.

[0020] Furthermore, it aims to provide a polycrystalline silicon carbide substrate having a low resistivity, reducing lattice defects and enhancing mechanical strength, a polycrystalline silicon carbide ingot, a manufacturing method of the polycrystalline silicon carbide substrate, and a power semiconductor device.

[0021] Also, it aims to provide a semiconductor substrate structure and a power semiconductor device including this semiconductor substrate structure, which can achieve cost reduction and improvement in device reliability while obtaining desired physical properties.

Means for Solving the Problems

[0022] In order to solve the above problems, the semiconductor substrate includes a first layer formed of a single crystal SiC semiconductor, and a second layer formed of a SiC semiconductor containing polycrystals on the surface of the first layer, and the second layer is formed on the surface of the first layer by CVD growth.

[0023] The first layer may be formed by epitaxial growth. The surface of the first layer may be the C-plane of the [000-1] orientation or the Si-plane of the

[0001] orientation of 4H-SiC.

[0024] The second layer may be formed of polycrystalline SiC semiconductor. The second layer also includes single-crystalline SiC semiconductor. The second layer may be formed of single-crystalline SiC semiconductor up to a predetermined height from the first layer, and the remainder exceeding the predetermined height from the first layer may be formed of polycrystalline SiC semiconductor.

[0025] The first layer has a thickness of 1 μm or more, the portion up to a predetermined height exceeding the first layer in the second layer has a thickness of 0.1 μm or more, and the remainder exceeding the predetermined height in the second layer may have a thickness of 10 μm or more.

[0026] The first layer and the second layer may be connected without having an interface at the joint surface. The diameter may be 100 mm or more.

[0027] The semiconductor device includes a first layer formed of single-crystalline SiC semiconductor and a second layer formed of SiC semiconductor containing polycrystal on the first layer. The second layer includes a semiconductor substrate formed by CVD growth on the surface of the first layer. The first layer is formed as a drift layer, the portion up to a predetermined height from the first layer in the second layer is formed as a buffer layer, and the remainder exceeding the predetermined height in the second layer is formed as a substrate layer.

[0028] The first layer of the semiconductor substrate may be formed by epitaxial growth. The drift layer may have a thickness of 1 μm or more, the buffer layer may have a thickness of 0.1 μm or more, and the substrate layer may have a thickness of 10 μm or more.

[0029] The second layer of the semiconductor substrate may be formed of polycrystalline SiC semiconductor. The second layer of the semiconductor substrate also includes single-crystalline SiC semiconductor. In the second layer, the buffer layer may be single-crystalline and the substrate layer may be polycrystalline.

[0030] The semiconductor device may include at least one of a Schottky barrier diode, a MOSFET, an IGBT, and an LED. The first layer and the second layer may be connected without having an interface at the bonding surface.

[0031] The method for manufacturing a semiconductor substrate includes a step of epitaxially growing a first layer formed of a single-crystalline SiC semiconductor on the surface of a base single-crystalline substrate, a step of growing a second layer formed of a SiC semiconductor containing polycrystals on the first layer by CVD, and a step of peeling the first layer together with the second layer from above the base single-crystalline substrate.

[0032] In the step of epitaxially growing the first layer, the first layer may be grown on the base single-crystalline substrate by remote epitaxy. The surface of the first layer may be a C plane in the [000-1] orientation or an Si plane in the

[1000] orientation of 4H-SiC.

[0033] In the step of growing the second layer by CVD, a second layer formed of a polycrystalline SiC semiconductor may be formed. In the step of growing the second layer by CVD, the second layer may be formed of a polycrystalline SiC semiconductor by high-speed CVD.

[0034] In the step of growing the second layer by CVD, a portion of the second layer up to a predetermined height from the first layer may be formed of a single-crystalline SiC semiconductor, and the remaining portion of the second layer exceeding the predetermined height from the first layer may be formed of a polycrystalline SiC semiconductor.

[0035] In the step of growing the second layer by CVD, the remaining portion of the second layer exceeding a predetermined height from the first layer may be formed of a polycrystalline SiC semiconductor by high-speed CVD.

[0036] In the step of epitaxially growing the first layer, the first layer may be grown to a thickness of 1 μm or more. In the step of growing the second layer by CVD, the second layer may be grown to a thickness of 0.1 μm or more up to a predetermined height exceeding the first layer, and the remaining portion exceeding the predetermined height may be grown to a thickness of 10 μm or more. The first layer and the second layer may be connected without having an interface at the bonding surface.

[0037] The manufacturing method of a semiconductor device includes a first layer formed of single-crystalline SiC semiconductor and a second layer formed of SiC semiconductor containing polycrystals on the first layer. The second layer includes a step of providing a semiconductor substrate formed by CVD growth on the surface of the first layer, and a step of forming a semiconductor device with the first layer as a drift layer, a buffer layer up to a predetermined height from the first layer in the second layer, and the remaining part exceeding the predetermined height in the second layer as a substrate layer.

[0038] The first layer of the semiconductor substrate may be formed by epitaxial growth. The drift layer may have a thickness of 1 μm or more, the buffer layer may have a thickness of 0.1 μm or more, and the substrate layer may have a thickness of 10 μm or more.

[0039] The second layer of the semiconductor substrate may be formed of polycrystalline SiC semiconductor. The second layer of the semiconductor substrate also includes single-crystalline SiC semiconductor. In the second layer, the buffer layer may be single-crystalline and the substrate layer may be polycrystalline. The semiconductor device may include at least one of a Schottky barrier diode, a MOSFET, an IGBT, and an LED.

[0040] The semiconductor substrate includes a first substrate formed of p-type SiC semiconductor with one surface as a bonding surface, and a second substrate formed of n-type SiC semiconductor with one surface as a bonding surface, and this bonding surface is covered with a thin film of p-type SiC semiconductor. The bonding surface of the first substrate and the bonding surface of the second substrate may be bonded via a thin film covering the bonding surface of the second substrate.

[0041] The thin film may have a film thickness of 1 nm or more. The first substrate may be single-crystalline or polycrystalline. The second substrate may be single-crystalline.

[0042] The semiconductor device may use the above semiconductor substrate. It may include an n-channel IGBT with the first substrate as a p-type substrate layer and the second substrate as an n-type drift layer.

[0043] The second substrate may further include a buffer layer in which the concentration of n-type impurities in the n-type SiC semiconductor is higher than the concentration of n-type impurities in the n-type SiC semiconductor in other portions of the second substrate from a predetermined depth from its bonding surface. The n-channel IGBT may include a trench-type gate.

[0044] A method for manufacturing a semiconductor substrate may include providing a first substrate formed of a p-type SiC semiconductor and having one surface as a bonding surface, providing a second substrate formed of an n-type SiC semiconductor and having one surface as a bonding surface, and the bonding surface being covered with a thin film of a p-type SiC semiconductor, and bonding the bonding surface of the first substrate and the bonding surface of the second substrate via the thin film covering the bonding surface of the second substrate.

[0045] The thin film may have a film thickness of 1 nm or more. The first substrate may be a single crystal. The step of providing the first substrate may further include a step of manufacturing a single crystal p-type SiC semiconductor substrate by an epitaxial method. The epitaxial method may be a remote epitaxial method. The step of providing the first substrate may further include a step of cutting a single crystal ingot to manufacture a single crystal p-type SiC semiconductor substrate.

[0046] The first substrate may be polycrystalline. The step of providing the first substrate may further include a step of manufacturing a polycrystalline p-type SiC semiconductor substrate by CVD growth. The step of providing the first substrate may further include a step of manufacturing a polycrystalline p-type SiC semiconductor substrate by sintering a powder material.

[0047] The second substrate may be a single crystal. The step of providing the second substrate may further include a step of manufacturing a single crystal n-type SiC semiconductor substrate by an epitaxial method. The step of manufacturing the single crystal n-type SiC semiconductor substrate may further include a step of forming a buffer layer in which the concentration of n-type impurities is higher than that in other portions of the main body of the second substrate from a predetermined depth from the bonding surface of the second substrate. The epitaxial method may be a remote epitaxial method. The step of providing the second substrate may further include a step of cutting a single crystal ingot to manufacture a single crystal n-type SiC semiconductor substrate.

[0048] The step of providing the second substrate may further include a step of forming a thin film of single-crystalline n-type SiC semiconductor by an epitaxial method so as to cover the bonding surface of the second substrate.

[0049] The step of bonding the bonding surface of the first substrate and the bonding surface of the second substrate may bond the first substrate and the second substrate by room-temperature bonding. The step of bonding the bonding surface of the first substrate and the bonding surface of the second substrate may bond the first substrate and the second substrate by diffusion bonding.

[0050] The method for manufacturing a semiconductor device may include a step of providing a semiconductor substrate using the method for manufacturing the semiconductor substrate, and a step of manufacturing an n-channel IGBT in which the first substrate of the semiconductor substrate is a p-type substrate layer and the main body of the second substrate is an n-type drift layer.

[0051] The polycrystalline silicon carbide substrate contains at least one of germanium and tin, and may further contain at least one dopant selected from nitrogen, phosphorus, and boron. The size of the crystallites contained in the crystal grains of the polycrystalline silicon carbide may be 100 nm or less. The relative density may be 99% or more.

[0052] A power semiconductor device including the above polycrystalline silicon carbide substrate may be provided. The power semiconductor device may include at least one or a plurality of types selected from the group of SiC Schottky barrier diodes, SiC-MOSFETs, SiC bipolar transistors, SiC diodes, SiC thyristors, or SiC insulated gate bipolar transistors.

[0053] The polycrystalline silicon carbide ingot contains at least one of germanium and tin, and may further contain at least one dopant selected from nitrogen, phosphorus, and boron. The size of the crystallites contained in the crystal grains of the polycrystalline silicon carbide may be 100 nm or less. The relative density may be 99% or more.

[0054] A method for manufacturing a polycrystalline silicon carbide substrate may include a step of preparing a mixed powder by blending at least two types of compounds of both a group-IV / group-V element and a group-III / group-IV element, or either one of the compounds, with silicon carbide powder as a main material, the mixed powder having an average particle size of 100 nm or less; a step of obtaining a polycrystalline silicon carbide ingot by subjecting the mixed powder to spark plasma sintering; and a step of cutting out the polycrystalline silicon carbide ingot to produce a polycrystalline silicon carbide substrate. The compound of the group-IV / group-V element may be at least one or more materials selected from the group consisting of Si 3 N 4 、Ge 3 N 4 、Sn 3 N 4 。The compound of the group-III / group-IV element may be at least one or more materials selected from the group consisting of B 4 C,SiB 4 。

[0055] A semiconductor substrate structure includes a polycrystalline substrate, a first epitaxial growth layer integrated with the polycrystalline substrate, and a second epitaxial growth layer disposed between the polycrystalline substrate and the first epitaxial growth layer and joined to each of the polycrystalline substrate and the first epitaxial growth layer. The first epitaxial growth layer contains a first dopant, and the second epitaxial growth layer contains a second dopant having the same conductivity type as the first dopant. The concentration of the second dopant may be higher than the concentration of the first dopant.

[0056] The second epitaxial growth layer and the polycrystalline substrate may be joined by room-temperature bonding. The second epitaxial growth layer and the first epitaxial growth layer may be joined by room-temperature bonding.

[0057] The concentration of the first dopant in the first epitaxial growth layer is 5×10 14 / cm 3 or more and 2×10 17 / cm3 is less than, and the concentration of the second dopant in the second epitaxial growth layer is 2×10 17 / cm 3 or more and 5×10 18 / cm 3 or less. The thickness of the second epitaxial growth layer may be 0.1 μm or more and 10 μm or less.

[0058] Each of the first epitaxial growth layer and the second epitaxial growth layer may contain at least one or a plurality of types selected from the group consisting of group IV element semiconductors, III-V group compound semiconductors, and II-VI group compound semiconductors. Each of the first epitaxial growth layer and the second epitaxial growth layer may contain at least one or a plurality of types selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0059] The polycrystalline substrate may contain at least one or a plurality of types selected from the group consisting of a sintered body, BN, AlN, Al 2 O 3 、Ga 2 O 3 、diamond, carbon, and graphite. The sintered body may contain at least one or a plurality of types of sintered bodies selected from the group consisting of group IV element semiconductors, III-V group compound semiconductors, and II-VI group compound semiconductors. The sintered body may contain at least one or a plurality of types of sintered bodies selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0060] The polycrystalline substrate may contain a dopant at a concentration of 5×10 18 / cm 3 or more and 2×10 22 / cm 3 or less. The thickness of the polycrystalline substrate may be 100 μm or more and 1000 μm or less. The polycrystalline substrate and the second epitaxial growth layer may form an ohmic contact.

[0061] Each of the first epitaxial growth layer and the second epitaxial growth layer includes an epitaxial growth layer made of 4HSiC, and the epitaxial growth layer made of 4H-SiC may have a surface of the (000-1) plane or the (0001) plane. The diameter of the polycrystalline substrate may be 100 mm or more.

[0062] A power semiconductor device including the above semiconductor substrate structure may be provided. The power semiconductor device may include at least one or a plurality of types selected from the group consisting of a SiC Schottky barrier diode, a SiC-MOSFET, a SiC bipolar transistor, a SiC diode, a SiC thyristor, a SiC insulated gate bipolar transistor, and an LED device.

[0063] The semiconductor device may further include a first metal electrode disposed on the surface of the polycrystalline substrate facing the bonding surface between the polycrystalline substrate and the second epitaxial growth layer. The semiconductor device may further include a second metal electrode disposed on the surface of the first epitaxial growth layer facing the bonding surface between the second epitaxial growth layer and the first epitaxial growth layer. The semiconductor device may include a second metal electrode disposed on the surface of the first epitaxial growth layer facing the bonding surface between the second epitaxial growth layer and the first epitaxial growth layer.

Advantages of the Invention

[0064] According to this invention, since neither room-temperature bonding nor diffusion bonding is required, polishing for ensuring surface roughness becomes unnecessary, and the manufacturing cost is reduced. Further, since there is no bonding interface, defects derived from the bonding interface are suppressed.

[0065] Further, the semiconductor substrate in which an n-type SiC semiconductor layer is laminated on a p-type SiC semiconductor layer so as to be applicable to an IGBT may include an n-type SiC semiconductor layer having high crystallinity. Further, for such a semiconductor substrate, throughput may be ensured and the cost may be reduced.

[0066] Furthermore, there may be provided a polycrystalline silicon carbide substrate having a low resistivity and reduced lattice defects to enhance strength, a polycrystalline silicon carbide ingot, a method for manufacturing the polycrystalline silicon carbide substrate, and a power semiconductor device using the polycrystalline silicon carbide substrate.

[0067] In addition, it may be possible to provide a semiconductor substrate structure and a power semiconductor device including the semiconductor substrate structure, which can achieve cost reduction and improvement in device reliability while obtaining desired physical properties.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0069] (First Embodiment) The semiconductor substrate, semiconductor device, and manufacturing method thereof according to the first embodiment will be described in detail with reference to the drawings. FIG. 2 is a cross-sectional view showing a schematic configuration of the semiconductor substrate according to the first embodiment.

[0070] The semiconductor substrate 10 according to the first embodiment includes a first-layer drift layer 11 that is a single-crystalline SiC semiconductor layer, and a buffer layer 12a and a substrate layer 12b of a second layer 12 that are single-crystalline or polycrystalline SiC semiconductor layers. In the second layer 12, a buffer layer 12a is formed from the surface of the drift layer 11 of the first layer to a predetermined height in the direction of the second layer 12, and the remaining portion exceeding the predetermined height in the second layer 12 forms a substrate layer 12b. In the semiconductor substrate 10 according to the first embodiment, the first-layer drift layer 11 and the buffer layer 12a of the second layer 12 are connected without an interface existing at the bonding surface.

[0071] In the semiconductor substrate 10, the first-layer drift layer 11 may have a thickness of 1 μm or more, the buffer layer 12a of the second layer 12 may have a thickness of 0.1 μm or more, and the substrate layer 12b may have a thickness of 10 μm or more. The semiconductor substrate 10 may have a diameter of 100 mm or more.

[0072] In the semiconductor substrate 10, the first-layer drift layer 11 that is a single-crystalline SiC semiconductor is formed by epitaxial growth using chemical vapor deposition (CVD). The buffer layer 12a of the second layer 12 is a single-crystalline or polycrystalline SiC semiconductor, and the substrate layer 12b is a polycrystalline SiC semiconductor. The buffer layer 12a and the substrate layer 12b of the second layer 12 are formed on the surface of the first-layer drift layer 11 using CVD. The polycrystalline buffer layer 12a and the substrate layer 12b may be formed by high-speed CVD.

[0073] The semiconductor substrate 10 of the first embodiment is configured by forming a buffer layer 12a and a substrate layer 12b of a second layer 12 on an epitaxial layer of a drift layer 11 of a first layer by CVD. Therefore, the joint surface between the drift layer 11 of the first layer and the buffer layer 12a of the second layer 12 is connected without the presence of an interface. Therefore, a high-quality and strong interface strength can be obtained at the joint surface between the first layer and the second layer 12. In addition, it is not necessary to consider defects generated at the joint interface, and the manufacturing yield can be ensured. Furthermore, since the semiconductor substrate 10 is manufactured by CVD of the buffer layer 12a and the substrate layer 12b of the second layer 12 on the drift layer 11 of the first layer, polishing processing required for room temperature bonding and diffusion bonding is not necessary, and the man-hours can be reduced and the cost can be reduced.

[0074] FIG. 3 is a flowchart of a method for manufacturing the semiconductor substrate 10 of the first embodiment. As shown in FIG. 3(a), a single-crystal seed SiC semiconductor substrate 21 that is the basis for epitaxial growth is prepared. In the manufacturing method of the first embodiment, the seed SiC semiconductor substrate 21 is 4H-SiC, and the surface of the seed SiC semiconductor substrate 21 used for epitaxial growth may be either an Si plane with an orientation of

[0001] or a C plane with an orientation of [000-1]. In the first embodiment, remote epitaxy is used for epitaxial growth.

[0075] FIG. 4 is a diagram for explaining the crystal plane of SiC. The Si plane 121 of the SiC wafer 200 on which a primary orifla (orientation flat) 111 and a secondary orifla 112 are formed is shown in the plan view of FIG. 4(a). In the side view seen from the [-1100] orientation of FIG. 4(b), an Si plane 121 with an orientation of

[0001] is formed on the upper surface, and a C plane 1222 with an orientation of [000-1] is formed on the lower surface.

[0076] In FIG. 3(b), using the seed SiC semiconductor substrate 21 of 4H-SiC whose surface prepared in FIG. 3(a) is the Si surface or the C surface, a graphene film 22 is formed so as to cover the surface of the seed SiC semiconductor substrate 21 in order to apply remote epitaxy. The graphene film 22 can be formed using, for example, CVD or the like.

[0077] In FIG. 3(c), a first drift layer 11 is formed on the surface of the seed SiC semiconductor substrate 21 on which the graphene film 22 is formed in FIG. 3(b) through the graphene film 22. The drift layer 11 is formed by epitaxially growing a single crystal on the Si surface or the C surface of the seed SiC semiconductor substrate 21 using CVD.

[0078] Following the formation of the drift layer 11, a second layer 12 is formed on the first drift layer 11 using CVD. In the second layer 12, a single crystal or polycrystalline buffer layer 12a is formed up to a predetermined height from the surface of the drift layer 11, and the remaining portion exceeding the predetermined height from the surface of the drift layer 11 in the second layer 12 forms a polycrystalline substrate layer 12b. The polycrystalline buffer layer 12a and the substrate layer 12b may be formed by high-speed CVD.

[0079] Table 1 describes the growth rate of the SiC layer by each method. According to Table 1, the epitaxial CVD used for the formation of the first drift layer 11 has a low growth rate of 50 μm / h. In contrast, the ultra-high-speed CVD that can be used for the formation of the polycrystalline buffer layer 12a and the substrate layer 12b of the second layer 12 has a high growth rate of 450 to 1700 μm / h. For any CVD method, the gas species are SiCl 4 and CH 4 . Note that Table 1 also describes sublimation growth for comparison, but like epitaxial CVD, the growth rate is low.

[0080]

Table 1

[0081] By using high-speed CVD, the polycrystalline buffer layer 12a and the substrate layer 12b can be formed at a high growth rate. The polycrystalline buffer layer 12a grown by high-speed CVD becomes cubic polycrystals with a high orientation on the Si surface or the C surface of the seed SiC semiconductor substrate 21. When grown at an even higher speed, it becomes polycrystals with a cubic structure or a random orientation.

[0082] In the formation of the first-layer drift layer 11 and the buffer layer 12a and the substrate layer 12b of the second layer 12 by CVD in FIG. 3(c), the epitaxial growth of the first-layer drift layer 11 by CVD and the formation of the buffer layer 12a of the second layer 12 by CVD can be carried out continuously. The first-layer drift layer 11 and the buffer layer 12a of the second layer 12 are connected without forming an interface at the junction surface.

[0083] The formation of the buffer layer 12a and the substrate layer 12b of the second layer 12 from the formation of the first-layer drift layer 11 can be carried out as a series of CVD processes while changing conditions such as the deposition rate and the concentration of additives. For example, the drift layer 11 is formed to a thickness of 7 μm or more by adding a dopant at a carrier concentration Nd of 10 16 / cm 3 , the buffer layer 12a is formed to a thickness of 1 μm by adding a dopant at a carrier concentration Nd of 10 18 / cm 3 , and the substrate layer 12b may be formed to a thickness of 350 μm by adding a dopant at a carrier concentration Nd of 10 19 / cm 3 . The dopant may be an n-type impurity such as nitrogen or phosphorus, or a p-type impurity such as boron or aluminum.

[0084] In FIG. 3(d), the first-layer drift layer 11 formed on the surface of the seed SiC semiconductor substrate 21 and the buffer layer 12a and the substrate layer 12b of the second layer 12 in FIG. 3(c) are peeled off from the surface of the seed SiC semiconductor substrate 21. A graphene film 22 is formed on the surface of the seed SiC semiconductor substrate 21, and the first-layer drift layer 11 and the buffer layer 12a and the substrate layer 12b of the second layer 12 are stacked on the graphene film 22. Since graphene and SiC form a van der Waals bond, the first-layer drift layer 11 and the buffer layer 12a and the substrate layer 12b of the second layer 12 stacked on the seed SiC semiconductor substrate 21 via the graphene film 22 can be easily peeled off from the seed SiC semiconductor substrate 21.

[0085] In FIG. 3(e), the first-layer drift layer 11 and the buffer layer 12a and the substrate layer 12b of the second layer 12 peeled off from the seed SiC semiconductor substrate 21 in FIG. 3(d) are reversed upside down. Due to the upside-down reversal, the lowermost layer becomes the substrate layer 12b, and the buffer layer 12a and the drift layer 11 are sequentially stacked on the substrate layer 12b. Thereby, the semiconductor substrate 10 of the first embodiment having the configuration as shown in FIG. 2 is obtained.

[0086] According to the method for manufacturing a semiconductor substrate of the first embodiment, the first-layer drift layer 11 and the buffer layer 12a and the substrate layer 12b of the second layer 12 are formed using CVD. For this reason, the drift layer 11 and the buffer layer 12a are connected without an interface existing at the bonding surface. Therefore, a high-quality and strong interface strength can be obtained at the bonding surface between the first layer and the second layer 12. Further, it is not necessary to consider defects generated at the bonding interface, and the manufacturing yield can be ensured. In addition, since the first-layer drift layer 11 and the buffer layer 12a and the substrate layer 12b of the second layer 12 are produced by CVD, there is no need for the polishing process required for room-temperature bonding or diffusion bonding, and the man-hours can be reduced and the cost can be reduced.

[0087] In the method for manufacturing a semiconductor substrate according to the first embodiment, a first-layer drift layer 11, a buffer layer 12a of a second layer 12, and a substrate layer 12b are formed on a seed SiC semiconductor substrate 21 via a graphene film 22 according to remote epitaxy. The first-layer drift layer 11, the buffer layer 12a of the second layer 12, and the substrate layer 12b formed via the graphene film 22 can be easily peeled off from the seed SiC semiconductor substrate 21. Therefore, peeling can be surely advanced without damaging or degrading the first-layer drift layer 11, the buffer layer 12a of the second layer 12, and the substrate layer 12b laminated during peeling.

[0088] In the method for manufacturing a semiconductor substrate according to the first embodiment, the buffer layer 12a of the second layer 12 and the substrate layer 12b can be formed in a short time by high-speed CVD. Therefore, the throughput for manufacturing the semiconductor substrate 10 can be increased.

[0089] In the method for manufacturing a semiconductor according to the first embodiment, remote epitaxy is used to form a graphene film 22 on the surface of the seed SiC semiconductor substrate 21 in FIG. 3(b), and peeling is performed at the bonding surface with the graphene film 22 intervening the first-substrate drift layer 11, the buffer layer 12a of the second layer 12, and the substrate layer 12b laminated on the surface of the seed SiC semiconductor substrate 21. However, peeling can also be performed by other methods than remote epitaxy. For example, the first-substrate drift layer, the buffer layer 12a of the second layer 12, and the substrate layer 12b are laminated without forming the graphene film 22 on the surface of the seed SiC semiconductor substrate 21, and the seed SiC semiconductor substrate 21 can be peeled off by polishing or scribing it.

[0090] FIG. 5 is an image obtained by observing a cross-section of the junction surface between the drift layer 11 of the first layer and the buffer layer 12a of the second layer by a transmission electron microscope (TEM) and an energy dispersive X-ray spectrometry (EDX). FIG. 5(a) is a transmission electron microscope image, FIG. 5(b) is an image obtained by K-rays of C, FIG. 5(c) is an image obtained by K-rays of O, and FIG. 5(d) is an image obtained by K-rays of Si. The left side in the figure is the drift layer 11 of the first layer, and the right side in the figure is the buffer layer 12a of the second layer. It can be seen that there is no amorphous interface at the junction surface between the drift layer 11 of the first layer and the buffer layer 12a of the second layer.

[0091] FIG. 6 is a cross-sectional view showing a Schottky barrier diode 30 to which the semiconductor substrate 10 of the first embodiment is applied. This semiconductor substrate 10 is formed as an n-type SiC semiconductor doped with an n-type impurity such as nitrogen or phosphorus in SiC. The carrier concentration Nd of the n-type impurity is set such that the substrate layer 12b has a higher concentration and the drift layer 11 has a lower concentration with respect to the buffer layer 12a.

[0092] In this Schottky barrier diode 30, the drift layer 11 of the first layer of the semiconductor substrate 10 corresponds to an n-type drift layer 31, the buffer layer 12a of the second layer corresponds to an n-type buffer layer 32, and the substrate layer 12b of the second layer corresponds to an n+-type substrate layer 33. The n-type and n+-type of the n-type drift layer 31 and the n+-type substrate layer 33 indicate that the carrier concentration Nd of the n-type impurity is lower and higher, respectively, than that of the n-type buffer layer 32.

[0093] In the Schottky barrier diode 30, a cathode electrode 35, a metal silicide 34, an n+-type substrate layer 33, an n-type buffer layer 32, and an n−-type drift layer 31 are stacked in this order. On the surface of the n−-type drift layer 31, a metal film 39 is formed via an insulating film 37 having an opening, and the metal film 39 forms a Schottky barrier in contact with the n−-type drift layer 31 at the opening of the insulating film 37.

[0094] As shown in FIG. 3, the Schottky barrier diode 30 of the first embodiment uses the semiconductor substrate 10 of the first embodiment in which the drift layer 11 of the first layer, the buffer layer 12a of the second layer 12, and the substrate layer 12b are stacked by CVD. Therefore, the n+-type substrate layer 33 corresponding to the substrate layer 12b, the n-type buffer layer 32 corresponding to the buffer layer 12a, and the n−-type drift layer 31 corresponding to the drift layer 11 of the first layer can be set to have characteristics such as desired crystallinity and resistivity, respectively.

[0095] Note that, in the Schottky barrier diode 30 of FIG. 6, an n-type semiconductor and a metal are in contact with each other, but the present invention is not limited to this. A p-type semiconductor may be used instead of the n-type semiconductor. In this case, in the method for manufacturing the semiconductor substrate shown in FIG. 3, a p-type impurity such as boron or aluminum may be doped.

[0096] FIG. 7 is a cross-sectional view showing a MOSFET 40 to which the semiconductor substrate 10 of the first embodiment is applied. In this MOSFET 40, the drift layer 11 of the first layer of the semiconductor substrate 10 corresponds to an n−-type drift layer 41, the buffer layer 12a of the second layer 12 corresponds to an n-type buffer layer 42, and the substrate layer 12b of the second layer 12 corresponds to an n+-type substrate layer 43. The n−-type and n+-type of the n−-type drift layer 41 and the n+-type substrate layer 43 indicate that the carrier concentration Nd of the n-type impurity is lower and higher than that of the n-type buffer layer 42, respectively.

[0097] In MOSFET 40, a drain electrode 45, a metal silicide 44, an n+-type substrate layer 43, an n-type buffer layer 42, and an n−-type drift layer 41 are stacked in this order. On the surface of the n−-type drift layer 41, a well-shaped p-type channel region 51, an n+-type source region 52, and a p+-type channel connect region 53 are formed. A gate electrode 47 covered with a gate insulating film 48 is disposed so as to straddle the n+-type source region 52 at a portion where the n−-type drift layer 41 reaches the surface, and an interlayer insulating film 49 is stacked so as to cover the n+-type source region 52, the p+-type channel connect region 53, and the gate electrode 47 on the surface of the n−-type drift layer 41.

[0098] As shown in FIG. 3, the MOSFET 40 of the first embodiment forms the drift layer 11 of the first layer and the buffer layer 12a and the substrate layer 12b of the second layer 12 by CVD. Therefore, similar to the Schottky barrier diode 30 shown in FIG. 6, the n+-type substrate layer 43 corresponding to the substrate layer 12b, the n-type buffer layer 42 corresponding to the buffer layer 12a, and the n−-type drift layer 41 corresponding to the drift layer 11 of the first layer can be set to have characteristics such as desired crystallinity and resistivity, respectively.

[0099] The MOSFET 40 of the first embodiment has an n-type buffer layer 42 between the n+-type substrate layer 43 and the n−-type drift layer 41. Similarly, the Schottky barrier diode 30 of the first embodiment also has an n-type buffer layer 32 between the n+-type substrate layer 33 and the n−-type drift layer 31. In a semiconductor device incorporating the MOSFET 40 and the Schottky barrier diode 30, by providing an ohmic junction with an impurity concentration adjusted by CVD and a buffer layer with a high doping concentration, the spread of the depletion layer is adjusted to suppress the growth of basal plane dislocation (BPD) from a line defect to a stacking defect which is a plane defect, and an increase in resistance due to the growth of the stacking defect, and thus an increase in the forward voltage Vf of the body diode can also be suppressed.

[0100] Note that although the MOSFET 40 in FIG. 7 was an n-channel MOSFET, it is not limited to this. In the method for manufacturing a semiconductor substrate shown in FIG. 3, a p-channel MOSFET can also be manufactured using a p-type SiC semiconductor substrate doped with p-type impurities such as boron and aluminum.

[0101] In the first embodiment, the Schottky barrier diode in FIG. 6 and the MOSFET in FIG. 7 are exemplified, but the first embodiment is not limited to this. The semiconductor substrate 10 of the first embodiment can also be applied to other types of devices such as an LED (light emitting diode).

[0102] FIG. 8 is a diagram for explaining a method for manufacturing a semiconductor substrate of a comparative example. In the first comparative example, as shown in FIG. 8(a), a single-crystalline SiC semiconductor substrate 132 formed by sublimation is attached to the surface of a polycrystalline SiC semiconductor substrate 131 formed by CVD using room-temperature bonding or diffusion bonding. Then, as shown in FIG. 8(b), a single-crystalline epitaxial layer 133 is epitaxially grown on the surface of the single-crystalline SiC semiconductor substrate 132 by CVD.

[0103] In the first comparative example, in order to epitaxially grow a single-crystalline epitaxial layer 133 on the single-crystalline SiC semiconductor substrate 132 attached to the surface of the polycrystalline SiC semiconductor substrate 131, it was necessary to attach a high-quality single-crystalline SiC semiconductor substrate 132 to the polycrystalline SiC semiconductor substrate 131 without defects. In addition, a certain cost was required for polishing to ensure the surface roughness necessary for room-temperature bonding and diffusion bonding, and the yield might decrease due to defects generated at the bonding interface between the polycrystalline SiC semiconductor substrate 131 and the single-crystalline SiC semiconductor substrate 132.

[0104] FIG. 9 is a TEM-EDX image obtained by observing the bonding interface of Comparative Example 1 using a transmission electron microscope and energy-dispersive X-ray spectroscopy (TEM-EDX). FIG. 9(a) is a transmission electron microscope image, FIG. 9(b) is an image obtained by K-line of C, FIG. 9(c) is an image obtained by K-line of O, and FIG. 9(d) is an image obtained by K-line of Si. The left side in the figure is the polycrystalline SiC semiconductor substrate 131 formed by CVD, and the right side in the figure is the single-crystalline SiC semiconductor substrate 132 formed by the sublimation method. It can be seen that an amorphous interface exists at the bonding surface between the polycrystalline SiC semiconductor substrate 131 and the single-crystalline SiC semiconductor substrate 132.

[0105] Returning to FIG. 8, in the second comparative example, as shown in FIG. 8(c), an epitaxially grown single-crystalline SiC semiconductor substrate 135 is bonded to the surface of a polycrystalline SiC semiconductor substrate 134 produced by sintering such as spark plasma sintering (SPS) by room-temperature bonding or diffusion bonding. Also in this second comparative example, an amorphous interface exists at the bonding surface between the polycrystalline SiC semiconductor substrate 134 and the single-crystalline SiC semiconductor substrate 135.

[0106] In the second comparative example, since a high-quality single-crystalline SiC semiconductor substrate 135 is directly bonded to a low-quality polycrystalline SiC semiconductor substrate 134, material constraints can be eliminated, enabling cost reduction and acquisition of desired physical properties. On the other hand, a certain cost is required for polishing to ensure the surface roughness necessary for room-temperature bonding and diffusion bonding, and the yield may decrease due to defects generated at the bonding interface between the polycrystalline SiC semiconductor substrate 134 and the single-crystalline SiC semiconductor substrate 135.

[0107] (Second Embodiment) The semiconductor substrate, semiconductor device, and their manufacturing methods according to the second embodiment will be described. FIG. 10 is a flowchart showing the manufacturing method of the semiconductor substrate according to the second embodiment. As shown in FIG. 10(a), a p-type SiC semiconductor substrate 211 is provided, and an n-type SiC semiconductor substrate 212 is provided.

[0108] The p-type SiC semiconductor substrate 211, which is the first substrate, has a predetermined thickness with one surface as the bonding surface, and is a p-type SiC semiconductor doped with p-type impurities such as boron and aluminum in SiC, and may be a single crystal or a polycrystal. The single-crystalline p-type SiC semiconductor substrate 211 may be formed by an epitaxy method in which a single-crystalline epitaxial layer is grown on a base crystal. Also, graphene may be formed on the base substrate, and a remote epitaxy method in which a single-crystalline epitaxial layer is grown through the graphene may be used. In the remote epitaxy method, since SiC and graphene are in van der Waals bonding, the epitaxial layer can be easily removed from the base crystal. Also, the single-crystalline p-type SiC semiconductor substrate 211 may be obtained by cutting a single-crystalline ingot of a p-type SiC semiconductor into a predetermined thickness with a wire saw or the like. The polycrystalline p-type SiC semiconductor substrate 211 may be formed by CVD, or may be formed by sintering from a powder material, for example, by a method such as SPS (spark plasma sintering).

[0109] The n-type SiC semiconductor substrate 212, which is the second substrate, has a predetermined thickness with one surface as the bonding surface, and is formed of a single crystal of an n-type SiC semiconductor doped with n-type impurities such as nitrogen and phosphorus in SiC. The single-crystalline n-type SiC semiconductor substrate 212 may be formed by an epitaxy method. Also, graphene may be formed on the base substrate, and a remote epitaxy method in which a single-crystalline epitaxial layer is grown through the graphene may be used. Also, the single-crystalline n-type SiC semiconductor substrate 212 may be obtained by cutting a single-crystalline ingot of an n-type SiC semiconductor into a predetermined thickness with a wire saw or the like.

[0110] On the n-type SiC semiconductor substrate 212, a thin film 212a of a p-type SiC semiconductor having a predetermined thickness is formed so as to cover the bonding surface of this n-type SiC semiconductor substrate 212. The thin film 212a of the p-type SiC semiconductor may have a thickness of, for example, 10 nm or more. The thin film 212a of the p-type SiC semiconductor may be a single crystal or a polycrystal, similar to the p-type SiC semiconductor substrate 211.

[0111] As shown in FIG. 10(b), an n-type SiC semiconductor substrate 212 is stacked on a p-type SiC semiconductor substrate 211 such that the bonding surface of the p-type SiC semiconductor substrate 211 faces and contacts the bonding surface of the n-type SiC semiconductor substrate 212. Then, the bonding surface of the p-type SiC semiconductor substrate 211 and the bonding surface of the n-type SiC semiconductor substrate 212 are bonded via a thin film 212a of a p-type SiC semiconductor that covers the bonding surface of the n-type SiC semiconductor substrate 212. The bonding between the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 can be performed by several methods such as room temperature bonding and diffusion bonding.

[0112] FIG. 11 is a diagram for explaining the bonding of substrates by room temperature bonding. As shown in FIG. 11(a), a contaminant layer 261 is deposited on the bonding surface of the p-type SiC semiconductor substrate 211, and a contaminant layer 262 is also deposited on the bonding surface of the n-type SiC semiconductor substrate 212. As shown in FIG. 11(b), the bonding surface of the p-type SiC semiconductor substrate 211 on which the contaminant layer 261 is deposited and the bonding surface of the n-type SiC semiconductor substrate 212 on which the contaminant layer 262 is deposited are each irradiated with an ion beam from an ion beam generator 263 and etched. As shown in FIG. 11(c), by the etching, the contaminant layer 261 deposited on the bonding surface of the p-type SiC semiconductor substrate 211 and the contaminant layer 262 deposited on the bonding surface of the n-type SiC semiconductor substrate 212 are each removed, and the bonding surface of the p-type SiC semiconductor substrate 211 and the bonding surface of the n-type SiC semiconductor substrate 212 are cleaned and smoothed at the atomic level. The bonding surface of the p-type SiC semiconductor substrate 211 and the bonding surface of the n-type SiC semiconductor substrate 212 are each activated, and atoms having a bonding hand 211b of p-type SiC are exposed from the bonding surface of the p-type SiC semiconductor substrate 211, and atoms having a bonding hand 212b of p-type SiC of the thin film 212a of the p-type SiC semiconductor that covers the bonding surface of the n-type SiC semiconductor substrate 212 are exposed from the bonding surface of the n-type SiC semiconductor substrate 212. As shown in FIG. 11(d), when the activated bonding surface of the p-type SiC semiconductor substrate 211 and the bonding surface of the n-type SiC semiconductor substrate 212 in FIG. 11(c) are brought into contact at room temperature, the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 are bonded and integrated.

[0113] In the room-temperature bonding as shown in FIG. 11, the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 can be bonded without heating to a high temperature. Therefore, the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 are not deteriorated by heat, and a semiconductor substrate having high crystallinity and low resistivity can be formed.

[0114] FIG. 12 is a micrograph showing the bonded portion of the substrates. In the figure, it can be seen that the left p-type SiC semiconductor substrate 211 and the right n-type SiC semiconductor substrate 212 are bonded via the thin film 212a of the p-type SiC semiconductor in the center. Such a structure of the bonded portion can be obtained in the same manner by bonding using the following other methods.

[0115] FIG. 13 is a diagram for explaining diffusion bonding. The n-type SiC semiconductor substrate 212 is stacked on the p-type SiC semiconductor substrate 211 such that the bonding surface of the n-type SiC semiconductor substrate 212 contacts the bonding surface of the p-type SiC semiconductor substrate 211. The bonding surface of the p-type SiC semiconductor substrate 211 contacts the bonding surface of the n-type SiC semiconductor substrate 212 via the thin film 212a of the p-type SiC semiconductor that covers the bonding surface of the n-type SiC semiconductor substrate 212. The bonding surface of the p-type SiC semiconductor substrate 211 has voids 211d. The p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 stacked in this way are diffusion-bonded by heating and pressurizing them. In the figure, the heating direction is indicated by the arrow TH, and the pressurizing direction is indicated by the arrow P.

[0116] FIG. 14 is a diagram for further explaining diffusion bonding. FIG. 14 shows changes in the vicinity of the interface where the bonding surface of the p-type SiC semiconductor substrate 211 and the bonding surface of the n-type SiC semiconductor substrate 212 are in contact in the diffusion bonding shown in FIG. 13. As shown in FIG. 14(a), the bonding surface of the p-type SiC semiconductor substrate 211 is in contact with the bonding surface of the n-type SiC semiconductor substrate 212 through a thin film 212a of p-type SiC semiconductor that covers the bonding surface of the n-type SiC semiconductor substrate 212. A gap 211d is formed between the bonding surface of the p-type SiC semiconductor substrate 211 and the thin film 212a of p-type SiC semiconductor that covers the bonding surface of the n-type SiC semiconductor substrate 212. As shown in FIG. 14(b), due to heating and pressurization, the gap 211d gradually becomes smaller. As shown in FIG. 14(c), due to atomic diffusion at the interface between the bonding surface of the p-type SiC semiconductor substrate 211 and the thin film 212a of p-type SiC semiconductor that covers the bonding surface of the n-type SiC semiconductor substrate 212, the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 are joined together to form a single body, and the gap 211d also disappears.

[0117] In the diffusion bonding as shown in FIG. 14, the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 are pressurized and heated to diffuse the atoms on the bonding surface for bonding. In diffusion bonding, as the bonding progresses, the gap 211d on the bonding surface disappears, and the bonding surface between the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 is surely bonded by atomic diffusion.

[0118] FIG. 15 is a diagram for explaining diffusion bonding using an insert metal. When using an insert metal, a metal such as Ni or Al is deposited on the bonding surface of the p-type SiC semiconductor substrate 211 or the bonding surface of the n-type SiC semiconductor substrate 212 covered with the thin film 212a of the p-type SiC semiconductor. Then, the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 are heated and pressurized as shown in FIG. 13. As shown in FIG. 15(a), the bonding surface of the p-type SiC semiconductor substrate 211 and the bonding surface of the n-type SiC semiconductor substrate 212 covered with the thin film 212a of the p-type SiC semiconductor are in contact via the layer of the insert metal 225. As shown in FIG. 15(b), due to heating and pressurization, the insert metal 225 fills the reduced void 111d. As shown in FIG. 15(c), the insert metal 225 undergoes atomic diffusion and is absorbed into the thin film 212a of the p-type SiC semiconductor that covers the bonding surface of the p-type SiC semiconductor substrate 211 and the bonding surface of the n-type SiC semiconductor substrate 212, and the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 are bonded together to form an integral body. In such diffusion bonding using an insert metal, when the insert metal 225 is in a solid phase in the state of being heated and pressurized as shown in FIG. 15(b), it is called solid-phase diffusion bonding, and when the insert metal 225 is in a liquid phase, it is called liquid-phase diffusion bonding.

[0119] In the diffusion bonding using an insert metal as shown in FIG. 15, the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 with the insert metal sandwiched between their bonding surfaces are pressurized and heated. After filling the void 211d on the bonding surface with the solid-phase or liquid-phase insert metal, the atoms on the bonding surface are diffused to achieve bonding. According to the diffusion bonding using an insert metal, bonding may be possible even when it is difficult to bond the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 by ordinary diffusion bonding.

[0120] Referring again to FIG. 10, in FIG. 10(c), the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 are joined together to form an integrated single semiconductor substrate 210. In this semiconductor substrate 210, the portion that was the p-type SiC semiconductor substrate 211 constitutes the lower p-type SiC semiconductor layer 221, and the portion that was the n-type SiC semiconductor substrate 212 constitutes the upper n-type SiC semiconductor layer 222. The thin film 212a of the p-type SiC semiconductor that covered the bonding surface of the n-type SiC semiconductor substrate 212 has been absorbed by the lower p-type SiC semiconductor layer 221 that was the p-type SiC semiconductor substrate 211.

[0121] In the second embodiment, the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 are separately prepared and joined to form a single semiconductor substrate 220. In the semiconductor substrate 220, the portion that was the p-type SiC semiconductor substrate 211 constitutes the lower p-type SiC semiconductor layer 221, and the portion that was the n-type SiC semiconductor substrate 212 constitutes the upper n-type SiC semiconductor layer 222. Therefore, the semiconductor substrate 220 can be applied to an n-channel IGBT having the p-type SiC semiconductor layer 221 as a p-type substrate layer and the n-type SiC semiconductor layer 222 as an n-type drift layer.

[0122] Since the semiconductor substrate 220 of the second embodiment is formed by separately preparing and joining the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212, the characteristics such as the desired crystallinity and resistivity of the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212 can be set. For example, the n-type SiC semiconductor substrate 212 can be made to have high crystallinity. Also, since the p-type SiC semiconductor substrate 211 does not need to be a base for growing the n-type SiC semiconductor substrate 212 by the epitaxy method, the crystallinity of the p-type SiC semiconductor substrate 211 may decrease, and the doping amount may be increased to ensure mobility.

[0123] In the second embodiment, since it is sufficient to separately prepare and bond the p-type SiC semiconductor substrate 211 and the n-type SiC semiconductor substrate 212, the manufacturing man-hours are few, the manufacturing throughput is high, the cost is low, and it is suitable for mass production.

[0124] FIG. 16 is a diagram for explaining the terrace processing of the semiconductor substrate 220. FIG. 16(a) shows an end face of the semiconductor substrate 220 manufactured by the series of steps shown in FIG. 10. In the semiconductor substrate 220, the lower p-type SiC semiconductor layer 221 that was the p-type SiC semiconductor substrate 211 and the upper n-type SiC semiconductor layer 222 that was the n-type SiC semiconductor substrate 212 each form edges protruding radially at their respective circumferences.

[0125] In the terrace processing, as shown in FIG. 16(b), a portion from the circumference of the n-type SiC semiconductor layer 222 and the p-type SiC semiconductor layer 221 to a predetermined distance is polished with a grindstone 228 from the upper surface of the n-type SiC semiconductor layer 222 to a depth exceeding the lower surface of the n-type SiC semiconductor layer 222 to chamfer it in the circumferential direction and process it into a terrace-like shape. The grindstone 228 has a shape that can chamfer the upper surface simultaneously with the chamfering of the circumference of the semiconductor substrate 220. Subsequently, as shown in FIG. 16(c), the portion around the circumference is further polished downward with a grindstone to advance the chamfering in the circumferential direction, and at the same time, with another portion of this grindstone, the n-type SiC semiconductor layer 222 is polished downward from the upper surface of the n-type SiC semiconductor layer 222 until it reaches a predetermined thickness to chamfer the upper surface. Finally, as shown in FIG. 16(d), the p-type SiC semiconductor layer 221 is polished upward from the lower surface of the p-type SiC semiconductor layer 221 with another grindstone until it reaches a predetermined thickness to chamfer the lower surface.

[0126] According to the terrace processing shown in FIG. 16, the circumference of the semiconductor substrate 220 is chamfered simultaneously with the chamfering of the upper surface of the semiconductor substrate 220. Therefore, there is no need to provide a separate process for chamfering the circumference, and the chamfering of the circumference of the semiconductor substrate 220 can be surely performed. When the circumference of the semiconductor substrate 220 is chamfered, the edges of the circumference are prevented from cracking and generating dust.

[0127] FIG. 17 is a cross-sectional view showing an n-channel IGBT 230 to which a semiconductor substrate 220 of a second embodiment is applied. In this IGBT 230, a p-type SiC semiconductor layer 221 of the semiconductor substrate 220 constitutes a p+-type substrate layer 231, and an n-type SiC semiconductor layer 222 of the semiconductor substrate 220 constitutes an n--type drift layer 233. Here, p+-type indicates that a p-type impurity with a higher concentration than other p-type regions is doped, and n--type indicates that an n-type impurity with a lower concentration than other n-type regions is doped. The same shall apply hereinafter.

[0128] In the IGBT 230, a drain electrode 235, a metal silicide 234, a p+-type substrate layer 231, and an n--type drift layer 233 are laminated in this order. On the surface of the n--type drift layer 233, a well-shaped p-type channel region 241, an n+-type emitter region 242, and a p+-type channel connect region 243 are formed. A gate electrode 237 covered with a gate insulating film 238 is disposed so as to straddle the n+-type emitter region 242 at a portion where the n--type drift layer 233 reaches the surface, and an interlayer insulating film 239 is laminated so as to cover the n+-type emitter region 242, the p+-type channel connect region 243, and the gate electrode 237 on the surface of the n--type drift layer.

[0129] As shown in FIG. 10, the IGBT 230 of the second embodiment is formed on a semiconductor substrate 220 prepared by separately preparing and joining a p-type SiC semiconductor substrate 211 and an n-type SiC semiconductor substrate 212. Therefore, the p+-type substrate layer 231 corresponding to the p-type SiC semiconductor substrate 211 and the n--type drift layer corresponding to the n-type SiC semiconductor substrate 212 can be set to have characteristics such as desired crystallinity and resistivity, respectively.

[0130] In addition, the semiconductor substrate 220 on which the IGBT 230 of the second embodiment is formed can be manufactured with high throughput and low cost. Therefore, the IGBT 230 formed on such a semiconductor substrate 220 can also be manufactured at low cost.

[0131] FIG. 18 is a cross-sectional view showing the n-channel IGBT 240 of Modification 1. The IGBT 240 of this Modification 1 is different from the IGBT 230 shown in FIG. 17 in that an n+-type buffer layer 232 is added between the p+-type substrate layer 231 and the n−-type drift layer 233. That is, in the IGBT 240 of Modification 1, the drain electrode 235, the metal silicide 234, the p+-type substrate layer 231, the n+-type buffer layer, and the n−-type drift layer 233 are stacked in this order. Regarding other configurations, they are the same as those of the IGBT shown in FIG. 17. Therefore, for common components, the same reference numerals are given and the description is omitted.

[0132] The n+-type buffer layer 232 added in the IGBT 240 of Modification 1 can be manufactured by depositing an epitaxial layer so as to form an n−-layer corresponding to the n−-type drift layer 233 on an n+-type layer corresponding to the n+-type buffer layer 232 when forming the n-type SiC semiconductor substrate 212 by, for example, an epitaxial method. The n-type SiC semiconductor substrate 212 in which such an n+-layer and an n−-layer are stacked constitutes the upper n-type SiC semiconductor layer 222 of the semiconductor substrate 220 joined to the p-type SiC semiconductor substrate 211 as shown in FIG. 10(c), and the n-type SiC semiconductor layer 222 of the semiconductor substrate 220 corresponds to the n+-type buffer layer 232 and the n−-type drift layer 233.

[0133] In the IGBT 240 of Modification 1, the n+-type buffer layer 232 provided under the n−-type drift layer 233 promotes the recombination of holes and electrons, and the number of holes reaching the interface between the n+-type buffer layer 232 and the p+-type substrate layer 231 decreases. As a result, the growth of basal plane dislocation (BPD), which is a line defect to a stacking defect that is a plane defect, due to the recombination energy of holes and electrons at the interface is suppressed. Therefore, an increase in resistance due to the growth of stacking defects, and thus an increase in the forward voltage Vf of the body diode, are also suppressed.

[0134] FIG. 19 is a cross-sectional view showing the n-channel IGBT 250 of Modification 2. The IGBT 250 of this Modification 2 is different from the IGBT shown in FIG. 17 in that the gate electrode 253 has a trench-type structure. For the components common to the IGBT 230 shown in FIG. 17, the same reference numerals are used and the description thereof is omitted.

[0135] In the IGBT 250, a drain electrode 235, a metal silicide 234, a p+-type substrate layer 231, and an n−-type drift layer 233 are laminated in this order. On the upper part of the n−-type drift layer 233, a p base 251 is formed from the surface to a predetermined depth, and an n+-type emitter region 254 and a p+-type channel connect region 255 are formed on the surface of the p base 251. In a portion where the p base 251 is shallower, a trench-type gate electrode 253 covered with a gate insulating film 256 is formed so as to penetrate the n+-type emitter region 254 and the p base 251 from the surface, and a p+-type shielding region 252 is formed directly below the gate electrode 253. An interlayer insulating film 239 is laminated so as to cover the n+-type emitter region 254, the p+-type channel connect region 255, and the gate insulating film 256.

[0136] The IGBT 250 of Modification 2 has a trench-type gate electrode structure. Therefore, the channel density can be improved, and since there is no resistance due to a planar JFET, the on-voltage is reduced.

[0137] FIG. 20 is a flowchart showing a method for manufacturing a semiconductor substrate of Comparative Example 1. Comparative Example 1 is different from the method for manufacturing a semiconductor substrate according to the second embodiment in which a p-type SiC semiconductor substrate and an n-type SiC semiconductor substrate are bonded in that an n-type SiC semiconductor substrate and an n-type SiC semiconductor substrate are bonded. In FIG. 20(a), a first n-type SiC semiconductor substrate 271 having one surface as a bonding surface and a second n-type SiC semiconductor substrate 272 having one surface as a bonding surface are provided. The first n-type SiC semiconductor substrate 271 and the second n-type SiC semiconductor substrate 272 may be single crystals or polycrystals. The single crystal may be an epitaxial crystal or a single crystal ingot cut therefrom. The polycrystal may be formed by CVD or may be a sintered body.

[0138] In FIG. 20(b), the second n-type SiC semiconductor substrate 272 is stacked so that the bonding surface thereof faces and contacts the bonding surface of the first n-type SiC semiconductor substrate 271, and the bonding surface of the first n-type SiC semiconductor substrate 271 and the bonding surface of the second n-type SiC semiconductor substrate 272 are bonded to form an integral substrate. The bonding between the first n-type SiC semiconductor substrate 271 and the second n-type SiC semiconductor substrate 272 may be room temperature bonding or diffusion bonding. The diffusion bonding may be solid-phase diffusion bonding or liquid-phase diffusion bonding via an insert metal. The first n-type SiC semiconductor substrate 271 and the second n-type SiC semiconductor substrate 272 are bonded together to form a single n-type SiC semiconductor substrate 270.

[0139] FIG. 21 is a flowchart showing Comparative Example 2 of the method for manufacturing a semiconductor substrate of Comparative Example 2. Comparative Example 2 is different from the method for manufacturing a semiconductor substrate of the second embodiment in which a thin film of p-type SiC semiconductor covering the bonding surface of the n-type semiconductor substrate was formed, in that a thin film 212a of p-type SiC semiconductor was not formed covering the bonding surface of the n-type SiC semiconductor substrate 212. In FIG. 21(a), a p-type SiC semiconductor substrate 273 having one surface as a bonding surface and an n-type SiC semiconductor substrate 274 having one surface as a bonding surface are provided. The p-type SiC semiconductor substrate 273 may be single crystal or polycrystalline. The n-type SiC semiconductor substrate 274 is single crystal. The single crystal may be an epitaxial crystal or may be a cut piece of a single crystal ingot. The polycrystal may be formed by CVD or may be a sintered body.

[0140] In FIG. 21(b), the bonding surface of the n-type SiC semiconductor substrate 274 is stacked so as to face and contact the bonding surface of the p-type SiC semiconductor substrate 273, and the bonding surface of the p-type SiC semiconductor substrate 273 and the bonding surface of the n-type SiC semiconductor substrate 274 are bonded to form an integrated substrate. The bonding of the p-type SiC semiconductor substrate 273 and the n-type SiC semiconductor substrate 274 may be by room temperature bonding or diffusion bonding. The diffusion bonding may be by solid phase diffusion bonding or liquid phase diffusion bonding via an insert metal. The p-type SiC semiconductor substrate 273 and the n-type SiC semiconductor substrate 274 are bonded together to form a single semiconductor substrate 280. In this semiconductor substrate 280, the portion that was the p-type SiC semiconductor substrate 273 constitutes the lower p-type SiC semiconductor layer 283, and the portion that was the n-type SiC semiconductor substrate 274 constitutes the upper n-type SiC semiconductor layer 282.

[0141] In the semiconductor substrate 280 of Comparative Example 2, defect levels may occur at the bonding interface between the p-type SiC semiconductor layer 283 and the n-type SiC semiconductor layer 282. For this reason, in the semiconductor substrate 280 of Comparative Example 2, leakage current resulting from the defect levels may occur, and the electrical characteristics may deteriorate.

[0142] (Third Embodiment) Next, a third embodiment will be described. In the description of the drawings given below, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationships such as the thickness and planar dimensions of each component are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Also, it goes without saying that there are parts where the relationships and ratios of the dimensions to each other are different even between the drawings.

[0143] Further, the third embodiment shown below exemplifies an apparatus and a method for embodying a technical idea, and does not specify the material, shape, structure, arrangement, etc. of each component. Various modifications can be made to this third embodiment within the scope of the claims.

[0144] (Polycrystalline silicon carbide substrate) The polycrystalline silicon carbide substrate 310 according to the third embodiment contains at least one of germanium (Ge) and tin (Sn), and further contains at least one dopant selected from nitrogen (N), phosphorus (P), and boron (B).

[0145] The relative density of the polycrystalline silicon carbide substrate 310 may be 99% or more.

[0146] When only a dopant is doped into the polycrystalline silicon carbide substrate, during the recrystallization process of silicon carbide during sintering, if the C site in the single crystal grain is replaced by N which is the dopant, or the Si site is replaced by P or B which are the dopants, it is described in "S.A. Reshanov et al, Diamond and Related Materials 10 (2001), 1278 - 1282" that the nearest neighbor bond length of the dopant is shortened and lattice strain occurs.

[0147] Therefore, when these dopants are doped at a high concentration to reduce the resistivity of a polycrystalline silicon carbide substrate, lattice constant mismatch may occur, and vacancy defects may easily occur within crystal grains. Furthermore, there is a risk of unnecessary microcrystallization or amorphization. In particular, when the dopant concentration is increased, these phenomena become prominent and may reduce the density of the entire sintered body.

[0148] On the other hand, the polycrystalline silicon carbide substrate 310 according to the third embodiment is doped with a dopant selected from N, P, and B to reduce the resistivity, and further contains at least one of Ge and Sn.

[0149] As a result, Si sites within a single crystal grain formed during sintering are substituted by Ge or Sn, the nearest neighbor bond length of Ge or Sn increases, and the lattice mismatch within the SiC crystal caused by the addition of the dopant can be reduced. As a result, the density of the entire sintered body increases, and the mechanical strength of the polycrystalline silicon carbide substrate can be improved.

[0150] (Manufacturing process) The polycrystalline silicon carbide substrate 310 according to the third embodiment may be manufactured by a method of pressure sintering or chemical vapor deposition (CVD). Examples of pressure sintering include hot press sintering, hot isostatic pressing, and spark plasma sintering. Spark plasma sintering is preferred because of process stability and the absence of a need for a sintering aid.

[0151] (Polycrystalline silicon carbide substrate 310 by spark plasma sintering method) FIG. 22 is a flowchart showing a manufacturing method in the case of manufacturing a polycrystalline silicon carbide substrate 310 according to the third embodiment by a spark plasma sintering method. FIG. 23 is a schematic bird's-eye view structural diagram showing a manufacturing process of the polycrystalline silicon carbide substrate 310 according to the third embodiment. FIG. 23(a) is a process diagram of preparing a polycrystalline silicon carbide ingot 310A, cutting it out, and polishing it to form a plurality of polycrystalline silicon carbide bare wafers. FIG. 23(b) is a process diagram of removing the cut surface of the polycrystalline silicon carbide bare wafer after machining to form the polycrystalline silicon carbide substrate 310.

[0152] In the manufacturing method of manufacturing a polycrystalline silicon carbide substrate by a spark plasma sintering method, at least two kinds of either one or both of a compound of a Group IV-V Group element and a compound of a Group III-IV Group element are blended with silicon carbide (SiC) powder as the main material. Then, a mixture of silicon carbide powder blended with a compound of a Group IV-V Group element and a compound of a Group III-IV Group element is mixed to prepare a mixed powder having an average particle size of 100 nm or less (step S10).

[0153] Next, the mixed powder is filled into a desired amount and a desired sintering mold (die). Then, the mixed powder filled in the sintering mold is spark plasma sintered to obtain a polycrystalline silicon carbide ingot 310A (step S11).

[0154] Next, the polycrystalline silicon carbide ingot 310A is cut out to create a polycrystalline silicon carbide substrate 310 (step S12).

[0155] The compound of a Group IV-V Group element blended with silicon carbide powder may be at least one or a plurality of materials selected from the group of Si 3 N 4 、Ge 3 N 4 、Sn 3 N 4

[0156] The compound of group III-IV elements incorporated into the silicon carbide powder may be at least one or a plurality of materials selected from the group of B 4 C, SiB 4 and may be any one or more materials selected from the group.

[0157] In addition, in the above manufacturing method, the method of cutting out the polycrystalline silicon carbide substrate 310 after creating the polycrystalline silicon carbide ingot 310A was described. However, the method of creating the wafer is not limited to this. For example, by appropriately selecting the shape of the sintering mold and the amount of mixed powder to be filled during manufacturing, a sintered body can be manufactured in a desired wafer shape.

[0158] The polycrystalline silicon carbide ingot 310A before cutting out the polycrystalline silicon carbide substrate 310 contains at least one of germanium and tin, and further contains at least one dopant selected from nitrogen, phosphorus, and boron.

[0159] The polycrystalline silicon carbide ingot 310A may have a crystallite size of 100 nm or less in the crystal particles of the polycrystalline silicon carbide. Further, its relative density may be 99% or more. Note that the average size of the crystallites in the sintered body is the average size of the crystallites measured by observing the microstructure with SEM, EBSD, or TEM.

[0160] When cutting out the polycrystalline silicon carbide ingot 310A to create the polycrystalline silicon carbide substrate 310, first, as shown in Fig. 23(a), a plurality of silicon carbide bare wafers are cut out from the polycrystalline silicon carbide ingot 310A. Next, the cut surface 310B of the silicon carbide bare wafer is polished by machining such as lapping.

[0161] Next, as shown in FIG. 23(b), a cut surface 310B is removed from the silicon carbide wafer by, for example, about 500 nm or more. As the removal method, for example, Chemical Mechanical Polishing (CMP) technology, plasma etching technology, etc. can be applied. Preferably, it is performed by plasma etching. Since SiC is a very hard material, it takes a relatively long time to remove 500 nm or more by CMP with less damage, but it only takes about 20 minutes by plasma etching. Note that due to the improvement of polishing technology, it has become possible to remove the damaged layer by CMP in about 20 minutes per sheet, and it can be appropriately selected. On the other hand, regarding the cut surface 310B of the silicon carbide wafer, since silicon carbide is very hard, the damage by plasma etching is small. By the above removal process, the damaged layer of the cut surface 310B of the silicon carbide wafer generated by machining after cutting is sufficiently removed, and a polycrystalline silicon carbide substrate 310 having a thickness of, for example, about 200 μm to about 500 μm is obtained.

[0162] The average size of the crystallites contained in the crystal grains of the manufactured polycrystalline silicon carbide substrate 310 may be 100 nm or less. When the average size of the crystallites contained in the crystal grains of the polycrystalline silicon carbide substrate 310 is 100 nm or less, it is possible to effectively suppress the coarsening of the crystal structure and the decrease in the relative density of the sintered body during the process of creating the sintered body by the spark plasma sintering method.

[0163] The concentration of Ge contained in the manufactured polycrystalline silicon carbide substrate 310 may be more than 0 ppm and 1000 ppm or less. Since the polycrystalline silicon carbide substrate 310 manufactured by SPS can easily control the composition of the mixed powder, the dopant can be easily doped at a high concentration.

[0164] (Manufacturing apparatus for silicon carbide sintered body using spark plasma sintering) FIG. 24 is a schematic diagram of a manufacturing apparatus 450 for manufacturing a polycrystalline (silicon carbide sintered body) that forms a polycrystalline silicon carbide substrate 310 according to the third embodiment.

[0165] The above polycrystalline silicon carbide ingot 310A or polycrystalline silicon carbide wafer is manufactured by the silicon carbide sintered body manufacturing apparatus 450 shown in FIG. 24. The inside 450A of the silicon carbide sintered body manufacturing apparatus 450 is in a vacuum atmosphere of about several Pa or replaced with Ar / N 2 gas.

[0166] The polycrystalline (SiC sintered body) manufacturing apparatus 450 employs a solid compression sintering method by spark plasma sintering (SPS). A graphite (carbon) sintering mold (graphite die) 490 filled with a powder or solid SiC polycrystalline material 494 is pressurized and energized by a DC pulse power supply 452 and further heated. A thermocouple or radiation thermometer 492 is housed in the graphite die 490.

[0167] The graphite die 490 is connected to the pressure shafts 460A and 460B via graphite punches 480A and 480B and graphite spacers 470A and 470B. The DC pulse power supply 452 is further connected to the pressure shafts 460A and 460B. By applying a voltage between the pressure shafts 460A and 460B while pressurizing, the SiC polycrystalline material 494 is energized, pressurized, and heated. The heating temperature is, for example, about 1800°C to 2000°C, the pressurizing pressure P is, for example, up to about 100 MPa, and the pulse voltage of the DC pulse is, for example, about 5 to 10 V.

[0168] When manufacturing a polycrystalline (silicon carbide sintered body) that forms the polycrystalline silicon carbide substrate 310 according to the third embodiment by SPS, a polycrystalline sintered body can be formed at a relatively low temperature and in a short time.

[0169] In addition, since the polycrystalline silicon carbide substrate 310 according to the third embodiment contains at least one of germanium and tin, the occurrence of crystallization, amorphization, and crystal defects that affect strength is suppressed. Therefore, even when a temperature around 2000 °C is maintained for a certain period of time to form a SiC polycrystal, the density of the entire sintered body can be increased, and it is possible to effectively suppress the formation of a microstructure that is prone to grain boundary slip due to excessive grain growth or the like and causes a decrease in strength.

[0170] In addition, when manufacturing a polycrystal (silicon carbide sintered body) that forms the polycrystalline silicon carbide substrate 310 according to the third embodiment by SPS, the occurrence of defects inside the crystal grains can be reduced while doping the dopant at a high concentration. As a result, the generation of intragranular pores is suppressed, the amorphous layer and pores at the grain boundaries are also reduced, the change in the crystal state due to high-temperature treatment becomes small, and the internal stress generated at that time can also be reduced. As a result, the heat resistance is improved. In addition, in order to optimize the amount of impurities to be introduced together with the sintering conditions, the change in physical properties in the high-temperature region caused by the solid solution of excess impurity elements can be minimized.

[0171] In addition, when manufacturing a polycrystal (silicon carbide sintered body) that forms the polycrystalline silicon carbide substrate 310 according to the third embodiment by SPS, high-concentration doping such as dopants can be easily performed without degrading other performances. As a result, a low resistance close to the theoretical value can be obtained.

[0172] In addition, when manufacturing a polycrystal (silicon carbide sintered body) that forms the polycrystalline silicon carbide substrate 310 according to the third embodiment by SPS, the throughput is significantly higher than that of silicon carbide crystal bulk growth by the sublimation method or the solution method. Even if the material utilization efficiency by processing is the same, the impact on cost is small. In addition, the effect of reducing fixed costs due to capital investment in equipment and space saving in the manufacturing area is also high. In addition, since the activation treatment of impurities doped at a high concentration during sintering can be performed simultaneously, the effect of cost reduction due to process simplification can also be obtained.

[0173] In addition, when manufacturing the polycrystalline silicon carbide substrate 310 according to the third embodiment using a polycrystal (silicon carbide sintered body), the generation of vacancy defects within the crystal grains is suppressed, an appropriate crystallite size can be obtained, and unnecessary amorphous layers and vacancy defects existing at grain boundaries are also suppressed. Therefore, a surface state that can be easily smoothed by polishing can be provided.

[0174] (Polycrystalline silicon carbide substrate 310 manufactured by CVD) The polycrystalline silicon carbide substrate 310 according to the third embodiment may be manufactured by CVD. For example, it may be manufactured by planar batch type low-pressure CVD.

[0175] As the raw materials for the polycrystalline silicon carbide substrate 310 manufactured by CVD, for example, SiCL is used as the Si-based gas 4 , and C is used as the C-based gas 3 F 8 is supplied. Also, N is used as the dopant, Ge is used as the additive element, and NH is used as the N-based gas of the raw materials 3 or N 2 , and GeH is used as the Ge-based gas 4 is supplied. Each gas is diluted with H 2 gas and supplied into the reaction furnace. A growth rate of 500 μm or more per hour in the thickness direction can be obtained with dense 3C-type polycrystalline SiC.

[0176] The growth temperature is carried out in the range of 1300 °C or higher and 1600 °C or lower. For example, a range of about 1400 °C or higher and 1500 °C or lower was appropriate.

[0177] The obtained polycrystalline silicon carbide ingot 310A has a bulk crystal length of about 30 mm.

[0178] Note that the process of cutting the polycrystalline silicon carbide ingot 310A into the polycrystalline silicon carbide substrate 310 is the same as in the case of SPS.

[0179] When manufacturing by CVD, the polycrystalline silicon carbide substrate 310 can easily increase the relative density of the substrate because voids are difficult to form in the substrate. Note that the relative density of the polycrystalline silicon carbide substrate 310 may be 99% or more.

[0180] (SiC Semiconductor Device Using Polycrystalline Silicon Carbide Substrate) The polycrystalline silicon carbide substrate 310 according to the above-described third embodiment can be used, for example, in the manufacture of various SiC semiconductor devices. Hereinafter, as an example thereof, examples of a SiC Schottky Barrier Diode (SBD), a SiC Trench (T)-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and a SiC planar gate type MOSFET will be shown.

[0181] FIG. 25(a) is a schematic bird's-eye view configuration diagram of a semiconductor substrate structure 301 using the polycrystalline silicon carbide substrate 310 according to the third embodiment. FIG. 25(b) is a schematic cross-sectional structure diagram of the semiconductor substrate structure 301 shown in FIG. 25(a).

[0182] To use the polycrystalline silicon carbide substrate 310 according to the third embodiment in the manufacture of various SiC semiconductor devices, first, the semiconductor substrate structure 301 shown in FIG. 25 is created, and the created semiconductor substrate structure 301 can be used in the manufacture of various SiC semiconductor devices.

[0183] As shown in FIG. 25, the schematic bird's-eye view configuration of the semiconductor substrate structure (wafer) 301 using the polycrystalline silicon carbide substrate 310 according to the third embodiment includes a polycrystalline silicon carbide substrate 310, a buffer layer 313 joined to the substrate 310, and an epitaxial growth layer 312 joined to the buffer layer 313. Each of the substrate 310 and the buffer layer 313, and the buffer layer 313 and the epitaxial growth layer 312 are joined by room-temperature bonding. Here, the room-temperature bonding includes at least one or a plurality of types selected from surface-activated bonding, plasma-activated bonding, and atomic diffusion bonding.

[0184] Note that the polycrystalline silicon carbide substrate 310 and the buffer layer 313, and the buffer layer 313 and the epitaxial growth layer 312 may be joined by diffusion bonding.

[0185] When using room-temperature bonding, the surface roughness Ra of the substrate surface is set to about 1 nm or less. As a result, the thickness of the bonding interface layer 314 with different compositions is about 1 nm to 10 nm.

[0186] When using diffusion bonding, the surface roughness of the substrate surface may be rough depending on the material and the bonding temperature. In order to utilize atomic diffusion, the thickness of the bonding interface layer 314 with different composition gradients due to atomic diffusion is about 1 nm to 10 μm.

[0187] The epitaxial growth layer 312 may include at least one or a plurality of types selected from the group of group-IV element semiconductors, III-V group compound semiconductors, and II-VI group compound semiconductors.

[0188] The epitaxial growth layer 312 may include at least one or a plurality of types selected from the group of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0189] In addition, when the epitaxial growth layer 312 includes silicon carbide, the silicon carbide may be composed of any one of 4H-SiC, 6H-SiC, 2H-SiC, or 3C-SiC materials.

[0190] The buffer layer 313 may include at least one or a plurality of types selected from the same group as the epitaxial growth layer 312. However, if the epitaxial growth layer 312 has the same conductivity type, it may contain the same type of dopant or different types of dopants.

[0191] The concentration of the first dopant in the epitaxial growth layer 312 is 5×10 14 / cm 3 or more and less than 2×10 17 / cm 3 and the concentration of the second dopant in the buffer layer 313 may be 2×10 17 / cm 3 or more and 5×10 18 / cm 3 or less.

[0192] The thickness of the polycrystalline silicon carbide substrate 310 is, for example, about 200 μm to about 500 μm, the thickness of the SiC epitaxial growth layer 312 is, for example, about 4 μm to about 100 μm, and the thickness of the SiC buffer layer 313 may be, for example, about 0.5 μm to about 1 μm.

[0193] (SiC Epitaxial Wafer) When the epitaxial growth layer 312 and the buffer layer 313 are formed of silicon carbide, the epitaxial growth layer (SiC epitaxial growth layer) 312 and the buffer layer (SiC buffer layer) 313 may be made of, for example, 4H-SiC epitaxially grown by CVD and may have an off-angle of less than 4 degrees. Specifically, the SiC epitaxial growth layer 312 and the SiC buffer layer 313 may be SiC single crystal epitaxial wafers manufactured by so-called remote epitaxy obtained by epitaxially growing on a graphene layer formed on a SiC single crystal substrate and peeling them off from the graphene layer.

[0194] (SiC-SBD) The SiC-SBD 321 fabricated from the semiconductor substrate structure 301 manufactured using the polycrystalline silicon carbide substrate 310 according to the third embodiment includes a semiconductor substrate structure 301 composed of a polycrystalline silicon carbide substrate 310, a SiC epitaxial growth layer 312, and a buffer layer 313, as shown in FIG. 26. The polycrystalline silicon carbide substrate 310 and the buffer layer 313, and the buffer layer 313 and the SiC epitaxial growth layer 312 are joined by room temperature bonding. Note that a bonding interface layer 314 may be interposed between the polycrystalline silicon carbide substrate 310 and the buffer layer 313, or between the buffer layer 313 and the SiC epitaxial growth layer 312.

[0195] The polycrystalline silicon carbide substrate 310 and the buffer layer 313 are doped with n+ type (the impurity density is, for example, about 1×10 18 cm -3 ~about 1×10 21 cm -3 ), and the SiC epitaxial growth layer 312 is doped with n- type (the impurity density is, for example, about 5×10 14 cm -3 ~about 5×10 16 cm -3 ).

[0196] Further, the SiC epitaxial growth layer 312 may be composed of any one of 4H-SiC, 6H-SiC, 2H-SiC, or 3C-SiC.

[0197] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), etc. can be applied.

[0198] As the p-type doping impurity, for example, B (boron), Al (aluminum), etc. can be applied.

[0199] The back surface of the polycrystalline silicon carbide substrate 310 is provided with a cathode electrode 322 so as to cover the entire area thereof, and the cathode electrode 322 is connected to a cathode terminal K.

[0200] Further, the surface 300 (for example, (0001) plane (Si plane)) of the SiC epitaxial growth layer 312 is provided with a contact hole 324 that exposes a part of the SiC epitaxial growth layer 312 as an active region 323, and a field insulating film 326 is formed in a field region 325 surrounding the active region 23.

[0201] The field insulating film 326 is made of SiO 2 (silicon oxide), but may be made of other insulators such as silicon nitride (SiN). An anode electrode 327 is formed on the field insulating film 326, and the anode electrode 327 is connected to an anode terminal A.

[0202] A p-type JTE (Junction Termination Extension) structure 328 is formed near the surface 300 (surface layer portion) of the SiC epitaxial growth layer 312 so as to be in contact with the anode electrode 327. The JTE structure 328 is formed along the contour of the contact hole 324 so as to straddle inside and outside the contact hole 324 of the field insulating film 326.

[0203] (SiC-TMOSFET) The trench gate type MOSFET 331 fabricated from the semiconductor substrate structure 301 manufactured using the polycrystalline silicon carbide substrate 310 according to the third embodiment includes a semiconductor substrate structure 301 composed of a polycrystalline silicon carbide substrate 310, a SiC epitaxial growth layer 312, and a buffer layer 313, as shown in FIG. 27. The polycrystalline silicon carbide substrate 310 and the buffer layer 313, and the buffer layer 313 and the SiC epitaxial growth layer 312 are joined by room temperature joining. Note that a joining interface layer 314 may be interposed between the polycrystalline silicon carbide substrate 310 and the buffer layer 313, or between the buffer layer 313 and the SiC epitaxial growth layer 312.

[0204] The polycrystalline silicon carbide substrate 310 and the buffer layer 313 are doped to n+ type (impurity density is, for example, about 1×10 18 cm -3 ~ about 1×10 21 cm -3 ), and the SiC epitaxial growth layer 312 is doped to n- type (impurity density is, for example, about 5×10 14 cm -3 ~ about 5×10 16 cm -3 ).

[0205] In addition, the SiC epitaxial growth layer 312 may be made of any of the materials of 4H-SiC, 6H-SiC, 2H-SiC, or 3C-SiC.

[0206] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), etc. can be applied.

[0207] As the p-type doping impurity, for example, B (boron), Al (aluminum), etc. can be applied.

[0208] The back surface ((000-1) plane, C plane) of the polycrystalline silicon carbide substrate 310 is provided with a drain electrode 332 so as to cover the entire area, and the drain electrode 332 is connected to a drain terminal D.

[0209] In the vicinity (surface layer part) of the surface 300 ((0001) plane, Si plane) of the SiC epitaxial growth layer 312, a body region 333 of p-type (impurity density is, for example, about 1×10 16 cm -3 ~about 1×10 19 cm -3 ) is formed. In the SiC epitaxial growth layer 312, the part on the side of the polycrystalline silicon carbide substrate 310 with respect to the body region 333 is an n-type drain region 334 (312) in which the state of the SiC epitaxial growth layer is maintained.

[0210] A gate trench 335 is formed in the SiC epitaxial growth layer 312. The gate trench 335 penetrates the body region 333 from the surface 300 of the SiC epitaxial growth layer 312, and its deepest part reaches the drain region 334.

[0211] A gate insulating film 336 is formed on the inner surface of the gate trench 335 and the surface 300 of the SiC epitaxial growth layer 312 so as to cover the entire inner surface of the gate trench 335. Then, by filling the inside of the gate insulating film 336 with, for example, polysilicon, a gate electrode 337 is embedded in the gate trench 335. A gate terminal G is connected to the gate electrode 337.

[0212] An n+-type source region 338 that forms a part of the side surface of the gate trench 335 is formed in the surface layer part of the body region 333.

[0213] Also, in the SiC epitaxial growth layer 312, a p+-type (impurity density is, for example, about 1×10 18 cm -3 ~about 1×10 21 cm -3 ) body contact region 339 is formed, which penetrates the source region 338 from the surface 300 and is connected to the body region 333.

[0214] On the SiC epitaxial growth layer 312, SiO2 An interlayer insulating film 340 consisting of [material] is formed. Through a contact hole 341 formed in the interlayer insulating film 340, a source electrode 342 is connected to a source region 338 and a body contact region 339. A source terminal S is connected to the source electrode 342.

[0215] With a predetermined potential difference generated between the source electrode 342 and the drain electrode 332 (between source and drain), by applying a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) to the gate electrode 337, a channel can be formed in the vicinity of the interface with the gate insulating film 336 in the body region 333 due to the electric field from the gate electrode 337. As a result, a current can flow between the source electrode 342 and the drain electrode 332, and the SiC-TMOSFET 331 can be turned on.

[0216] (SiC planar gate type MOSFET) The planar gate type MOSFET 351 fabricated from a semiconductor substrate structure 301 manufactured using a polycrystalline silicon carbide substrate 310 according to the third embodiment, as shown in FIG. 28, includes a semiconductor substrate structure 301 composed of a polycrystalline silicon carbide substrate 310, a SiC epitaxial growth layer 312, and a buffer layer 313. The polycrystalline silicon carbide substrate 310 and the buffer layer 313, and the buffer layer 313 and the SiC epitaxial growth layer 312 are joined by room temperature bonding. Note that a bonding interface layer 314 may be interposed between the polycrystalline silicon carbide substrate 310 and the buffer layer 313, or between the buffer layer 313 and the SiC epitaxial growth layer 312.

[0217] The polycrystalline silicon carbide substrate 310 and the buffer layer 313 are doped to be n+ type (the impurity density is, for example, about 1×10 18 cm -3 ~about 1×10 21 cm -3 ), and the SiC epitaxial growth layer 312 is n- type (the impurity density is, for example, about 5×10 14 cm -3 It should be noted that the [material] in the translation of needs to be filled in according to the actual content in the original text. Also, the specific doping density values in the translation of - are filled in according to the original text's format, but the specific numbers should be determined based on the complete original text information.~ about 5×10 16 cm -3 ) is doped.

[0218] Further, the SiC epitaxial growth layer 312 may be composed of any one of materials such as 4H-SiC, 6H-SiC, 2H-SiC, or 3C-SiC.

[0219] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), etc. can be applied.

[0220] As the p-type doping impurity, for example, B (boron), etc. can be applied.

[0221] On the back surface ((000-1) plane) of the polycrystalline silicon carbide substrate 310, a drain electrode 352 is formed so as to cover the entire area, and a drain terminal D is connected to the drain electrode 352.

[0222] Near the surface 300 ((0001) plane) (surface layer portion) of the SiC epitaxial growth layer 312, a p-type (impurity density is, for example, about 1×10 16 cm -3 ~ about 1×10 19 cm -3 ) body region 353 is formed in a well shape. In the SiC epitaxial growth layer 312, the portion on the SiC substrate 310 side with respect to the body region 353 is an n-type drain region 354 (312) that maintains the state as it is after epitaxial growth.

[0223] An n+-type source region 355 is formed in the surface layer portion of the body region 353 at a distance from the periphery of the body region 353.

[0224] Inside the source region 355, a p+-type (impurity density is, for example, about 1×10 18 cm -3 ~ about 1×10 21 cm -3) A body contact region 356 is formed. The body contact region 356 penetrates the source region 355 in the depth direction and is connected to the body region 353.

[0225] A gate insulating film 357 is formed on the surface 300 of the SiC epitaxial growth layer 312. The gate insulating film 357 covers a portion of the body region 353 that surrounds the source region 355 (the peripheral portion of the body region 353) and the outer peripheral edge of the source region 355.

[0226] A gate electrode 358 made of, for example, polysilicon is formed on the gate insulating film 357. The gate electrode 358 faces the peripheral portion of the body region 353 with the gate insulating film 357 interposed therebetween. A gate terminal G is connected to the gate electrode 358.

[0227] An interlayer insulating film 359 made of SiO 2 is formed on the SiC epitaxial growth layer 312. Through a contact hole 360 formed in the interlayer insulating film 359, a source electrode 61 is connected to the source region 355 and the body contact region 356. A source terminal S is connected to the source electrode 361.

[0228] With a predetermined potential difference generated between the source electrode 361 and the drain electrode 352 (between source and drain), by applying a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) to the gate electrode 358, a channel can be formed in the vicinity of the interface between the body region 353 and the gate insulating film 357 due to the electric field from the gate electrode 358. As a result, a current can flow between the source electrode 361 and the drain electrode 352, and the planar gate type MOSFET 351 can be turned on.

[0229] Although the third embodiment has been described above, it can also be implemented in other forms.

[0230] For example, although illustration is omitted, a power semiconductor device can also be manufactured using a semiconductor substrate structure 301 manufactured using a polycrystalline silicon carbide substrate 310 according to the third embodiment. Specifically, a vertical device structure using the semiconductor substrate structure 301 can also be manufactured. That is, a polycrystalline silicon carbide substrate 310, an epitaxial growth layer 312 integrated with the polycrystalline silicon carbide substrate 310, and a buffer layer 313 disposed between the polycrystalline silicon carbide substrate 310 and the epitaxial growth layer 312 and joined to each of the polycrystalline silicon carbide substrate 310 and the epitaxial growth layer 312. The epitaxial growth layer 312 contains a first dopant, the buffer layer 313 contains a second dopant having the same conductivity type as the first dopant, and the concentration of the second dopant contained in the buffer layer 313 is higher than the dopant concentration contained in the epitaxial growth layer 312. A vertical power semiconductor device including a first metal electrode disposed on the substrate surface of the semiconductor substrate structure 301 facing the bonding surface between the polycrystalline silicon carbide substrate 310 and the buffer layer 313 may be formed.

[0231] Further, a vertical power semiconductor device further including a second metal electrode disposed on the surface of the epitaxial growth layer 312 facing the bonding surface between the buffer layer 313 and the epitaxial growth layer 312 may be formed.

[0232] Further, for example, a lateral device structure can also be manufactured using the semiconductor substrate structure 301 manufactured using the polycrystalline silicon carbide substrate 310 according to the third embodiment. That is, a polycrystalline silicon carbide substrate 310, an epitaxial growth layer 312 integrated with the polycrystalline silicon carbide substrate 310, and a buffer layer 313 disposed between the polycrystalline silicon carbide substrate 310 and the epitaxial growth layer 312 and joined to each of the polycrystalline silicon carbide substrate 310 and the epitaxial growth layer 312. The epitaxial growth layer 312 contains a first dopant, the buffer layer 313 contains a second dopant having the same conductivity type as the first dopant, and the concentration of the second dopant contained in the buffer layer 313 is higher than the dopant concentration contained in the epitaxial growth layer 312. A lateral power semiconductor device including a second metal electrode disposed on the surface of the epitaxial growth layer 312 facing the bonding surface between the buffer layer 313 and the epitaxial growth layer 312 of the semiconductor substrate structure 301 may be formed.

[0233] In the vertical or lateral power semiconductor device described above, an example in which the epitaxial growth layer 312 and the buffer layer 313 are silicon carbide has been shown, but the epitaxial growth layer 312 and the buffer layer 313 are not limited thereto. For example, each of the epitaxial growth layer 312 and the buffer layer 313 may include at least one or a plurality of types selected from the group consisting of group IV element semiconductors, III-V group compound semiconductors, and II-VI group compound semiconductors. Further, each of the epitaxial growth layer 312 and the buffer layer 313 may include at least one or a plurality of types selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0234] Further, for example, although illustration is omitted, a MOS capacitor can also be manufactured using the semiconductor substrate structure 301 manufactured using the polycrystalline silicon carbide substrate 310 according to the third embodiment. In the MOS capacitor, the yield and reliability can be improved.

[0235] Although not shown, a bipolar transistor can also be manufactured using a semiconductor substrate structure 301 manufactured using a polycrystalline silicon carbide substrate 310 according to the third embodiment. In addition, the semiconductor substrate structure 1 according to the third embodiment can also be used for manufacturing SiC-pn diodes, SiC insulated gate bipolar transistors (IGBTs), SiC complementary MOSFETs, and the like.

[0236] A power semiconductor device including a semiconductor substrate structure 301 manufactured using a polycrystalline silicon carbide substrate 310 according to the third embodiment may include any one of SiC-based, Si-based, GaN-based, AlN-based, and gallium oxide-based IGBTs, diodes, MOSFETs, thyristors, and LED devices.

[0237] A power semiconductor device including a semiconductor substrate structure 301 manufactured using a polycrystalline silicon carbide substrate 310 according to the third embodiment may have a configuration of any one of a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module.

[0238] According to the third embodiment, a semiconductor substrate structure having a stable interface structure even at high temperatures and a power semiconductor device including this semiconductor substrate structure can be provided.

[0239] According to the third embodiment, it is possible to eliminate material constraints and provide a semiconductor substrate structure capable of reducing costs and obtaining desired physical properties, and a power semiconductor device including this semiconductor substrate structure.

[0240] According to the semiconductor substrate structure according to the third embodiment, instead of forming a SiC epitaxial growth layer on a SiC single crystal substrate, any substrate and a SiC epitaxial growth layer are bonded and joined using room temperature bonding technology, so that the range of combinations of the epitaxial growth layer and the substrate can be expanded.

[0241] According to the semiconductor substrate structure according to the third embodiment, as the substrate material, for example, a low-cost SiC polycrystalline substrate or a carbon substrate can be used instead of a high-cost SiC single crystal substrate.

[0242] Further, according to the semiconductor substrate structure according to the third embodiment, since a combination of a substrate having desired characteristics and a SiC epitaxial growth layer is possible, the characteristics of the power semiconductor device can be improved. Specifically, since the thermal expansion coefficient, the thermal conductivity, the electrical conductivity, and the mechanical properties can be set to a desired combination, the switching characteristics, the heat resistance, and the mechanical reliability of the power semiconductor device can be improved.

[0243] Further, according to the semiconductor substrate structure according to the third embodiment and the power semiconductor device including this semiconductor substrate structure, any substrate and the completed SiC epitaxial growth layer are bonded and joined using room temperature bonding technology or diffusion bonding technology, so that the period of the process can be shortened. Further, since any substrate and the completed SiC epitaxial growth layer can be combined, the manufacturing yield can be improved.

[0244] Further, according to the semiconductor substrate structure according to the third embodiment and the power semiconductor device including this semiconductor substrate structure, since a SiC buffer layer having a higher dopant concentration than the SiC epitaxial growth layer is provided, the breakdown voltage of the semiconductor substrate structure can be improved. Thereby, when this semiconductor substrate structure is applied to a device, the reliability of the device can be improved.

[0245] [Implementation of Other Forms] As described above, several forms of implementation have been described, but the discussions and drawings that form part of the disclosure are exemplary and should not be construed as limiting. Various alternative forms of implementation, examples, and operation techniques will become apparent to those skilled in the art from this disclosure.

[0246] Thus, the third embodiment includes various forms of implementation and the like that are not described herein.

[0247] (Fourth Embodiment) Next, the fourth embodiment will be described. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationships such as the thickness and planar dimensions of each component are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Also, it goes without saying that there are parts where the relationships and ratios of the dimensions to each other are different among the drawings.

[0248] Also, the fourth embodiment shown below exemplifies an apparatus and a method for embodying a technical idea, and does not specify the materials, shapes, structures, arrangements, etc. of each component. Various changes can be made to this fourth embodiment within the scope of the claims.

[0249] The schematic cross-sectional structure of the semiconductor substrate structure according to the fourth embodiment is represented as shown in FIG. 29.

[0250] As shown in FIG. 29, the semiconductor substrate structure 501 according to the fourth embodiment includes a polycrystalline substrate 510, an epitaxial growth layer 512 integrated with the polycrystalline substrate 510, and a buffer layer 513 disposed between the polycrystalline substrate 510 and the epitaxial growth layer 512 and joined to each of the polycrystalline substrate 510 and the epitaxial growth layer 512. The epitaxial growth layer 512 contains a first dopant, and the buffer layer 513 contains a second dopant having the same conductivity type as the first dopant. The concentration of the second dopant contained in the buffer layer 513 is higher than the concentration of the first dopant contained in the epitaxial growth layer 512. Here, the first dopant and the second dopant may be the same type of dopant or different types of dopants as long as they have the same conductivity type.

[0251] The polycrystalline substrate 510 and the buffer layer 513 may be joined to each other by room-temperature bonding. Here, the room-temperature bonding includes at least one or a plurality of types selected from surface activation bonding, plasma activation bonding, and atomic diffusion bonding.

[0252] The buffer layer 513 and the epitaxial growth layer 512 may be joined to each other by room-temperature bonding.

[0253] The concentration of the first dopant in the epitaxial growth layer 512 is 5×10 14 / cm 3 or more and 2×10 17 / cm 3 less than, and the concentration of the second dopant in the buffer layer 513 may be 2×10 17 / cm 3 or more and 5×10 18 / cm 3 or less.

[0254] The thickness of the buffer layer 513 may be 0.1 μm or more and 10 μm or less.

[0255] Each of the epitaxial growth layer 512 and the buffer layer 513 may include at least one or more types selected from the group consisting of group IV element semiconductors, III-V group compound semiconductors, and II-VI group compound semiconductors. Further, it may include at least one or more types selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0256] Note that the types of inorganic materials included in the epitaxial growth layer 512 and the buffer layer 513 may be the same or different.

[0257] Further, the polycrystalline substrate 510 may include at least one or more types selected from the group consisting of a sintered body, BN, AlN, Al 2 O 3 、Ga 2 O 3 、diamond, carbon, and graphite.

[0258] Here, the sintered body may include at least one or more types of sintered bodies selected from the group consisting of group IV element semiconductors, III-V group compound semiconductors, and II-VI group compound semiconductors.

[0259] Further, the sintered body may include at least one or more types of sintered bodies selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0260] The polycrystalline substrate 510 may contain a dopant at a concentration of 5×10 18 / cm 3 or more and 2×10 22 / cm 3 or less.

[0261] The thickness of the polycrystalline substrate 510 may be 100 μm or more and 1000 μm or less. Further, the diameter of the polycrystalline substrate 510 may be 100 mm or more.

[0262] The polycrystalline substrate 510 and the buffer layer 513 may form an ohmic junction.

[0263] Each of the epitaxial growth layer 512 and the buffer layer 513 may include an epitaxial growth layer made of 4H-SiC. The epitaxial growth layer made of 4H-SiC may have a surface of the (000-1) plane (C plane) or the (0001) plane (Si plane).

[0264] In the example of FIG. 29, an example is shown in which the epitaxial growth layer 512 is made of SiC, the buffer layer 513 is an epitaxial growth layer made of SiC having a higher dopant concentration than the epitaxial growth layer 512, and the polycrystalline substrate 510 is a SiC sintered body.

[0265] In the example of FIG. 29, the SiC buffer layer 513 and the SiC polycrystalline substrate 510 are joined at room temperature. The SiC buffer layer 513 and the SiC epitaxial growth layer 512 are also joined at room temperature. That is, the SiC buffer layer 513 is joined to each of the SiC polycrystalline substrate 510 and the SiC epitaxial growth layer 512 at room temperature.

[0266] In the example of FIG. 29, a bonding interface layer 514 formed during room-temperature bonding is formed at the interface between the SiC buffer layer 513 and the SiC polycrystalline substrate 510. That is, the SiC buffer layer 513 and the SiC polycrystalline substrate 510 are joined via the bonding interface layer 514.

[0267] During room-temperature bonding, the surface roughness Ra (arithmetic mean roughness) of the surface of the polycrystalline substrate 510 on the bonding side is made about 1 nm or less. As a result, the thickness of the bonding interface layer 514 having a different composition from the polycrystalline substrate 510 is about 1 nm to 10 nm. The bonding interface layer 514 may be amorphous SiC.

[0268] Further, the polycrystalline substrate 510 which is a SiC sintered body has a structure including a plurality of crystal grains 515 and includes a plurality of voids (pores) 517.

[0269] In the example of FIG. 29, the polycrystalline substrate 510 is a SiC sintered body, but the polycrystalline substrate 510 is not limited to the sintered body. For example, the polycrystalline substrate 510 may be a SiC polycrystal formed by Chemical Vapor Deposition (CVD).

[0270] As the dopant contained in the epitaxial growth layer 512 used in the fourth embodiment, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be applied as n-type dopants, and for example, Al (aluminum), etc. can be applied as p-type dopants.

[0271] The dopant contained in the buffer layer 513 used in the fourth embodiment may include at least one or a plurality of types selected from the same group as the epitaxial growth layer 512. However, if the conductivity type is the same as that of the epitaxial growth layer 12, it may contain the same type of dopant or different types of dopants.

[0272] According to the fourth embodiment, it is possible to provide a semiconductor substrate structure and a power semiconductor device including this semiconductor substrate structure that can achieve cost reduction while obtaining desired physical properties by eliminating material constraints.

[0273] According to the semiconductor substrate structure according to the fourth embodiment, instead of forming a SiC epitaxial growth layer on a SiC single crystal substrate, at room temperature bonding technology is used to bond and join any polycrystalline substrate, epitaxial growth layer, and buffer layer, so the range of combinations of the substrate, epitaxial growth layer, and buffer layer can be expanded.

[0274] Also, according to the semiconductor substrate structure according to the fourth embodiment, a combination of a substrate having desired characteristics and a SiC epitaxial growth layer is possible, so that the characteristics of the power semiconductor device can be improved. Specifically, since the thermal expansion coefficient, thermal conductivity, electrical conductivity, and mechanical properties can be set to a desired combination, the switching characteristics, heat resistance, and mechanical reliability of the power semiconductor device can be improved.

[0275] Also, according to the semiconductor substrate structure according to the fourth embodiment and the power semiconductor device including this semiconductor substrate structure, since the completed SiC epitaxial growth layer and buffer layer are bonded to an arbitrary substrate using room temperature bonding technology, the manufacturing process period can be shortened. Further, since an arbitrary substrate can be combined with the completed SiC epitaxial growth layer and buffer layer, the manufacturing yield can be improved.

[0276] Also, according to the semiconductor substrate structure according to the fourth embodiment and the power semiconductor device including this semiconductor substrate structure, since the completed SiC epitaxial growth layer and buffer layer are bonded to an arbitrary substrate using room temperature bonding technology, for example, when a polycrystalline substrate that is a sintered body is used as the substrate, the sintered body is manufactured by a high-temperature process of 2000°C or higher, and the stress remaining in the substrate is reduced. Therefore, warping of the substrate is less likely to occur even when bonded to the SiC epitaxial growth layer and buffer layer.

[0277] Also, in the semiconductor substrate structure according to the fourth embodiment and the power semiconductor device including this semiconductor substrate structure, when a polycrystalline substrate that is a sintered body is used as the substrate, the concentration of the dopant can be easily increased only by changing the raw material composition. Therefore, the substrate can be easily made to have a low resistance.

[0278] (Method for manufacturing a semiconductor substrate structure) The manufacturing method of the semiconductor substrate structure 1 according to the fourth embodiment is represented as shown in FIG. 30.

[0279] First, prepare a polycrystalline substrate 510, an epitaxial growth layer 512 and a buffer layer 513, each of which is separate from the polycrystalline substrate 510. Then, apply CMP technology or MP technology to smooth the surface of the polycrystalline substrate 510 that joins the buffer layer 513 so that the surface roughness Ra is, for example, 1 nm or less (surface smoothing step S20). Note that as the smoothing technology, a high-speed atomic beam irradiation technology such as argon or neon with neutralized ion beams may be applied.

[0280] Next, bond the polycrystalline substrate 510 and the buffer layer 513 by room-temperature bonding (bonding step S21 of the polycrystalline substrate and the buffer layer), and bond the epitaxial growth layer 512 and the buffer layer 513 by room-temperature bonding (bonding step S22 of the epitaxial growth layer and the buffer layer). Note that either of the bonding step S21 of the polycrystalline substrate and the buffer layer and the bonding step S22 of the epitaxial growth layer and the buffer layer may be performed first.

[0281] (Room-temperature bonding technology) Room-temperature bonding technology includes surface activation bonding technology, plasma activation bonding technology, atomic diffusion bonding technology, etc. Room-temperature bonding technology is a technology in which after removing oxides and adsorbed molecules on the solid surface by using a high-speed atomic beam or the like in a vacuum by sputtering effect to activate the surface, the active surfaces are brought into contact with each other to form an atomic bond at room temperature. In room-temperature bonding technology, the bonding surface is surface-treated in a vacuum to make the surface atoms in an active state in which chemical bonding is easy. Room-temperature bonding technology forms a strong bond by directly bonding the bonding hands of the surface atoms by removing the surface layer that hinders bonding. By using room-temperature bonding technology, many materials can be bonded at room temperature.

[0282] As semiconductor materials, for example, it is applicable to homo-bonding of Si, SiC, GaAs, InP, GaP, InAs, etc. and hetero-material bonding between these. As single-crystalline oxides, Si / LiNbO 3 、Si / LiTaO 3 、Si / Gd 3 Ga 5 O12 、 Si / Al 2 O 3 (Sapphire) and the like. As metals, it is applicable to Au, Pt, Ag, Cu, Al, Sn, Pb, Zn, bulk materials, foils, bumps, etc. of solder. Additionally, it is applicable to film materials such as Au, Pt, Cu, and Al fabricated on a substrate. Also, as metal / ceramic structures, it is applicable to joining of different materials of Al such as Al / Al 2 O 3 、 Al / silicon nitride, Al / SiC, Al / AlN, etc.

[0283] In room-temperature bonding technology, it is necessary that the bonding surfaces are clean and smooth at the atomic level. Therefore, in the smoothing process S20, it is desirable that the surface roughness Ra of the bonding surfaces is smoothed to, for example, 1 nm or less.

[0284] For the removal of the surface layer, for example, sputter etching using an ion beam or plasma is applicable. The surface after sputter etching is in a state where it easily reacts with surrounding gas molecules. An inert gas such as argon is used for the ion beam, and the process is carried out in a vacuum chamber evacuated to a high vacuum. The surface with exposed atoms having unbonded hands after sputter etching is in an active state with a strong bonding force with other atoms, and by bonding these, a strong bond can be obtained at room temperature.

[0285] In room-temperature bonding applicable to the manufacturing method of the semiconductor substrate structure according to the fourth embodiment, in the bonding process S21 of the polycrystalline substrate and the buffer layer, in a vacuum chamber evacuated to a high vacuum, the contaminant layers covering the surfaces on the bonding sides of the polycrystalline substrate 510 and the buffer layer 513 are removed by etching, and the bonding surfaces are cleaned (etching process S211). Here, the etching process S211 is carried out by irradiating a high-speed atomic beam from an argon high-speed ion beam generator.

[0286] After the etching step S211, the interface between the cleaned polycrystalline substrate 510 and the buffer layer 513 becomes an active state where the bonding hands are exposed. By bringing the polycrystalline substrate 510 and the buffer layer 513 in this active state into contact within a vacuum chamber, the bonding hands existing on the active surfaces are joined together, and the polycrystalline substrate 510 and the buffer layer 513 can be bonded (bonding step S212).

[0287] In the bonding step S22 of the epitaxial growth layer and the buffer layer as well, similar to the bonding step S21 of the polycrystalline substrate and the buffer layer, an etching step S221 is performed to clean the surfaces of the buffer layer 513 and the epitaxial growth layer 512 to an active state, and a bonding step S222 is performed to bond the buffer layer 513 and the epitaxial growth layer 512.

[0288] According to the method for manufacturing a semiconductor substrate structure according to the fourth embodiment, since there is little damage to the bonding interface, high productivity with a high yield can be obtained.

[0289] (Device breakdown voltage simulation) FIG. 31 is a graph showing simulation results of voltage-current density characteristics when a reverse bias is applied to a device, for each of a simulation model of a Schottky barrier diode using a semiconductor substrate structure according to the fourth embodiment ("with buffer layer"), a simulation model of a Schottky barrier diode without defects at the interface between the substrate and the epitaxial growth layer and without a buffer layer ("voidless"), and a simulation model of a Schottky barrier diode with defects at the interface between the substrate and the epitaxial growth layer and without a buffer layer ("with void").

[0290] Figure 32 shows the simulation results of the electric field distribution when the breakdown voltage is applied to each simulation model used in Figure 31. Figure 32A shows the simulation results of a model of a Schottky barrier diode using the semiconductor substrate structure according to the fourth embodiment. Figure 32B shows the simulation results of a model of a Schottky barrier diode without defects at the interface between the substrate and the epitaxial growth layer and without a buffer layer. Figure 32C shows the simulation results of a model of a Schottky barrier diode with defects at the interface between the substrate and the epitaxial growth layer and without a buffer layer. Figure 32D is an enlarged view of the vicinity of the defect in the simulation results of Figure 32C. In Figures 32A to 32C, it is an enlarged view of the range from near the surface of the substrate where the electric field distribution varies greatly to the electrode disposed on the upper surface of the epitaxial growth layer.

[0291] A Schottky barrier diode using the semiconductor substrate structure according to the fourth embodiment was modeled, and the breakdown voltage performance was investigated by device simulation. The specific simulation model will be described below.

[0292] In all simulation models of Schottky barrier diodes, the upper layer is formed of a defect-free SiC layer with a thickness of 5 μm, a width of 5 μm, and a dopant concentration of 1×10 15 / cm 3 and an electrode is formed on the upper surface of this upper layer, which is a common configuration.

[0293] The simulation model shown in the simulation results of "with buffer layer" in Figure 31 and Figure 32A includes a lower layer that is a SiC layer with a width of 5 μm and a dopant concentration of 1×10 19 / cm 3 On the upper layer side surface of the lower layer, a 1 μm square hole is formed. And this simulation model includes a buffer layer formed of a defect-free SiC layer with a thickness of 0.5 μm, a width of 5 μm, and a dopant concentration of 1×10 18 / cm 3 between the upper layer and the lower layer.

[0294] The simulation models shown in the "void present" of Fig. 31 and the simulation results in Figs. 32C and 32D are different from the simulation model used in the "buffer layer present" of Fig. 31 and Fig. 32A in that they do not have a buffer layer.

[0295] The simulation models shown in the "void absent" of Fig. 31 and the simulation results in Fig. 32B are different from the simulation model used in the "buffer layer present" of Fig. 31 and Fig. 32A in that they do not have a buffer layer and no voids are formed on the surface of the lower layer.

[0296] (Simulation results) In the simulation results of the "void absent" simulation model shown in Figs. 31 and 32B, where there are no voids on the surface of the substrate, the original breakdown voltage performance of the device is shown in Fig. 31. And in the simulation results of the "void present" simulation model shown in Figs. 31 and 32C, where there are voids on the surface of the substrate, the breakdown voltage performance is lower than that in the case of "void absent".

[0297] On the contrary, in the simulation results of the "buffer layer present" simulation model that models the semiconductor substrate structure 501 according to the fourth embodiment shown in Figs. 31 and 32A, the breakdown voltage performance is significantly improved.

[0298] In the "void absent" simulation model, as shown in Figs. 32C and 32D, electric field concentration occurs around the position in contact with the void at the interface between the layer with a low dopant concentration where the upper electrode is formed and the substrate with a high dopant concentration. In contrast, in the "buffer layer present" simulation model, since a buffer layer with a high dopant concentration and no voids is joined to the substrate surface, even when there are voids on the substrate surface, the electric field concentration around the position in contact with the void is prevented and the breakdown voltage performance is significantly improved.

[0299] As described above, the simulation results in the simulation model of "with buffer layer" obtained by modeling the semiconductor substrate structure according to the fourth embodiment indicate that the breakdown voltage performance of the device using the semiconductor substrate structure according to the fourth embodiment is significantly improved and the reliability of the device is enhanced.

[0300] Therefore, according to the semiconductor substrate structure 1 according to the fourth embodiment, as the substrate, for example, a low-cost polycrystalline substrate 510 can be used instead of a high-cost single-crystalline substrate.

[0301] In the example of FIG. 29, an example of a SiC sintered body was given as the polycrystalline substrate 510. However, the polycrystalline substrate 510 is not limited to the sintered body, and may be a SiC polycrystal formed by CVD.

[0302] In this case, the voids 517 formed inside the polycrystalline substrate 510 are significantly reduced. However, in the polycrystal, recesses may be formed on the surface due to grain detachment or the like in the surface smoothing process S20. Therefore, the surface state can be the same as the "with voids" state in this simulation. For this reason, even in a device using a SiC polycrystal formed by CVD as the polycrystalline substrate 510, the breakdown voltage performance of the device is improved by adopting the configuration of the semiconductor substrate structure 501 according to the fourth embodiment.

[0303] (Manufacturing apparatus for SiC sintered body) The manufacturing apparatus 650 for the polycrystal (SiC sintered body) used in the semiconductor substrate structure according to the fourth embodiment is schematically represented as shown in FIG. 33. The interior 650A of the polycrystal (SiC sintered body) manufacturing apparatus 650 is in a vacuum atmosphere of about several Pa or is gas-substituted with Ar / N 2 gas.

[0304] The polycrystalline body (SiC sintered body) manufacturing apparatus 650 employs a solid compression sintering method by hot press (HP). A graphite (carbon) sintering mold (graphite die) 690 filled with a powder or solid SiC polycrystalline material 694 is heated while being pressurized. A thermocouple or a radiation thermometer 692 is housed in the graphite die 690.

[0305] The graphite die 690 is connected to the pressure shafts 660A and 660B via graphite punches 680A and 680B and graphite spacers 670A and 670B. By applying pressure between the pressure shafts 660A and 660B, the SiC polycrystalline material 694 is pressurized and heated. The heating temperature is, for example, about 200°C to 350°C, and the pressurizing pressure P is, for example, up to about 50 MPa. In addition to hot press sintering (HP), for example, spark plasma sintering (SPS) may be applied.

[0306] According to the polycrystalline body (SiC sintered body) manufacturing apparatus 650 of the semiconductor substrate structure according to the fourth embodiment, since the heating range is limited, rapid heating and cooling (several minutes to several hours) are possible compared to atmospheric heating in an electric furnace or the like. By pressurization and rapid heating, it is possible to produce a dense SiC sintered body with grain growth suppressed. Also, it is applicable not only to sintering but also to sintering joining and porous body sintering.

[0307] The semiconductor substrate structure 1 according to the above fourth embodiment can be used, for example, in the manufacture of various SiC semiconductor elements. Hereinafter, as an example thereof, examples of a SiC Schottky barrier diode (SBD), a SiC trench gate (Trench: T) type metal oxide semiconductor field effect transistor (MOSFET), and a SiC planar gate type MOSFET are shown.

[0308] (SiC-SBD) The SiC-SBD521 fabricated using the semiconductor substrate structure according to the fourth embodiment includes a semiconductor substrate structure 501 composed of a SiC sintered body 510, a SiC epitaxial growth layer 512, and a buffer layer 513. The SiC sintered body 510 and the buffer layer 513, and the buffer layer 513 and the SiC epitaxial growth layer 512 are joined by room-temperature bonding. Incidentally, a bonding interface layer 514 may be interposed between the SiC sintered body 510 and the buffer layer 513, or between the buffer layer 513 and the SiC epitaxial growth layer 512.

[0309] The SiC sintered body 510 and the buffer layer 513 are doped with n+(the impurity density is, for example, about 1×10 18 cm -3 ~about 1×10 21 cm -3 ), and the SiC epitaxial growth layer 512 is doped with n-(the impurity density is, for example, about 5×10 14 cm -3 ~about 5×10 16 cm -3 ).

[0310] In addition, the SiC epitaxial growth layer 512 may be composed of any one of 4H-SiC, 6H-SiC, 2H-SiC, or 3C-SiC. Further, instead of the SiC sintered body 510, any one of BN, AlN, Al 2 O 3 , Ga 2 O 3 , diamond, carbon, or graphite may be provided.

[0311] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. are applicable.

[0312] As the p-type doping impurity, for example, Al (aluminum), etc. are applicable.

[0313] The back surface of the SiC sintered body 510 is provided with a cathode electrode 522 so as to cover the entire area thereof, and the cathode electrode 522 is connected to a cathode terminal K.

[0314] Also, the surface 500 (for example, (0001) plane (Si plane)) of the SiC epitaxial growth layer 512 is provided with a contact hole 524 that exposes a part of the SiC epitaxial growth layer 512 as an active region 523, and a field insulating film 526 is formed in a field region 525 surrounding the active region 523.

[0315] The field insulating film 526 is made of SiO 2 (silicon oxide), but may be made of other insulating materials such as silicon nitride (SiN). An anode electrode 527 is formed on the field insulating film 526, and the anode electrode 527 is connected to an anode terminal A.

[0316] A p-type JTE (Junction Termination Extension) structure 528 is formed in the vicinity of the surface 500 (surface layer portion) of the SiC epitaxial growth layer 512 so as to be in contact with the anode electrode 527. The JTE structure 528 is formed along the contour of the contact hole 524 so as to straddle inside and outside the contact hole 524 of the field insulating film 526.

[0317] (SiC-TMOSFET) The trench gate type MOSFET 531 fabricated using the semiconductor substrate structure according to the fourth embodiment includes a semiconductor substrate structure 501 composed of a SiC sintered body 510, a SiC epitaxial growth layer 512, and a buffer layer 513, as shown in FIG. 35. The SiC sintered body 510 and the buffer layer 513, and the buffer layer 513 and the SiC epitaxial growth layer 512 are joined by room temperature joining. Note that a joining interface layer 514 may be interposed between the SiC sintered body 510 and the buffer layer 513, or between the buffer layer 513 and the SiC epitaxial growth layer 512.

[0318] The SiC sintered body 510 and the buffer layer 513 are doped to n+ type (the impurity density is, for example, about 1×10 18 cm -3 ~ about 1×10 21 cm -3 ), and the SiC epitaxial growth layer 512 is doped to n- type (the impurity density is, for example, about 5×10 14 cm -3 ~ about 5×10 16 cm -3 ).

[0319] Also, the SiC epitaxial growth layer 512 may be composed of any of the materials of 4H-SiC, 6H-SiC, 2H-SiC, or 3C-SiC.

[0320] Also, instead of the SiC sintered body 510, it may be provided with any of BN, AlN, Al 2 O 3 , Ga 2 O 3 , diamond, carbon, or graphite.

[0321] As n-type doping impurities, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. are applicable.

[0322] As p-type doping impurities, for example, Al (aluminum), etc. are applicable.

[0323] The back surface ((000-1) plane, C plane) of the SiC sintered body 510 is provided with a drain electrode 532 so as to cover the entire area, and the drain electrode 532 is connected to a drain terminal D.

[0324] Near the surface 500 ((0001) plane, Si plane) (surface layer portion) of the SiC epitaxial growth layer 512, it is p-type (the impurity density is, for example, about 1×10 16 cm -3 ~ about 1×10 19 cm -3) The body region 533 is formed. In the SiC epitaxial growth layer 512, the portion on the SiC sintered body 510 side with respect to the body region 533 is an n-type drain region 534(512) in which the state of the SiC epitaxial growth layer is maintained as it is.

[0325] A gate trench 535 is formed in the SiC epitaxial growth layer 512. The gate trench 535 penetrates the body region 533 from the surface 500 of the SiC epitaxial growth layer 512, and its deepest part reaches the drain region 534.

[0326] A gate insulating film 536 is formed on the inner surface of the gate trench 535 and the surface 500 of the SiC epitaxial growth layer 512 so as to cover the entire inner surface of the gate trench 535. Then, the gate electrode 537 is embedded in the gate trench 535 by filling the inside of the gate insulating film 536 with, for example, polysilicon. A gate terminal G is connected to the gate electrode 537.

[0327] An n+-type source region 538 that forms a part of the side surface of the gate trench 535 is formed in the surface layer portion of the body region 533.

[0328] Also, in the SiC epitaxial growth layer 512, a p+-type (the impurity density is, for example, about 1×10 18 cm -3 ~about 1×10 21 cm -3 ) body contact region 539 is formed that penetrates the source region 538 from the surface 500 and is connected to the body region 533.

[0329] On the SiC epitaxial growth layer 512, an interlayer insulating film 540 made of SiO 2 is formed. The source electrode 542 is connected to the source region 538 and the body contact region 539 through a contact hole 541 formed in the interlayer insulating film 540. A source terminal S is connected to the source electrode 542.

[0330] With a predetermined potential difference generated between the source electrode 542 and the drain electrode 532 (between source and drain), by applying a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) to the gate electrode 537, a channel can be formed in the vicinity of the interface with the gate insulating film 536 in the body region 533 due to the electric field from the gate electrode 537. As a result, a current can flow between the source electrode 542 and the drain electrode 532, and the SiC-TMOSFET 531 can be turned on.

[0331] (SiC planar gate type MOSFET) As shown in FIG. 36, the planar gate type MOSFET 551 fabricated using the semiconductor substrate structure 1 according to the fourth embodiment includes a semiconductor substrate structure 501 composed of a SiC sintered body 510, a SiC epitaxial growth layer 512, and a buffer layer 513. The SiC sintered body 510 and the buffer layer 513, and the buffer layer 513 and the SiC epitaxial growth layer 512 are joined by room temperature bonding. Incidentally, a bonding interface layer 514 may be interposed between the SiC sintered body 510 and the buffer layer 513, or between the buffer layer 513 and the SiC epitaxial growth layer 512.

[0332] The SiC sintered body 510 and the buffer layer 513 are doped with n+ type (impurity density is, for example, about 1×10 18 cm -3 ~ about 1×10 21 cm -3 ), and the SiC epitaxial growth layer 512 is doped with n- type (impurity density is, for example, about 5×10 14 cm -3 ~ about 5×10 16 cm -3 ).

[0333] Also, the SiC epitaxial growth layer 512 may be composed of any one of 4H-SiC, 6H-SiC, 2H-SiC, or 3C-SiC. Also, instead of the SiC sintered body 510, BN, AlN, Al 2 O 3 , Ga 2 O3 It may be provided with any one of diamond, carbon, or graphite.

[0334] As the n-type doping impurity, for example, N (nitrogen), P (phosphorus), As (arsenic), etc. can be applied.

[0335] As the p-type doping impurity, for example, Al (aluminum), etc. can be applied.

[0336] On the back surface ((000-1) plane) of the SiC sintered body 510, a drain electrode 552 is formed so as to cover the entire area, and a drain terminal D is connected to the drain electrode 552.

[0337] In the vicinity (surface layer portion) of the surface 500 ((0001) plane) of the SiC epitaxial growth layer 512, a p-type (impurity density is, for example, about 1×10 16 cm -3 ~ about 1×10 19 cm -3 ) body region 553 is formed in a well shape. In the SiC epitaxial growth layer 512, the portion on the SiC substrate 510 side with respect to the body region 553 is an n-type drain region 554 (512) that maintains the state as it is after epitaxial growth.

[0338] An n+-type source region 555 is formed in the surface layer portion of the body region 553 with a gap from the periphery of the body region 553.

[0339] Inside the source region 555, a p+-type (impurity density is, for example, about 1×10 18 cm -3 ~ about 1×10 21 cm -3 ) body contact region 556 is formed. The body contact region 556 penetrates the source region 555 in the depth direction and is connected to the body region 553.

[0340] On the surface 500 of the SiC epitaxial growth layer 512, a gate insulating film 557 is formed. The gate insulating film 557 covers a portion (the peripheral portion of the body region 553) surrounding the source region 555 in the body region 553 and the outer peripheral edge of the source region 555.

[0341] On the gate insulating film 557, a gate electrode 558 made of, for example, polysilicon is formed. The gate electrode 558 faces the peripheral portion of the body region 553 with the gate insulating film 557 interposed therebetween. A gate terminal G is connected to the gate electrode 558.

[0342] On the SiC epitaxial growth layer 512, an interlayer insulating film 559 made of SiO 2 is formed. Through a contact hole 560 formed in the interlayer insulating film 559, a source electrode 561 is connected to the source region 555 and the body contact region 556. A source terminal S is connected to the source electrode 561.

[0343] With a predetermined potential difference generated between the source electrode 561 and the drain electrode 552 (between source and drain), by applying a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) to the gate electrode 558, a channel can be formed in the vicinity of the interface between the gate insulating film 557 and the body region 553 due to the electric field from the gate electrode 558. As a result, a current can flow between the source electrode 561 and the drain electrode 552, and the planar gate type MOSFET 551 can be turned on.

[0344] As described above, the fourth embodiment has been explained, but it can also be implemented in other forms.

[0345] For example, although illustration is omitted, a power semiconductor device can also be manufactured using the semiconductor substrate structure 501 according to the fourth embodiment. Specifically, a vertical device structure using the semiconductor substrate structure 501 can also be manufactured. That is, a polycrystalline substrate 510, an epitaxial growth layer 512 integrated with the polycrystalline substrate 510, and a buffer layer 513 disposed between the polycrystalline substrate 510 and the epitaxial growth layer 512 and joined to each of the polycrystalline substrate 510 and the epitaxial growth layer 512 are provided. The epitaxial growth layer 512 contains a first dopant, the buffer layer 513 contains a second dopant having the same conductivity type as the first dopant, and the concentration of the second dopant contained in the buffer layer 513 is higher than the dopant concentration contained in the epitaxial growth layer 512. A vertical power semiconductor device including a first metal electrode disposed on the substrate surface of the semiconductor substrate structure 501 facing the bonding surface between the polycrystalline substrate 510 and the buffer layer 513 may be formed.

[0346] Further, a vertical power semiconductor device further including a second metal electrode disposed on the surface of the epitaxial growth layer 512 facing the bonding surface between the buffer layer 513 and the epitaxial growth layer 512 may be formed.

[0347] Also, for example, a lateral device structure can also be manufactured using the semiconductor substrate structure 501 according to the fourth embodiment. That is, a polycrystalline substrate 510, an epitaxial growth layer 512 integrated with the polycrystalline substrate 510, and a buffer layer 513 disposed between the polycrystalline substrate 510 and the epitaxial growth layer 512 and joined to each of the polycrystalline substrate 510 and the epitaxial growth layer 512 are provided. The epitaxial growth layer 512 contains a first dopant, the buffer layer 513 contains a second dopant having the same conductivity type as the first dopant, and the concentration of the second dopant contained in the buffer layer 513 is higher than the dopant concentration contained in the epitaxial growth layer 512. A lateral power semiconductor device including a second metal electrode disposed on the surface of the epitaxial growth layer 512 of the semiconductor substrate structure 501 facing the bonding surface between the buffer layer 513 and the epitaxial growth layer 512 may be formed.

[0348] Even in the above-described vertical or horizontal power semiconductor device, each of the epitaxial growth layer 512 and the buffer layer 513 may include at least one or a plurality of types selected from the group consisting of group IV element semiconductors, III-V group compound semiconductors, and II-VI group compound semiconductors. Further, each of the epitaxial growth layer 512 and the buffer layer 513 may include at least one or a plurality of types selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0349] Even in the above-described vertical or horizontal power semiconductor device, the polycrystalline substrate may include at least one or a plurality of types selected from the group consisting of a sintered body, BN, AlN, Al 2 O 3 、Ga 2 O 3 、diamond, carbon, and graphite. Further, the sintered body may include at least one or a plurality of types of sintered bodies selected from the group consisting of group IV element semiconductors, III-V group compound semiconductors, and II-VI group compound semiconductors. Further, the sintered body may include at least one or a plurality of types of sintered bodies selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0350] Also, for example, although illustration is omitted, a MOS capacitor can also be manufactured using the semiconductor substrate structure 1 according to the fourth embodiment. In the MOS capacitor, the yield and reliability can be improved.

[0351] Also, although illustration is omitted, a bipolar transistor can also be manufactured using the semiconductor substrate structure 501 according to the fourth embodiment. In addition, the semiconductor substrate structure 501 according to the fourth embodiment can also be used for manufacturing an SiC-pn diode, a silicon carbide insulated gate bipolar transistor (IGBT), a SiC complementary MOSFET, and the like.

[0352] As shown in FIG. 37, the schematic bird's-eye view configuration of the semiconductor substrate structure (wafer) 501 according to the fourth embodiment includes a polycrystalline substrate 510, a buffer layer 513 joined to the polycrystalline substrate 510, and an epitaxial growth layer 512 joined to the buffer layer 513. The polycrystalline substrate 510 and the buffer layer 513, and the buffer layer 513 and the epitaxial growth layer 512 are each joined by room-temperature bonding. Here, the room-temperature bonding includes at least one or more selected from surface activation bonding, plasma activation bonding, and atomic diffusion bonding.

[0353] Note that the polycrystalline substrate 510 and the buffer layer 513, and the buffer layer 513 and the epitaxial growth layer 512 may be joined by diffusion bonding.

[0354] When using room-temperature bonding, the surface roughness Ra of the substrate surface is set to about 1 nm or less. As a result, the thickness of the bonding interface layer 514 with different compositions is about 1 nm to 10 nm.

[0355] When using diffusion bonding, the surface roughness of the substrate surface may be rough depending on the material and bonding temperature. In order to utilize atomic diffusion, the thickness of the bonding interface layer 514 with different composition gradients due to atomic diffusion is about 1 nm to 10 μm.

[0356] The epitaxial growth layer 512 may include at least one or more selected from the group of group-IV element semiconductors, III-V compound semiconductors, and II-VI compound semiconductors.

[0357] The epitaxial growth layer 512 may include at least one or more selected from the group of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0358] In addition, the SiC epitaxial growth layer may be composed of any one of 4H-SiC, 6H-SiC, 2H-SiC, or 3C-SiC.

[0359] The buffer layer 513 may include at least one or a plurality of types selected from the same group as the epitaxial growth layer 512. However, if the conductivity type is the same as that of the epitaxial growth layer 512, it may contain the same type of dopant or different types of dopants.

[0360] The polycrystalline substrate 510 may include at least one or a plurality of types selected from the group of sintered bodies, BN, AlN, Al 2 O 3 、Ga 2 O 3 、 diamond, carbon, and graphite.

[0361] Here, the sintered body may include at least one or a plurality of types of sintered bodies selected from the group of group IV element semiconductors, III-V group compound semiconductors, and II-VI group compound semiconductors. Further, the sintered body may include at least one or a plurality of types of sintered bodies selected from the group of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide.

[0362] The thickness of the polycrystalline substrate (SiC sintered body) 510 is, for example, about 200 μm to about 500 μm, the thickness of the SiC epitaxial growth layer 512 is, for example, about 4 μm to about 100 μm, and the thickness of the SiC buffer layer 513 may be, for example, about 0.5 μm to about 1 μm.

[0363] (SiC Epitaxial Wafer) The SiC epitaxial growth layer 512 and the SiC buffer layer 513 are made of, for example, 4H-SiC epitaxially grown by CVD and may have an off-angle of less than 4 degrees. Specifically, the SiC epitaxial growth layer 512 and the SiC buffer layer 513 may be a SiC single-crystal epitaxial wafer manufactured by so-called remote epitaxy obtained by epitaxially growing on a graphene layer formed on a SiC single-crystal substrate and peeling off from the graphene layer.

[0364] (Example of crystal structure) The schematic bird's-eye view configuration of the unit cell of 4H-SiC crystal applicable to the SiC epitaxial growth layer 512 and the SiC buffer layer 513 is represented as shown in Fig. 38(a). The schematic configuration of the two-layer part of the 4H-SiC crystal is represented as shown in Fig. 38(b), and the schematic configuration of the four-layer part of the 4H-SiC crystal is represented as shown in Fig. 38(c).

[0365] Also, the schematic configuration of the unit cell of the crystal structure of 4H-SiC shown in Fig. 38(a) as viewed directly above the (0001) plane is represented as shown in Fig. 39.

[0366] As shown in Figs. 38(a) to 38(c), the crystal structure of 4H-SiC can be approximated to a hexagonal system, and four C atoms are bonded to one Si atom. The four C atoms are located at the four vertices of a regular tetrahedron with the Si atom at the center. These four C atoms are such that one Si atom is located in the

[0001] axis direction with respect to the C atoms, and the other three C atoms are located on the [000-1] axis side with respect to the Si atom. In Fig. 38(a), the off-angle θ is, for example, about 4 degrees or less.

[0367] The

[0001] axis and the [000-1] axis are along the axial direction of the hexagonal prism, and the plane with the

[0001] axis as the normal (the top surface of the hexagonal prism) is the (0001) plane (Si plane). On the other hand, the plane with the [000-1] axis as the normal (the bottom surface of the hexagonal prism) is the (000-1) plane (C plane).

[0368] Also, the directions passing through the non-adjacent vertices of the hexagonal prism when viewed directly above the (0001) plane and perpendicular to the

[0001] axis are the a1 axis [2-1-10], the a2 axis [-12-10], and the a3 axis [-1-120], respectively.

[0369] As shown in Fig. 39, the direction passing through the vertex between the a1 axis and the a2 axis is the [11-20] axis, the direction passing through the vertex between the a2 axis and the a3 axis is the [-2110] axis, and the direction passing through the vertex between the a3 axis and the a1 axis is the [1-210] axis.

[0370] Between each of the six axes passing through the respective vertices of the hexagonal prism, axes that are inclined at an angle of 30° with respect to the axes on both sides thereof and that are normal to each side surface of the hexagonal prism are, in clockwise order starting from between the a1 axis and the [11-20] axis, the [10-10] axis, the [1-100] axis, the [0-110] axis, the [-1010] axis, the [-1100] axis, and the [01-10] axis. Each surface (side surface of the hexagonal prism) having these axes as normals is a crystal plane perpendicular to the (0001) plane and the (000-1) plane.

[0371] The power semiconductor device including the semiconductor substrate structure according to the fourth embodiment may include any one of an IGBT, a diode, a MOSFET, a thyristor, and an LED device of an SiC-based, Si-based, GaN-based, AlN-based, or gallium oxide-based type.

[0372] The power semiconductor device including the semiconductor substrate structure according to the fourth embodiment may have a configuration of any one of a one-in-one module, a two-in-one module, a four-in-one module, a six-in-one module, a seven-in-one module, an eight-in-one module, a twelve-in-one module, or a fourteen-in-one module.

[0373] According to the fourth embodiment, it is possible to provide a semiconductor substrate structure having a stable interface structure even at high temperatures and a power semiconductor device including this semiconductor substrate structure.

[0374] According to the fourth embodiment, it is possible to provide a semiconductor substrate structure capable of eliminating material constraints and achieving cost reduction and desired physical properties, and a power semiconductor device including this semiconductor substrate structure.

[0375] According to the semiconductor substrate structure according to the fourth embodiment, instead of forming an SiC epitaxial growth layer on an SiC single crystal substrate, any substrate and an SiC epitaxial growth layer are bonded together using a room temperature bonding technique, so that the range of combinations of the epitaxial growth layer and the substrate can be expanded.

[0376] According to the semiconductor substrate structure according to the fourth embodiment, as the substrate material, for example, a low-cost SiC polycrystalline substrate or a carbon substrate can be used instead of the high-cost SiC single-crystalline substrate.

[0377] According to the semiconductor substrate structure according to the fourth embodiment, as the substrate material, for example, a low-cost SiC polycrystalline substrate or a carbon substrate can be used instead of the high-cost SiC single-crystalline substrate.

[0378] Also, according to the semiconductor substrate structure according to the fourth embodiment, a combination of a substrate having desired characteristics and a SiC epitaxial growth layer is possible, so that the characteristics of the power semiconductor device can be improved. Specifically, in order to combine the thermal expansion coefficient, the thermal conductivity, the electrical conductivity, and the mechanical properties as desired, the switching characteristics, the heat resistance, and the mechanical reliability of the power semiconductor device can be improved.

[0379] Also, according to the semiconductor substrate structure according to the fourth embodiment and the power semiconductor device including this semiconductor substrate structure, by using a room-temperature bonding technique or a diffusion bonding technique, an arbitrary substrate and a completed SiC epitaxial growth layer are bonded and joined, so that the period of the process can be shortened. Further, since an arbitrary substrate and a completed SiC epitaxial growth layer can be combined, the manufacturing yield can be improved.

[0380] Also, according to the semiconductor substrate structure according to the fourth embodiment and the power semiconductor device including this semiconductor substrate structure, since a SiC buffer layer having a higher dopant concentration than the SiC epitaxial growth layer is provided, the breakdown voltage of the semiconductor substrate structure can be improved. Thereby, when this semiconductor substrate structure is applied to a device, the reliability of the device can be improved.

[0381] [Implementation of Other Forms] As described above, although several forms of implementation have been described, the discussions and drawings that form part of the disclosure are exemplary and should not be construed as limiting. Various alternative forms of implementation, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

[0382] Thus, the fourth embodiment includes various forms of implementation and the like that are not described herein.

Industrial Applicability

[0383] This invention can be used in Schottky barrier diodes and MOSFETs made of SiC, etc. It may also be used in n-channel IGBTs made of SiC.

[0384] The semiconductor substrate structure and the power semiconductor device including this semiconductor substrate structure can also be used in various semiconductor module technologies such as IGBT modules, diode modules, and MOS modules (Si, SiC, GaN, AlN, gallium oxide), and can be applied to a wide range of application fields such as power modules for inverter circuits that drive electric motors used as power sources for electric vehicles (including hybrid vehicles), trains, industrial robots, etc., and power modules for inverter circuits that convert the power generated by solar cells, wind turbines, and other power generation devices (especially home power generation devices) into commercial power.

[0385] The semiconductor substrate structure and the power semiconductor device including this semiconductor substrate structure can also be used in various semiconductor module technologies such as IGBT modules, diode modules, and MOS modules (Si, SiC, GaN, AlN, gallium oxide), and can be applied to a wide range of application fields such as power modules for inverter circuits that drive electric motors used as power sources for electric vehicles (including hybrid vehicles), trains, industrial robots, etc., and power modules for inverter circuits that convert the power generated by solar cells, wind turbines, and other power generation devices (especially home power generation devices) into commercial power.

[0386] Incidentally, the second embodiment may include the following configurations.

[0387] 1.1 A first substrate formed of a p-type SiC semiconductor, having one surface as a bonding surface, and a second substrate formed of an n-type SiC semiconductor, having one surface as a bonding surface, and the bonding surface being covered with a thin film of a p-type SiC semiconductor. A semiconductor substrate in which the bonding surface of the first substrate and the bonding surface of the second substrate are bonded via a thin film covering the bonding surface of the second substrate.

[0388] 1.2 The semiconductor substrate according to item 1.1, wherein the thin film has a film thickness of 1 nm or more.

[0389] 1.3 The semiconductor substrate according to item 1.1 or 1.2, wherein the first substrate is single crystal or polycrystalline.

[0390] 1.4 The semiconductor substrate according to any one of items 1.1 to 1.3, wherein the second substrate is single crystal.

[0391] 1.5 A semiconductor device using the semiconductor substrate according to any one of items 1.1 to 1.4.

[0392] 1.6 The semiconductor device according to item 1.5, including an n-channel IGBT having the first substrate as a p-type substrate layer and the second substrate as an n-type drift layer.

[0393] 1.7 The semiconductor device according to item 1.6, wherein the second substrate further includes a buffer layer in which the concentration of n-type impurities in the n-type SiC semiconductor is higher than the concentration of n-type impurities in the other part of the n-type SiC semiconductor of the second substrate from a predetermined depth from the bonding surface.

[0394] 1.8 The semiconductor device according to item 1.6 or 1.7, wherein the n-channel IGBT includes a trench-type gate.

[0395] 1.9 A step of providing a first substrate formed of a p-type SiC semiconductor, having one surface as a bonding surface, and Providing a second substrate formed of an n-type SiC semiconductor, having one surface as a bonding surface, and the bonding surface being covered with a thin film of a p-type SiC semiconductor; Bonding the bonding surface of the first substrate and the bonding surface of the second substrate via the thin film covering the bonding surface of the second substrate; A method for manufacturing a semiconductor substrate including these steps.

[0396] 1.10 The method for manufacturing a semiconductor substrate according to item 1.9, wherein the thin film has a film thickness of 1 nm or more.

[0397] 1.11 The method for manufacturing a semiconductor substrate according to item 1.9 or 1.10, wherein the first substrate is a single crystal.

[0398] 1.12 The method for manufacturing a semiconductor substrate according to item 1.11, wherein the step of providing the first substrate further includes a step of producing a single crystal p-type SiC semiconductor substrate by an epitaxial method.

[0399] 1.13 The method for manufacturing a semiconductor substrate according to item 1.12, wherein the epitaxial method is a remote epitaxial method.

[0400] 1.14 The method for manufacturing a semiconductor substrate according to item 1.11, wherein the step of providing the first substrate further includes a step of cutting a single crystal ingot to produce a single crystal p-type SiC semiconductor substrate.

[0401] 1.15 The method for manufacturing a semiconductor substrate according to any one of items 1.9 to 1.13, wherein the first substrate is polycrystalline.

[0402] 1.16 The method for manufacturing a semiconductor substrate according to item 1.15, wherein the step of providing the first substrate further includes a step of producing a polycrystalline p-type SiC semiconductor substrate by CVD growth.

[0403] 1.17 The method for manufacturing a semiconductor substrate according to item 1.15, wherein the step of providing the first substrate further includes a step of producing a polycrystalline p-type SiC semiconductor substrate by sintering a powder material.

[0404] 1.18 The method for manufacturing a semiconductor substrate according to any one of items 1.9 to 1.17, wherein the second substrate is a single crystal.

[0405] 1.19 The method for manufacturing a semiconductor substrate according to item 1.18, wherein the step of providing the second substrate further includes a step of manufacturing a single crystal n-type SiC semiconductor substrate by an epitaxial method.

[0406] 1.20 The method for manufacturing a semiconductor substrate according to item 1.19, wherein the step of manufacturing the single crystal n-type SiC semiconductor substrate further includes a step of forming a buffer layer in which the concentration of n-type impurities is higher than that of other parts of the main body of the second substrate to a predetermined depth from the bonding surface of the second substrate.

[0407] 1.21 The method for manufacturing a semiconductor substrate according to item 1.19 or 1.20, wherein the epitaxial method is a remote epitaxial method.

[0408] 1.22 The method for manufacturing a semiconductor substrate according to item 1.18, wherein the step of providing the second substrate further includes a step of cutting a single crystal ingot to manufacture a single crystal n-type SiC semiconductor substrate.

[0409] 1.23 The method for manufacturing a semiconductor substrate according to any one of items 1.18 to 1.22, wherein the step of providing the second substrate further includes a step of forming a thin film of a single crystal n-type SiC semiconductor by an epitaxial method so as to cover the bonding surface of the second substrate.

[0410] 1.24 The method for manufacturing a semiconductor substrate according to any one of items 1.9 to 1.23, wherein the step of bonding the bonding surface of the first substrate and the bonding surface of the second substrate bonds the first substrate and the second substrate by room temperature bonding.

[0411] 1.25 The method for manufacturing a semiconductor substrate according to any one of items 1.9 to 1.23, wherein the step of bonding the bonding surface of the first substrate and the bonding surface of the second substrate bonds the first substrate and the second substrate by diffusion bonding.

[0412] 1.26 A step of providing a semiconductor substrate using the method for manufacturing a semiconductor substrate according to any one of items 1.19 to 1.25, and a step of fabricating an n-channel IGBT in which the first substrate of the semiconductor substrate is a p-type substrate layer and the main body of the second substrate is an n-type drift layer A method for manufacturing a semiconductor device including the above.

[0413] The third embodiment may include the following configuration.

[0414] 2.1 A polycrystalline silicon carbide substrate containing at least one of germanium and tin and further containing at least one dopant selected from nitrogen, phosphorus, and boron. A polycrystalline silicon carbide substrate characterized by further containing at least one dopant selected from nitrogen, phosphorus, and boron.

[0415] 2.2 The polycrystalline silicon carbide substrate according to item 2.1, wherein the size of crystallites contained in the crystal grains of the polycrystalline silicon carbide is 100 nm or less.

[0416] 2.3 The polycrystalline silicon carbide substrate according to item 2.1 or 2.2, having a relative density of 99% or more.

[0417] 2.4 A power semiconductor device using the polycrystalline silicon carbide substrate according to any one of items 2.1 to 2.3 as a support substrate.

[0418] 2.5 The power semiconductor device according to item 2.4, wherein the power semiconductor device includes at least one or a plurality of types selected from the group consisting of a SiC Schottky barrier diode, a SiC-MOSFET, a SiC bipolar transistor, a SiC diode, a SiC thyristor, or a SiC insulated gate bipolar transistor.

[0419] 2.6 Containing at least one of germanium and tin, A polycrystalline silicon carbide ingot, further comprising at least one dopant selected from nitrogen, phosphorus, and boron.

[0420] 2.7 The polycrystalline silicon carbide ingot according to item 2.6, wherein the size of the crystallites contained in the crystal grains of the polycrystalline silicon carbide is 100 nm or less.

[0421] 2.8 The polycrystalline silicon carbide ingot according to item 2.6 or 2.7, having a relative density of 99% or more.

[0422] 2.9 A step of preparing a mixed powder by blending at least two compounds selected from compounds of group IV-V elements and compounds of group III-IV elements with silicon carbide powder as a main material, and having an average particle size of 100 nm or less; A step of obtaining a polycrystalline silicon carbide ingot by subjecting the mixed powder to spark plasma sintering; A method for manufacturing a polycrystalline silicon carbide substrate, comprising a step of cutting out the polycrystalline silicon carbide ingot to produce a polycrystalline silicon carbide substrate.

[0423] 2.10 The method for manufacturing a polycrystalline silicon carbide substrate according to item 2.9, wherein the compound of group IV-V elements is at least one or more materials selected from the group consisting of Si 3 N 4 Ge 3 N 4 Sn 3 N 4 The method for manufacturing a polycrystalline silicon carbide substrate according to item 2.9, wherein the compound of group III-IV elements is at least one or more materials selected from the group consisting of B

[0424] 2.11 The method for manufacturing a polycrystalline silicon carbide substrate according to item 2.10, wherein the compound of group III-IV elements is at least one or more materials selected from the group consisting of B 4 C, SiB 4 The method for manufacturing a polycrystalline silicon carbide substrate according to item 2.10, wherein the compound of group III-IV elements is at least one or more materials selected from the group consisting of C, SiB.

[0425] The fourth embodiment may include the following configuration.

[0426] 3.1 A polycrystalline substrate, a first epitaxial growth layer integrated with the polycrystalline substrate, and a second epitaxial growth layer disposed between the polycrystalline substrate and the first epitaxial growth layer and joined to each of the polycrystalline substrate and the first epitaxial growth layer. The first epitaxial growth layer contains a first dopant, and the second epitaxial growth layer contains a second dopant having the same conductivity type as the first dopant. A semiconductor substrate structure in which the concentration of the second dopant is higher than the concentration of the first dopant.

[0427] 3.2 The semiconductor substrate structure according to item 3.1, wherein the second epitaxial growth layer and the polycrystalline substrate are joined by room-temperature bonding.

[0428] 3.3 The semiconductor substrate structure according to item 3.1 or 3.2, wherein the second epitaxial growth layer and the first epitaxial growth layer are joined by room-temperature bonding.

[0429] 4 The concentration of the first dopant in the first epitaxial growth layer is 5×10 14 / cm 3 or more and less than 2×10 17 / cm 3 and the concentration of the second dopant in the second epitaxial growth layer is 2×10 17 / cm 3 or more and 5×10 18 / cm 3 or less. The semiconductor substrate structure according to any one of items 3.1 to 3.3.

[0430] 3.5 The semiconductor substrate structure according to any one of items 3.1 to 3.4, wherein the thickness of the second epitaxial growth layer is 0.1 μm or more and 10 μm or less.

[0431] 3.6 Each of the first epitaxial growth layer and the second epitaxial growth layer includes at least one or a plurality of types selected from the group consisting of group-IV element semiconductors, group-III-V compound semiconductors, and group-II-VI compound semiconductors, and the semiconductor substrate structure according to any one of items 3.1 to 3.5.

[0432] 3.7 Each of the first epitaxial growth layer and the second epitaxial growth layer includes at least one or a plurality of types selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide, and the semiconductor substrate structure according to any one of items 3.1 to 3.5.

[0433] 3.8 The polycrystalline substrate includes at least one or a plurality of types selected from the group consisting of a sintered body, BN, AlN, Al 2 O 3 、Ga 2 O 3 、diamond, carbon, and graphite, and the semiconductor substrate structure according to any one of items 3.1 to 3.7.

[0434] 3.9 The sintered body includes at least one or a plurality of types of sintered bodies selected from the group consisting of group-IV element semiconductors, group-III-V compound semiconductors, and group-II-VI compound semiconductors, and the semiconductor substrate structure according to item 3.8.

[0435] 3.10 The sintered body includes at least one or a plurality of types of sintered bodies selected from the group consisting of silicon carbide, gallium nitride, silicon, aluminum nitride, and gallium oxide, and the semiconductor substrate structure according to item 3.8.

[0436] 3.11 The polycrystalline substrate contains a dopant at a concentration of 5×10 18 / cm 3 or more and 2×10 22 / cm 3 or less, and the semiconductor substrate structure according to any one of items 3.8 to 3.10.

[0437] 3.12 The semiconductor substrate structure according to any one of Items 3.8 to 3.11, wherein the thickness of the polycrystalline substrate is 100 μm or more and 1000 μm or less.

[0438] 3.13 The semiconductor substrate structure according to any one of Items 3.8 to 3.12, wherein the polycrystalline substrate and the second epitaxial growth layer form an ohmic junction.

[0439] 3.14 Each of the first epitaxial growth layer and the second epitaxial growth layer includes an epitaxial growth layer made of 4H-SiC, and the semiconductor substrate structure according to Item 3.13, wherein the epitaxial growth layer made of 4H-SiC has a surface of the (000-1) plane or the (0001) plane.

[0440] 3.15 The semiconductor substrate structure according to any one of Items 3.1 to 3.14, wherein the diameter of the polycrystalline substrate is 100 mm or more.

[0441] 3.16 A power semiconductor device including the semiconductor substrate structure according to any one of Items 3.1 to 3.15.

[0442] 3.17 The power semiconductor device according to Item 3.16, including at least one or a plurality of types selected from the group consisting of a SiC Schottky barrier diode, a SiC-MOSFET, a SiC bipolar transistor, a SiC diode, a SiC thyristor, a SiC insulated gate bipolar transistor, and an LED device.

[0443] 3.18 The power semiconductor device according to Item 3.16, further including a first metal electrode disposed on the surface of the polycrystalline substrate facing the junction surface between the polycrystalline substrate and the second epitaxial growth layer.

[0444] 3.19 The power semiconductor device according to Item 3.18, further including a second metal electrode disposed on the surface of the first epitaxial growth layer facing the junction surface between the second epitaxial growth layer and the first epitaxial growth layer.

[0445] 3.20 The power semiconductor device according to item 3.16, comprising a second metal electrode disposed on the surface of the first epitaxial growth layer facing the bonding surface between the second epitaxial growth layer and the first epitaxial growth layer.

Explanation of symbols

[0446] 10… semiconductor substrate, 11… drift layer, 12… second layer, 12a… buffer layer, 21b… substrate layer, 21… seed SiC semiconductor substrate 211… p-type SiC semiconductor substrate, 212… n-type SiC semiconductor substrate, 212a… thin film of p-type SiC semiconductor, 220… semiconductor substrate, 221… p-type SiC semiconductor layer, 222… n-type SiC semiconductor layer, 230… IGBT 301… semiconductor substrate structure, 310… polycrystalline silicon carbide substrate, 310A… polycrystalline silicon carbide ingot, 312… silicon carbide epitaxial growth layer (first epitaxial growth layer), 313… silicon carbide buffer layer (second epitaxial growth layer), 314… bonding interface layer, 221… power semiconductor device (SiC-SBD), 331… power semiconductor device (SiC-TMOSFET), 351… power semiconductor device (SiC-MOSFET), 450… manufacturing apparatus for polycrystal (SiC sintered body), 494… silicon carbide sintered body material, S… source terminal, D… drain terminal, G… gate terminal, A… anode terminal, K… cathode terminal 501… semiconductor substrate structure, 510… polycrystalline substrate, 512… SiC epitaxial growth layer (first epitaxial growth layer), 513… SiC buffer layer (second epitaxial growth layer), 514… bonding interface layer, 521… power semiconductor device (SiC-SBD), 531… power semiconductor device (SiC-TMOSFET), 551… power semiconductor device (SiC-MOSFET), 650… manufacturing apparatus for polycrystal (SiC sintered body), 694… SiC polycrystalline material, S… source terminal, D… drain terminal, G… gate terminal, A… anode terminal, K… cathode terminal

Claims

1. A semiconductor device in which semiconductor elements are formed on a semiconductor substrate, wherein the semiconductor substrate includes a first layer formed of a single-crystalline SiC semiconductor, and a second layer formed of a SiC semiconductor containing polycrystals, on the first layer, the first layer is formed as a drift layer, a buffer layer up to a predetermined height from the first layer in the second layer, and the remaining portion of the second layer exceeding the predetermined height is formed as a substrate layer, and the second layer also includes a single-crystalline SiC semiconductor. In the second layer, the buffer layer is a single-crystalline having a different impurity concentration from the first layer, and the substrate layer is a polycrystalline semiconductor device.

2. The semiconductor device according to claim 1, wherein the first layer of the semiconductor substrate is an epitaxial growth layer.

3. The semiconductor device according to claim 1 or 2, wherein the drift layer has a thickness of 1 μm or more, the buffer layer has a thickness of 0.1 μm or more, and the substrate layer has a thickness of 10 μm or more.

4. The semiconductor device according to any one of claims 1 to 3, wherein the impurity concentration of the buffer layer is lower than the impurity concentration of the substrate layer.

5. The semiconductor device according to any one of claims 1 to 4, wherein the substrate layer is a p-type SiC semiconductor layer, and the buffer layer is an n-type SiC semiconductor layer.

6. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor element includes at least one of a Schottky barrier diode, a MOSFET, an IGBT, and an LED.

7. The semiconductor device according to any one of claims 1 to 6, wherein the first layer and the second layer are connected without having an interface at the bonding surface.

8. A method for manufacturing a semiconductor device in which semiconductor elements are formed on a semiconductor substrate, wherein the semiconductor substrate includes a first layer formed of a single-crystalline SiC semiconductor, and a second layer formed of a SiC semiconductor containing polycrystals, on the first layer. The method includes providing a semiconductor substrate formed by CVD growth on the surface of the first layer, forming the semiconductor element by using the first layer as a drift layer, a buffer layer up to a predetermined height from the first layer in the second layer, and the remaining portion of the second layer exceeding the predetermined height as a substrate layer, and the second layer of the semiconductor substrate also includes a single-crystalline SiC semiconductor. In the second layer, the The buffer layer is a single crystal with an impurity concentration different from that of the first layer, and the substrate layer is a poly crystalline semiconductor device manufacturing method.

9. The first layer of the semiconductor substrate is formed by epitaxial growth by CVD, according to the claim 8 semiconductor device manufacturing method.

10. The drift layer has a thickness of 1 μm or more, and the buffer layer has a thickness of 0.1 μm or more having, the substrate layer has a thickness of 10 μm or more, according to claim 8 or 9 Semiconductor device manufacturing method.

11. The impurity concentration of the buffer layer is lower than the impurity concentration of the substrate layer, according to the claim 8 to 10 semiconductor device manufacturing method according to any one of the items.

12. The substrate layer is a p-type SiC semiconductor layer, and the buffer layer is an n-type SiC semiconductor layer, according to any one of claims 8 to 11 semiconductor device manufacturing method.

13. The semiconductor element includes at least one of a Schottky barrier diode, a MOSFET, an IGBT, and an LE D, according to any one of claims 8 to 12 semiconductor device manufacturing method.

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