Random access memory circuit and memory system

Abstract

Provided is a random access-type memory which can implement an increase in access speed. This memory circuit 1 comprises: a memory array unit 11 which includes a plurality of memory cells MC, and word lines WL which connect the plurality of memory cells MC to each other and through which a driving voltage for driving the memory cells MC is applied; a driving voltage control unit 23 which controls to generate the driving voltage in which a prepulse is set at a timing corresponding to the rising or falling of a voltage signal that varies stepwise by as much as a prescribed voltage value, apply the driving voltage to terminals TL of the word lines WL, and variably set a time width or a peak value of the prepulse at the driving voltage on the basis of address information that is received from the outside and designates a memory cell MC of an access destination; and a sense amplifier unit 13 which accesses the memory cell MC designated by the address information.

Description

Random access memory circuit and memory system

[0001] The embodiments relate to a random access memory circuit and a memory system.

[0002] Semiconductor memories (such as flash memories and 3D cross-point memories) that have become widespread in recent years have linear wiring sections as word lines for driving memory cells arranged in a row. Because such wiring sections have parasitic resistance and parasitic capacitance, voltage signals propagating through the wiring sections experience delay times determined by these resistances and capacitances. Therefore, in order to increase the access speed of such semiconductor memories, it is important to shorten the delay times of signals in the wiring sections. A technique known as pre-emphasis, which raises the front portion of a pulse waveform applied to the wiring section more than usual, is used to shorten the delay times in such wiring sections. Non-Patent Document 1 describes a technique for optimizing the time width of pre-emphasis to shorten delay times.

[0003] Kazuki Matsuyama and Toru Tanzawa, “A Pre-Emphasis Pulse Generator Insensitive to Process Variation for Driving Large Memory and Panel Display Arrays with Minimal Delay Time”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov. 2019.

[0004] In the conventional technology described above, when targeting random access memories that access memory cells at addresses specified by external commands, the access speed tends to be insufficient. That is, since voltage signals with the same waveform are applied to wiring sections to which multiple memory cells are connected, there is room for improvement in controlling the waveform of voltage signals in random access memories.

[0005] The present embodiment has been made in view of the above-mentioned problems, and aims to provide a random access memory that can achieve high access speeds, and a memory system including the same.

[0006] In order to solve the above problem, a random access memory circuit according to one embodiment of the present disclosure comprises: a memory array section including a plurality of memory cells and a wiring section for connecting the plurality of memory cells to each other and applying a drive voltage to drive the memory cells; a voltage application section that generates a drive voltage having a pre-pulse set at a timing corresponding to the rise or fall of a voltage signal that changes stepwise by a predetermined voltage value, and applies the drive voltage to a terminal of the wiring section; a control section that controls the voltage application section so as to variably set the time width or peak value of the pre-pulse in the drive voltage based on address information received from outside that specifies the memory cell to be accessed; and an access section that accesses the memory cell specified by the address information.

[0007] In the random access memory circuit of the above embodiment, the voltage application unit generates a drive voltage having a pre-pulse set at the rising or falling timing of a step-like voltage signal, and applies the drive voltage to the terminal of the wiring unit. At this time, the control unit changes the time width or peak value of the pre-pulse based on address information received from the outside, and the access unit accesses the memory cell specified by the address information. This allows the memory cell to be accessed using a drive voltage having a pre-pulse with a time width or peak value corresponding to the address of the memory cell, thereby shortening the delay time of the rise of the drive voltage transmitted to the memory cell. As a result, the drive time of the memory cell to be accessed in the random access memory circuit can be shortened each time, thereby achieving an increased access speed.

[0008] According to the embodiment, it is possible to achieve an increase in access speed in a random access memory circuit.

[0009] 1 is a diagram showing a schematic configuration of a memory device including a random access memory circuit according to a preferred embodiment of the present invention. FIG. 2 is a block diagram showing the overall configuration of the memory circuit 1 of FIG. 1. FIG. 3 is a diagram showing the circuit configuration around a memory array section 11 of the memory circuit 1. FIG. 4 is a diagram showing the waveform of a drive voltage generated by a drive voltage control section 23. FIG. 5 is a diagram showing a pre-pulse period T ｐｒｅ The delay time t of the drive voltage at each connection point on the word line WL when ｄｅｌａｙ 1 is a graph showing the results of theoretical calculations. FIG. 2 is a timing chart showing an example of signal waveforms at each part of the memory circuit 1 when the memory cell MC to be accessed is in "range 1" on the near end side. FIG. 3 is a timing chart showing an example of signal waveforms at each part of the memory circuit 1 when the memory cell MC to be accessed is in "range 2" on the far end side. FIG. 4 is a diagram showing waveforms of drive voltages generated in an embodiment.

[0010] Hereinafter, preferred embodiments of the random access memory circuit according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same or corresponding parts are designated by the same reference numerals, and duplicated explanations will be omitted.

[0011] As shown in FIG. 1 , memory circuit 1, which is a random-access memory circuit according to a preferred embodiment of the present invention, can be used as a memory device (memory system) 100 in combination with a memory controller 3. Memory controller 3 is an IC connected to memory circuit 1 via a system bus BUS to transmit and receive electrical signals and controls the operation of memory circuit 1. Memory controller 3 writes data to memory circuit 1 or reads data from memory circuit 1, i.e., accesses memory circuit 1, via the system bus BUS. In detail, in response to an external request, memory controller 3 transmits, via the system bus BUS, to memory circuit 1, address information for specifying an address (memory cell) to be accessed within memory circuit 1 and a command requesting access by specifying the type of access. The types specified by the command include reading data from a memory cell within memory circuit 1 and writing data to a memory cell within memory circuit 1. In response to this, memory controller 3 transmits and receives data to be written to or read from the specified address within memory circuit 1 to and from memory circuit 1.

[0012] 2 is a block diagram showing the overall configuration of memory circuit 1. Memory circuit 1 is a semiconductor memory having a plurality of transistors (MOSFETs) mounted on a semiconductor chip, and as shown in Fig. 2, is configured to include a memory array section 11, a sense amplifier section (access section) 13, an input buffer circuit 15, an output buffer circuit 17, address decoders 19 and 21, a drive voltage control section (voltage application section, control section) 23, and a line decoder 25. The memory array section 11, the sense amplifier section 13, the input buffer circuit 15, the output buffer circuit 17, the address decoders 19 and 21, the drive voltage control section 23, and the line decoder 25 are formed on the same semiconductor chip.

[0013] The memory array unit 11 is configured by arranging a plurality of memory cells, each of which is made up of transistors (MOSFETs), in a two-dimensional array, and has the function of storing binary or multi-valued data. The memory array unit 11 includes a plurality of subarray units, each of which has a plurality of (e.g., 1024) memory cells arranged one-dimensionally (linearly).

[0014] The input buffer circuit 15 receives address information and commands from the memory controller 3 via the system bus BUS. The address decoder 19 converts the address information into a row address (hereinafter referred to as a row address) that specifies a sub-array unit to be accessed within the memory array unit 11. The address decoder 21 converts the address information into a column address (hereinafter referred to as a column address) that specifies a memory cell within the sub-array unit to be accessed.

[0015] The sense amplifier unit 13 measures the current or voltage of the bit line electrically connected to each memory cell in the subarray unit of the memory array unit 11, and detects the value of the data stored in each memory cell according to the current or voltage (performs data sensing). That is, the sense amplifier unit 13 performs data sensing on the memory cell corresponding to the column address output from the address decoder 21, and outputs the detected data to the output buffer circuit 17.

[0016] The drive voltage control unit 23 controls the operation of writing or reading data to or from a memory cell at a predetermined address in the memory circuit 1 in accordance with address information and a command received from the memory controller 3 via the input buffer circuit 15. For example, when writing data, the drive voltage control unit 23 controls the input buffer circuit 15 and a data writing circuit unit (not shown) to store the data in a memory cell at the predetermined address. When reading data, the drive voltage control unit 23 controls the line decoder 25 and the sense amplifier unit 13 to read the data from the memory cell at the predetermined address. The drive voltage control unit 23 includes a control circuit such as a small processor and a voltage signal generation circuit including an amplifier, a transistor, etc.

[0017] Specifically, when a command requests data reading, the drive voltage control unit 23 generates a drive voltage in which the time width or peak value of a pre-pulse is set corresponding to the column address specified by the address information, based on the address information (details will be described later). The drive voltage control unit 23 also controls the timing at which data sensing by the sense amplifier unit 13 starts and the timing at which data is output from the sense amplifier unit 13.

[0018] The line decoder 25 selects a sub-array unit corresponding to the row address input from the address decoder 19, and applies the drive voltage generated by the drive voltage control unit 23 to the selected sub-array unit. The output buffer circuit 17 outputs the value of data detected by the sense amplifier unit 13 for the memory cell corresponding to the column address to the memory controller 3 via the system bus BUS.

[0019] 3 shows the circuit configuration around the memory array unit 11 of the memory circuit 1. Each subarray unit 11a in the memory array unit 11 has a plurality of (e.g., 1024) memory cells MC arranged linearly and word lines WL, which are linear wiring portions electrically connected to the memory cells MC and for applying a drive voltage to drive the memory cells MC. For example, if the memory cells MC are configured with FETs, the word lines WL are electrically connected to the gates of the memory cells MC. However, in this embodiment, the plurality of memory cells MC are not limited to being arranged linearly, and may be arranged along a curved line or a broken line. In such a case, the word lines WL are formed in a curved or broken line shape to connect the plurality of memory cells MC to each other.

[0020] In detail, the word line WL has a terminal TL for applying a driving voltage from the line decoder 25, and the gates of the plurality of memory cells MC are connected to connection points CL provided at predetermined intervals along the word line WL from the terminal TL side. １ , C.L. ２ , C.L. ３ , C.L. ４ , ... are electrically connected to a word line WL. When a row address of the sub-array unit 11 a is designated by address information, a switch 27 included in the line decoder 25 is turned on, and a drive voltage is selectively applied to a terminal TL of this word line WL from the drive voltage control unit 23.

[0021] Furthermore, each memory cell MC in the subarray unit 11a is electrically connected to a plurality of sense amplifiers SA (e.g., 1024 sense amplifiers SA) provided in the sense amplifier unit 13 corresponding to each memory cell MC via bit lines BL, which are wiring components. For example, if the memory cell MC is configured with an FET, the sense amplifier SA is electrically connected to the drain of the memory cell MC. Each sense amplifier SA in the sense amplifier unit 13 is provided in common to each corresponding memory cell MC in the multiple subarray units 11a. When reading data from each memory cell MC, these sense amplifiers SA detect the drain current (or drain voltage) of each memory cell MC in response to a drive voltage, which is a step-like voltage signal applied to the word line WL, and determine the value of the data stored in each memory cell MC by comparing the drain current (or drain voltage) with a threshold value. At this time, the sense amplifier SA corresponding to the column address output from the address decoder 21 is selected, and the data value determined by the selected sense amplifier SA is output to the output buffer circuit 17.

[0022] Next, the drive voltage generated by the drive voltage control unit 23 will be described in detail.

[0023] 4 shows the waveform of the drive voltage generated by the drive voltage control unit 23. Assuming that time t=0 is the start of an access operation to the memory cells MC of each sub-array unit 11a, the drive voltage control unit 23 generates a drive voltage in which a pre-pulse with a peak value (α×E, where α is a preset real number) is set at the timing of time t=0 corresponding to the rising edge of a voltage signal that changes (rises) in a stepwise manner by a predetermined voltage value E. At this time, the drive voltage control unit 23 sets a period (time width) T during which the pre-pulse is set from time t=0. ｐｒｅ the connection point CL of the memory cell MC to be accessed on the word line WL. １ , C.L. ２ , C.L. ３ , C.L. ４In other words, the drive voltage control unit 23 sets a variable period T ｐｒｅ The driving voltage is set so that a pre-emphasis voltage of a voltage value α×E is generated.

[0024] In detail, the drive voltage control unit 23 determines the row address of the memory cell MC designated by the address information, and determines whether the connection point CL of the memory cell MC is a １ , C.L. ２ , C.L. ３ , C.L. ４ , . . . and the terminal TL, and the pre-pulse period T ｐｒｅ The distance here refers to the distance along the path of the word line WL. As an example, the drive voltage control unit 23 adjusts the range of the distance between the connection point of the memory cell MC and the terminal TL by adjusting the distance between the connection point CL closest to the terminal TL on the word line WL and the １ The range is divided into a range "range 1" from the midpoint to the terminal TL and a range "range 2" from the midpoint to the farthest connection point from the terminal TL. If the specified range is "range 1", the period T ｐｒｅ for a relatively short period T Ｓ If the specified range is "range 2", the period T ｐｒｅ for a relatively long period T Ｌ However, the range of the distance between the connection point of the memory cell MC and the terminal TL specified by the drive voltage control unit 23 is not limited to two ranges, and may be three or more ranges. In this case, the drive voltage control unit 23 sets the period T ｐｒｅ Increase or decrease.

[0025] The word line WL, through which the drive voltage generated by the drive voltage control unit 23 propagates, can be considered equivalent to a transmission line in which impedance components (parasitic resistance components) and capacitance components (parasitic capacitance components) excluding conductance components and reactance components are distributed. In detail, the word line WL can be considered as a transmission line with a length of 1 [m] from the terminal TL to the farthest connection point, a resistance per unit length of R [Ω / m], and a capacitance per unit length of C [F / m], and the total resistance can be estimated as R×1 [Ω] and the total capacitance as C×1 [F]. In FIG. 5, the pre-pulse period T ｐｒｅ 1 shows a graph of the results of theoretical calculations of the delay time of the drive voltage at each connection point on the word line WL when the delay time t is changed. Here, the position x of the terminal TL to which the drive voltage is applied is set to x=0, and the position x of the connection point at the farthest end of the word line WL is set to x=1. In addition, the delay time t ｄｅｌａｙ The theoretical time required for the voltage at an arbitrary position x on the word line WL to reach a voltage value of (1-β)×E (where β=0.1) is estimated as the time required for the voltage to reach a voltage value of (1-β)×E (where β=0.1).

[0026] In this way, the delay time t ｄｅｌａｙ The period T of the pre-pulse to reduce ｐｒｅ It can be seen that the period T varies depending on the position of the connection point on the word line WL. For example, at the position x=1 of the farthest connection point, ｐｒｅ = 0.74 ms, the delay time t ｄｅｌａｙ It can be seen that the minimum value of 0.9 ms can be achieved at the other connection points. ｐｒｅ By setting the delay time t ｄｅｌａｙ It can also be seen that the delay time t ｄｅｌａｙ The duration of the pre-pulse T ｐｒｅ At this time, the drive voltage control unit 23 sets the pre-pulse period T at each connection point with a value proportional to the magnitude of the resistance R and capacitance C of the word line WL. ｐｒｅ Set.

[0027] The drive voltage control unit 23 controls the timing at which the sense amplifier unit 13 starts sensing data and the timing at which data is output from the sense amplifier unit 13 in accordance with the drive voltage control as described above.

[0028] That is, the drive voltage control unit 23 increases or decreases the waiting time (hereinafter referred to as latency) from the start timing of the access operation until the start of data sensing and data output, depending on the row address of the memory cell MC to be accessed. More specifically, the drive voltage control unit 23 variably sets the latency depending on the range of the distance between the connection position on the word line WL of the memory cell MC determined by the row address and the terminal TL. This waiting time is determined depending on the connection position on the word line WL and the set pre-pulse period T ｐｒｅ and the estimated delay time t ｄｅｌａｙ At this time, the drive voltage control unit 23 sets the latency corresponding to the memory cell MC to be accessed with a value proportional to the magnitude of the resistance R and capacitance C of the word line WL.

[0029] 6 shows an example of signal waveforms at various parts of the memory circuit 1 when the memory cell MC to be accessed is in "range 1" on the near end side, with part (a) showing the waveform of the drive voltage applied to the memory cell MC, part (b) showing the waveform of the data signal output from the sense amplifier SA, and part (c) showing the waveform of the data signal output from the output buffer circuit 17. Also, Fig. 7 shows an example of signal waveforms at various parts of the memory circuit 1 when the memory cell MC to be accessed is in "range 2" on the far end side, with part (a) showing the waveform of the drive voltage applied to the memory cell MC, part (b) showing the waveform of the data signal output from the sense amplifier SA, and part (c) showing the waveform of the data signal output from the output buffer circuit 17.

[0030] As shown in FIGS. 6 and 7, the delay time t of the applied drive voltage varies depending on the position of the memory cell MC to be accessed on the word line WL. ｄｅｌａｙ The waveform of the driving voltage is controlled so that the delay time t ｄｅｌａｙ The data sensing period T of the sense amplifier SA corresponds toｓｅｎｓｅ The latency is set to t ｄｅｌａｙ and the data sensing period T ｓｅｎｓｅ The data output period t of the output buffer circuit 17 corresponds to ｏｕｔ This controls the latency from the start of the access operation to the data output. ｒｅａｄ can be reduced by about 20% on average compared to when the waveform of the drive voltage is not controlled.

[0031] Returning to FIG. 1, the memory controller 3 determines the read access time t ｒｅａｄ In response to the command, the memory controller 3 has a function of controlling the waiting time from sending a command until reading out the data output from the memory circuit 1. In detail, the memory controller 3 increases or decreases the waiting time from sending a command until reading out the data output on the system bus BUS according to the row address of the memory cell MC specified by the address information. This waiting time is determined based on the read access time t ｒｅａｄ This allows the access time when the memory controller 3 accesses the memory circuit 1 to be minimized.

[0032] The effects of the memory device 100 of the above-described embodiment will be described.

[0033] In the memory circuit 1 described above, the drive voltage control unit 23 generates a drive voltage in which a pre-pulse is set at the timing of the rising edge of a step-like voltage signal, and the line decoder 25 applies the drive voltage to the terminal TL of the word line WL. At this time, the drive voltage control unit 23 changes the time width of the pre-pulse based on address information received from the outside, and the sense amplifier unit 13 accesses the memory cell MC specified by the address information. As a result, the memory cell MC can be driven using a drive voltage having a pre-pulse with a time width corresponding to the row address of the memory cell MC to be accessed, and the rise delay time t of the drive voltage transmitted to the memory cell MC is reduced. ｄｅｌａｙAs a result, the drive time of the memory cell MC to be accessed in the random access memory circuit 1 can be shortened each time, and the access speed can be increased.

[0034] Here, the drive voltage control unit 23 is controlled to increase or decrease the time width of the pre-pulse depending on the distance between the terminal TL and the connection position of the memory cell MC specified by the address information and the word line WL. In this case, the time width of the pre-pulse is increased or decreased depending on the distance between the connection position of the memory cell MC on the word line WL and the terminal TL to which the drive voltage is applied, thereby reducing the delay time t ｄｅｌａｙ As a result, the access speed can be easily increased.

[0035] Furthermore, the sense amplifier unit 13 increases or decreases the waiting time from when access is requested until data access depending on the distance between the connection position of the memory cell MC specified by the address information and the word line WL and the terminal TL. In this way, the waiting time until data access to the memory cell MC is increased or decreased depending on the distance between the connection position of the memory cell MC on the word line WL and the terminal TL to which the drive voltage is applied, thereby making it possible to control the speed of access to the memory cell MC by adjusting the delay time t ｄｅｌａｙ As a result, the access speed can be increased reliably.

[0036] The drive voltage control unit 23 also controls the pre-pulse so as to set a time width corresponding to the magnitude of the parasitic resistance and parasitic capacitance in the word line WL. In this case, the delay time t ｄｅｌａｙ As a result, an increase in access speed can be achieved in accordance with memory circuits 1 having different electrical characteristics.

[0037] Furthermore, the sense amplifier unit 13 sets the data access wait time to a time corresponding to the magnitude of the parasitic resistance and parasitic capacitance in the word line WL. In this case, the speed of data access to the memory cell MC can be optimized to a speed corresponding to the electrical characteristics of the word line WL. As a result, an increase in access speed corresponding to memory circuits 1 with different electrical characteristics is realized.

[0038] Alternatively, the memory device 100 has a configuration including the memory circuit 1 and the memory controller 3, thereby speeding up access to the memory cells MC in the memory circuit 1. In this memory device 100, the memory controller 3 increases or decreases the latency from sending a command to reading data according to the position of the memory cell MC specified by address information. With this configuration, the memory controller 3 speeds up reading of data from the memory circuit 1.

[0039] The present invention is not limited to the above-described embodiment, and the configuration of the above-described embodiment can be modified in various ways.

[0040] The above embodiment is not limited to storing binary (1-bit) data in the memory cell MC, but may also operate to store multi-level (2-bit or more) data.

[0041] Furthermore, the above-described embodiment and modified examples are not limited to using a drive voltage that increases in a stepwise manner, and may be configured to apply a drive voltage that decreases in a stepwise manner. In this case, the drive voltage control unit 23 generates a drive voltage in which a pre-pulse is set at a timing corresponding to the falling edge of the step-like voltage signal.

[0042] In the above embodiment, the time width of the pre-pulse of the driving voltage is set to be variable depending on the position of the memory cell MC to be accessed, but the peak value of the pre-pulse may also be set to be variable depending on the position.Furthermore, both the time width and the peak value of the pre-pulse may also be set to be variable depending on the position of the memory cell MC.

[0043] Furthermore, in the above embodiment, the waveform of the drive voltage is controlled when reading data from the memory cell MC, but the waveform of the drive voltage may be controlled in the same manner when writing data to the memory cell MC.

[0044] In addition, when controlling the writing of data to memory cells MC, the memory controller 3 constituting the memory device 100 of the above embodiment preferably operates to write important data that needs to be read as quickly as possible to an address corresponding to a connection point on the word line WL that is the closest to the terminal TL.

[0045] Furthermore, the above embodiment is not limited to storing binary (1-bit) data in the memory cell MC, but may operate to store multi-level (2-bit or more) data. Furthermore, the above example is not limited to using a drive voltage that increases in a stepwise manner, but may be configured to apply a drive voltage that decreases in a stepwise manner.

[0046] 8, (a) shows the waveform of the drive voltage when 1-bit data is stored, (b) shows the waveform of the drive voltage when 2-bit data is stored, and (c) shows the waveform of the drive voltage that drops in a step-like manner. Thus, when reading 1-bit data, a waveform in which a pre-pulse is set for a voltage signal that rises to a voltage value E is used, and when reading 2-bit data, a drive voltage that rises in a step-like manner in multiple stages to multiple voltage values ​​E1, E2, E3 (E1<E2<E3) in sequence and has pre-pulses set at multiple timings synchronized with (corresponding to) the rising timing of each voltage value may be used. Alternatively, when reading 2-bit data, a drive voltage that first rises in a step-like manner to a voltage value E3 and then drops in a step-like manner in multiple stages to voltage values ​​E2 and E1 in sequence (E1<E2<E3) may be used. In this case, a pre-pulse with a high peak value in the positive voltage direction relative to the rising width is set in synchronization with the rising timing of voltage E3 first (overdrive), and then pre-pulses with a high peak value in the negative voltage direction relative to the falling width are set in synchronization with the falling timing of voltages E2 and E1 (underdrive).In these cases, too, the change in the time width of each pre-pulse is controlled based on the address information.

[0047] In the above embodiment, it is also preferable that the control unit controls the pre-pulse so as to increase or decrease its time width or peak value depending on the distance between the terminal and the connection position of the memory cell and the wiring unit specified by the address information. In this case, the pre-pulse time width or peak value is increased or decreased depending on the distance between the connection position of the memory cell in the wiring unit and the terminal to which the drive voltage is applied, thereby easily shortening the delay time of the rise of the drive voltage transmitted to the memory cell. As a result, an increase in access speed is easily achieved. Note that the "distance" here refers to the distance along the path of the wiring unit.

[0048] It is also preferable that the access by the access unit is to read data from the memory cells, in which case data can be output from the random access memory circuit at high speed.

[0049] It is also preferable that the access unit increases or decreases the waiting time from when an access is requested until the access is performed, depending on the distance between the terminal and the connection position of the memory cell specified by the address information and the wiring unit. In this way, the waiting time until the access to the memory cell is increased or decreased depending on the distance between the connection position of the memory cell in the wiring unit and the terminal to which the drive voltage is applied, so that the access speed to the memory cell can be optimized to a speed corresponding to the delay time of the rise of the drive voltage. As a result, an increase in access speed is reliably achieved.

[0050] It is also preferable that the control unit controls the pre-pulse to have a time width or a peak value corresponding to the magnitude of the parasitic resistance and the parasitic capacitance in the wiring portion. In this case, the delay time of the rise of the drive voltage transmitted to the memory cell can be shortened according to the electrical characteristics of the wiring portion. As a result, an increase in the access speed corresponding to memory circuits with different electrical characteristics can be realized.

[0051] It is also preferable that the access unit sets the waiting time to a time corresponding to the magnitude of the parasitic resistance and parasitic capacitance in the wiring unit. In this case, the speed of access to the memory cell can be optimized to a speed corresponding to the electrical characteristics of the wiring unit. As a result, an increase in the access speed corresponding to memory circuits with different electrical characteristics can be achieved.

[0052] Alternatively, a memory system according to another aspect of the present invention includes the random access memory circuit described above, and a control circuit connected to the random access memory circuit via a bus and transmitting address information and commands requesting access to the random access memory circuit. In this memory system, the control circuit speeds up access to memory cells in the random access memory circuit in response to the address information and commands.

[0053] Here, it is also preferable that the control circuit transmits a command requesting the reading of data from a memory cell specified by the address information, reads the data output from the random access memory circuit in response to the transmission of the command, and increases or decreases the waiting time from the transmission of the command to the reading of the data depending on the position of the memory cell specified by the address information. With this configuration, when reading data output from a memory cell in the random access memory circuit to the bus, the control circuit increases or decreases the waiting time for reading the data from the bus depending on the position of the memory cell. This increases or decreases the speed at which the control circuit reads data from the random access memory circuit.

[0054] One aspect of the present disclosure is to use a random access memory circuit and a memory system, and to achieve an increased access speed.

[0055] 1... random access memory circuit, 3... memory controller (control circuit), 11... memory array section, 13... sense amplifier section (access section), 23... drive voltage control section (voltage application section, control section), 100... memory device (memory system), MC... memory cell, WL... word line (wiring section), T ｐｒｅ ...period (time width), TL...terminal, BUS...system bus.

Claims

1. A random access memory circuit comprising: a memory array section including a plurality of memory cells and a wiring section for connecting the plurality of memory cells to each other and applying a drive voltage to drive the memory cells; a voltage application section that generates a drive voltage with a pre-pulse set at a timing corresponding to the rise or fall of a voltage signal that changes stepwise by a predetermined voltage value, and applies the drive voltage to a terminal of the wiring section; a control section that controls the voltage application section to variably set the time width or peak value of the pre-pulse in the drive voltage based on address information received from outside that specifies the memory cell to be accessed; and an access section that accesses the memory cell specified by the address information.

2. The random access memory circuit according to claim 1, wherein the control unit controls to increase or decrease the time width or peak value of the pre-pulse depending on the distance between the terminal and the connection position of the memory cell and the wiring unit specified by the address information.

3. The random access memory circuit according to claim 1 or 2, wherein the access by said access unit is to read data from said memory cells.

4. A random access memory circuit according to any one of claims 1 to 3, wherein the access unit increases or decreases the waiting time from when access is requested until the access is actually performed, depending on the distance between the terminal and the connection position of the memory cell specified by the address information and the wiring unit.

5. A random access memory circuit according to any one of claims 1 to 4, wherein the control unit controls to set the time width or peak value of the pre-pulse corresponding to the magnitude of the parasitic resistance and parasitic capacitance in the wiring section.

6. The random access memory circuit according to claim 4, wherein said access section sets said waiting time to a time corresponding to the magnitude of parasitic resistance and parasitic capacitance in said wiring section.

7. A memory system comprising: a random access memory circuit according to any one of claims 1 to 6; and a control circuit connected to said random access memory circuit via a bus, for transmitting said address information and a command requesting access to said random access memory circuit.

8. The memory system of claim 7, wherein the control circuit transmits the command requesting the reading of data from the memory cell specified by the address information, reads the data output from the random access memory circuit in response to the transmission of the command, and increases or decreases the waiting time from the transmission of the command to the reading of the data in response to the position of the memory cell specified by the address information.

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