Processing of Radar Signals

Abstract

To provide a radar system that efficiently performs signal processing, a vehicle comprising such radar device, and an according method as well as a computer program product.SOLUTION: A radar device conducts the steps of: selecting a set of operands comprising a plurality of operands; determining a common exponent for the operands of the set of operands; normalizing the operands based on the common exponent; compressing each operand by reducing the resolution of its mantissa; and storing the common exponent and the compressed operands in a memory.SELECTED DRAWING: Figure 1

Description

[Technology Field]

[0001] Embodiments of the present invention relate to radar applications, and more particularly to an efficient method for processing radar signals obtained by at least one radar sensor, for example, via at least one antenna. Herein, processing of radar signals refers specifically to radar signals received by the sensor or antenna. [Background technology]

[0002] Multiple radar variations may be used in vehicles for various purposes. For example, radar can be used for blind spot detection (parking assistance, pedestrian protection, cross-traffic), collision mitigation, lane change assistance, and adaptive driving control. In many use cases, radar equipment may be oriented in various directions (e.g., rear, left, right, front), at various angles (e.g., azimuth), and / or at various distances (short, medium, or long range). For example, adaptive driving control may use azimuth angles up to ±18 degrees, and since the radar signal is emitted from the front of the vehicle, a detection range of several hundred meters can be obtained.

[0003] A radar source emits a signal, and a sensor detects the reflected signal. The frequency shift between the emitted signal and the detected signal (for example, based on a moving vehicle emitting a radar signal) can be used to obtain information based on the reflection of the emitted signal. Front-end processing of the signal obtained by the sensor involves a Fast Fourier Transform (FFT), which can produce a signal spectrum, i.e., a signal distributed across the entire frequency range. The amplitude of the signal can indicate the amount of echo, where the peak may represent a target that must be detected and can be used for further processing, such as adjusting the vehicle speed based on another vehicle traveling ahead.

[0004] The radar processing unit can provide various types of outputs, such as commands to the control unit, objects or lists of objects to be post-processed by at least one control unit, and at least one FFT peak to be post-processed by at least one control unit. Utilizing the FFT peak enables high-performance post-processing.

[0005] U.S. Patent Application Publication No. 2016 / 0033631 describes radar data compression that reduces the amount of data that needs to be stored between range FFT and Doppler FFT in a radar system using Fast Chirp Waveform. [Overview of the project] [Problems that the invention aims to solve]

[0006] The objective of the present invention is to improve existing solutions, and in particular to efficiently process signals in a radar system that can ultimately lead to improved target recognition. [Means for solving the problem]

[0007] This problem is solved by the features of the independent claim. Further embodiments can be obtained from the dependent claims.

[0008] The embodiments proposed herein may be based on at least one of the following solutions. In particular, combinations of the following features are also available to achieve the desired results. Features of this method may be combined with features of any device, apparatus, or system, and conversely, features of any device, apparatus, or system may be combined with features of this method.

[0009] The radar system • A step of selecting an operand set containing multiple operands, • A step of finding a common exponent for the operands of the operand pair, • A step of normalizing the operands based on a common exponent, The steps include: compressing each operand by reducing the resolution of the operand's mantissa, The steps include: storing the common exponent and the compressed operands in memory, It is configured to perform the following actions.

[0010] According to one embodiment, the operand is the operand provided by the FFT operation.

[0011] The FFT unit may be provided as part of the radar system or as an external device. The FFT unit is capable of providing FFT results, which are used as operands.

[0012] The FFT calculation may be a first-stage, second-stage, or third-stage FFT calculation performed based on signals acquired (detected, sampled) by the radar device.

[0013] According to one embodiment, multiple operand sets are processed before all operands are compressed and stored in memory.

[0014] According to one embodiment, the operand set is compressed to a predetermined block size.

[0015] The block size may be 64 bits, 128 bits, or any multiple thereof.

[0016] According to one embodiment, the operands of the operand pair are floating-point numbers including a sign, exponent, and mantissa.

[0017] According to one embodiment, the operands of an operand pair are compressed using the resolution of a single mantissa.

[0018] According to one embodiment, the operands of an operand pair are compressed using at least two resolutions obtained by at least two mantissas whose size is reduced compared to the resolution of the uncompressed operand mantissa.

[0019] According to one embodiment, the common exponent is determined based on the operand pair.

[0020] According to one embodiment, the common exponent is determined based on the maximum exponent in the operand pair.

[0021] According to one embodiment, the common exponent is determined based on the operand pair and at least one of an additional value, an offset, or a constant.

[0022] A vehicle provided with at least one radar device described herein is proposed.

[0023] Furthermore, a method for processing a radar signal, comprising: · selecting an operand pair including a plurality of operands; · determining a common exponent for the operands of the operand pair; · normalizing the operands based on the common exponent; · compressing each operand by reducing the resolution of the mantissa of the operand; · storing the common exponent and the compressed operands in a memory is proposed.

[0024] Also proposed is a computer program product directly loadable into the memory of a digital processing device, having software code portions for performing each step of the method described herein.

[0025] Embodiments are described and illustrated with reference to the drawings. The drawings are used to explain the basic scheme and show only aspects necessary for understanding the basic scheme. The drawings are not drawn to scale. The same reference signs in the drawings denote similar features.

Brief Description of the Drawings

[0026] [Figure 1] This is a schematic diagram illustrating the steps for acquiring and saving compressed radar data. [Figure 2] This is a schematic diagram illustrating other methods for acquiring and storing compressed radar data. [Figure 3] Figure 1 shows an example of a compression schema in this table. [Figure 4] This table shows the values ​​of "mantissa 12" (see column 8 in Figure 3), "mantissa 7" (see column 9 in Figure 3), and "mantissa 8" for operands 1 to 8. [Modes for carrying out the invention]

[0027] The method described herein specifically proposes the use of data compression for floating-point representations of values ​​usable in radar processing applications. By compressing data before it is stored in memory, existing memory can be used more efficiently, and a smaller memory space can be required.

[0028] A suitable data format may be floating-point and can be subjected to the compression described above. Radar systems may utilize, for example, 8-bit or 16-bit operand formats.

[0029] Figure 1 is a schematic diagram illustrating the steps for acquiring and storing compressed radar data. The FFT unit 101 provides the FFT results. The operand set (or selection) of the FFT results is determined in the next step 102. In the next step 103, the operands are analyzed and further normalized in step 104 to obtain a shared exponent used for all operands. In the next step 105, the resolution of the operand mantissa is adjusted, and in step 106, the compressed data is stored.

[0030] In step 107, it is checked whether all operands have been compressed. If this is true, the compression is complete (see step 108). If this is not true and there are further operands that need to be compressed, the process returns to step 102. Thus, multiple operand pairs can be compressed using the compression scheme according to steps 103 through 105, and the compressed operand pairs are saved in step 106.

[0031] Therefore, after the FFT stage (which may be the first, second, or third FFT), the FFT result is compressed based on at least one operand pair.

[0032] The operand may be a real number or a complex number, or it may be the real or imaginary number of the selected operand.

[0033] Figure 3 is a table illustrating the compression schema shown in Figure 1. Note that this schema is not a mandatory solution for all types of configurations. The table is used to explain and illustrate the steps performed to achieve compression.

[0034] The first column, "Operand #," indicates the operand number. In this embodiment, eight operands are shown numbered 1 through 8. Here, the eight operands constitute an exemplary operand set.

[0035] The second column, "16-bit floating storage," shows the 16-bit representation of the operand. • The first sign bit (see also column 3), • The following 5 bits (see also column 4) represent the exponent, • The remaining 10 bits (see also column 5) represent the fractional part. Includes.

[0036] The subscript "h" indicates that it is a hexadecimal value. Furthermore, the binary representation of the operands for 16-bit floating storage is shown in the second column.

[0037] Column 6 shows the temporary value "m_tmp", Column 7 shows the temporary value "m_tmp12", Column 8 shows the mantissa "mantissa12", and Column 9 shows the compressed mantissa "mantissa7". Columns 6 through 8 are used to explain the conversion process in more detail.

[0038] The compressed mantissa "mantissa 7" can be obtained by performing the following steps: (1) Based on the indices of the operands shown in column 4, find the highest value among operands 1 to 8. In this embodiment, operand 1 has the highest indices, 1A. h It has this characteristic, and this is selected as the common index. (2) The temporary value "m_tmp" is obtained by extending the MSB (most significant bit, i.e., the leftmost bit) of the binary representation of the fractional part by two bits "01" (by adding two bits "01" to the left of the fractional part value). For operand 2, the 10-bit representation of the fractional part is extended, [Math 1] As shown, the 12-bit representation "m_tmp" is obtained. (3) If the sign is 1, the temporary value "m_tmp12" is obtained by creating two's complement. If the sign is 0, m_tmp12 is equal to m_tmp. The two's complement can be obtained by (i) inverting the bits of m_tmp and (ii) adding 1. Examples for operands 2, 4, 5, and 8 are shown in Figure 3. (4) The mantissa 12 value is obtained by "sign-extending and right-shifting" the "m_tmp12" value, depending on the sign value and the difference between the common exponent and the actual exponent. The following applies to operand 2. The common exponent is 1A. h (=26 10 ) and the operand 2 index is 19 h (=25 10 Therefore, the difference between the exponents is 1. "Sign extension, right shift" involves right-shifting the "m_tmp" value by one bit, which fills the left side of the bit with the sign value, which is 1 in operand 2. As another example, consider operand 3. The difference between the common exponent and the exponent of operand 3 is 7. Since the sign of operand 3 is 0, seven zeros are input to the left, and the value of "m_tmp12" is right-shifted by 7 bits. The results of "sign extension, right shift" are shown in column 8 of the table in Figure 3. (5) The value of "mantissa 7" is determined based on "mantissa 12" as follows: The seven most significant bits of mantissa 12 are obtained, and the eighth most significant bit of the value of mantissa 12 is used to determine whether or not the rounding function is applied. If the eighth most significant bit is 1, the value 1 is added; if the eighth most significant bit is 0, no addition is performed. In other words, if the eighth most significant bit of mantissa 12 is 0, the value of mantissa 7 can be obtained by extracting the seven most significant bits from mantissa 12. This also applies to operands 2, 3, 7, and 8. If the eighth most significant bit of mantissa 12 is 1, the value of mantissa 7 can be obtained by extracting the seven most significant bits from mantissa 12 and adding the binary value 1. This also applies to operands 1, 4, 5, and 6.

[0039] In this way, a common exponent (1A) is used for all operands 1 to 8. h By concatenating the bits of ) to the bits of mantissa 7, we can find the block of compressed data, and from there, the next bit, i.e., [Math 2] This is obtained, where "X" represents an additional (arbitrary) bit. In this embodiment, these three "X" bits are added to fill the 64-bit block.

[0040] The expression in question is, [Math 3] As shown above, it can be rearranged into 4-bit parts, which in hexadecimal is [Math 4] It corresponds to.

[0041] In the second column of the table in Figure 3, the 16-bit floating-point representation requires 128 bits of memory space, which is eight times the amount of 16 bits, while the compressed representation requires only four times the amount of 16 bits, or 64 bits of memory space.

[0042] Figure 2 is a schematic diagram illustrating another method for acquiring and storing compressed radar data. The FFT unit 201 provides the FFT result. The operand set (or selection) of the FFT result is determined in the next step 202. Next, in step 203, the first portion of the operand is compressed using the first compression scheme. In the next step 204, at least one remaining portion of the operand is compressed using at least one additional compression scheme.

[0043] Following steps 203 and 204, in step 205, each compressed data is saved.

[0044] Step 206, following step 204, checks whether all operands have been compressed. If this is true, the compression is complete (see step 207). If this is not true and there are further operands that need to be compressed, return to step 202.

[0045] Thus, the alternative form shown in Figure 2 proposes a combination of different compression schemes rather than a single one. This allows for flexible bit allocation and efficient use of a given block size (e.g., 64 bits). In particular, the size of the mantissa can be varied depending on the compression scheme.

[0046] Based on the embodiment described in Figure 3 above, by providing an 8-bit mantissa "mantissa 8" instead of a 7-bit mantissa "mantissa 7" for the three operands, the three unused bits designated as "X" can be efficiently utilized.

[0047] Therefore, variable-precision coding can be applied so that some operands are preserved with higher precision than others. Based on the example shown above, a lower-precision mantissa "mantissa 7" can be used for operands 1, 3, 5, 7, and 8, while a higher-precision mantissa "mantissa 8" can be used for operands 2, 4, and 6.

[0048] Figure 4 is a table showing the values ​​of "Mantissa 12" (see column 8 in Figure 3), "Mantissa 7" (see column 9 in Figure 3), and "Mantissa 8" for operands 1 to 8.

[0049] The value of mantissa 8 is determined in the same way as the value of mantissa 7. That is, the most significant bit of the 8th value of mantissa 12 is obtained, and the most significant bit of the 9th value of mantissa 12 is used to determine whether or not the rounding function is applied. Therefore, if the most significant bit of the 9th value is 1, the value 1 is added, and if the most significant bit of the 9th value is 0, no addition is performed.

[0050] This allows a common exponent (1A) to be applied to each operand. h By concatenating the bits of ) and the bits of mantissa 7 with the bits of mantissa 8 (operands 2, 4, 6), a 64-bit block of compressed data is obtained. [Math 5] This can be obtained.

[0051] The expression in question is, [Math 6] As shown above, it can be rearranged into 4-bit parts, which in hexadecimal is [Number 7] It corresponds to.

[0052] This compressed representation efficiently utilizes all bits of a 64-bit block.

[0053] Further embodiments, alternative forms, and advantages In the above-described embodiments, the common exponent is determined as the maximum exponent of the selected operand group.

[0054] As an alternative, the common exponent may be pre-set or pre-configured. As another alternative, the common exponent may be determined based on a constant or offset that can be subtracted from the highest exponent of the set operands. In connection with the above embodiments (see particularly the table of FIG. 3), the constant value 5 is subtracted from the highest exponent 1A h to obtain 15, which is used as the common exponent. h is obtained.

[0055] Thus, the embodiments described herein relate to a method for compressing radar signals in which a selected operand group is normalized to a common exponent and the mantissa is adjusted according to the selected common exponent and a predefined precision, so that the floating-point representation is used in an efficient and improved form.

[0056] Such compression can be used for operands used in various areas of radar applications, such as in a given range, Doppler, and / or antenna area.

[0057] Such compression enables efficient use of existing memory space or applications that do not require much physical memory. This increases the flexibility for radar applications that can be implemented, for example, in a vehicle.

[0058] In one or more embodiments, the functions described herein can be implemented at least in part in hardware, for example in a specific hardware component or processor. More generally, the technology may be implemented in hardware, a processor, software, firmware, or a combination thereof. When implemented in software, the functions may be stored or transmitted as one or more instructions or codes on a computer-readable medium, or executed by a hardware-based processing unit. Computer-readable medium may include computer-readable storage media, such as tangible media such as data storage media, or communication media including any medium that enables the transfer of computer programs from one place to another, for example, according to a communication protocol. Thus, computer-readable medium may generally correspond to (1) non-transient tangible computer-readable storage media, or (2) communication media such as signals or carrier waves. Data storage media may be any medium that is accessible to one or more computers or one or more processors and from which instructions, codes and / or data structures for implementing the technology described herein can be obtained. Computer program products may include computer-readable medium.

[0059] Such computer-readable storage media may include, but are not limited to, RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices, other magnetic storage devices, flash memory, or any other media that can be used to store desired program code in the form of instructions or data structures and are accessible from a computer. Any connection may also be appropriately referred to as a computer-readable medium, i.e., a computer-readable communication medium. For example, if instructions are transmitted from a website, server or other remote source using coaxial cable, fiber optic cable, stranded pair, digital subscriber line (DSL), or wireless technology, such as infrared, radio, or microwave, then coaxial cable, fiber optic cable, stranded pair, DSL, or wireless technology, such as infrared, radio, and microwave, are included in the definition of a medium. However, it should be understood that computer-readable storage media and data storage media do not include connections, carriers, signals, or other temporary media, and are intended to be non-temporary tangible storage media. In this specification, the term "disk" includes compact discs (CDs), laser discs, optical discs, digital multipurpose discs (DVDs), floppy disks, and Blu-ray discs. Generally, a "disk" reproduces data magnetically, while a "disc" reproduces data optically using a laser. The above combinations should also be included within the scope of computer-readable media.

[0060] Instructions may be executed by one or more processors, such as one or more central processing units (CPUs), digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPGAs), or other equivalent integrated or individual logic circuits. Therefore, the term “processor” as used herein may refer to any of the above-described structures or other structures, as long as they are suitable for realizing the technology described herein. Furthermore, in some embodiments, the functions described herein may be provided in dedicated hardware and / or software modules configured for encoding and decoding, or incorporated into a combined codec. Moreover, the technology is fully implementable in one or more circuits or logic elements.

[0061] The technology of this disclosure can be implemented in a variety of devices or apparatus, including wireless handsets, integrated circuits (ICs), and sets of ICs (e.g., chipsets). While various components, modules, or units have been described in this disclosure to highlight the functional aspects of devices configured to implement the technology of this disclosure, these may not necessarily be implemented in different hardware units. Rather, as described above, the various units may be combined as a single piece of hardware, or they may be provided by a collection of interacting hardware units, including one or more processors as described above, in conjunction with appropriate software and / or firmware.

[0062] While various exemplary forms of the present invention have been disclosed, it will be apparent to those skilled in the art that various modifications or alterations can be made to achieve some of the advantages of the present invention without departing from the spirit and scope of the invention. It will also be apparent to those skilled in the art that other components performing the same function can be appropriately substituted. Features described with reference to certain figures can be combined with features in other figures, even if not explicitly stated otherwise. Furthermore, the methods of the present invention may be implemented solely in software using appropriate processor instructions, or in a hybrid form utilizing a combination of hardware logic and software logic to achieve the same results. Such modifications to the inventive concept are also intended to be included in the appended claims.

Claims

1. A radar device, comprising: selecting an operand set comprising a plurality of operands; determining a common exponent for the operands of the operand set; normalizing the operands based on the common exponent; compressing each operand by reducing the resolution of the mantissa of said operand; storing the common exponent and the compressed operand in a memory; 1. A radar device configured to:

2. The operands are operands provided by an FFT operation.

10. The device of claim 1.

3. Multiple operand pairs are processed before all operands are compressed and stored in memory.

3. The device of claim 1 or 2.

4. The operand set is compressed to a predetermined block size.

4. Apparatus according to any one of claims 1 to 3.

5. the operands of the operand set are floating-point numbers including a sign, an exponent, and a mantissa; 5. Apparatus according to any one of claims 1 to 4.

6. the operands of the operand set are packed using a resolution of one mantissa; 6. Apparatus according to any one of claims 1 to 5.

7. the operands of the operand set are compressed using at least two resolutions provided by at least two mantissas that are reduced in size from the resolution of the mantissas of the uncompressed operands; 6. Apparatus according to any one of claims 1 to 5.

8. the common exponent is determined based on the set of operands; 8. Apparatus according to any one of claims 1 to 7.

9. the common exponent is determined based on the largest exponent in the set of operands; 9. The device of claim 8.

10. the common exponent is determined based on the set of operands and at least one of an additional value, an offset, or a constant.

10. The device of claim 8 or 9.

11. A vehicle equipped with at least one device according to any one of claims 1 to 10.

12. 1. A method for processing a radar signal, comprising: selecting an operand set comprising a plurality of operands; determining a common exponent for the operands of the operand set; normalizing the operands based on the common exponent; compressing each operand by reducing the resolution of the mantissa of said operand; storing the common exponent and the compressed operand in a memory; A method comprising:

13. A computer program directly loadable into the memory of a digital processing device, comprising software code portions for performing the steps of the method according to claim 12. Computer program.

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