Silicon carbide semiconductor device and method of manufacturing the same

Abstract

To provide a silicon carbide semiconductor device capable of suppressing fluctuations in Vth and stabilizing device characteristics by reducing trapping of charges in an oxide film, and a manufacturing method of the silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device 70 includes a first conductivity type silicon carbide semiconductor substrate 1, a first conductivity type first semiconductor layer 20, a first conductivity type second semiconductor layer 21, a first conductivity type third semiconductor layer 2, a second conductivity type fourth semiconductor layer 6, a first conductive type first semiconductor region 7, a gate insulating film 9, a gate electrode 10, a first electrode 12, and a second electrode 13. When a current is passed from the first electrode 12 to the second electrode 13, the peak emission intensity around the wavelength of 390 nm is lower than the peak emission intensity around the wavelength of 500 nm.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

Background Art

[0002] Silicon carbide (SiC) is expected as a next-generation semiconductor material to replace silicon (Si). A semiconductor device using silicon carbide as a semiconductor material (hereinafter referred to as a silicon carbide semiconductor device) has various advantages compared with a conventional semiconductor device using silicon as a semiconductor material, such as being able to reduce the resistance of the device in the on state to one-hundredth or less, and being usable in an environment at a higher temperature (200°C or higher). This is due to the characteristics of the material itself that the bandgap of silicon carbide is about three times larger than that of silicon, and the dielectric breakdown field strength is nearly one order of magnitude larger than that of silicon.

[0003] As silicon carbide semiconductor devices, a Schottky Barrier Diode (SBD), and vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with a planar gate structure or a trench gate structure have been commercialized so far.

[0004] The planar gate structure is a MOS gate structure in which a flat MOS gate is provided on the front surface of a semiconductor substrate. The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed in a direction perpendicular to the front surface of the semiconductor substrate along the side wall of the trench. Therefore, compared with the planar gate structure in which a channel is formed along the front surface of the semiconductor substrate, the unit cell (constituent unit of the device) density per unit area can be increased, and the current density per unit area can be increased, which is advantageous in terms of cost.

[0005] FIG. 12 is a cross-sectional view showing a trench gate structure of a conventional silicon carbide semiconductor device. The structure of the conventional silicon carbide semiconductor device will be described by taking the trench type MOSFET 170 as an example. The trench gate structure is an n + -type silicon carbide epitaxial layer 102 is deposited on the front surface of the n - -type silicon carbide substrate 101. An n - -type high-concentration region 105 is provided on the surface side opposite to the n + -type silicon carbide substrate side of the n-type silicon carbide epitaxial layer. A first p + -type base region 103 is selectively provided between the trenches 116 on the surface of the n-type high-concentration region 105. A second p + -type base region 104 is selectively provided in the n-type high-concentration region 105 so as to cover the entire bottom surface of the trench 116.

[0006] The MOS gate of the trench gate structure is composed of a p-type base layer 106, an n + -type source region 107, a p + -type contact region 108, a trench 116, a gate insulating film 109, and a gate electrode 110. Note that the p + -type contact region 108 may not be provided.

[0007] Also, an interlayer insulating film 111 is provided on the gate electrode 110, and a source electrode 112 in contact with the n + -type source region 107 and the p + -type contact region 108 is provided in the opening of the interlayer insulating film 111. A barrier metal 114 may be provided between the interlayer insulating film 111 and the source electrode 112. A back surface electrode 113 serving as a drain electrode is provided on the back surface of the n + -type silicon carbide substrate 101.

[0008] The vertical MOSFET having such a structure incorporates a parasitic pn diode formed by the p-type base layer 106 and the n - -type silicon carbide epitaxial layer 102 between the source and the drain. This parasitic pn diode can be operated by applying a high potential to the source electrode 112, and the p +From the p-type contact region 108, current flows through the p-type base layer 106 and the n - -type silicon carbide epitaxial layer 102 in the direction of the n + -type silicon carbide substrate 101. Thus, unlike an IGBT, a MOSFET incorporates a parasitic pn diode, so the free-wheeling diode (FWD) used in an inverter can be omitted, contributing to cost reduction and miniaturization. Hereafter, the parasitic pn diode of the MOSFET will be referred to as the body diode.

[0009] Here, the p + -type contact region 108 contains holes (minority carriers), and the n + -type silicon carbide substrate 101 and the n - -type silicon carbide epitaxial layer 102 contain electrons. Therefore, when current flows through the body diode, holes are injected from the p + -type contact region 108, and recombination of electrons and holes occurs in the n - -type silicon carbide epitaxial layer 102 or the n + -type silicon carbide substrate 101. At this time, if there are defects in the crystal of the n + -type silicon carbide substrate 101, due to the recombination energy corresponding to the bandgap (3 eV) generated, basal plane dislocations (BPD), which are a type of crystal defect existing in the n + -type silicon carbide substrate 101, move, and single Shockley-type stacking faults (1SSF) sandwiched between two basal plane dislocations expand.

[0010] When the stacking faults expand, the stacking faults make it difficult for current to flow, so the on-resistance of the MOSFET and the forward voltage of the body diode increase. If such an operation continues, the stacking faults expand cumulatively, so the losses generated in the inverter circuit increase over time, and the amount of heat generation also increases, leading to device failure.

[0011] Therefore, as shown in FIG. 12, the n -An n-type boundary layer 120 and a high-concentration n-type buffer layer 121 are provided between the silicon carbide epitaxial layer 102 of the p-type and the n-type silicon carbide substrate 101. For example, by forming a highly doped layer such as the high-concentration n-type buffer layer 121 doped with a high concentration of nitrogen (N), a lifetime killer is introduced to promote the recombination of holes from the n-type silicon carbide epitaxial layer 102 and control the hole concentration reaching the n-type silicon carbide substrate 101, thereby suppressing the generation and area expansion of stacking defects. Also, the n-type boundary layer 120 is doped with, for example, nitrogen at an impurity concentration lower than that of the n-type silicon carbide substrate 101. The n-type boundary layer 120 is provided to prevent the crystal defects of the n-type silicon carbide substrate 101 from being transmitted to the n-type silicon carbide epitaxial layer 102. + type silicon carbide substrate 101, a hole concentration reaching the n-type silicon carbide substrate 101 is controlled to suppress the generation and area expansion of stacking defects. Also, the n-type boundary layer 120 is doped with, for example, nitrogen at an impurity concentration lower than that of the n-type silicon carbide substrate 101. The n-type boundary layer 120 is provided to prevent the crystal defects of the n-type silicon carbide substrate 101 from being transmitted to the n-type silicon carbide epitaxial layer 102. + type buffer layer 121 doped with a high concentration of nitrogen (N), a lifetime killer is introduced to promote the recombination of holes from the n-type silicon carbide epitaxial layer 102 and control the hole concentration reaching the n-type silicon carbide substrate 101, thereby suppressing the generation and area expansion of stacking defects. Also, the n-type boundary layer 120 is doped with, for example, nitrogen at an impurity concentration lower than that of the n-type silicon carbide substrate 101. The n-type boundary layer 120 is provided to prevent the crystal defects of the n-type silicon carbide substrate 101 from being transmitted to the n-type silicon carbide epitaxial layer 102. + type buffer layer 121 doped with a high concentration of nitrogen (N), a lifetime killer is introduced to promote the recombination of holes from the n-type silicon carbide epitaxial layer 102 and control the hole concentration reaching the n-type silicon carbide substrate 101, thereby suppressing the generation and area expansion of stacking defects. Also, the n-type boundary layer 120 is doped with, for example, nitrogen at an impurity concentration lower than that of the n-type silicon carbide substrate 101. The n-type boundary layer 120 is provided to prevent the crystal defects of the n-type silicon carbide substrate 101 from being transmitted to the n-type silicon carbide epitaxial layer 102. - type silicon carbide epitaxial layer 102 and control the hole concentration reaching the n-type silicon carbide substrate 101, thereby suppressing the generation and area expansion of stacking defects. Also, the n-type boundary layer 120 is doped with, for example, nitrogen at an impurity concentration lower than that of the n-type silicon carbide substrate 101. The n-type boundary layer 120 is provided to prevent the crystal defects of the n-type silicon carbide substrate 101 from being transmitted to the n-type silicon carbide epitaxial layer 102. + type silicon carbide substrate 101, a hole concentration reaching the n-type silicon carbide substrate 101 is controlled to suppress the generation and area expansion of stacking defects. Also, the n-type boundary layer 120 is doped with, for example, nitrogen at an impurity concentration lower than that of the n-type silicon carbide substrate 101. The n-type boundary layer 120 is provided to prevent the crystal defects of the n-type silicon carbide substrate 101 from being transmitted to the n-type silicon carbide epitaxial layer 102. + type silicon carbide substrate 101, a hole concentration reaching the n-type silicon carbide substrate 101 is controlled to suppress the generation and area expansion of stacking defects. Also, the n-type boundary layer 120 is doped with, for example, nitrogen at an impurity concentration lower than that of the n-type silicon carbide substrate 101. The n-type boundary layer 120 is provided to prevent the crystal defects of the n-type silicon carbide substrate 101 from being transmitted to the n-type silicon carbide epitaxial layer 102. + type silicon carbide substrate 101 from being transmitted to the n-type silicon carbide epitaxial layer 102. - type silicon carbide epitaxial layer 102.

[0012] Also, it is known that a semiconductor device having a low on-resistance can be obtained by a substrate made of silicon carbide having a single crystal structure having a physical property such that the ratio of the peak intensity near a wavelength of 500 nm to the peak intensity near a wavelength of 390 nm in photoluminescence measurement is 0.1 or less (see Patent Document 1 below).

[0013] Also, by implanting protons at a concentration of 1×10 or more and 1×10 or less per cm in a region 3 μm or more from the surface on the semiconductor substrate side, a silicon carbide semiconductor device capable of suppressing the expansion of stacking defects stably at low cost is known (see Patent Document 2 below). 13 / cm 3 above 1×10 15 / cm 3 below, a silicon carbide semiconductor device capable of suppressing the expansion of stacking defects stably at low cost is known (see Patent Document 2 below).

Prior Art Documents

Patent Documents

[0014]

Patent Document 1

Patent Document 2

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0015] When an electric current is applied to the body diode of a silicon carbide semiconductor device, electrons and holes recombine to emit light. At this time, band-edge emission with a wavelength near 390 nm and emission with a wavelength near 500 nm caused by impurity levels due to ion implantation occur. Under conditions of high temperature and high current close to the rated value of the silicon carbide semiconductor device, the intensity of the band-edge emission near 390 nm becomes strong. Due to this emission, charges are excited and trapped in the oxide film constituting the gate insulating film 109. As a result, there is a problem that the threshold voltage (Vth) fluctuates due to the charges in the oxide film, and the device characteristics deteriorate. For example, during operation, the on-resistance may increase and losses may occur.

[0016] In order to solve the problems caused by the above-described conventional technology, an object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can suppress fluctuations in Vth and stabilize device characteristics by reducing the trapping of charges in the oxide film.

MEANS FOR SOLVING THE PROBLEMS

[0017] In order to solve the above-described problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is provided on the front surface of the silicon carbide semiconductor substrate of the first conductivity type. On the surface of the first semiconductor layer opposite to the side facing the silicon carbide semiconductor substrate with an impurity concentration higher than that of the first semiconductor layerA second semiconductor layer of a first conductivity type is provided. A third semiconductor layer of the first conductivity type having an impurity concentration lower than that of the silicon carbide semiconductor substrate is provided on the surface of the second semiconductor layer opposite to the side of the silicon carbide semiconductor substrate. A fourth semiconductor layer of a second conductivity type is provided on the surface of the third semiconductor layer opposite to the side of the silicon carbide semiconductor substrate. A first semiconductor region of the first conductivity type is selectively provided in the surface layer of the fourth semiconductor layer opposite to the side of the silicon carbide semiconductor substrate. A gate electrode is provided via a gate insulating film on at least a part of the surface of the fourth semiconductor layer sandwiched between the first semiconductor region and the third semiconductor layer. A first electrode is provided on the surfaces of the fourth semiconductor layer and the first semiconductor region. A second electrode is provided on the back surface of the silicon carbide semiconductor substrate. The silicon carbide semiconductor substrate, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer by protons or helium Point defects are introduced. When current is passed from the first electrode to the second electrode, the peak emission intensity near a wavelength of 390 nm is lower than the peak emission intensity near a wavelength of 500 nm.

[0018] Further, in the silicon carbide semiconductor device according to this invention, in the above-described invention, the peak emission intensity near a wavelength of 390 nm is 1 / 20 of the peak emission intensity near a wavelength of 500 nm as follows This is a feature.

[0019] Further, in the silicon carbide semiconductor device according to this invention, in the above-described invention, The peak emission intensity near a wavelength of 500 nm is 2000 emission counts or less This is a feature.

[0020] In order to solve the above-described problems and achieve the object of the present invention, the manufacturing method of the silicon carbide semiconductor device according to this invention has the following features. First, a first step of forming a first semiconductor layer of the first conductivity type having an impurity concentration lower than that of the silicon carbide semiconductor substrate is performed on the front surface of the silicon carbide semiconductor substrate of the first conductivity type. Next, on the surface of the first semiconductor layer opposite to the side of the silicon carbide semiconductor substrate, with an impurity concentration higher than that of the first semiconductor layerA second step of forming a second semiconductor layer of a first conductivity type is performed. Next, a third step of forming a third semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is performed on the surface of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side. Next, a fourth step of forming a fourth semiconductor layer of a second conductivity type is performed on the surface of the third semiconductor layer opposite to the silicon carbide semiconductor substrate side. Next, a fifth step of selectively forming a first semiconductor region of a first conductivity type is performed on the surface layer of the fourth semiconductor layer opposite to the silicon carbide semiconductor substrate side. Next, a sixth step of forming a gate electrode via a gate insulating film on at least a part of the surface of the fourth semiconductor layer sandwiched between the first semiconductor region and the third semiconductor layer is performed. Next, from the back surface of the silicon carbide semiconductor substrate of protons or helium A particle beam is irradiated to introduce point defects into the silicon carbide semiconductor substrate, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer by protons or helium in a seventh step. Next, an eighth step of forming a first electrode on the surfaces of the fourth semiconductor layer and the first semiconductor region is performed. Next, a ninth step of forming a second electrode on the back surface of the silicon carbide semiconductor substrate is performed.

[0021] Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the particles of the particle beam are protons, and in the seventh step, the irradiation amount of the protons is 5×10 11 / cm 2 or more.

[0022] According to the above-described invention, point defects are introduced from the substrate to the range of the drift layer. Thereby, when the body diode is energized, the peak emission intensity near a wavelength of 390 nm is lower than the peak emission intensity near a wavelength of 500 nm. For this reason, it is possible to suppress the trapping of charges in the SiO 2 oxide film, suppress the variation of Vth, and stabilize the device characteristics. Further, particle beam irradiation is performed from the back surface side of the silicon carbide substrate to form point defects. Thereby, the influence of particle beam irradiation on the gate electrode can be reduced.

Effect of the Invention

[0023] According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, by reducing the trapping of charges in the oxide film, it is possible to suppress the variation of Vth and stabilize the device characteristics.

Brief Description of the Drawings

[0024]

Figure 1

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Figure 12

Embodiments for Carrying Out the Invention

[0025] With reference to the accompanying drawings, preferred embodiments of a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, in a layer or region preceded by n or p, it means that electrons or holes are the majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layer or region to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted. In this specification, in the notation of Miller indices, "-" means a bar attached to the immediately following index, and a negative index is represented by attaching "-" before the index. And the description of the same or equivalent should preferably include within 5% in consideration of variations in manufacturing.

[0026] (Embodiment) The semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In an embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described by taking a trench type MOSFET 70 as an example. FIG. 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment. In FIG. 1, only the active region through which the main current of the trench type MOSFET 70 flows is shown.

[0027] As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment includes an n + type silicon carbide substrate (a silicon carbide semiconductor substrate of the first conductivity type) 1 on the first main surface (front surface), for example, the (0001) surface (Si surface), an n-type boundary layer (a first semiconductor layer of the first conductivity type) 20, a high-concentration n + type buffer layer (a second semiconductor layer of the first conductivity type) 21, an n - type silicon carbide epitaxial layer (a third semiconductor layer of the first conductivity type) 2, and a p-type base layer (a fourth semiconductor layer of the second conductivity type) 6, and is configured using a silicon carbide semiconductor substrate 18 formed by laminating them in this order.

[0028] n- On the surface of the n-type silicon carbide epitaxial layer 2 opposite to the n-type silicon carbide substrate 1 side, an n-type high-concentration region 5 may be provided. The n-type high-concentration region 5 is a high-concentration n-type drift layer having an impurity concentration lower than that of the n-type silicon carbide substrate 1 and higher than that of the n-type silicon carbide epitaxial layer 2. + On the surface of the n-type silicon carbide epitaxial layer 2 opposite to the n-type silicon carbide substrate 1 side, an n-type high-concentration region 5 may be provided. The n-type high-concentration region 5 is a high-concentration n-type drift layer having an impurity concentration lower than that of the n-type silicon carbide substrate 1 and higher than that of the n-type silicon carbide epitaxial layer 2. + On the surface of the n-type silicon carbide epitaxial layer 2 opposite to the n-type silicon carbide substrate 1 side, an n-type high-concentration region 5 may be provided. The n-type high-concentration region 5 is a high-concentration n-type drift layer having an impurity concentration lower than that of the n-type silicon carbide substrate 1 and higher than that of the n-type silicon carbide epitaxial layer 2. - On the surface of the n-type silicon carbide epitaxial layer 2 opposite to the n-type silicon carbide substrate 1 side, an n-type high-concentration region 5 may be provided. The n-type high-concentration region 5 is a high-concentration n-type drift layer having an impurity concentration lower than that of the n-type silicon carbide substrate 1 and higher than that of the n-type silicon carbide epitaxial layer 2.

[0029] The n-type boundary layer 20 has an impurity concentration lower than that of the n-type silicon carbide substrate 1 and is doped with, for example, nitrogen (N). The n-type boundary layer 20 is provided to fix the starting point of the expansion of stacking defects and prevent the crystal defects of the n-type silicon carbide substrate 1 from being transmitted to the n-type silicon carbide epitaxial layer 2. The high-concentration n-type buffer layer 21 is a highly doped layer doped with, for example, a high concentration of nitrogen. + The n-type boundary layer 20 has an impurity concentration lower than that of the n-type silicon carbide substrate 1 and is doped with, for example, nitrogen (N). The n-type boundary layer 20 is provided to fix the starting point of the expansion of stacking defects and prevent the crystal defects of the n-type silicon carbide substrate 1 from being transmitted to the n-type silicon carbide epitaxial layer 2. The high-concentration n-type buffer layer 21 is a highly doped layer doped with, for example, a high concentration of nitrogen. + The n-type boundary layer 20 has an impurity concentration lower than that of the n-type silicon carbide substrate 1 and is doped with, for example, nitrogen (N). The n-type boundary layer 20 is provided to fix the starting point of the expansion of stacking defects and prevent the crystal defects of the n-type silicon carbide substrate 1 from being transmitted to the n-type silicon carbide epitaxial layer 2. The high-concentration n-type buffer layer 21 is a highly doped layer doped with, for example, a high concentration of nitrogen. - The n-type boundary layer 20 has an impurity concentration lower than that of the n-type silicon carbide substrate 1 and is doped with, for example, nitrogen (N). The n-type boundary layer 20 is provided to fix the starting point of the expansion of stacking defects and prevent the crystal defects of the n-type silicon carbide substrate 1 from being transmitted to the n-type silicon carbide epitaxial layer 2. The high-concentration n-type buffer layer 21 is a highly doped layer doped with, for example, a high concentration of nitrogen. + The n-type boundary layer 20 has an impurity concentration lower than that of the n-type silicon carbide substrate 1 and is doped with, for example, nitrogen (N). The n-type boundary layer 20 is provided to fix the starting point of the expansion of stacking defects and prevent the crystal defects of the n-type silicon carbide substrate 1 from being transmitted to the n-type silicon carbide epitaxial layer 2. The high-concentration n-type buffer layer 21 is a highly doped layer doped with, for example, a high concentration of nitrogen.

[0030] In the trench-type MOSFET 70 of the embodiment, by irradiating particle beams such as protons (p) and helium (He) from the back surface, point defects 22 are introduced up to the range of the drift layer (n-type silicon carbide epitaxial layer 2) from the substrate (n-type silicon carbide substrate 1). These point defects 22 serve as recombination centers, increasing the proportion of light emission near a wavelength of 500 nm and shifting the light emission during body diode energization (when current flows from the source electrode 12 to the back surface electrode 13) to the longer wavelength side. As a result, in the trench-type MOSFET 70 of the embodiment, during body diode energization, the peak light emission intensity near a wavelength of 390 nm is lower than the peak light emission intensity near a wavelength of 500 nm. For example, when the body diode is energized under the condition of 100 °C, the peak light emission intensity near a wavelength of 390 nm is preferably 1 / 20, and more preferably 1 / 100 of the peak light emission intensity near a wavelength of 500 nm. By suppressing the light emission near a wavelength of 390 nm with high energy in this way, it is possible to suppress the trapping of charges in the SiO + oxide film, suppress the variation of Vth, and stabilize the device characteristics. - oxide film, suppress the variation of Vth, and stabilize the device characteristics. 2 oxide film, suppress the variation of Vth, and stabilize the device characteristics.

[0031] Figures 2 and 3 are graphs showing the emission intensity of the body diode after proton irradiation. Figures 2 and 3 show the proton irradiation dose of 1×10 10 / cm 2 、1×10 11 / cm 2 、5×10 11 / cm 2 、1×10 12 / cm 2 、5×10 12 / cm 2 . The current density of 300 A / cm 2 was passed through the body diode with point defect 22 introduced, and the result was measured at a temperature of 100°C. In Figure 2, the horizontal axis represents the wavelength of the light emitted from the body diode, and the unit is nm. The vertical axis represents the intensity of the emission count light emitted from the body diode, and the unit is emission count. In Figure 3, the horizontal axis represents the proton irradiation dose, and the unit is / cm 2 . The vertical axis represents the intensity of the light emitted from the body diode, and the unit is emission count.

[0032] As shown in Figures 2 and 3, as the proton irradiation dose increases and the concentration of point defect 22 increases, the emission ratio near the wavelength of 390 nm decreases, and the emission ratio near the wavelength of 500 nm increases. From the results of Figures 2 and 3, the proton irradiation dose is preferably 5×10 11 / cm 2 or more at which the emission near the wavelength of 390 nm becomes almost zero. Here, the case where point defect 22 is caused by proton irradiation is shown, but the same applies to the case where point defect 22 is caused by helium irradiation.

[0033] Figure 4 is a diagram showing the oxide film, 4H-SiC, and the band offset. Here, the case where the side surface of the trench is the m-plane is shown, but the same applies to other planes. As shown in Figure 4, the band offset between 4H-SiC (tetragonal periodic hexagonal silicon carbide) and the SiO 2 oxide film constituting the gate insulating film 9 is about 2.49 eV (498 nm). Therefore, for the emission of high-energy wavelengths near 390 nm, SiO 2Although charges are easily trapped in the oxide film, in the case of light emission with a low energy wavelength near 500 nm, SiO 2 Charges are less likely to be trapped in the oxide film.

[0034] Figure 5 is a graph showing the current dependence of ΔVth. In Figure 5, currents of 20 A and 48 A are passed through the body diode, and it shows the measurement results of the PWM (Pulse Width Modulation) drive test at a temperature of 130°C. In Figure 5, the horizontal axis represents the test time, and the unit is h. The horizontal axis represents the variation of the threshold voltage (ΔVth), and the unit is V.

[0035] As shown in Figure 5, the variation of the threshold voltage decreases as the current decreases. Also, the emission intensity of the body diode has a current dependence, and when the current decreases, the emission intensity of the body diode decreases. This is a result suggesting that the variation of the threshold voltage can be suppressed by the decrease in the emission intensity of the body diode. When the point defect 22 is introduced, recombination at the defect level occurs, which can decrease the emission intensity of the body diode with a wavelength of 390 nm. Therefore, the variation of the threshold voltage can be decreased.

[0036] n + On the second main surface (back surface, that is, the back surface of the silicon carbide semiconductor substrate 18) of the n-type silicon carbide substrate 1, a back electrode 13 serving as a drain electrode is provided. On the surface of the back electrode 13, a drain electrode pad (not shown) is provided.

[0037] On the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate 18, a trench structure is formed. Specifically, the trench 16 penetrates the p-type base layer 6 from the surface on the side opposite to the n + type silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate 18) through the p-type base layer 6 to the n-type high-concentration region 5 (when the n-type high-concentration region 5 is not provided, n -The type of silicon carbide epitaxial layer 2 (hereinafter simply referred to as (2)) is reached. Along the inner wall of the trench 16, a gate insulating film 9 is formed on the bottom and side walls of the trench 16, and a gate electrode 10 is formed inside the gate insulating film 9 in the trench 16. The gate electrode 10 is insulated from the n-type high-concentration region 5(2) and the p-type base layer 6 by the gate insulating film 9. A part of the gate electrode 10 may protrude from above the trench 16 (the side where the source electrode 12 described later is provided) toward the source electrode 12 side.

[0038] n of the n-type high-concentration region 5(2) + On the surface layer on the side opposite to the side of the type silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor substrate 18), between the trenches 16, the first p + type base region 3 is provided. Also, in the n-type high-concentration region 5(2), a second p + type base region 4 that contacts the bottom of the trench 16 is provided. The second p + type base region 4 is provided at a position facing the bottom of the trench 16 in the depth direction (the direction from the source electrode 12 to the drain electrode 13). The width of the second p + type base region 4 is the same as or wider than the width of the trench 16. The bottom of the trench 16 may reach the second p + type base region 4, or may be located in the n-type high-concentration region 5(2) sandwiched between the p-type base layer 6 and the second p + type base region 4.

[0039] Inside the p-type base layer 6, an n + type source region (the first semiconductor region of the first conductivity type) 7 is selectively provided. Also, a p + type contact region 8 may be selectively provided. Also, the n + type source region 7 and the p + type contact region 8 are in contact with each other.

[0040] The interlayer insulating film 11 is provided so as to cover the gate electrode 10 embedded in the trench 16 over the entire first main surface side of the silicon carbide semiconductor substrate 18. The source electrode 12 is connected to the n + -type source region 7 and the p-type base layer 6 through a contact hole opened in the interlayer insulating film 11. Also, when a p + -type contact region 8 is provided, the source electrode 12 is connected to the n + -type source region 7, the p-type base layer 6, and the p + -type contact region 8. The source electrode 12 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 12. A barrier metal 14 for preventing diffusion of metal atoms from the source electrode 12 toward the gate electrode 10, for example, may be provided between the source electrode 12 and the interlayer insulating film 11.

[0041] (Method for manufacturing a silicon carbide semiconductor device according to an embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. FIGS. 6 to 11 are cross-sectional views showing states during the manufacture of the silicon carbide semiconductor device according to the embodiment.

[0042] First, an n + -type silicon carbide substrate 1 made of n-type silicon carbide is prepared. The n + -type silicon carbide substrate 1 has, for example, about 5.0×10 18 / cm 3 . Then, an n-type boundary layer 20 made of silicon carbide is epitaxially grown to a thickness of about 5 μm, for example, while doping an n-type impurity, such as nitrogen atoms (N), on the first main surface of the n + -type silicon carbide substrate 1.

[0043] Next, a high-concentration n + -type buffer layer 21 made of silicon carbide is epitaxially grown to a thickness of, for example, 1 μm or more and 5 μm or less, while doping an n-type impurity, such as nitrogen atoms (N), on the surface of the n-type boundary layer 20.

[0044] Next, the high-concentration n+ While doping the surface of the type buffer layer 21 with an n-type impurity, for example, a nitrogen atom (N), the lower n - type silicon carbide epitaxial layer 2a is epitaxially grown to a thickness of about 30 μm, for example. The state up to here is described in FIG. 6.

[0045] Next, the lower n - On the surface of the type silicon carbide epitaxial layer 2a, a mask for ion implantation having a predetermined opening is formed of, for example, an oxide film by photolithography technology. Then, a p-type impurity such as aluminum is implanted into the opening of the oxide film to form a lower first p + type base region 3a and a second p + type base region 4.

[0046] Next, a part of the mask for ion implantation is removed, and an n-type impurity such as nitrogen is ion-implanted into the opening, and a lower n-type high-concentration region 5a having a depth of about 0.5 μm may be formed in a part of the surface region of the lower n-type silicon carbide epitaxial layer 2a. The impurity concentration of the lower n-type high-concentration region 5a is set to, for example, 1×10 - / cm 17 / cm 3 or the like. The state up to here is described in FIG. 7.

[0047] Next, the lower n - On the surface of the type silicon carbide epitaxial layer 2a, an upper n - type silicon carbide epitaxial layer 2b doped with an n-type impurity such as nitrogen is formed to a thickness of about 0.5 μm. The impurity concentration of the upper n - type silicon carbide epitaxial layer 2b is set to be about 3×10 15 / cm 3 or the like. Thereafter, the lower n - type silicon carbide epitaxial layer 2a and the upper n - type silicon carbide epitaxial layer 2b are combined to form an n - type silicon carbide epitaxial layer 2.

[0048] Next, the upper n -On the surface of the silicon carbide epitaxial layer 2b, a mask for ion implantation having a predetermined opening is formed, for example, with an oxide film by photolithography. Then, p-type impurities such as aluminum are implanted into the opening of the oxide film to form an upper first p + type base region 3b with a depth of about 0.5 μm so as to overlap the lower first p + type base region 3a. The lower first p + type base region 3a and the upper first p + type base region 3b form a continuous region, which becomes the first p + type base region 3. The impurity concentration of the upper first p + type base region 3b is set to, for example, 5×10 18 / cm 3 or so.

[0049] Next, a part of the mask for ion implantation is removed, and n-type impurities such as nitrogen are ion-implanted into the opening to form, for example, an upper n-type high-concentration region 5b with a depth of about 0.5 μm in a part of the surface region of the n - type silicon carbide epitaxial layer 2. The impurity concentration of the upper n-type high-concentration region 5b is set to, for example, 1×10 17 / cm 3 or so. The upper n-type high-concentration region 5b and the lower n-type high-concentration region 5a are formed so as to be in contact with at least a part of each other to form an n-type high-concentration region 5. However, there are cases where this n-type high-concentration region 5 is formed over the entire surface of the substrate and cases where it is formed only in the active region and not in the breakdown voltage structure region on the outer periphery of the active region. The state up to this point is described in FIG. 8.

[0050] Next, on the surface of the n - type silicon carbide epitaxial layer 2, a p-type base layer 6 is formed to a thickness of about 1.1 μm by epitaxial growth. The impurity concentration of the p-type base layer 6 is set to 3.5×10 16 / cm 3 or so. After the p-type base layer 6 is formed by epitaxial growth, p-type impurities such as aluminum may be further ion-implanted into the p-type base layer 6.

[0051] Next, a predetermined region constituting the MOS gate is formed on the first main surface layer (the surface layer of the p-type base layer 6) of the silicon carbide semiconductor substrate 18. Specifically, an ion implantation mask having a predetermined opening is formed, for example, of an oxide film on the surface of the p-type base layer 6 by photolithography. N-type impurities such as nitrogen (N) and phosphorus (P) are ion-implanted into this opening, and n + type source regions 7 are formed in a part of the surface of the p-type base layer 6. Next, the ion implantation mask used for the formation of the n + type source regions 7 is removed, and in the same manner, an ion implantation mask having a predetermined opening is formed, and p-type impurities such as boron are ion-implanted into a part of the surface of the p-type base layer 6 to form p + type contact regions 8. The impurity concentration of the p + type contact regions 8 is set to be higher than the impurity concentration of the p-type base layer 6.

[0052] Next, a heat treatment (activation annealing) for activating all the regions formed by ion implantation is performed. For example, heat treatment (annealing) is performed in an inert gas atmosphere at about 1700 °C to perform activation treatment on the first p + type base region 3, the second p + type base region 4, the n + type source regions 7, and the p + type contact regions 8. Note that, as described above, each ion implantation region may be collectively activated by one heat treatment, or heat treatment may be performed each time ion implantation is performed for activation. The state up to this point is described in FIG. 9.

[0053] Next, a trench formation mask having a predetermined opening is formed, for example, of an oxide film on the surface of the p-type base layer 6 by photolithography. Next, a trench 16 that penetrates the p-type base layer 6 and reaches the n-type high-concentration region 5(2) is formed by dry etching. The bottom of the trench 16 may reach the second p + type base region 4 formed in the n-type high-concentration region 5(2). Next, the trench formation mask is removed.

[0054] Next, n +n-type source region 7 and p + A gate insulating film 9 is formed along the surface of the p-type contact region 8, the bottom and side walls of the trench 16. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000 °C in an oxygen atmosphere. Also, this gate insulating film 9 may be formed by a method of deposition by a chemical reaction such as High Temperature Oxide (HTO). The state up to this point is described in FIG. 10.

[0055] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 16. The polycrystalline silicon layer is patterned by photolithography and left inside the trench 16 to form the gate electrode 10.

[0056] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm to form an interlayer insulating film 11 so as to cover the gate insulating film 9 and the gate electrode 10. Next, a barrier metal 14 made of titanium (Ti) or titanium nitride (TiN) may be formed so as to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography to expose the n + n-type source region 7 and p + A contact hole exposing the p-type contact region 8 is formed. Thereafter, a heat treatment (reflow) is performed to flatten the interlayer insulating film 11.

[0057] Next, the interlayer insulating film 11 is selectively removed and a film of nickel (Ni) or Ti is formed on the surface of the silicon carbide semiconductor substrate 18. Next, the surface is protected and an Ni or Ti film is formed on the back side of the n + type silicon carbide substrate 1. Next, a heat treatment at about 1000 °C is performed to form an ohmic electrode on the surface side of the silicon carbide semiconductor substrate 18 and the surface side of the back surface of the n + type silicon carbide substrate 1.

[0058] Next, n +Particle beam irradiation 23 is performed from the back side of the silicon carbide substrate 1 of the type. The particle beam irradiation 23 irradiates protons. The irradiation dose of the protons is preferably 5×10 11 / cm 2 or more. Alternatively, helium may be irradiated instead of protons. The particle beam irradiation 23 is performed so that point defects 22 are introduced into the drift region from the substrate. Since the point defects 22 disappear at a temperature of 500°C or higher, the particle beam irradiation 23 is performed after activation annealing. Here, the particle beam irradiation 23 was performed after annealing to form nickel silicide, but it may be performed after annealing after the trench 16 is formed. Also, the particle beam irradiation 23 is preferably performed from the back side of the silicon carbide semiconductor substrate 18. In this case, the influence on the gate electrode 10 due to the particle beam irradiation 23 can be reduced. The state so far is described in FIG. 11.

[0059] Next, a conductive film serving as the source electrode 12 is provided on the interlayer insulating film 11 so as to contact the ohmic electrode portion formed in the contact hole, and n + type source region 7 and p + type contact region 8 are brought into contact with the source electrode 12.

[0060] Next, a back electrode 13 made of, for example, a nickel (Ni) film is formed on the second main surface of the n + type silicon carbide substrate 1. Thereafter, heat treatment is performed at a temperature of about 970°C, for example, to ohmically bond the n + type silicon carbide substrate 1 and the back electrode 13.

[0061] Next, an electrode pad serving as a source electrode pad (not shown) is deposited on the source electrode 12 on the front surface of the silicon carbide semiconductor substrate 18 and in the opening of the interlayer insulating film 11 by, for example, sputtering. The thickness of the portion of the electrode pad on the interlayer insulating film 11 may be, for example, 5 μm. The electrode pad may be formed of aluminum (Al—Si) containing silicon at a ratio of, for example, 1%. Next, the source electrode pad is selectively removed.

[0062] Next, for example, titanium (Ti), nickel (Ni), and gold (Au) are deposited in this order on the surface of the back electrode 13 as drain electrode pads (not shown). In this way, the silicon carbide semiconductor device shown in FIG. 1 is completed.

[0063] As described above, according to the embodiment, point defects are introduced from the substrate to the range of the drift layer. As a result, when the body diode is energized, the peak emission intensity near a wavelength of 390 nm is lower than the peak emission intensity near a wavelength of 500 nm. Therefore, 2 it is possible to suppress the trapping of charges in the SiO oxide film, suppress the variation of Vth, and stabilize the device characteristics. Further, particle beam irradiation is performed from the back side of the silicon carbide substrate to form point defects. Thereby, the influence of particle beam irradiation on the gate electrode can be reduced.

[0064] In the above, the present invention can be variously modified without departing from the gist of the present invention. In each of the above-described embodiments, for example, the dimensions, impurity concentrations, etc. of each part are variously set according to required specifications and the like. Further, in each of the above-described embodiments, a trench gate type vertical MOSFET has been described as an example, but the present invention is also applicable to a PiN diode, an IGBT (Insulated Gate Bipolar Transistor), etc. Further, in each of the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention also holds true when the first conductivity type is p-type and the second conductivity type is n-type.

Industrial Applicability

[0065] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices such as various industrial machines, and igniters for automobiles.

Explanation of Reference Numerals

[0066] 1, 101 n + type silicon carbide substrate 2, 102 n -Silicon carbide epitaxial layer 2a Lower n - Silicon carbide epitaxial layer 2b Upper n - Silicon carbide epitaxial layer 3, 103 First p + Base region 3a Lower first p + Base region 3b Upper first p + Base region 4, 104 Second p + Base region 5, 105 n-type high concentration region 5a Lower n-type high concentration region 5b Upper n-type high concentration region 6, 106 p-type base layer 7, 107 n + Source region 8, 108 p + Contact region 9, 109 Gate insulating film 10, 110 Gate electrode 11, 111 Interlayer insulating film 12, 112 Source electrode 13, 113 Back electrode 14, 114 Barrier metal 16, 116 Trench 18 Silicon carbide semiconductor substrate 20, 120 n-type boundary layer 21, 121 High concentration n + Type buffer layer 22 Point defect 23 Particle beam irradiation 70, 170 Trench type MOSFET

Claims

1. A silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate, provided on the front surface of the silicon carbide semiconductor substrate, a second semiconductor layer of a first conductivity type having a higher impurity concentration than the first semiconductor layer, provided on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, a third semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate, provided on the surface of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, a fourth semiconductor layer of a second conductivity type, provided on the surface of the third semiconductor layer opposite to the silicon carbide semiconductor substrate side, a first semiconductor region of a first conductivity type, selectively provided on the surface layer of the fourth semiconductor layer opposite to the silicon carbide semiconductor substrate side, a gate electrode provided via a gate insulating film on at least a part of the surface of the fourth semiconductor layer sandwiched between the first semiconductor region and the third semiconductor layer, a first electrode provided on the surfaces of the fourth semiconductor layer and the first semiconductor region, a second electrode provided on the back surface of the silicon carbide semiconductor substrate, comprising: point defects are introduced into the silicon carbide semiconductor substrate, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer by protons or helium, a silicon carbide semiconductor device characterized in that when a current is passed from the first electrode to the second electrode, the peak emission intensity near a wavelength of 390 nm is lower than the peak emission intensity near a wavelength of 500 nm.

2. The silicon carbide semiconductor device according to claim 1, characterized in that the peak emission intensity near a wavelength of 390 nm is 1 / 20 or less of the peak emission intensity near a wavelength of 500 nm.

3. The silicon carbide semiconductor device according to claim 1, characterized in that the peak emission intensity near a wavelength of 500 nm is 2000 emission counts or less.

4. a first step of forming, on the front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate, a second step of forming, on the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, a second semiconductor layer of a first conductivity type having a higher impurity concentration than the first semiconductor layer, a third step of forming, on the surface of the second semiconductor layer opposite to the silicon carbide semiconductor substrate side, a third semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate, A fourth step of forming a fourth semiconductor layer of a second conductivity type on a surface of the third semiconductor layer opposite to the silicon carbide semiconductor substrate side; A fifth step of selectively forming a first semiconductor region of a first conductivity type in a surface layer of the fourth semiconductor layer opposite to the silicon carbide semiconductor substrate side; A sixth step of forming a gate electrode via a gate insulating film on at least a part of a surface of the fourth semiconductor layer sandwiched between the first semiconductor region and the third semiconductor layer; A seventh step of irradiating a particle beam of protons or helium from a back surface of the silicon carbide semiconductor substrate to introduce point defects due to protons or helium into the silicon carbide semiconductor substrate, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; An eighth step of forming a first electrode on a surface of the fourth semiconductor layer and the first semiconductor region; A ninth step of forming a second electrode on a back surface of the silicon carbide semiconductor substrate; A method of manufacturing a silicon carbide semiconductor device, comprising the steps.

5. The particles of the particle beam are protons. In the seventh step, the proton irradiation dose is 5×10 11 / cm 2 or more. The method for manufacturing a silicon carbide semiconductor device according to claim 4, characterized by this.

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