Semiconductor device

Abstract

To provide a highly reliable semiconductor device which is easy to be fabricated (manufactured).SOLUTION: An FLR structure 20 is provided in an edge termination region 2 as a breakdown voltage structure. The FLR structure 20 is composed of a plurality of FLRs 101 to 118 concentrically surrounding an active region 2. The impurity concentration of the FLR101 to 118 is within the range of less than 1×1018 / cm3, preferably within the range of 3×1017 / cm3 or more and 9×1017 / cm3 or less. The thickness t10 of the FLR101 to 118 is 0.7 μm or more and 1.1 μm or less. A first distance w1 between the innermost FLR 101 and the outer p+ type region 62a is within a range of about 1.2 μm or less.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] This invention relates to a semiconductor device.

Background Art

[0002] Conventionally, there are multiple types of power semiconductor devices for controlling high voltage and large current, such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used appropriately according to the application.

[0003] For example, bipolar transistors and IGBTs have a higher current density than MOSFETs and can handle larger currents, but they cannot be switched at high speed. Specifically, the use of bipolar transistors is limited to a switching frequency of about several kHz, and the use of IGBTs is limited to a switching frequency of about several tens of kHz. On the other hand, MOSFETs have a lower current density than bipolar transistors and IGBTs and it is difficult to handle large currents, but they can perform high-speed switching operations up to about several MHz.

[0004] Also, different from IGBTs, MOSFETs incorporate a parasitic diode (body diode) formed by a pn junction between a p-type base region and an n - type drift region inside the semiconductor substrate (semiconductor chip). MOSFETs can use the parasitic diode built inside this semiconductor substrate as a function of a freewheeling diode for protecting themselves. Therefore, MOSFETs do not need to additionally connect an external freewheeling diode for self-protection, and are also attracting attention in terms of economy.

[0005] Silicon (Si) is used as a constituent material of power semiconductor devices. However, in the market, there is a strong demand for power semiconductor devices that combine high current and high speed. Considerable efforts have been made to improve IGBTs and MOSFETs, and currently, the development has advanced to almost the material limit. Therefore, semiconductor materials to replace silicon are being considered from the perspective of power semiconductor devices, and silicon carbide (SiC) has attracted attention as a semiconductor material capable of fabricating (manufacturing) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics.

[0006] Silicon carbide is a chemically very stable semiconductor material with a wide bandgap of 3 eV and can be used extremely stably as a semiconductor even at high temperatures. Also, since the maximum electric field strength of silicon carbide is more than one order of magnitude larger than that of silicon, it is expected as a semiconductor material that can sufficiently reduce the on-resistance. Such features of silicon carbide are also possessed by not only silicon carbide but all semiconductors with a wider bandgap than silicon (hereinafter referred to as wide bandgap semiconductors).

[0007] In high-voltage semiconductor devices, not only in the active region where the element structure is formed, but also in the edge termination region surrounding the active region, a high voltage is applied, and the electric field is concentrated in the edge termination region. The breakdown voltage of a semiconductor device is determined by the impurity concentration, thickness, and electric field strength of the semiconductor (drift region), and the breakdown tolerance determined by these semiconductor-specific features is equal from the active region to the edge termination region. Therefore, due to the concentration of the electric field in the edge termination region, an electrical load exceeding the breakdown tolerance is applied to the edge termination region, and there is a risk of breakdown in the edge termination region.

[0008] Therefore, a structure is known in which a breakdown voltage structure such as a Junction Termination Extension (JTE) structure or a Field Limiting Ring (FLR) structure is arranged in the edge termination region to relax or disperse the electric field in the edge termination region, thereby improving the breakdown voltage of the entire semiconductor device. Also, a structure is known in which a Field Plate (FP), which is a metal electrode with a floating potential in contact with the FLR, is arranged in the edge termination region to discharge the charges generated in the edge termination region, thereby improving the reliability of the semiconductor device.

[0009] The structure of a conventional silicon carbide semiconductor device will be described. FIG. 18 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. In FIG. 18, the FLRs 221 and 222 are shown with different hatchings. The conventional semiconductor device 230 shown in FIG. 18 is a vertical MOSFET having a trench gate structure including an active region 201 through which a main current flows and an edge termination region 202 surrounding the periphery of the active region 201 on a semiconductor substrate 210 made of silicon carbide. The semiconductor substrate 210 is formed by epitaxially growing an n-type drift region 232 and p-type base region 234 as epitaxial layers 272 and 273 in sequence on an n-type starting substrate 271 made of silicon carbide. + type starting substrate 271, an n - type drift region 232 and a p-type base region 234 as epitaxial layers 272 and 273 are epitaxially grown in sequence.

[0010] The portion of the p-type epitaxial layer 273 in the edge termination region 202 is removed by etching, and a step 253 is formed in the edge termination region 202 on the front surface of the semiconductor substrate 210. The front surface of the semiconductor substrate 210 is recessed on the drain electrode 252 side by a second surface 210b on the outer side (chip end (end of the semiconductor substrate 210) side) rather than a first surface 210a on the inner side (chip center (center of the semiconductor substrate 210) side) with the step 253 as a boundary. Due to this step 253, the p-type epitaxial layer 273 remains in a mesa shape on the central side of the front surface (main surface on the p-type epitaxial layer 273 side) of the semiconductor substrate 210.

[0011] The first and second surfaces 210a and 210b on the front surface of the semiconductor substrate 210 are formed of a p-type epitaxial layer 273 and an n - -type epitaxial layer 272, respectively. In the active region 201, a MOS gate of a trench gate structure is provided on the side of the first surface 210a of the front surface of the semiconductor substrate 210. In the edge termination region 202, a plurality of p - -type regions (FLRs) 221 and a plurality of p - -type regions (FLRs) 222 are selectively provided inside the n -- -type epitaxial layer 272 in the surface region of the second surface 210b of the front surface of the semiconductor substrate 210, and a space-modulated FLR structure 220 is configured. A field plate is not provided.

[0012] The space-modulated FLR structure 220 is a breakdown voltage structure in which the p-type impurity concentration per unit volume decreases stepwise toward the outside. Specifically, the plurality of FLRs 221 are arranged apart from each other and surround the active region 201 concentrically. The FLRs 221 arranged on the outside are narrower in width (width in the normal direction) and have a narrower interval from the adjacent FLR 221 on the inside. The innermost FLR 222 surrounds all the FLRs 221 and is arranged between all the adjacent FLRs 221. The innermost FLR 221 and the innermost FLR 222 are electrically connected to the p-type base region 234 (234a).

[0013] The plurality of FLRs 222 are arranged apart from each other and surround the active region 201 concentrically. The FLRs 222 arranged on the outside are narrower in width (width in the normal direction) and have a narrower interval from the adjacent FLR 222 on the inside. The plurality of FLRs 222 are arranged outside the FLRs 221 except for the innermost FLR 222. The n - -type drift region 232 surrounds all the FLRs 221 and is arranged between all the adjacent FLRs 221. Optimal conditions for the widths and arrangements of these FLRs 221 and FLRs 222 are disclosed (see, for example, Patent Documents 1 and 2 below).

[0014] Reference numeral 203 denotes an intermediate region between the active region 201 and the edge termination region 202. Reference numeral 210c denotes a third surface (stepped mesa edge) that connects the first surface 210a and the second surface 210b of the front surface of the semiconductor substrate 210. Reference numerals 231, 233, 235, 236, 238, 239, 240, 240a, 241, 281 to 283 denote, respectively, an n + -type drain region, an n-type current diffusion region, an n + -type source region, a p ++ -type contact region, a gate insulating film, a gate electrode, an interlayer insulating film, a contact hole, a metal silicide film, a field oxide film, a gate polysilicon wiring layer, and a gate metal wiring layer.

[0015] Reference numerals 241 to 245 denote metal films that constitute the barrier metal 246. Reference numerals 248 and 249 denote a plating film and a terminal pin that constitute a wiring structure on the source pad 247, respectively. Reference numerals 250 and 251 denote protective films (passivation films). Reference numerals 261 and 262 denote p + -type regions for electric field relaxation near the bottom surface of the trench 237. Reference numerals 262a, 234a, and 236a denote portions of the p + -type region 262, the p-type base region 234, and the p ++ -type contact region 236 that extend from the active region 201 to the intermediate region 203. Reference numeral 223 denotes an n + -type channel stop region.

[0016] Another example of the structure of a conventional silicon carbide semiconductor device will be described. FIG. 19 is a cross-sectional view showing another example of the structure of a conventional silicon carbide semiconductor device. The difference between the conventional semiconductor device 260 shown in FIG. 19 and the conventional semiconductor device 230 shown in FIG. 18 is that the withstand voltage structure of the edge termination region 202 is changed to a normal FLR structure 290 instead of the spatially modulated FLR structure 220. Also in the conventional semiconductor device 260 shown in FIG. 19, no field plate is provided as in the conventional semiconductor device 230 shown in FIG. 18, and the second surface 210b of the front surface of the semiconductor substrate 210 is covered with insulating layers such as the field oxide film 281 and the interlayer insulating film 240.

[0017] A normal FLR structure 290 is n in the surface region of the second surface 210b on the front surface of the semiconductor substrate 210 - A plurality (here, 18) of floating potential p-type regions (FLR (hatched portions)) 291 selectively provided inside the n-type epitaxial layer 272. - The innermost FLR 291 is located outside the p-type region 262a extending from the active region 201 to the intermediate region 203 (hereinafter referred to as the outer peripheral p-type region) 262a of the p-type region 262, + And is arranged at a predetermined width (first interval) w211 away from the outer peripheral p-type region 262a. The plurality of FLRs 291 are arranged apart from each other and concentrically surround the active region 201 via the intermediate region 203. + +

[0018] All the FLRs 291 have a substantially rectangular cross-sectional shape with the same configuration of substantially the same width w210, substantially the same thickness t201, and substantially the same impurity concentration. The impurity concentration of the FLR 291 is lower than the impurity concentration of the outer peripheral p-type region 262a, for example, about 5×10 / cm or more when the breakdown voltage is 1200 V or more. The plurality of FLRs 291 are arranged at substantially equal intervals w212. That the width, thickness, interval, and impurity concentration are substantially the same (substantially equal) means that they are the same width, the same thickness, the same interval, and the same impurity concentration within a range including the allowable error due to process variations. + 18 / cm 3

[0019] All the FLRs 291 terminate at a shallower position on the front surface side of the semiconductor substrate 210 than the outer peripheral p-type region 262a. The thickness t201 of the FLR 291 is about 0.4 μm to 0.5 μm from the second surface 210b on the front surface of the semiconductor substrate 210. To obtain the same breakdown voltage as that obtained by the spatially modulated FLR structure 220 in the normal FLR structure 290, the length of the edge termination region 202 (the length from the intermediate region 203 to the chip end) w202 needs to be widened up to about twice the length w201 of the edge termination region 202 (see FIG. 18) when the breakdown voltage structure is the spatially modulated FLR structure 220, and becomes about 300 μm, for example. + ​​​​​

[0020] Various JTE structures and ordinary FLR structures have also been disclosed (see, for example, Patent Documents 3 to 9 below). Patent Document 3 below discloses the position and impurity concentration range when a JTE structure is formed by two p-type regions. In Patent Document 4 below, by disposing the p - -type region constituting the JTE structure at a deep position away from the front surface of the semiconductor substrate, the electric field applied to the end corner portion of the p-type base region is relaxed to improve the breakdown voltage. In Patent Document 5 below, by gradually thinning the thickness of the p-type silicon carbide layer extending from the active region to the edge termination region, a JTE structure is formed in which the effective impurity concentration decreases toward the outside.

[0021] Patent Document 6 below discloses an ordinary FLR structure provided with a field plate. In Patent Document 6 below, field plates provided on each FLR constituting the ordinary FLR structure via an interlayer insulating film are extended onto the portions (n - -type drift region) between the FLRs adjacent to each other from above the FLRs. By making the thickness of the portion of the interlayer insulating film covering the FLR thinner than the thickness of the portion covering the n - -type drift region sandwiched between adjacent FLRs, the influence of the capacitance of the interlayer insulating film is suppressed, and the reliability is improved without optimizing the structure of the field plate.

[0022] Patent Documents 7 to 9 below disclose ordinary FLR structures not provided with a field plate. Patent Documents 7 and 8 below disclose that a p + -type region for electric field relaxation near the trench bottom and an FLR (p + -type region) are formed simultaneously. Further, in Patent Document 8 below, the FLR (p - -type region) is disposed at a deep position away from the front surface of the semiconductor substrate, and the pn junction between the FLR and the n - -type drift region is separated from the front surface of the semiconductor substrate, thereby suppressing an increase in the electric field strength at the outermost surface of the interlayer insulating film on the front surface of the semiconductor substrate and suppressing the occurrence of surface flashover at the outermost surface of the interlayer insulating film.

[0023] In Patent Document 9 below, the distance between the p-well region of the active region and the innermost FLR, and the distance between adjacent FLRs are adjusted with respect to the depletion layer that spreads outward from the active region, and these adjacent p-type regions are arranged close enough to each other to suppress the electric field strength increased by the shape effect due to the curvature of the p-well region and the p-type diffusion region serving as the FLR. Patent Document 9 below discloses that the distance between the p-well region of the active region and the innermost FLR is set to 0 μm or more and 1 μm or less, and the distance between adjacent FLRs is increased by 0.5 μm for each one arranged more outward.

Prior Art Documents

Patent Documents

[0024]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Patent Document 9

Summary of the Invention

Problems to be Solved by the Invention

[0025] However, in the conventional spatially modulated FLR structure 220 (see FIG. 18) described above, variations occur in the positions and impurity concentrations of the FLRs 221 and 222 that make up the FLR structure 220 due to ion implantation accuracy, and the degree of completion of the FLR structure 220 is low, which may reduce the reliability of the semiconductor device 230. On the other hand, as described above, in the normal FLR structure 290 (see FIG. 19), the length w202 of the edge termination region 202 becomes long, lacking in economy. Also, the margin (tolerance) of the interval w212 between adjacent FLRs 291 is small (see the conventional example in FIG. 12), and the reliability of the semiconductor device is low.

[0026] An object of the present invention is to provide a semiconductor device that is easy to fabricate (manufacture) and has high reliability in order to solve the problems caused by the above-described conventional technologies.

Means for Solving the Problems

[0027] In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention is a semiconductor device having an active region through which a main current flows and a termination region surrounding the periphery of the active region, and has the following features. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of a semiconductor having a wider bandgap than silicon. A second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first semiconductor region in the active region. A predetermined element structure is formed by a pn junction between the second semiconductor region and the first semiconductor region in the active region.

[0028] A first electrode is electrically connected to the second semiconductor region. A second electrode is provided on the second main surface of the semiconductor substrate. A plurality of second conductivity type breakdown voltage regions are selectively provided inside the first semiconductor region and spaced apart from each other in the surface region on the first main surface side of the semiconductor substrate in the termination region. The plurality of second conductivity type breakdown voltage regions concentrically surround the periphery of the active region. The Average impurity concentration is 1×10 18 / cm 3It is within the range of less than. The thickness of the second conductivity type breakdown voltage region is 0.7 μm or more and 1.1 μm or less. The second conductivity type breakdown voltage region has a barrel-shaped cross-sectional shape that is relatively wide at the central position in the depth direction. In the second conductivity type breakdown voltage region, the impurity concentration is the highest in the widest first portion, and is relatively low in the second portion excluding the first portion.

[0029] Further, in the semiconductor device according to the present invention, in the above-described invention, a second conductivity type high-concentration region that is selectively provided in contact with the second semiconductor region between the second semiconductor region and the first semiconductor region and surrounds the periphery of the active region and has a higher impurity concentration than the second semiconductor region is further provided. The second conductivity type breakdown voltage region is characterized in that it reaches a deeper position on the second main surface side of the semiconductor substrate than the second conductivity type high-concentration region. Also, in the semiconductor device according to this invention, in the above-described invention, the impurity concentration of the second conductivity type breakdown voltage region is 3×10 17 / cm 3 or more and 9×10 17 / cm 3 or less within the range.

[0030] Also, in the semiconductor device according to this invention, in the above-described invention, between the second semiconductor region and the first semiconductor region, a second conductivity type high-concentration region that is selectively provided in contact with the second semiconductor region and surrounds the periphery of the active region and has a higher impurity concentration than the second semiconductor region is further provided. The second conductivity type high-concentration region is provided between the active region and the second conductivity type breakdown voltage region and faces the second conductivity type breakdown voltage region in a direction parallel to the first main surface of the semiconductor substrate.

[0031] Also, in the semiconductor device according to this invention, in the above-described invention, the first interval between the innermost second conductivity type breakdown voltage region and the second conductivity type high-concentration region is within the range of 1.2 μm or less.

[0032] Also, in the semiconductor device according to this invention, in the above-described invention, the innermost second conductivity type breakdown voltage region is in contact with the second conductivity type high-concentration region.

[0033] Also, in the semiconductor device according to this invention, in the above-described invention, the second interval between the innermost second conductivity type breakdown voltage region and the second second conductivity type breakdown voltage region from the inside is within the range of 2.1 μm or less.

[0034] Further, in the semiconductor device according to this invention, in the above-described invention, a third interval between the second second-conductive-type breakdown voltage region from the inside and the third second-conductive-type breakdown voltage region from the inside is within a range of 3.1 μm or less.

[0035] Further, in the semiconductor device according to this invention, in the above-described invention, the third interval is within a range of 1.0 μm or less.

[0036] Further, in the semiconductor device according to this invention, in the above-described invention, a fourth interval between the third second-conductive-type breakdown voltage region from the inside and the fourth second-conductive-type breakdown voltage region from the inside is within a range of about 2.0 μm or less.

[0037] Further, in the semiconductor device according to this invention, in the above-described invention, intervals between the second-conductive-type breakdown voltage regions adjacent to each other after the fourth from the inside are wider than the first interval.

[0038] Further, in the semiconductor device according to this invention, in the above-described invention, the plurality of second-conductive-type breakdown voltage regions are all of the same width.

[0039] Further, in the semiconductor device according to this invention, in the above-described invention, widths of the second-conductive-type breakdown voltage regions after the second from the inside are wider than the width of the second-conductive-type breakdown voltage region of the innermost side.

[0040] Further, in the semiconductor device according to this invention, in the above-described invention, the second-conductive-type breakdown voltage region reaches the first main surface of the semiconductor substrate.

[0041] Further, in the semiconductor device according to this invention, in the above-described invention, the second-conductive-type breakdown voltage region is provided at a depth position away from the first main surface of the semiconductor substrate. The first semiconductor region is interposed between the first main surface of the semiconductor substrate and the second-conductive-type breakdown voltage region.

[0043] Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, no conductive film is provided on the first main surface of the semiconductor substrate in the terminal region.

[0044] Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the first main surface of the semiconductor substrate in the terminal region is covered with an insulating layer.

[0045] According to the above-described invention, since the margin of the interval between the second conductivity type breakdown voltage regions adjacent to each other can be increased, the degree of completion of the breakdown voltage structure is improved. Further, by increasing the margin of the interval between the second conductivity type breakdown voltage regions adjacent to each other, it is less likely to be affected by the poor accuracy of ion implantation for forming the second conductivity type breakdown voltage region, and the design of the breakdown voltage structure becomes easy.

Effect of the Invention

[0046] According to the semiconductor device of the present invention, there is an effect that a semiconductor device with simple manufacturing and high reliability can be provided.

Brief Description of the Drawings

[0047]

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Figure 19

Embodiments for Carrying Out the Invention

[0048] With reference to the accompanying drawings, preferred embodiments of the semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, for a layer or region prefixed with n or p, it means that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layer or region to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0049] (Embodiment 1) The structure of the semiconductor device according to Embodiment 1 will be described. FIG. 1 is a plan view showing the layout of the semiconductor device according to Embodiment 1 as viewed from the front side of the semiconductor substrate. FIG. 2 is a cross-sectional view showing the cross-sectional structure taken along the cutting line A-A' in FIG. 1. The semiconductor device 30 according to Embodiment 1 shown in FIGS. 1 and 2 is a vertical MOSFET having a trench gate structure (element structure) in the active region 1 of a semiconductor substrate (semiconductor chip) 10 made of silicon carbide (SiC), and a field limiting ring (FLR) structure 20 is provided as a breakdown voltage structure in the edge termination region 2 surrounding the active region 1.

[0050] The active region 1 is a region where the main current (drift current) flows when the MOSFET (semiconductor device 30) is turned on. In the active region 1, a plurality of unit cells (constituent units of the element) having the same structure of the MOSFET are arranged adjacent to each other. The active region 1 has, for example, a substantially rectangular planar shape and is arranged at substantially the center (chip center) of the semiconductor substrate 10. The active region 1 is a region inside (chip center side) of the side wall (side surface of the interlayer insulating film 40) outside (chip end side) of the outermost contact hole 40b. The intermediate region 3 between the active region 1 and the edge termination region 2 is adjacent to the active region 1 and surrounds the active region 1.

[0051] The boundary between the intermediate region 3 and the edge termination region 2 is the boundary between the first and third surfaces 10a and 10c of the semiconductor substrate 10 described later. The edge termination region 2 is a region between the active region 1 and the end portion (chip end portion) of the semiconductor substrate 10, surrounds the periphery of the active region 1 via the intermediate region 3, and has a function of relaxing the electric field on the front surface (first main surface) side of the semiconductor substrate 10 and maintaining the breakdown voltage. In the edge termination region 2, an FLR structure 20 is formed as a breakdown voltage structure on the front surface side of the semiconductor substrate 10. The breakdown voltage is the limit voltage at which avalanche breakdown occurs at the pn junction and the voltage between the source and drain does not increase any further even when the current between the source and drain increases.

[0052] On the front surface side of the semiconductor substrate 10 in the active region 1, a MOS gate is provided. The MOS gate is composed of a p-type base region 34, an n + -type source region 35, a p ++ -type contact region 36, a gate trench 37, a gate insulating film 38, and a gate electrode 39. The outside of the outermost gate trench 37 (the portion of the outer peripheral p-type base region 34a described later) is configured not to have an n + -type source region 35. The semiconductor substrate 10 is formed by epitaxially growing an n + -type drift region (first semiconductor region) 32 and a p-type base region (second semiconductor region) 34 as epitaxial layers 72 and 73 in sequence on the front surface of an n - -type starting substrate 71.

[0053] Taking the main surface on the p-type epitaxial layer 73 side of the semiconductor substrate 10 as the front surface and the main surface on the n + -type starting substrate 71 side as the back surface (second main surface). The n + -type starting substrate 71 is an n + -type drain region 31. The portion of the p-type epitaxial layer 73 in the edge termination region 2 is removed by etching, and a step 53 is formed on the front surface of the semiconductor substrate 10. The front surface of the semiconductor substrate 10 is recessed toward the n + -type drain region 31 at the portion (second surface) 10b of the edge termination region 2 rather than at the portion (first surface) 10a of the active region 1 and the intermediate region 3 with the step 53 as a boundary.

[0054] The second surface 10b of the front surface of the semiconductor substrate 10 is an n-type epitaxial layer exposed by removing the p-type epitaxial layer 73. - The third surface 10c of the front surface of the semiconductor substrate 10 is an exposed surface of the p-type epitaxial layer 72. The active region 1 and intermediate region 3 are isolated from the edge termination region 2 by a portion 10c (third surface: mesa edge of step 53) connecting the first surface 10a and second surface 10b of the front surface of the semiconductor substrate 10. ++ The p-type contact region 36a and an end portion of the peripheral p-type base region 34a (described later) are exposed.

[0055] Along the third surface 10c of the front surface of the semiconductor substrate 10, an outer periphery p ++ the peripheral p-type contact region 36a, the peripheral p-type base region 34a and the peripheral p + p to connect the mold region 62a + When the step 53 is formed, the p-type epitaxial layer 73 and the lower n-type epitaxial layer 74 are also formed. - The gate trench 37 extends in the depth direction Z from the first surface 10a of the front surface of the semiconductor substrate 10 through the p-type epitaxial layer 73. - Extending into the epitaxial layer 72 .

[0056] The gate trench 37 extends, for example, in a stripe shape in a direction parallel to the front surface of the semiconductor substrate 10 (here, the first direction X) and reaches the intermediate region 3. A gate electrode 39 is provided inside the gate trench 37 via a gate insulating film 38. The p-type base region 34 is formed by forming a n + type source region 35 and p ++ This is the portion excluding the p-type contact region 36. The p-type base region 34 extends outward (toward the chip end) from the active region 1 and reaches the third face 10c of the front surface of the semiconductor substrate 10.

[0057] The p-type base region 34 is provided over the entire active region 1 and intermediate region 3. The outer peripheral portion of the p-type base region 34 (hereinafter referred to as the outer peripheral p-type base region) 34a surrounds the periphery of the active region 1 in a substantially rectangular shape. The outer peripheral p-type base region 34a is the portion of the p-type base region 34 that is outside the n + -type source region 35 in the first direction X (the longitudinal direction of the gate trench 37), and is also the portion outside the outermost gate trench 37 in the second direction Y (the lateral direction of the gate trench 37) that is parallel to the front surface of the semiconductor substrate 10 and orthogonal to the first direction X.

[0058] n + -type source region 35 and the p ++ -type contact region 36 are selectively provided in contact with the p-type base region 34 between the first surface 10a of the front surface of the semiconductor substrate 10 and the p-type base region 34, and are exposed on the first surface 10a of the front surface of the semiconductor substrate 10. Here, being exposed on the first surface 10a of the front surface of the semiconductor substrate 10 means that the n + -type source region 35 and the p ++ -type contact region 36 are in contact with the NiSi film 41 through the contact hole 40a of the interlayer insulating film 40 described later.

[0059] n + -type source region 35 is in contact with the gate insulating film 38 on the side wall of the gate trench 37. The p ++ -type contact region 36 is arranged farther from the gate trench 37 than the n + -type source region 35. The p-type base region 34, the n + -type source region 35 and the p ++ -type contact region 36 extend, for example, in the longitudinal direction of the gate trench 37 (not shown) between adjacent gate trenches 37. The p ++ -type contact region 36 may be arranged at intervals in the first direction X.

[0060] Also, the p ++The p-type contact region 36 is provided in contact with the outer peripheral p-type base region 34a over the entire area between the first surface 10a of the front surface of the semiconductor substrate 10 and the outer peripheral p-type base region 34a. Hereinafter, this p ++ portion of the p-type contact region 36 between the first surface 10a of the front surface of the semiconductor substrate 10 and the outer peripheral p-type base region 34a is defined as the outer peripheral p ++ type contact region 36a. The outer peripheral p ++ type contact region 36a is in contact with the gate insulating film 38 at the outer sidewall of the outermost gate trench 37.

[0061] The outer peripheral p ++ type contact region 36a is exposed on the first surface 10a of the front surface of the semiconductor substrate 10. Here, being exposed on the first surface 10a of the front surface of the semiconductor substrate 10 means that the outer peripheral p ++ type contact region 36a is in contact with the NiSi film 41 through the outermost contact hole 40b. The outer peripheral p ++ type contact region 36a has a function of extracting holes accumulated in the edge termination region 2 due to switching of the MOSFET or the like to the source electrode through the outer peripheral p + type region 62a and the outer peripheral p-type base region 34a when the MOSFET is turned off.

[0062] The p ++ type contact region 36 and the outer peripheral p ++ type contact region 36a may not be provided. In this case, instead of the p ++ type contact region 36 and the outer peripheral p ++ type contact region 36a, the p-type base region 34 and the outer peripheral p-type base region 34a reach and are exposed on the front surface of the semiconductor substrate 10, respectively. Inside the semiconductor substrate 10, an n + type drift region 32 is provided in contact with these regions between the p-type base region 34 and the outer peripheral p-type base region 34a and the n + type starting substrate 71). - type drain region 31 (n

[0063] Between the p-type base region 34 and the outer peripheral p-type base region 34a and the n -Between the n-type drift region 32, an n-type current diffusion region 33 and first and second p- + type regions 61 and 62 are selectively provided respectively. The lower surfaces of the n-type current diffusion region 33 and the first and second p- + type regions 61 and 62 are arranged at a position deeper than the bottom surface of the gate trench 37 on the n- + type drain region 31 side. The upper surfaces of the n-type current diffusion region 33 and the second p- + type region 62 are in contact with the p-type base region 34. The n-type current diffusion region 33 and the first and second p- + type regions 61 and 62 extend linearly in the longitudinal direction of the gate trench 37 with substantially the same length as the gate trench 37.

[0064] The n-type current diffusion region 33 is a so-called Current Spreading Layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 33 is in contact with the first and second p- + type regions 61 and 62 between adjacent gate trenches 37. The n-type current diffusion region 33 may extend from the active region 1 to the intermediate region 3. The n-type current diffusion region 33 may not be provided. In this case, the n- - type drift region 32 extends to the front surface side of the semiconductor substrate 10 and is in contact with the p-type base region 34.

[0065] The first and second p- + type regions 61 and 62 have a function of relaxing the electric field applied to the gate insulating film 38 on the bottom surface of the gate trench 37. The depth of the first and second p- + type regions 61 and 62 can be set appropriately. For example, the first and second p- + type regions 61 and 62 may terminate inside the n-type current diffusion region 33 and be surrounded by the n-type current diffusion region 33, or may be at substantially the same depth position as the n-type current diffusion region 33 in the depth direction Z, or reach a position deeper than the n-type current diffusion region 33 on the n- + type drain region 31 side and be in contact with the n- - type drift region 32.

[0066] The first p- +The p-type region 61 is provided apart from the p-type base region 34 and faces the bottom surface of the gate trench 37 in the depth direction Z. The first p + type region 61 may reach the bottom surface of the gate trench 37. The first p + type region 61 may have a floating potential, but at a predetermined location between the first and second p + type regions 61 and 62, another p + type region (not shown) may be arranged, or a part of the first p + type region 61 may extend toward the second p + type region 62, so that the second p + type region 62 may be electrically connected at a predetermined location to the second p

[0067] The second p + type region 62 is provided between adjacent gate trenches 37, apart from the first p + type region 61 and the gate trench 37, and is adjacent to the p-type base region 34 in the depth direction Z. Also, the second p + type region 62 (hereinafter referred to as the outer peripheral p + type region (second conductivity type high concentration region) 62a) is provided outside the outermost gate trench 37, apart from the first p + type region 61 and the outermost gate trench 37, and is adjacent to the outer peripheral p-type base region 34a in the depth direction Z. The outer peripheral p + type region 62a extends outward from the active region 1 and is provided over the entire intermediate region 3.

[0068] The outer peripheral p + type region 62a surrounds the periphery of the active region 1 in a substantially rectangular shape and is connected to the ends of all the first and second p + type regions 61 and 62. The outer peripheral p + type region 62a extends outward from the intermediate region 3 beyond the step 53 and is exposed on the second surface 10b of the front surface of the semiconductor substrate 10. The outer peripheral p + type region 62a may also be exposed on the third surface 10c of the front surface of the semiconductor substrate 10. Being exposed on the second and third surfaces 10b and 10c of the front surface of the semiconductor substrate 10 means being in contact with the field oxide film 81 described later on the second and third surfaces 10b and 10c.

[0069] 1st and 2nd p + type regions 61 and 62 (outer periphery p + type region 62a included) and FLR101 to 118 described later are formed simultaneously, the 1st and 2nd p + type regions 61 and 62 (outer periphery p + type region 62a included), the impurity concentration is, for example, 1×10 18 / cm 3 less than, preferably, for example, 3×10 17 / cm 3 or more and 9×10 17 / cm 3 or less. Also, by setting the thickness (length in the depth direction Z) of the 2nd p + type region 62 to be, for example, in the range of 0.7 μm or more and 1.1 μm or less, the 2nd p + type region 62 (outer periphery p + type region 62a included) can be formed simultaneously with FLR101 to 118 described later.

[0070] n - portion of the n-type epitaxial layer 72 excluding the n-type current diffusion region 33, the 1st and 2nd p + type regions 61 and 62 (outer periphery p + type region 62a included), FLR101 to 118 described later, and the n + type channel stopper region 21 to be described later is the n - type drift region 32. The n - type drift region 32 is provided between these regions and the n + type drain region 31. The n - type drift region 32 extends from the active region 1 to the chip end and is exposed at the end of the semiconductor substrate 10 (side surface of the semiconductor substrate 10).

[0071] The interlayer insulating film 40 is provided on substantially the entire front surface of the semiconductor substrate 10 and covers all the gate electrodes 39. In the active region 1, contact holes 40a and 40b that penetrate the interlayer insulating film 40 in the depth direction Z are provided in the interlayer insulating film 40. In the contact hole 40a, n +The n-type source region 35 and the p ++ type contact region 36 are exposed. The contact hole 40b is provided, for example, in a substantially rectangular shape surrounding the periphery of the active region 1. In the contact hole 40b, the outer peripheral p ++ type contact region 36a is exposed.

[0072] In the intermediate region 3 and the edge termination region 2, the first to third surfaces 10a to 10c of the front surface of the semiconductor substrate 10 are the outer peripheral p ++ type contact region 36a and are covered with an insulating layer in which a field oxide film 81 and an interlayer insulating film 40 are laminated in this order on the entire surface outside. A field plate (conductive film) is not provided, and the first to third surfaces 10a to 10c of the front surface of the semiconductor substrate 10 in the intermediate region 3 and the edge termination region 2 are the outer peripheral p ++ type contact region 36a and the entire surface outside is in contact with the field oxide film 81.

[0073] In the intermediate region 3, on the field oxide film 81, the outer peripheral p ++ type contact region 36a and outside, a gate polysilicon (poly-Si) wiring layer 82 serving as a gate runner and a gate metal wiring layer 83 are laminated in this order. The gate polysilicon wiring layer 82 and the gate metal wiring layer 83 face the end of the gate trench 37 in the depth direction Z and are electrically connected to the gate electrode 39 at the end of the gate trench 37, and electrically connect the gate electrode 39 and a gate pad (not shown).

[0074] In the surface region of the second surface 10b of the front surface of the semiconductor substrate 10, n - type epitaxial layer 72, a plurality of p - type regions of floating potential (FLR (second conductivity type breakdown voltage region): hatched portion) constituting the FLR structure 20 are selectively provided, and outside thereof, an n + type channel stopper region 21 is selectively provided. The FLR structure 20 is preferably composed of 16 or more FLRs (here, 18 are used, and are numbered 101 to 118 from the inside). FLR101 to 118 and n +The p-type channel stopper region 21 is exposed on the second surface 10b of the front surface of the semiconductor substrate 10.

[0075] FLR101 to 118 are located outside the outer peripheral p- + type region 62a, and are provided separately from each other between the outer peripheral p- + type region 62a and the n- + type channel stopper region 21, and concentrically surround the periphery of the active region 1 via the intermediate region 3. The innermost FLR101 among the plurality of FLR101 to 118 is in a direction parallel to the front surface of the semiconductor substrate 10 and faces the outer peripheral p- + type region 62a. The outermost FLR118 among the plurality of FLR101 to 118 is in a direction parallel to the front surface of the semiconductor substrate 10 and faces the n- + type channel stopper region 21.

[0076] All of the FLR101 to 118 are surrounded by the n- - type drift region 32. The n- + type drift region 32 is disposed between the innermost FLR101 and the outer peripheral p- + type region 62a, between adjacent FLR101 to 118, and between the outermost FLR118 and the n- - type channel stopper region 21. At the pn junctions between these FLR101 to 118 and the n- - type drift region 32, the high voltage applied to the edge termination region 2 when the MOSFET is off is borne, and a predetermined breakdown voltage of the edge termination region 2 is ensured.

[0077] The first interval w1 between the innermost FLR101 and the outer peripheral p- + type region 62a is preferably within a range of, for example, 1.2 μm or less. The first interval w1 between the innermost FLR101 and the outer peripheral p- + type region 62a is the interval between the pn junction (main junction) between the outer peripheral p- + type region 62a and the n- - type drift region 32 and the innermost (the first one from the inside) FLR101. The innermost FLR101 and the outer peripheral p- +The first interval w1 with the p-type region 62a is set narrower as the breakdown voltage of the semiconductor device 30 is lower.

[0078] The innermost FLR101 may be provided at a position just in contact with the outer periphery p + type region 62a (w1 = 0.0 μm), or may be provided at a position overlapping and contacting the outer periphery p + type region 62a (w1 < 0.0 μm). For example, when the breakdown voltage of the semiconductor device 30 is 600 V, the innermost FLR101 is arranged in contact with the outer periphery p + type region 62a. When the innermost FLR101 is in contact with the outer periphery p + type region 62a, the second to 18th intervals w2 to w18 between adjacent FLR101 to 118 are set wider compared to the case where the innermost FLR101 is away from the outer periphery p + type region 62a.

[0079] The second to 18th intervals w2 to w18 between adjacent FLR101 to 118 are set narrower as the breakdown voltage of the semiconductor device 30 is lower. The second to 18th intervals w2 to w18 between adjacent FLR101 to 118 uniformly become wider with a predetermined increase width (width in the normal direction) as they are arranged more outward. The normal direction is the direction from the active region 1 side (inner side) toward the chip end. For example, when the increase width is 0.1 μm, the jth interval wj between adjacent FLR102 to 118 is a value obtained by adding 0.1 μm to the kth interval wk between adjacent FLR101 to 117 on the inner side (j = 2 to 18, k = j - 1).

[0080] When the innermost FLR101 is in contact with the outer periphery p + type region 62a, it is preferable to arrange from the innermost FLR101 to the fourth FLR104 from the inner side under the following conditions. The second interval w2 between the innermost FLR101 and the second FLR102 from the inner side may be, for example, within a range of about 2.1 μm or less. The third interval w3 between the second FLR102 from the inner side and the third FLR103 from the inner side may be, for example, within a range of about 3.1 μm or less, and preferably within a range of about 1.0 μm or less.

[0081] When the third interval w3 between the second FLR102 from the inside and the third FLR103 from the inside is about 1.0 μm or less, the fourth interval w4 between the third FLR103 from the inside and the fourth FLR104 from the inside may be, for example, within a range of about 2.0 μm or less. When the innermost FLR101 and the outer periphery p + type region 62a are separated, the fifth to eighteenth intervals w5 to w18 between the fourth and subsequent FLR104 to 118 from the inside should be wider than the first interval w1 between the innermost FLR101 and the outer periphery p + type region 62a.

[0082] All of the FLR101 to 118 are formed with the same configuration and have substantially the same width (width in the normal direction) w21, substantially the same thickness (length in the depth direction Z) t10, and substantially the same impurity concentration. The width w21 of the FLR101 to 118 is, for example, about 1 / 2 of the width w210 of the FLR291 of the conventional FLR structure 290 (see FIG. 19), and specifically, for example, about 5 μm or more and 15 μm or less (1200 V breakdown voltage). The thickness t10 of the FLR101 to 118 is, for example, about twice the thickness t201 of the FLR291 of the conventional FLR structure 290 (see FIG. 19), and specifically, for example, about 0.7 μm or more and 1.1 μm or less.

[0083] By making the thickness t10 of the FLR101 to 118 thicker than the thickness t201 of the FLR291 of the conventional FLR structure 290, compared with the conventional FLR structure 290, the electric field applied to the FLR101 to 118 when the semiconductor Device 30 is off can be relaxed. Therefore, compared with the conventional FLR structure 290, the width w21 of the FLR101 to 118, the first interval w1 between the innermost FLR101 and the outer periphery p + type region 62a, and the second to eighteenth intervals w2 to w18 between the adjacent FLR101 to 118 can be made narrower.

[0084] The length w20 of the edge termination region 2 (length from the intermediate region 3 to the chip end) is about half the length w202 (see FIG. 19) of the edge termination region 202 in which a conventional FLR structure 290 having the same number (18) of FLRs 291 is arranged, and is about the same as the length w201 (see FIG. 18) of the edge termination region 202 in which a spatially modulated FLR structure 220 is arranged (for example, about 100 μm to 200 μm in the case of a breakdown voltage of 1200 V). Each of the FLRs 101 to 118 has about the same cross-sectional area as the FLR 291 of the conventional FLR structure 290, and has a vertically elongated, approximately rectangular cross-sectional shape that is longer in the depth direction Z than the FLR 291.

[0085] In this way, by making all of the FLRs 101-118 have a vertically elongated cross-sectional shape that is long in the depth direction Z, even if charges are accumulated in the insulating layers (field oxide film 81, interlayer insulating film 40, and first protective film 50) on the second surface 10b of the front surface of the semiconductor substrate 10 due to the MOSFET being on for a long period of time, the FLRs are less likely to be adversely affected by the charges. The second and subsequent FLRs 102-118 from the inside may have a width w21 wider than the innermost FLR 101. In this case, the second and subsequent FLRs 102-118 from the inside all have approximately the same width w21.

[0086] The adverse effect of charges in the insulating layer is that when the insulating layer is positively charged, the positive charges in the insulating layer cause n - The depletion layer in the n-type drift region 32 is suppressed from spreading. In addition, when the insulating layer is negatively charged, the n-type drift region 32 is suppressed from spreading. - The potential in the type drift region 32 is pulled outward by the negative charge in the insulating layer and tends to extend outward. The FLR structure 20 is less susceptible to the adverse effects of the charge accumulated in the insulating layer, and therefore the withstand voltage characteristics of the FLR structure 20 can be stabilized.

[0087] The impurity concentration of the FLRs 101 to 118 is lower than the impurity concentration of the FLR 291 (see FIG. 19) constituting the conventional FLR structure 290, for example, 1×10 18 / cm 3It is within the range of less than. Preferably, the impurity concentration of FLR101 to 118 is, for example, 3×10 17 / cm 3 or more and 9×10 17 / cm 3 or less, and may be, for example, 5×10 17 / cm 3 or so. The lower the breakdown voltage of the semiconductor device 30, the higher the impurity concentration of FLR101 to 118 should be set.

[0088] By making the impurity concentration of FLR101 to 118 lower than the impurity concentration of FLR291 that constitutes the conventional FLR structure 290, compared with the conventional FLR structure 290, the electric field applied to FLR101 to 118 during the off state of the semiconductor Device 30 can be relaxed. Therefore, compared with the conventional FLR structure 290, the width w21 of FLR101 to 118, the first interval w1 between the innermost FLR101 and the outer peripheral p + -type region 62a, and the second to 18th intervals w2 to w18 between adjacent FLR101 to 118 can be made narrower.

[0089] FLR101 to 118 may be formed simultaneously with the first and second p + -type regions 61 and 62 (including the outer peripheral p + -type region 62a). FLR101 to 118 may reach a deeper position on the n + -type drain region 31 side than the first and second p + -type regions 61 and 62 (including the outer peripheral p + -type region 62a). In this case, compared with the case where FLR101 to 118 are at the same depth position as the first and second p + -type regions 61 and 62 on the n + -type drain region 31 side, the second to 18th intervals w2 to w18 between adjacent FLR101 to 118 are set wider.

[0090] n + -type channel stopper region 21 is provided outside the FLR structure 20 and separated from the FLR structure 20. n +The p-channel stopper region 21 is exposed at the end of the semiconductor substrate 10. n + By providing the p-channel stopper region 21, n + Compared with the case where the p-channel stopper region 21 is not provided, when the MOSFET is off, n - It is possible to suppress the depletion layer that spreads from the active region 1 to the outside in the p-type drift region 32. A channel stopper electrode (not shown) is not provided.

[0091] n + Instead of the p-channel stopper region 21, even when a p + -type channel stopper region (not shown) is provided, n + The same effect as that of the p-channel stopper region 21 can be obtained. Even when negative charges (negative charges) are accumulated in the insulating layer on the second surface 10b of the front surface of the semiconductor substrate 10, when the MOSFET is off, n - If the conditions of the FLR structure 20 are set so that the depletion layer that spreads from the active region 1 to the outside in the p-type drift region 32 does not reach the chip end, n + The p-channel stopper region 21 may not be provided.

[0092] The second and third surfaces 10b and 10c of the front surface of the semiconductor substrate 10 are covered with an insulating layer in which the field oxide film 81 and the interlayer insulating film 40 are laminated in this order as described above. The insulating layer is, on the second surface 10b of the front surface of the semiconductor substrate 10, FLR101 to 118, and n + -type channel stopper region 21, and the p - -type drift region 32 sandwiched between these regions. The first protective film 50 (passivation film) is a surface protective film that covers the entire front surface of the semiconductor substrate 10 and protects the front surface of the semiconductor substrate 10.

[0093] The total thickness t20 of the field oxide film 81, the interlayer insulating film 40, and the first protective film 50 is equal to or greater than the thickness of the gate insulating film 38, and may be a thickness that can withstand the applied voltage. Specifically, for example, when the breakdown voltage of the MOSFET is 1700 V, it is about 1.7 μm or more. The nickel silicide (NixSiy, where x and y are integers; hereinafter collectively referred to as NiSi) film 41 makes ohmic contact with the semiconductor substrate 10 inside the contact holes 40a and 40b, and n + type source region 35 and p ++ type contact region 36 are electrically connected.

[0094] The NiSi film 41 is electrically connected to the outer peripheral p ++ type contact region 36a in the contact hole 40b. When the p ++ type contact region 36 and the outer peripheral p ++ type contact region 36a are not provided, instead of the p ++ type contact region 36 and the outer peripheral p ++ type contact region 36a, the p-type base region 34 and the outer peripheral p-type base region 34a are exposed to the contact holes 40a and 40b, respectively, and are electrically connected to the NiSi film 41. A barrier metal 46 is provided along the surfaces of the interlayer insulating film 40 and the NiSi film 41 over the entire surfaces of the interlayer insulating film 40 and the NiSi film 41 in the active region 1.

[0095] The barrier metal 46 has a function of preventing mutual reaction between the metal films of the barrier metal 46 or between the regions facing each other with the barrier metal 46 interposed therebetween. The barrier metal 46 may have, for example, a laminated structure in which a first titanium nitride (TiN) film 42, a first titanium (Ti) film 43, a second TiN film 44, and a second Ti film 45 are laminated in this order. The first TiN film 42 covers the entire surface of the interlayer insulating film 40 in the active region 1. The first Ti film 43 is provided over the entire surfaces of the first TiN film 42 and the NiSi film 41.

[0096] The second TiN film 44 is provided on the entire surface of the first Ti film 43. The second Ti film 45 is provided on the entire surface of the second TiN film 44. An aluminum (Al) electrode film 47 is provided on the entire surface of the second Ti film 45. The Al electrode film 47 is electrically connected to the n + -type source region 35, p ++ -type contact region 36 and the outer peripheral p ++ -type contact region 36a. The Al electrode film 47 and the barrier metal 46 terminate inside the gate metal wiring layer 83 described later in the intermediate region 3.

[0097] The Al electrode film 47 may be, for example, an Al film having a thickness of about 5 μm, an aluminum-silicon (Al-Si) film, or an aluminum-silicon-copper (Al-Si-Cu) film. The Al electrode film 47, the barrier metal 46, and the NiSi film 41 function as a source electrode (first electrode). One end of the terminal pin 49 is joined to the Al electrode film 47 via a plating film 48 and a solder layer (not shown). The other end of the terminal pin 49 is joined to a metal bar (not shown) disposed facing the front surface of the semiconductor substrate 10.

[0098] Also, the other end of the terminal pin 49 is exposed outside the case (not shown) on which the semiconductor substrate 10 is mounted and is electrically connected to an external device (not shown). The terminal pin 49 is solder-joined to the plating film 48 in a state of standing substantially perpendicular to the front surface of the semiconductor substrate 10. The terminal pin 49 is a round bar-shaped (cylindrical) wiring member having a predetermined diameter corresponding to the current capacity of the MOSFET and is connected to an external ground potential (lowest potential). The terminal pin 49 is an external connection terminal for taking out the potential of the Al electrode film 47 to the outside.

[0099] The first and second protective films 50 and 51 are heat-resistant organic polymer material films such as polyimide. The first protective film 50 covers the portions of the surface of the Al electrode film 47 other than the plating film 48. The first protective film 50 extends to the chip end so as to cover the Al electrode film 47, the interlayer insulating film 40, and the gate metal wiring layer 83, and functions as a passivation film. The portion of the Al electrode film 47 exposed at the opening of the first protective film 50 serves as a source pad. The second protective film 51 covers the boundary between the plating film 48 and the first protective film 50.

[0100] On the front surface of the semiconductor substrate 10, an n-type epitaxial layer may be exposed in the edge termination region 2, and a flat surface continuous from the active region 1 to the chip end may be provided without providing the step 53. The drain electrode (second electrode) 52 is in ohmic contact with the entire back surface (the back surface of the n-type starting substrate 71) of the semiconductor substrate 10. On the drain electrode 52, a drain pad (electrode pad: not shown) is provided with a laminated structure in which, for example, a Ti film, a nickel (Ni) film, and a gold (Au) film are laminated in sequence. - + - +

[0101] By bonding the terminal pin 49 to the Al electrode film 47 on the front surface of the semiconductor substrate 10 and bonding the drain pad on the back surface to the metal base plate of the insulating substrate, the semiconductor substrate 10 has a double-sided cooling structure with a cooling structure on each of the two main surfaces. The heat generated in the semiconductor substrate 10 is radiated from the fin portion of the cooling fins through the metal base plate bonded to the drain pad on the back surface of the semiconductor substrate 10, and is also radiated from the metal bar bonded to the terminal pin 49 on the front surface of the semiconductor substrate 10.

[0102] The operation of the semiconductor device 30 according to Embodiment 1 will be described. When a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 39 in a state where a positive voltage (forward voltage) is applied to the source electrode (Al electrode film 47) with respect to the drain electrode 52, a channel (n-type inversion layer) is formed in the portion along the gate trench 37 of the p-type base region 34. Thereby, from the n-type drain region 31 through the channel to the n- + type source region 32, a current flows.+ A current flows toward the type source region 35, and the MOSFET turns on.

[0103] On the other hand, when a voltage lower than the gate threshold voltage is applied to the gate electrode 39 while a forward voltage is applied between the source and the drain, in the active region 1, the first and second p + type regions 61 and 62, the p-type base region 34, the n-type current diffusion region 33, and the n - type drift region 32 are reverse-biased, and no current flows, so the MOSFET maintains the off state. At this time, when the pn junction is reverse-biased, a depletion layer spreads from the pn junction, and the breakdown voltage of the active region 1 is ensured.

[0104] Furthermore, when the MOSFET is off, the depletion layer spreading from the pn junction in the active region 1 extends the edge termination region 2 outward in the normal direction (toward the chip end) by the pn junction between the FLR101 to 118 in the edge termination region 2 and the n - type drift region 32. A predetermined breakdown voltage based on the breakdown electric field strength of silicon carbide and the depletion layer width (the width in the direction from the active region 1 toward the chip end (the normal direction of the concentrically arranged FLR101 to 118)) can be ensured by the amount by which the depletion layer extends the edge termination region 2 outward.

[0105] Also, when the MOSFET is off, by applying a negative voltage to the drain electrode 52 with respect to the source electrode (Al electrode film 47), a current can flow in the forward direction through the parasitic diode formed by the pn junction between the first and second p + type regions 61 and 62, the p-type base region 34, the n-type current diffusion region 33, and the n - type drift region 32. For example, when the MOSFET is a device for an inverter, the parasitic diode built into the semiconductor substrate 10 can be used as a freewheeling diode for protecting the MOSFET itself.

[0106] Next, a method for manufacturing the semiconductor device 30 according to Embodiment 1 will be described. FIGS. 3 to 8 are cross-sectional views showing the states during the manufacture of the semiconductor device according to Embodiment 1. FIGS. 3 to 8 show the active region 1, and reference is made to FIG. 2 for the edge termination region 2 and the intermediate region 3. Here, a case will be described as an example in which each part of the edge termination region 2 and the intermediate region 3 is formed simultaneously with each part having the same impurity concentration and depth as each part formed in the active region 1.

[0107] First, as shown in FIG. 3, an n-type starting substrate (starting wafer) 71 made of silicon carbide is prepared. Next, + an n-type epitaxial layer 72a (72) doped with nitrogen at a lower concentration than the n-type starting substrate 71 is epitaxially grown on the front surface of the n-type starting substrate 71. + The thickness t1 of the n-type epitaxial layer 72 is, for example, about 30 μm when the breakdown voltage is in the 3300 V class, and about 10 μm when the breakdown voltage is in the 1200 V class. + On the front surface of the n-type starting substrate 71, - an n-type epitaxial layer 72a (72) doped with nitrogen at a lower concentration than the n-type starting substrate 71 is epitaxially grown. - The thickness t1 of the n-type epitaxial layer 72 is, for example, about 30 μm when the breakdown voltage is in the 3300 V class, and about 10 μm when the breakdown voltage is in the 1200 V class.

[0108] Next, as shown in FIG. 4, by photolithography and ion implantation of a p-type impurity such as Al, etc., in the active region 1, - a first p-type region 61, and a p-type region 91 that becomes a part of the second p-type region 62 are formed in the surface region of the n-type epitaxial layer 72. At this time, + simultaneously with the first p-type region 61, an outer peripheral p-type region 62a and each p-type region 91 that becomes a part of FLR101 to 118 are formed in the surface region of the n-type epitaxial layer 72. + a p-type region 91 that becomes a part of the second p-type region 62 are formed in the surface region of the n-type epitaxial layer 72. + simultaneously with the first p-type region 61, an outer peripheral p-type region 62a and each p-type region 91 that becomes a part of FLR101 to 118 are formed in the surface region of the n-type epitaxial layer 72. - a first p-type region 61, and a p-type region 91 that becomes a part of the second p-type region 62 are formed in the surface region of the n-type epitaxial layer 72. + simultaneously with the first p-type region 61, an outer peripheral p-type region 62a and each p-type region 91 that becomes a part of FLR101 to 118 are formed in the surface region of the n-type epitaxial layer 72. + simultaneously with the first p-type region 61, an outer peripheral p-type region 62a and each p-type region 91 that becomes a part of FLR101 to 118 are formed in the surface region of the n-type epitaxial layer 72. + a p-type region 91 that becomes a part of the second p-type region 62 are formed in the surface region of the n-type epitaxial layer 72.

[0109] Next, by photolithography and ion implantation of an n-type impurity such as nitrogen (N), etc., in the surface region of the n-type epitaxial layer 72, - an n-type region 92 that becomes a part of the n-type current diffusion region 33 is formed in the surface region of the n-type epitaxial layer 72. +Each ion implantation for forming the p-type regions 61 and 91 and the n-type region 92 may be a multi-step ion implantation in which a predetermined dose amount is implanted in multiple times (multiple steps) under different conditions. p + The formation order of the p-type regions 61 and 91 and the n-type region 92 may be swapped.

[0110] In the active region 1, the distance d2 between the adjacent p + -type regions 61 and 91 is about 1.5 μm, for example. p + The p-type regions 61 and 91 have a depth d1 of about 0.5 μm, for example, and an impurity concentration of 1.0×10 18 / cm 3 or less. The depth d3 and the impurity concentration of the n-type region 92 are, for example, about 0.4 μm and 1.0×10 17 / cm 3 or more and 5.0×10 18 / cm 3 or less, respectively.

[0111] Next, as shown in FIG. 5, an n - -type epitaxial layer 72b doped with an n-type impurity such as nitrogen, for example, is further epitaxially grown on the n-type epitaxial layer 72a with a thickness t2 of about 0.5 μm, for example, to make the n - -type epitaxial layer 72 have a predetermined thickness. The impurity concentration of the n - -type epitaxial layer 72 (72a, 72b) is, for example, 3×10 - / cm 15 or so. 3 Next, by photolithography and ion implantation of a p-type impurity such as Al, a p

[0112] -type region 93 that becomes part of the second p - -type region 62 is formed in the n + -type epitaxial layer 72b in the active region 1. At this time, while the p + -type region 93 is formed in the n - -type epitaxial layer 72b, an outer peripheral p + -type region 62a and each p + -type region that becomes part of the FLR101 to 118 are also formed. +A type region 93 is formed.

[0113] Next, by photolithography and ion implantation of an n-type impurity such as nitrogen, an n - type region 94 that becomes part of the n-type current diffusion region 33 is formed in the n-type epitaxial layer 72b. The p + type regions 91 and 93 adjacent to each other in the depth direction Z are connected, and the second p + type region 62, the outer peripheral p + type region 62a, and FLR101 to 118 are formed. The n-type regions 92 and 94 adjacent to each other in the depth direction Z are connected, and the n-type current diffusion region 33 is formed.

[0114] The thickness t10 of FLR101 to 118 is set so that even if the surface region of FLR101 to 118 is slightly removed after the formation of the subsequent step 53, it falls within the above-described range (for example, about 0.7 μm or more and 1.1 μm or less). p + The conditions such as the impurity concentration of the p + type region 93 and the n-type region 94 are the same as those of the p + type region 91 and the n-type region 92, respectively. The formation order of the p

[0115] Next, as shown in FIG. 6, a p-type epitaxial layer 73 doped with a p-type impurity such as aluminum is epitaxially grown on the n - type epitaxial layer 72. The thickness t3 and the impurity concentration of the p-type epitaxial layer 73 are, for example, about 1.3 μm and 4×10 17 / cm 3 respectively. In the steps up to here, a semiconductor substrate (semiconductor wafer) 10 in which the epitaxial layers 72 and 73 are sequentially stacked on the n + type starting substrate 71 is completed.

[0116] Next, the portions of the p-type epitaxial layer 73 on both sides of the edge termination region 2 are removed by etching to form a step 53 that is lower at the portion of the edge termination region 2 (second surface 10b) than at the portions of the active region 1 and the intermediate region 3 (first surface 10a) on the front surface of the semiconductor substrate 10. At this time, the etching may be stopped on the condition (stopper) that FLR101 to 118 are exposed on the front surface of the semiconductor substrate 10 in the edge termination region 2.

[0117] By stopping the etching for forming this step 53 immediately after FLR101 to 118 are exposed on the front surface of the semiconductor substrate 10, FLR101 to 118 can be left with a predetermined thickness t10. Therefore, a predetermined breakdown voltage based on the design conditions of the FLR structure can be stably obtained. On the second surface 10b that newly becomes the front surface of the semiconductor substrate 10 in the edge termination region 2, an n - -type epitaxial layer 72 is exposed.

[0118] The third surface 10c connecting the first surface 10a and the second surface 10b of the front surface of the semiconductor substrate 10 may form an obtuse angle (inclined surface) or a substantially right angle (vertical surface) with respect to the first and second surfaces 10a and 10b, for example. On the third surface 10c of the front surface of the semiconductor substrate 10, the p-type epitaxial layer 73 is exposed. By the etching for forming this step 53, the surface region of the n - -type epitaxial layer 72 may be slightly removed together with the p-type epitaxial layer 73.

[0119] Next, an n + -type source region 35, a p ++ -type contact region 36, and an outer peripheral p ++ -type contact region 36a are selectively formed on the surface region of the p-type epitaxial layer 73 by photolithography and ion implantation under predetermined conditions. By ion implantation, an n - -type channel stopper region 21 is selectively formed on the surface region of the n + -type epitaxial layer 72 exposed on the second surface 10b of the front surface of the semiconductor substrate 10 in the edge termination region 2.

[0120] n + -type source region 35, p ++ -type contact region 36, outer peripheral p ++ -type contact region 36a and n + The formation order of the n-type channel stopper region 21 can be interchanged. For example, n + -type source region 35 and n + -type channel stopper region 21 may be formed simultaneously. n + -type source region 35, p ++ -type contact region 36 and outer peripheral p ++ -type contact region 36a may be formed before the formation of the step 53.

[0121] Next, a heat treatment (hereinafter referred to as activation annealing) for activating the impurities implanted into the epitaxial layers 72 and 73 is performed. The activation annealing may be performed once collectively after all the diffusion regions are formed by ion implantation, or may be performed each time a diffusion region is formed by ion implantation. The temperature and time of the activation annealing may be, for example, about 1700°C and about 2 minutes, respectively.

[0122] By this activation annealing, all the diffusion regions formed by ion implantation (n-type current diffusion region 33, first and second p + -type regions 61 and 62, outer peripheral p + -type region 62a, n + -type source region 35, p ++ -type contact region 36, outer peripheral p ++ -type contact region 36a, n + -type channel stopper region 21 and FLR101 to 118), the impurities are activated, and impurity diffusion according to each impurity concentration and impurity diffusion coefficient occurs according to Gauss's law.

[0123] Next, as shown in FIG. 7, by photolithography and etching, from the front surface of the semiconductor substrate 10, n + -type source region 35 and p-type base region 34 are penetrated, and inside the n-type current diffusion region 33, the first p +A gate trench 37 is formed to face the p-type region 61. The p-type base region 34 is a portion of the p-type epitaxial layer 73 that remains p-type without being ion-implanted. An etching for forming the gate trench 37 may be used to form a step 53.

[0124] Next, as shown in FIG. 8, a gate insulating film 38 is formed along the first surface 10a of the front surface of the semiconductor substrate 10 and the inner walls (side walls and bottom surface) of the gate trench 37. The gate insulating film 38 may be, for example, a thermal oxide film formed by thermally oxidizing the semiconductor surface at a temperature of about 1000° C. in an oxygen (O 2 ) atmosphere, or may be a deposited film by high temperature oxidation (HTO: High Temperature Oxide).

[0125] Next, a phosphorus (P)-doped polysilicon layer is deposited (formed) on the front surface of the semiconductor substrate 10 so as to be embedded inside the gate trench 37. Next, this polysilicon layer is selectively removed, and only the portion that becomes the gate electrode 39 is left inside the gate trench 37. Also, a part of the polysilicon layer may be left as the gate electrode 39 and at the same time, a part of the polysilicon layer may be left as the gate polysilicon wiring layer 82.

[0126] When the gate electrode 39 and the gate polysilicon wiring layer 82 are formed simultaneously, after the formation of the gate insulating film 38 and before the deposition of the phosphorus-doped polysilicon layer, a field oxide film 81 is formed on the front surface of the semiconductor substrate 10 in the intermediate region 3 and the edge termination region 2. Although not shown in FIG. 2, the gate insulating film 38 may remain between the front surface of the semiconductor substrate 10 and the field oxide film 81.

[0127] Next, an interlayer insulating film 40, such as BPSG (Boro Phospho Silicate Glass) or PSG, which covers the entire front surface of the semiconductor substrate 10, the gate electrode 39, and the gate polysilicon wiring layer 82, is formed, for example, with a thickness of 1 μm. Next, contact holes 40a and 40b that penetrate the interlayer insulating film 40 and the gate insulating film 38 in the depth direction Z are formed by photolithography and etching.

[0128] In the contact hole 40a, an n + -type source region 35 and a p ++ -type contact region 36 are exposed. In the contact hole 40b, an outer peripheral p ++ -type contact region 36a is exposed. Also, simultaneously with the formation of the contact holes 40a and 40b, a contact hole through which the gate polysilicon wiring layer 82 is exposed is formed in the interlayer insulating film 40. Next, the interlayer insulating film 40 is planarized (reflowed) by heat treatment.

[0129] Next, a first TiN film 42 that covers only the interlayer insulating film 40 in the active region 1 is formed. Next, a NiSi film 41 that makes an ohmic contact with the front surface of the semiconductor substrate 10 is formed inside the contact holes 40a and 40b. Also, as a drain electrode 52, a NiSi film that makes an ohmic contact with the back surface of the semiconductor substrate 10 is formed. The NiSi film is formed by reacting a nickel film with the semiconductor substrate 10 by heat treatment at a temperature of, for example, 970°C.

[0130] Next, by sputtering, a first Ti film 43, a second TiN film 44, and a second Ti film 45 are sequentially stacked so as to cover the NiSi film 41 and the first TiN film 42, and a barrier metal 46 is formed so as to cover substantially the entire active region 1. Next, an Al electrode film 47 is deposited on the second Ti film 45. Also, simultaneously with the Al electrode film 47, a gate pad (not shown) is formed on the interlayer insulating film 40 at a distance from the Al electrode film 47.

[0131] Meanwhile, simultaneously with the Al electrode film 47, a gate metal wiring layer 83 is formed on the gate polysilicon wiring layer 82. Next, on the surface of the drain electrode 52, for example, a Ti film, a Ni film, and a gold (Au) film are sequentially laminated to form a drain pad (not shown). Next, a first protective film 50 made of an organic polymer material such as polyimide is formed on the entire front surface of the semiconductor substrate 10, and the Al electrode film 47, the gate pad, and the gate metal wiring layer 83 are covered with the first protective film 50.

[0132] Next, the first protective film 50 is selectively removed to expose the Al electrode film 47 (source pad) and the gate pad in different formed openings. Next, after general plating pretreatment, a plating film 48 is formed in each opening of the first protective film 50 by a general plating process. Next, the plating film 48 is dried by heat treatment (baking). Next, a second protective film 51 made of an organic polymer material such as polyimide is formed to cover the boundary between the plating film 48 and the first protective film 50.

[0133] Next, the strength of the first and second protective films 50 and 51 is improved by heat treatment (curing). Next, terminal pins 49 are joined to the plating film 48 by solder layers respectively. On the gate pad (not shown), a wiring structure with terminal pins joined in the same manner as on the Al electrode film 47 is also formed. Thereafter, the semiconductor substrate 10 (semiconductor wafer) is diced (cut) into individual chip-like pieces, and thus the MOSFET (semiconductor device 30) shown in FIGS. 1 and 2 is completed.

[0134] As described above, according to Embodiment 1, the edge termination region is provided with an FLR structure as a breakdown voltage structure, and the impurity concentrations of the plurality of FLRs constituting the FLR structure are lower than the impurity concentrations of the FLRs of the conventional FLR structure (see FIG. 19) and are in the range of less than 1×10 18 / cm 3 and the thickness of the FLR is thicker than the thickness of the FLR of the conventional FLR structure and is 0.7 μm or more and 1.1 μm or less. Thereby, since the margin of the interval between adjacent FLRs can be increased, the degree of completion of the FLR structure is increased, and the reliability of the semiconductor device can be improved.

[0135] Also, according to Embodiment 1, by reducing the impurity concentration of the FLR, the electric field applied to the FLR during the off state is relaxed. By increasing the thickness of the FLR, the FLR reaches a deep position from the front surface of the semiconductor substrate, so it is less affected by the adverse effects of external charges accumulated in the insulating layer on the front surface of the semiconductor substrate in the edge termination region. As a result, the breakdown voltage of the edge termination region can be improved, and thus the length of the edge termination region can be shortened to about 1 / 2 compared with the conventional FLR structure.

[0136] Also, according to Embodiment 1, by using a normal FLR structure for the breakdown voltage structure, the design of the breakdown voltage structure becomes easier compared to the case of using a spatially modulated FLR structure (see FIG. 18), and it is less affected by the ion implantation accuracy. Also, as described above, since the margin of the interval between adjacent FLRs becomes larger, it is less affected by the ion implantation accuracy compared with the conventional FLR structure. Therefore, the fabrication (manufacture) of the semiconductor device becomes simpler compared to the case of forming a spatially modulated FLR structure or a conventional FLR structure as the breakdown voltage structure.

[0137] (Embodiment 2) Next, the structure of the semiconductor device according to Embodiment 2 will be described. FIG. 9 is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 2. The layout of the semiconductor device 100a according to Embodiment 2 as viewed from the front surface side of the semiconductor substrate 10 is the same as that in FIG. 1. The difference between the FLR structure 120 of the semiconductor device 100a according to Embodiment 2 shown in FIG. 9 and the FLR structure 20 (see FIG. 2) of the semiconductor device 30 according to Embodiment 1 is that the FLRs (p - -type regions) 121 to 138 constituting the FLR structure 120 are not exposed on the front surface of the semiconductor substrate 10.

[0138] In Embodiment 2, between the second surface 10b on the front surface of the semiconductor substrate 10 and the FLRs 121 to 138, n -The P-type drift region 32 is provided. The upper ends (the ends on the second surface 10b side of the front surface of the semiconductor substrate 10) of FLR121 to 138 are separated from the second surface 10b of the front surface of the semiconductor substrate 10 by, for example, about 0.1 μm or more and 0.2 μm or less. Specifically, for example, they may be at the same depth position as the upper end of the first P + type region 61. The conditions of the impurity concentration of FLR121 to 138 are the same as those of FLR101 to 118 in the first embodiment.

[0139] The depth position of the ends (lower ends) of FLR121 to 138 on the n + type drain region 31 side is the same as that of FLR101 to 118 in the first embodiment. The conditions of the thickness (length in the depth direction Z) t11 and the width w30 of FLR121 to 138 are the same as the thickness t10 and the width w21 of FLR101 to 118 in the first embodiment, respectively. The condition of the first interval w1 between the innermost FLR121 and the outer peripheral P + type region 62a, and the conditions of the second to 18th intervals w2 to w18 between adjacent FLR121 to 138 are the same as those of FLR101 to 118 in the first embodiment.

[0140] The manufacturing method of the semiconductor device 100a according to the second embodiment is the manufacturing method of the semiconductor device 30 according to the first embodiment, in which, similar to the first P + type region 61 (see FIG. 5), FLR121 to 138 are formed only on the n - type epitaxial layer 72a, and it is not necessary to form them on the n - type epitaxial layer 72b deposited on the n - type epitaxial layer 72a. Thereby, FLR121 to 138 can be formed at a deep position that does not reach the surface of the n - type epitaxial layer 72 (72a, 72b) that becomes the second surface 10b of the front surface of the semiconductor substrate 10.

[0141] As described above, according to the second embodiment, the same effects as those of the first embodiment To obtain can be obtained. Also, according to the second embodiment, between the FLR and the n -Since the pn junction with the drift region is arranged at a deep position away from the second surface on the front side of the semiconductor substrate, it is less likely to be affected by external charges accumulated in the insulating layer on the front side of the semiconductor substrate in the edge termination region, the breakdown voltage characteristics of the FLR structure can be stabilized, and the reliability of the semiconductor device can be improved.

[0142] (Embodiment 3) Next, the structure of the semiconductor device according to Embodiment 3 will be described. FIG. 10 is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 3. The layout of the semiconductor device 100b according to Embodiment 3 as viewed from the front side of the semiconductor substrate 10 is the same as that of FIG. 1. The difference between the semiconductor device 100b according to Embodiment 3 shown in FIG. 10 and the semiconductor device 30 (see FIG. 2) according to Embodiment 1 is that the FLR (p - -type regions) 141 to 158 that make up the FLR structure 140 have a relatively wide barrel-shaped cross-sectional shape with a width w40 at a substantially central position in the depth direction Z.

[0143] In Embodiment 3, the FLRs 141 to 158 are formed in a barrel-shaped cross-sectional shape, for example, by causing impurity diffusion by activation annealing at a substantially central position in the depth direction Z. For this reason, the FLRs 141 to 158 have the highest impurity concentration at the widest portion with the width w40, and the impurity diffusion occurs by activation annealing, for example, 1×10 18 / cm 3 or so. The impurity concentration of the portions of the FLRs 141 to 158 other than the widest portion with the width w40 is, for example, 1×10 17 / cm 3 or so where impurity diffusion does not occur by activation annealing.

[0144] The conditions for the average impurity concentration of the FLRs 141 to 158 are the same as the conditions for the impurity concentration of the FLRs 101 to 118 in Embodiment 1. The widest portion (the portion with the highest impurity concentration) of the FLRs 141 to 158 is preferably set so that the length w20 of the edge termination region 2 becomes as short as possible. The widest portion of the innermost FLR 141 and the outer peripheral p +The condition of the first interval w41 with the p-type region 62a is the same as that of the innermost FLR101 and the outer periphery p in Embodiment 1. + It is the same as the first interval w1 with the p-type region 62a.

[0145] The conditions of the second to eighteenth intervals w42 to w58 between the widest portions of the widths w40 of the adjacent FLR141 to 158 are the same as those of the second to eighteenth intervals w2 to w18 between the adjacent FLR101 to 118 in Embodiment 1. The depth positions of both end portions (upper end portion and lower end portion) of the FLR141 to 158 in the depth direction Z are the same as those of the FLR101 to 118 in Embodiment 1. The condition of the thickness (length in the depth direction Z) t12 of the FLR141 to 158 is the same as that of the thickness t10 of the FLR101 to 118 in Embodiment 1.

[0146] The manufacturing method of the semiconductor device 100b according to Embodiment 3 is the manufacturing method of the semiconductor device 30 according to Embodiment 1, in which, using the same ion implantation mask, the FLR141 to 158 may be formed by performing multi-stage ion implantation of a predetermined dose amount in a plurality of times (multi-stages) under different conditions into the n-type epitaxial layers 72 (72a, 72b). For example, when performing multi-stage ion implantation in nine stages, multi-stage ion implantation is performed at a low dose amount such that impurity diffusion does not occur during activation annealing, two stages each near the upper end portion and the lower end portion of the FLR141 to 158. - Near the substantially central position in the depth direction Z of the FLR141 to 158, multi-stage ion implantation in five stages is performed at a high dose amount such that impurity diffusion occurs during activation annealing. If the impurity concentration near the substantially central position in the depth direction Z of the FLR141 to 158 due to this five-stage multi-stage ion implantation is, for example, 1×10

[0147] / cm 18 / cm, 3 the vicinity of the substantially central position in the depth direction Z of the FLR141 to 158 can be made relatively wider by about 0.3 μm each (a total of about 0.6 μm) in the inner and outer directions in the normal direction due to impurity diffusion during activation annealing.

[0148] FLR141 to 158 into the first and second p + type regions 61, 62 (outer periphery p+ It may be formed simultaneously (including the p-type region 62a). In this case, the first and second p + type regions 61 and 62 (outer periphery p + type region 62a) has a relatively wide cross-sectional shape at substantially the same depth as the center position of FLR141 to 158 in the depth direction Z. FLR141 to 158 and the first and second p + type regions 61 and 62 (outer periphery p + type region 62a) may be formed in a separate process, and the impurity concentration distribution in the depth direction Z between FLR141 to 158 and the first and second p + type regions 61 and 62 may be different.

[0149] As described above, according to the third embodiment, even when the cross-sectional shape of the FLR is variously changed, by setting the impurity concentration and depth of the FLR to the same predetermined conditions as in the first embodiment, the same effects as in the first embodiment can be obtained.

[0150] (Embodiment 4) Next, the structure of the semiconductor device according to the fourth embodiment will be described. FIG. 11 is a cross-sectional view showing the structure of the semiconductor device according to the fourth embodiment. The layout of the semiconductor device 100c according to the fourth embodiment as viewed from the front surface side of the semiconductor substrate 10 is the same as that in FIG. 1. The semiconductor device 100c according to the fourth embodiment shown in FIG. 11 includes an FLR structure 160 in which the configuration of the FLR structure 120 (see FIG. 9) of the semiconductor device 100a according to the second embodiment is applied to the FLR structure 140 (see FIG. 10) of the semiconductor device 100b according to the third embodiment.

[0151] That is, in the fourth embodiment, the FLRs (p - type regions) 161 to 178 of the FLR structure 160 have a substantially barrel-shaped cross-sectional shape that is relatively wide in width w60 at a substantially central position in the depth direction Z, similar to the third embodiment. In addition, similar to the second embodiment, an n - type drift region 32 is provided between the second surface 10b of the front surface of the semiconductor substrate 10 and the FLRs 161 to 178. The FLRs 161 to 178 are not exposed on the second surface 10b of the front surface of the semiconductor substrate 10.

[0152] The conditions for the impurity concentrations of FLR161 to 178 are the same as those for the impurity concentrations of FLR141 to 158 in Embodiment 3. The widest part (the part with the highest impurity concentration) of FLR161 to 178 in terms of width w60 is preferably set so that the length w20 of the edge end region 2 is as short as possible, similar to Embodiment 3. The widest part of the innermost FLR161 in terms of width w60 and the outer periphery p + The condition for the first interval w41 between the type region 62a is the same as that for the first interval w1 between the innermost FLR101 and the outer periphery p + type region 62a in Embodiment 1.

[0153] The conditions for the second to 18th intervals w42 to w58 between the widest parts in terms of width w60 of adjacent FLR161 to 178 are the same as those for the second to 18th intervals w2 to w18 between adjacent FLR101 to 118 in Embodiment 1. The depth positions of both ends (the upper end and the lower end) of FLR161 to 178 in the depth direction Z are the same as those of FLR121 to 138 in Embodiment 2. The condition for the thickness (the length in the depth direction Z) t13 of FLR161 to 178 is the same as that for the thickness t10 of FLR101 to 118 in Embodiment 1.

[0154] The manufacturing method of the semiconductor device 100c according to Embodiment 4 is the manufacturing method of the semiconductor device 100b according to Embodiment 3, in which, similar to the first p + type region 61 (see FIG. 5), FLR161 to 178 are formed only on the n - type epitaxial layer 72a and do not need to be formed on the n - type epitaxial layer 72b deposited on the n - type epitaxial layer 72a. As a result, FLR161 to 178 having a barrel-shaped cross-sectional shape can be formed at a deep position that does not reach the surface of the n - type epitaxial layer 72 (72a, 72b) on the front surface of the semiconductor substrate 10.

[0155] As described above, according to Embodiment 4, the same effects as those of Embodiments 1 to 3 can be obtained.

[0156] (Example) Verification was performed on the first interval w1 between the innermost (the first one from the inside) FLR101 and the outer peripheral p + type region 62a. FIG. 12 is a characteristic diagram showing the result of simulating the relationship between the first interval between the main junction of the example and the innermost FLR and the breakdown voltage. The main junction is the outer peripheral p + type region 62a and n - type drift region 32. The horizontal axis in FIG. 12 is the first interval w1 between the innermost FLR101 and the outer peripheral p + type region 62a, and the vertical axis is the breakdown voltage.

[0157] In FIG. 12, when the first interval w1 = 0.0 μm, the innermost FLR101 is arranged at a position just in contact with the outer peripheral p + type region 62a. When the first interval w1 < 0.0 μm, the innermost FLR101 is arranged at a position overlapping and in contact with the outer peripheral p + type region 62a. When the first interval w1 > 0.0 μm, the innermost FLR101 is arranged away from the outer peripheral p + type region 62a.

[0158] Regarding the semiconductor device 30 according to the above-described Embodiment 1 (hereinafter referred to as an example; see FIG. 2), the first interval w1 between the innermost FLR101 and the outer peripheral p + type region 62a was variously changed and the result of simulating the breakdown voltage is shown in FIG. 12. FIG. 12 also shows the result of simulating the breakdown voltage by variously changing the interval w211 between the innermost FLR291 and the outer peripheral p + type region 262a for the conventional semiconductor device 260 (hereinafter referred to as a conventional example; see FIG. 19).

[0159] In the example, the impurity concentrations and the thickness t10 of the FLR101 to 118 of the FLR structure 20 are each 5×10 17 / cm 3And it was set to 1 μm. Under the condition of achieving a breakdown voltage of 1200 V class, the width w21 of FLR101 to 118 of the FLR structure 20 and the second to 18th intervals w2 to w18 between adjacent FLR101 to 118 were set. The length w20 of the edge termination region 2 in the example was 100 μm.

[0160] The innermost FLR101 and the outer periphery p + The first interval w1 between the type region 62a was set to 1.0 μm, and the increase width of the second to 18th intervals w2 to w18 between adjacent FLR101 to 118 was set to 0.1 μm. That is, the second to 18th intervals w2 to w18 between adjacent FLR101 to 118 were set as w2 = 1.1 μm, w3 = 1.2 μm,..., wi = 1.0 μm + 0.1 μm × (i - 1) (where i = 4 to 18).

[0161] In the conventional example, the impurity concentration and thickness t201 of FLR291 of the FLR structure 290 were 1×10 18 / cm 3 And 0.5 μm, respectively. Under the condition of achieving a breakdown voltage of 1200 V class, the width w210 of FLR291 of the FLR structure 290 and the interval w212 between adjacent FLR291 were set. The plurality of FLR291 constituting the FLR structure 290 were arranged at equal intervals. The length w202 of the edge termination region 202 in the conventional example was 200 μm.

[0162] From the results shown in FIG. 12, in the example, compared with the conventional example, the margin for realizing a predetermined breakdown voltage (1200 V) of the first interval w1 between the innermost FLR101 and the outer periphery p + type region 62a is large, and it was confirmed that the breakdown voltage can be improved. Also, it was confirmed that in the example, the length w20 of the edge termination region 2 can be made 1 / 2 compared to the length w202 of the edge termination region 2 in the conventional example. The reason is as follows.

[0163] In the conventional example, due to the high impurity concentration of FLR291, the innermost FLR291 and the outer periphery p +The margin of the distance w211 from the type region 262a becomes small. Also, because the impurity concentration of FLR291 is high and the depth (thickness t201) of FLR291 is shallow, the electric field applied to FLR291 becomes high. Therefore, it is necessary to secure a certain distance w212 between adjacent FLR291s, and the length w202 of the edge termination region 202 becomes long.

[0164] On the other hand, in the embodiment, the impurity concentration of FLR101 to 118 is about one digit lower than the impurity concentration of FLR291 in the conventional example, and the depth (thickness t10) of FLR101 to 118 is about twice as deep as the depth of FLR291 in the conventional example. As a result, compared with the conventional example, the margin of the first distance w1 between the innermost FLR101 and the outer periphery p + type region 62a can be made sufficiently large.

[0165] Also, in the embodiment, because the impurity concentration of FLR101 to 118 is low and the depth of FLR101 to 118 is deep, the electric field applied to FLR101 to 118 becomes low. Therefore, compared with the conventional example, the second to 18th distances w2 to w18 between adjacent FLR101 to 118 can be narrowed. As a result, the length w20 of the edge termination region 2 can be shortened to about the same extent as when the spatially modulated FLR structure 220 (see FIG. 18) is arranged.

[0166] Also, from the results shown in FIG. 12, in the embodiment, the innermost FLR101 and the outer periphery p + When the first distance w1 from the type region 62a exceeds 1.2 μm, a predetermined breakdown voltage can be ensured, but it was confirmed that the breakdown voltage decreases as the first distance w1 becomes wider. On the other hand, even if the innermost FLR101 is in contact with the outer periphery p + type region 62a (w1 ≤ 0.0 μm), it was confirmed that the breakdown voltage does not decrease and a sufficient breakdown voltage can be ensured.

[0167] (Experimental Example) Verification was performed on the other four conditions of the FLR structure 20. First, as the first verification, the impurity concentrations of FLR101 to 118 were verified. FIG. 13 is a characteristic diagram showing the result of simulating the relationship between the impurity concentration and the breakdown voltage of the FLR in the experimental example. The vertical axis and the horizontal axis in FIG. 13 are the same as those in FIG. 12. For the semiconductor device 30 (see FIG. 2) according to the above-described Embodiment 1, the breakdown voltage was simulated by changing the impurity concentrations of FLR101 to 118 (hereinafter referred to as Experimental Examples 1 to 3).

[0168] For Experimental Examples 1 to 3, the first interval w1 between the innermost FLR101 and the outer peripheral p + type region 62a was variously changed and the result of simulating the breakdown voltage is shown in FIG. 13. In Experimental Examples 1 to 3, the impurity concentrations of FLR101 to 118 were 3×10 17 / cm 3 , 5×10 17 / cm 3 and 9×10 17 / cm 3 respectively. The configurations other than the impurity concentrations of FLR101 to 118 in Experimental Examples 1 to 3 are the same as those in the embodiment of FIG. 12. Experimental Example 2 corresponds to the embodiment of FIG. 12.

[0169] From the results shown in FIG. 13, it was confirmed that in all of Experimental Examples 1 to 3, if the first interval w1 between the innermost FLR101 and the outer peripheral p + type region 62a is 1.2 μm or less, a predetermined breakdown voltage (1200 V) can be sufficiently obtained. Therefore, by setting the impurity concentrations of FLR101 to 118 within the range of 3×10 17 / cm 3 or more and 9×10 17 / cm 3 or less, and setting the first interval w1 between the innermost FLR101 and the outer peripheral p + type region 62a within the range of 1.2 μm or less, a predetermined breakdown voltage can be sufficiently obtained.

[0170] As a second verification, the increase widths of the second interval w2 between adjacent FLRs 101 and 102 and the third interval w3 between adjacent FLRs 102 and 103 were verified. FIG. 14 is a characteristic diagram showing the result of simulating the relationship between the increase width of the second interval between the first and second FLRs from the inside of the experimental example and the withstand voltage. FIG. 15 is a characteristic diagram showing the result of simulating the relationship between the increase width of the third interval between the second and third FLRs from the inside of the experimental example and Breakdown voltage and is a characteristic diagram showing the result of simulation.

[0171] The horizontal axis of FIG. 14 is the increase width of the second interval w2 between adjacent FLRs 101 and 102 (between the innermost FLR 101 and the second FLR 102 from the inside), and the vertical axis is the withstand voltage. The horizontal axis of FIG. 15 is the increase width of the third interval w3 between adjacent FLRs 102 and 103 (between the second FLR 102 from the inside and the third FLR 103 from the inside), and the vertical axis is the withstand voltage.

[0172] Regarding the semiconductor device 30 according to the above-described Embodiment 1 (hereinafter referred to as Experimental Example 4: see FIG. 2), the increase width of the second interval w2 between adjacent FLRs 101 and 102 was variously changed, and the result of simulating the withstand voltage is shown in FIG. 14. Regarding the semiconductor device 30 according to the above-described Embodiment 1 (hereinafter referred to as Experimental Example 5: see FIG. 2), the increase width of the third interval w3 between adjacent FLRs 102 and 103 was By variously changing, the breakdown voltage simulated, and the result is shown in FIG. 15.

[0173] The increase width of the second interval w2 between adjacent FLRs 101 and 102 is the increase width from the first interval w1 between the innermost FLR 101 and the outer peripheral p + type region 62a (= w2 - w1). The increase width of the third interval w3 between adjacent FLRs 102 and 103 is the increase width from the second interval w2 (= w3 - w2). The configuration other than the second interval w2 in Experimental Example 4 is the same as that in the embodiment of FIG. 12. The configuration other than the third interval w3 in Experimental Example 5 is the same as that in the embodiment of FIG. 12.

[0174] From the results shown in FIGS. 14 and 15, it was confirmed that if the increase widths of the second to eighteenth intervals w2 to w18 between adjacent FLRs 101 to 118 are 0.7 μm or less, even if the intervals between adjacent FLRs become wider at a predetermined increase width as the number of FLRs increases, it does not adversely affect the breakdown voltage. Note that the relationship (not shown) between the increase widths of the fourth to eighteenth intervals w4 to w18 between adjacent FLRs 103 to 118 and the breakdown voltage also has the same tendency as FIGS. 14 and 15.

[0175] As a third verification, the thickness (depth) t10 of FLRs 101 to 118 was verified. FIG. 16 is a characteristic diagram showing the result of simulating the relationship between the thickness of the FLR in the experimental example and the breakdown voltage. The vertical axis and the horizontal axis in FIG. 16 are the same as those in FIG. 12. For the semiconductor device 30 (see FIG. 2) according to the above-described Embodiment 1, the breakdown voltage was simulated while changing the thickness t10 of FLRs 101 to 118 (hereinafter referred to as Experimental Examples 6 to 8).

[0176] Regarding these Experimental Examples 6 to 8, the first interval w1 between the innermost FLR 101 and the outer peripheral p + type region 62a was variously changed and the result of simulating the breakdown voltage is shown in FIG. 16. In Experimental Examples 6 to 8, the thicknesses t10 of FLRs 101 to 118 were 0.5 μm, 0.7 μm, and 0.9 μm, respectively. The configurations of Experimental Examples 6 to 8 other than the thickness t10 of FLRs 101 to 118 are the same as those of the embodiment in FIG. 12.

[0177] From the results shown in FIG. 16, when the impurity concentration of FLRs 101 to 118 is 5×10 17 / cm 3 and the thickness t10 of FLRs 101 to 118 is in the range of about 0.5 μm or more and 0.9 μm or less, it was confirmed that a predetermined breakdown voltage (1200 V) can be sufficiently obtained. Although not shown, even when the impurity concentration of FLRs 101 to 118 is in the range of 3×10 17 / cm 3 or more and 9×10 17 / cm 3 or less, the relationship between the thickness t10 of FLRs 101 to 118 and the breakdown voltage has the same tendency as FIG. 16.

[0178] As a fourth verification, the number of FLRs in the FLR structure 20 was verified. FIG. 17 is a characteristic diagram showing the result of simulating the relationship between the number of FLRs in the FLR structure of the experimental example and the breakdown voltage. The horizontal axis in FIG. 17 is the number of FLRs in the FLR structure 20, and Vertical axis is the breakdown voltage. FIG. 17 also includes the result of simulating the external charge dependence of the FLRs in the FLR structure 20. The external charge is a positive charge that positively charges the insulating layer on the FLR or a negative charge that negatively charges it.

[0179] Regarding the semiconductor device 30 (see FIG. 2) according to the above-described Embodiment 1, the insulating layer (the insulating layer in which the field oxide film 81 on the FLR, the interlayer insulating film 40, and the first protective film 50 are laminated in this order) on the second surface 10b of the front surface of the semiconductor substrate 10 in the edge termination region 2 was simulated for the breakdown voltage when not charged (charge zero), when positively charged (positive charge), and when negatively charged (negative charge) (hereinafter referred to as Experimental Examples 9 to 11).

[0180] FIG. 17 shows the results of simulating the breakdown voltage by variously changing the number of FLRs in the FLR structure 20 for these Experimental Examples 9 to 11. The configuration other than the number of FLRs in the FLR structure 20 in Experimental Examples 9 to 11 is the same as that in the embodiment of FIG. 12. Experimental Example 9 corresponds to the embodiment of FIG. 12. Experimental Example 9 is the simulation result when used in a low-humidity environment (such as indoors with general air-conditioning control and ventilation, etc.) and corresponds to the result obtained by a general voltage application test according to actual use.

[0181] Experimental Example 10 (the insulating layer is positively charged) is a simulation result when used in a high humidity environment (for example, in a special environment such as a factory), and corresponds to the result obtained by a THB (Temperature Humidity Bias) test. In a high humidity environment, the insulating layer on the second surface 10b of the front surface of the semiconductor substrate 10 in the edge termination region 2 is positively charged, making it difficult for the depletion layer to extend outward from the active region 1, and the breakdown voltage and leakage current fluctuate. Therefore, Experimental Example 10 verifies the fluctuations in breakdown voltage and leakage current in a high humidity environment.

[0182] Experimental Example 11 (the insulating layer is negatively charged) is a simulation result when a high voltage is applied between the drain and source, and corresponds to the result obtained by a high voltage application test. When the surface region of the front surface of the semiconductor substrate 10 in the edge termination region 2 is depleted due to the depletion layer extending outward from the active region 1 when the MOSFET is off, this depleted portion becomes in the same state as being positively charged. As a result, negative charges are accumulated in the insulating layer on the second surface 10b of the front surface of the semiconductor substrate 10 in the edge termination region 2.

[0183] The negative charges accumulated in the insulating layer are discharged and have no adverse effect if the voltage application between the drain and source is for a short time. However, if a high voltage equal to or higher than the breakdown voltage (for example, about 1400V or 1500V in the case of a 1200V class breakdown voltage) between the drain and source is continuously applied for a long time (for example, about 3000 hours), they are not discharged and function to further extend the depletion layer outward, fluctuating the breakdown voltage and leakage current. Therefore, Experimental Example 11 verifies the fluctuations in breakdown voltage and leakage current when a high voltage is applied between the drain and source for a long time.

[0184] From the results shown in FIG. 17, it was confirmed that if the number of FLRs of the FLR structure 20 is 16 or more regardless of the presence or absence of external charges, a predetermined withstand voltage (1200V) can be sufficiently obtained. The reason is that, compared with the conventional example (see FIG. 19), the thickness t10 of the FLR is thick, and the FLR reaches a deep position from the second surface 10b of the front surface of the semiconductor substrate 10 in the edge termination region 2, so that it is not easily affected by the external charges accumulated in the insulating layer on the second surface 10b of the front surface of the semiconductor substrate 10 in the edge termination region 2.

[0185] Although not shown, also in the conventional example, the adverse effects due to the external charges accumulated in the insulating layer on the second surface 210b of the front surface of the semiconductor substrate 210 in the edge termination region 202 appear in a similar tendency to FIG. 17. However, in the conventional example, the margin of the FLR291 of the FLR structure 290 that satisfies the predetermined withstand voltage is small as compared with Experimental Examples 9 to 11, similar to the margin of the interval w211 between the innermost FLR291 and the outer peripheral p + type region 262a (see FIG. 12), as confirmed by the inventor.

[0186] As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. For example, in Embodiments 1 and 2, in order to relax the electric field applied to the gate insulating film on the bottom surface of the gate trench, the p + type region provided near the bottom surface of the gate trench may have a substantially wide barrel-shaped cross-sectional shape at a substantially central position in the depth direction. Even when a wide-bandgap semiconductor other than silicon carbide is used instead of using silicon carbide as the semiconductor material, the present invention is applicable. Further, the present invention similarly holds even when the conductivity type (n-type, p-type) is reversed.

Industrial Applicability

[0187] As described above, the semiconductor device according to the present invention is useful for a power semiconductor device that controls high voltage and large current.

Explanation of Reference Numerals

[0188] 1 Active region 2 Edge termination region 3 Intermediate region 10 Semiconductor substrate 10a~10c First to third surfaces of the front side of the semiconductor substrate 20, 120, 140, 160 FLR structure 21 n + -type channel stopper region 30, 100a~100c Semiconductor devices 31 n + -type drain region 32 n - -type drift region 33 n-type current diffusion region 34 p-type base region 34a Peripheral p-type base region 35 n + -type source region 36 p ++ -type contact region 36a Peripheral p ++ -type contact region 37 Gate trench 38 Gate insulating film 39 Gate electrode 40 Interlayer insulating film 40a, 40b Contact holes in the interlayer insulating film 41 NiSi film 42 First TiN film 43 First Ti film 44 Second TiN film 45 Second Ti film 46 Barrier metal 47 Al electrode film 48 Plating film 49 Terminal pin 50 First protective film 51 Second protective film 52 Drain electrode 53 Step 61, 62, 91, 93 p + -type region 62a Peripheral p + -type region 71 n + -type starting substrate 72, 72a, 72b n- Type epitaxial layer 73 p-type epitaxial layer 81 Field oxide film 82 Gate polysilicon wiring layer 83 Gate metal wiring layer 92,94 n-type regions 101~118,121~138,141~158,161~178 FLR The first direction parallel to the front surface of the X semiconductor substrate The second direction parallel to the front surface of the Y semiconductor substrate and perpendicular to the first direction Z Depth direction d1 p + Depth of the p-type region d2 Distance between adjacent p + type regions d3 Depth of the n-type region t1,t2 n - Thickness of the n-type epitaxial layer t3 Thickness of the p-type epitaxial layer t10~t13 Thickness of the FLR t20 Total thickness of the insulating layer on the front surface of the semiconductor substrate (on the FLR) in the edge termination region w1,w41 The first interval between the innermost FLR and the outer peripheral p + type region wm The mth interval between the (m - 1)th FLR from the inside and the mth FLR from the inside (where m = 2~18) wn The (n - 40)th interval between the (n - 41)th FLR from the inside and the (n - 40)th FLR from the inside (where n = 42~58) w20 Length of the edge termination region w21,w30,w40,w60 Width of the FLR

Claims

1. A semiconductor device having an active region through which a main current flows and a termination region surrounding the periphery of the active region, a semiconductor substrate made of a semiconductor having a wider bandgap than silicon, a first semiconductor region of a first conductivity type provided inside the semiconductor substrate, a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region in the active region, a predetermined element structure formed by a pn junction between the second semiconductor region and the first semiconductor region in the active region, a first electrode electrically connected to the second semiconductor region, a second electrode provided on the second main surface of the semiconductor substrate, a plurality of second conductivity type breakdown voltage regions selectively provided inside the first semiconductor region and spaced apart from each other in the surface region on the first main surface side of the semiconductor substrate in the termination region, and concentrically surrounding the periphery of the active region, comprising: The average impurity concentration in the second conductivity type breakdown voltage region is 1×10 18 / cm 3 and is within the range less than the thickness of the second conductivity type breakdown voltage region is 0.7 μm or more and 1.1 μm or less, the second conductivity type breakdown voltage region has a barrel-shaped cross-sectional shape that is relatively wide at the center position in the depth direction, the second conductivity type breakdown voltage region is characterized in that the impurity concentration is the highest in the widest first portion, and the impurity concentration is relatively low in the second portion excluding the first portion. A semiconductor device.

2. Further comprising a second conductivity type high-concentration region that is selectively provided in contact with the second semiconductor region between the second semiconductor region and the first semiconductor region and surrounds the periphery of the active region, and has a higher impurity concentration than the second semiconductor region, the semiconductor device according to claim 1, wherein the second conductivity type breakdown voltage region reaches a deeper position on the second main surface side of the semiconductor substrate than the second conductivity type high-concentration region.

3. The semiconductor device according to claim 1 or 2, wherein the impurity concentration of the second conductivity type breakdown voltage region is in the range of 3×10 17 / cm 3 or more and 9×10 17 / cm 3 or less.

4. Further comprising a second conductivity type high-concentration region that is selectively provided in contact with the second semiconductor region between the second semiconductor region and the first semiconductor region and surrounds the periphery of the active region, and has a higher impurity concentration than the second semiconductor region, the semiconductor device according to claim 1, wherein the second conductivity type high-concentration region is provided between the active region and the second conductivity type breakdown voltage region and faces the second conductivity type breakdown voltage region in a direction parallel to the first main surface of the semiconductor substrate.

5. The semiconductor device according to claim 2 or 4, wherein a first interval between the innermost second conductivity type breakdown voltage region and the second conductivity type high concentration region is within a range of 1.2 μm or less.

6. The semiconductor device according to claim 2 or 4, wherein the innermost second conductivity type breakdown voltage region is in contact with the second conductivity type high concentration region.

7. The semiconductor device according to claim 6, wherein a second interval between the innermost second conductivity type breakdown voltage region and the second second conductivity type breakdown voltage region from the inside is within a range of 2.1 μm or less.

8. The semiconductor device according to claim 6 or 7, wherein a third interval between the second second conductivity type breakdown voltage region from the inside and the third second conductivity type breakdown voltage region from the inside is within a range of 3.1 μm or less.

9. The semiconductor device according to claim 8, wherein the third interval is within a range of 1.0 μm or less.

10. The semiconductor device according to claim 9, wherein a fourth interval between the third second conductivity type breakdown voltage region from the inside and the fourth second conductivity type breakdown voltage region from the inside is within a range of 2.0 μm or less.

11. The semiconductor device according to claim 5, wherein an interval between the second conductivity type breakdown voltage regions adjacent to each other after the fourth from the inside is wider than the first interval.

12. The semiconductor device according to any one of claims 1 to 11, wherein the plurality of second conductivity type breakdown voltage regions are all of the same width.

13. The semiconductor device according to any one of claims 1 to 11, wherein a width of the second second conductivity type breakdown voltage region and subsequent regions from the inside is wider than a width of the innermost second conductivity type breakdown voltage region.

14. The semiconductor device according to any one of claims 1 to 13, wherein the second conductivity type breakdown voltage region reaches a first main surface of the semiconductor substrate.

15. The second conductivity type breakdown voltage region is provided at a depth position away from a first main surface of the semiconductor substrate, The semiconductor device according to any one of claims 1 to 13, wherein the first semiconductor region is interposed between the first main surface of the semiconductor substrate and the second conductivity type breakdown voltage region.

16.

17. The semiconductor device according to any one of claims 1 to 15, wherein a conductive film is not provided on the first main surface of the semiconductor substrate in the terminal region.

17. The semiconductor device according to any one of claims 1 to 16, characterized in that, in the terminal region, a first main surface of the semiconductor substrate is covered with an insulating layer.

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