Silicon carbide semiconductor device and method of manufacturing the same

Abstract

To provide a silicon carbide semiconductor device capable of improving the amount of resistance to surge current, and a method of manufacturing the silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device 40 is a SiC-SBD that includes an SBD structure composed of a Schottky barrier of a titanium film 31 as a lowermost layer of a top surface electrode 14 and an n- type drift region 12 and a JBS structure composed of a pn junction of a p type region 13 and the n- type drift region 12 mixedly on the top surface side of a semiconductor substrate 30 made of silicon carbide in an active region 10. The p type region 13 forms an ohmic junction with the titanium film 31 as the lowermost layer of the top surface electrode 14. After ion injection for forming the p type region 13, activation annealing is carried out at a temperature of 1700°C to 1900°C for a processing time exceeding 20 minutes, so that the contact resistance between the titanium film 31 and p type region 13 is controlled to within a range of 5×10-4 Ω cm2 to 8×10-3 Ω cm2.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] This invention relates to a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device.

Background Art

[0002] In a Schottky Barrier Diode (SiC-SBD) using silicon carbide (SiC) as a semiconductor material, on the front surface side of a semiconductor substrate (semiconductor chip), a Schottky junction between a front surface electrode (anode electrode) and an n - -type drift region and a pn junction between a p-type region and an n - -type drift region are mixed in a known JBS (Junction Barrier Schottky) structure. The p-type region constituting the JBS structure is selectively formed in the surface region of the front surface of the semiconductor substrate by ion implantation of p-type impurities and subsequent heat treatment (activation annealing) for impurity activation. The conditions for this activation annealing are a temperature of about 1640°C and a treatment time of about 3 minutes.

[0003] When the forward current flowing through this SiC-SBD is below the rated value, the forward current only flows through the path from the front surface electrode through the Schottky junction to the back surface electrode (cathode electrode), and no current flows through the p-type region constituting the JBS structure. On the other hand, when a large current (surge current) exceeding the rated value flows in the forward direction of the SiC-SBD, such as during a surge application due to lightning strike, the entire surge current cannot be borne only by the above-mentioned path through the Schottky junction, and the surge current also flows into the p-type region constituting the JBS structure from the front surface electrode. At this time, the pn diode formed by the pn junction between the p-type region and the n - -type drift region operates in a bipolar manner, and a forward current also starts to flow through the pn diode.

[0004] As a conventional SiC-SBD, a p +An apparatus has been proposed that forms a low-resistance ohmic contact with a front surface electrode by means of a type-contact region (see, for example, Patent Document 1 below). In Patent Document 1 below, a p-type contact region with an impurity concentration of 1×10 19 / cm 3 or higher is formed in the surface region of the p-type region constituting the JBS structure by ion implantation of p-type impurities, and subsequent activation annealing is performed at a temperature of 1700 °C for 10 minutes. As a result, the contact resistance between the p + -type contact region and the front surface electrode made of titanium (Ti) or nickel (Ni) is reduced to about 1×10 + . -2 Ωcm 2

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in a conventional SiC-SBD, when a large current (surge current) due to surge application flows through the p-type region constituting the JBS structure, the contact resistance between the p-type region and the front surface electrode is high, making it difficult for bipolar operation to occur at the pn junction between the p-type region and the n - -type drift region. As a result, the surge current becomes locally concentrated, causing the SiC-SBD (semiconductor base plate) to generate heat and lead to destruction.

[0007] An object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can improve the surge current withstand capacity in order to solve the problems caused by the above-described conventional technologies.

Means for Solving the Problems

[0008] In order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. A first step of forming a first conductivity type region forming the first main surface of the semiconductor substrate is performed inside a semiconductor substrate made of silicon carbide. A second step of selectively forming one or more second conductivity type regions in a surface region of the first main surface of the semiconductor substrate by ion implantation of second conductivity type impurities to form a pn junction between the second conductivity type region and the first conductivity type region is performed. A third step of activating the second conductivity type impurities by heat treatment is performed. After the third step, a titanium film is formed as a first electrode on the first main surface of the semiconductor substrate, a Schottky junction between the titanium film and the first conductivity type region is formed, and a fourth step of forming an ohmic junction between the titanium film and the second conductivity type region is performed. A fifth step of forming a second electrode on the second main surface of the semiconductor substrate is performed. In the third step, the heat treatment is performed at a temperature of 1700 ° C or higher and 1900 ° C or lower for a treatment time exceeding 20 minutes. Between the first main surface of the semiconductor substrate and the first electrode, a contact metal formed by a silicide reaction with the second conductivity type region is not formed.

[0009] Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the contact resistance between the titanium film and the second conductivity type region is 5 × 10 -4 Ω·cm 2 or more and 8 × 10 -3 Ω·cm 2 or less.

[0010] Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the contact resistance between the titanium film and the second conductivity type region is 3 × 10 -3 Ω·cm 2 or more and 7 × 10 -3 Ω·cm 2 or less.

[0011] Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the third step, the activation rate of the second conductivity type impurities is 70% or more and 90% or less.

[0012] Also, in the method for manufacturing a silicon carbide semiconductor device according to this invention, in the above-described invention, in the second step, the doping concentration of the second conductivity type region is 3×10 19 / cm 3 or more and 5×10 20 / cm 3 or less.

[0013] Also, in the method for manufacturing a silicon carbide semiconductor device according to this invention, in the above-described invention, in the second step, a plurality of the second conductivity type regions are formed in a matrix shape when viewed from the first main surface side of the semiconductor substrate, or in a stripe shape extending parallel to the first main surface of the semiconductor substrate.

[0014] Also, in the method for manufacturing a silicon carbide semiconductor device according to this invention, in the above-described invention, in the second step, all of the second conductivity type regions are connected to each other at a predetermined location.

[0015] Also, in the method for manufacturing a silicon carbide semiconductor device according to this invention, in the above-described invention, in the second step, a plurality of the second conductivity type regions are formed in a stripe shape extending parallel to the first main surface of the semiconductor substrate and connected to each other at the longitudinal ends.

[0016] Also, in order to solve the above-described problems and achieve the object of the present invention, a silicon carbide semiconductor device according to this invention has the following features. A first conductivity type region is provided inside a semiconductor substrate made of silicon carbide. The first conductivity type region forms the first main surface of the semiconductor substrate. A second conductivity type region is selectively provided in contact with the first conductivity type region between the first main surface of the semiconductor substrate and the first conductivity type region. The second conductivity type region forms the first main surface of the semiconductor substrate. A first electrode is provided on the first main surface of the semiconductor substrate, contacts the first conductivity type region and forms a Schottky junction with the first conductivity type region, and contacts the second conductivity type region and forms an ohmic junction with the second conductivity type region, and includes a titanium film. A second electrode is provided on the second main surface of the semiconductor substrate. The contact resistance between the titanium film and the second conductivity type region is 5×10-4 Ω·cm 2 8×10 or more -3 Ω·cm 2 It is within the following range.

[0017] Further, in the silicon carbide semiconductor device according to this invention, in the above-described invention, the contact resistance between the titanium film and the second conductivity type region is 3×10 -3 Ω·cm 2 7×10 or more -3 Ω·cm 2 It is characterized by being within the following range.

[0018] Further, the silicon carbide semiconductor device according to this invention is characterized in that, in the above-described invention, no contact metal due to a silicide reaction with the second conductivity type region is provided between the first main surface of the semiconductor substrate and the first electrode.

[0019] According to the above-described invention, without providing a contact metal such as a nickel silicide film formed by a silicide reaction with the second conductivity type region between the lowermost titanium film of the first electrode and the second conductivity type region, the contact resistance between the titanium film and the second conductivity type region can be reduced. As a result, when a large forward current flows, bipolar operation occurs at the pn junction between the second conductivity type region and the first conductivity type region, and a forward current can flow.

Effect of the Invention

[0020] According to the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device of the present invention, there is an effect that the surge current withstand capacity can be improved.

Brief Description of the Drawings

[0021]

Figure 1

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Figure 11

Figure 12

Embodiments for Carrying Out the Invention

[0022] Hereinafter, with reference to the accompanying drawings, preferred embodiments of the silicon carbide semiconductor device and the manufacturing method of the silicon carbide semiconductor device according to the present invention will be described in detail. In this specification and the accompanying drawings, in the layers and regions with n or p prefixed, it means that electrons or holes are the majority carriers, respectively. Also, + and - attached to n and p mean higher impurity concentration and lower impurity concentration than the layers and regions to which they are not attached, respectively. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0023] (Embodiment) The structure of the silicon carbide semiconductor device fabricated (manufactured) by the method for manufacturing a silicon carbide semiconductor device according to the embodiment will be described with reference to FIGS. 1 to 3. FIGS. 1 to 3 are plan views showing layout examples of the silicon carbide semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate. FIGS. 1 and 3 show layout examples of the p-type region 13. FIG. 2 shows a layout example of the bonding pad 41 when the layout example of the p-type region 13 in FIG. 1 is adopted.

[0024] In the silicon carbide semiconductor device 40 according to the embodiment shown in FIGS. 1 and 2, on the front surface (first main surface) side of a semiconductor substrate (semiconductor chip) 30 made of silicon carbide (SiC) in the active region 10, a front surface electrode (first electrode) 14 (see FIG. 4) and an n - type drift region (first conductivity type region) 12 form a Schottky junction, and a p-type region (second conductivity type region) 13 and an n - type drift region 12 form a pn junction. It is a SiC-SBD with a JBS structure in which these are mixed.

[0025] n - type drift region 12 and p-type region 13 are arranged substantially evenly in a substantially uniform pattern within the plane of the active region 10. Arranged substantially evenly in a substantially uniform pattern means that they are aligned so as to be arranged in the same pattern and at the same interval within a range including the tolerance due to process variations. n - type drift region 12 reaches up to the front surface of the semiconductor substrate 30 between adjacent p-type regions 13.

[0026] Specifically, the n - type drift region 12 and the p-type region 13 may be arranged in stripes extending in the same direction parallel to the front surface of the semiconductor substrate 30, for example, and may be alternately and repeatedly arranged adjacent to each other in the short direction orthogonal to the longitudinal direction in which they extend in stripes (FIG. 1). The p-type region 13 may be arranged in a matrix shape, for example. In this case, the n - type drift region 12 surrounds a plurality of p-type regions 13 arranged in a matrix shape in a lattice pattern (FIG. 3).

[0027] The active region 10 is a region through which the forward current of the SiC-SBD flows. The active region 10 has, for example, a substantially rectangular planar shape and is disposed at substantially the center (chip center) of the semiconductor substrate 30. The edge termination region 20 is a region between the active region 10 and the edge (chip edge) of the semiconductor substrate 30, surrounds the periphery of the active region 10, and relaxes the electric field on the front surface side of the semiconductor substrate 30 to maintain the breakdown voltage. The breakdown voltage is the limit voltage at which the element does not malfunction or break down.

[0028] A breakdown voltage structure such as a Junction Termination Extension (JTE) structure is disposed in the edge termination region 20 (see FIG. 4). The JTE structure is a breakdown voltage structure in which a plurality of p-type regions (reference numerals 22 and 23 in FIG. 4) having different impurity concentrations are arranged concentrically around the active region 10 such that p-type regions with a lower impurity concentration are arranged as they move from the inside (chip center side) to the outside (chip edge side).

[0029] Also, a Field Limiting Ring (FLR) 21 is disposed between the active region 10 and the JTE structure in the edge termination region 20. The FLR 21 is a p + -type region that surrounds the periphery of the active region 10 in a substantially rectangular shape and is adjacent to the innermost p - -type region 22 of the JTE structure. The longitudinal end of the p-type region 13 may be in contact with the FLR 21 (FIG. 1).

[0030] When the longitudinal end of the p-type region 13 is not in contact with the FLR 21 (not shown) or when the p-type regions 13 are arranged in a matrix (FIG. 3), the adjacent p-type regions 13 may be connected or separated at a predetermined location within the active region 10. Even when the longitudinal end of the p-type region 13 is in contact with the FLR 21 (FIG. 1), the adjacent p-type regions 13 may be connected at a predetermined location within the active region 10.

[0031] On the front surface of the semiconductor substrate 30, bonding pads 41 are provided. An aluminum (Al) wire (not shown in the figure), which is the most common wiring connection when supplying current to the bonding pad 41 during mounting of the semiconductor substrate 30, is bonded (joined) to the bonding pad 41. In FIG. 2, the joint 42 between the bonding pad 41 and the aluminum wire (not shown) is shown in a circular planar shape.

[0032] The bonding pad 41 is preferably disposed at the center of the semiconductor substrate 30, but the arrangement and planar shape of the bonding pad 41 can be set as appropriate. As described above, since the n-type drift region 12 and the p-type region 13 are arranged substantially evenly in a substantially uniform pattern within the plane of the active region 10, even if the bonding pad 41 is not disposed at the center of the semiconductor substrate 30, it does not adversely affect the electrical characteristics. - Since the n-type drift region 12 and the p-type region 13 are arranged substantially evenly in a substantially uniform pattern within the plane of the active region 10, even if the bonding pad 41 is not disposed at the center of the semiconductor substrate 30, it does not adversely affect the electrical characteristics.

[0033] Next, the cross-sectional structure of the silicon carbide semiconductor device 40 according to the embodiment will be described. FIG. 4 is a cross-sectional view showing the cross-sectional structure taken along the cutting line A-A' in FIG. 2. As described above, in the silicon carbide semiconductor device 40 according to the embodiment, the active region 10 of the semiconductor substrate 30 made of silicon carbide is a SiC-SBD constituting a JBS structure, and the edge termination region 20 is provided with a JTE structure as a breakdown voltage structure.

[0034] The semiconductor substrate 30 is an epitaxial substrate in which an n-type epitaxial layer that becomes the n-type drift region 12 is laminated on the front surface of an n-type starting substrate 11 made of silicon carbide. + On the front surface of the n-type starting substrate 11, an n-type epitaxial layer that becomes the n-type drift region 12 is laminated. - The n-type starting substrate 11 is an n-type cathode region. The semiconductor substrate 30 has the front surface as the main surface on the n-type drift region 12 side (the surface of the n-type epitaxial layer that becomes the n-type drift region 12), and the back surface (the second main surface) as the main surface on the n-type starting substrate 11 side (the back surface of the n-type starting substrate 11). - type epitaxial layer. + The n-type starting substrate 11 is an n-type cathode region. + The semiconductor substrate 30 is an n-type cathode region. - On the main surface on the n-type drift region 12 side (the surface of the n-type epitaxial layer that becomes the n-type drift region 12), - the n-type drift region 12 - type epitaxial layer), + and the main surface on the n-type starting substrate 11 side (the back surface of the n-type starting substrate 11) + is the back surface (the second main surface).

[0035] In the active region 10, one or more p-type regions 13 constituting a JBS structure are selectively provided between the front surface of the semiconductor substrate 30 and the n - -type drift region 12. The p-type region 13 is exposed on the front surface of the semiconductor substrate 30 and is in contact with the n - -type drift region 12. The p-type region 13 is a diffusion region formed by a first ion implantation (step S2 in FIG. 5) described later. The doping concentration (impurity concentration) of the p-type region 13 is, for example, 3×10 19 / cm 3 or more and 5×10 20 / cm 3 or less.

[0036] The effective majority carrier (hole) concentration of the p-type region 13 is determined by the activation rate of the p-type impurity implanted by the first ion implantation to form the p-type region 13 (hereinafter referred to as the activation rate of the p-type region 13). Specifically, the effective majority carrier concentration of the p-type region 13 is calculated by multiplying the doping concentration of the p-type region 13 and the activation rate of the p-type region 13, and is, for example, about 70% or more and 90% or less with respect to the doping concentration of the p-type region 13. The activation rate of the p-type region 13 is adjusted by an activation anneal (see FIG. 5) in step S3 described later.

[0037] In the active region 10, on the front surface of the semiconductor substrate 30, in a portion other than the portion where the p-type region 13 is exposed, n + mold starting substrate 11 from n - -type drift region 12 extends and is exposed. The periphery of the p-type region 13 is surrounded by the n - -type drift region 12. In the active region 10, being exposed on the front surface of the semiconductor substrate 30 means being in contact with the front surface electrode 14 described later on the front surface of the semiconductor substrate 30.

[0038] In the edge termination region 20, on the surface region of the front surface of the semiconductor substrate 30, FLR21, one or more p-type regions (here, two: p - -type region 22 and p --p-type region 23) and n + type channel stopper regions 24 are selectively provided, respectively. FLR21, p - type region 22, p -- type region 23 and n + type channel stopper region 24 is provided between the front surface of the semiconductor substrate 30 and the n - type drift region 12.

[0039] FLR21, p - type region 22, p -- type region 23 and n + type channel stopper region 24 is exposed on the front surface of the semiconductor substrate 30 and is in contact with the n - type drift region 12. FLR21, p - type region 22, p -- type region 23 and n + type channel stopper region 24 may have substantially the same depth as the depth of the p-type region 13. The inside of FLR21 is the active region 10. p - type region 22 is provided outside FLR21 and adjacent to FLR21.

[0040] p -- type region 23 is p - type region 22 is provided outside the p - type region 22 and is adjacent to the p + type region 22. n -- type channel stopper region 24 is outside the p -- type region 23 and is provided away from the p + type region 23. n -- type channel stopper region 24 is exposed at the end of the semiconductor substrate 30 (chip end). p + type region 23 and n n + mold starting substrate 11 from n - type drift region 12 extends and On the front surface of the semiconductor substrate 30 is exposed.

[0041] The front surface of the semiconductor substrate 30 is covered with a field oxide film 15. The field oxide film 15 may be, for example, a stacked film in which a thermal oxide film 16 and a deposited oxide film 17 are stacked in this order. By including the deposited oxide film 17, the field oxide film 15 can be formed in a shorter time than when the entire field oxide film 15 is a thermal oxide film 16. The thermal oxide film 16 can improve the adhesion between the semiconductor substrate 30 and the field oxide film 15.

[0042] A contact hole 15a that exposes the entire front surface of the semiconductor substrate 30 in the active region 10 is provided in the field oxide film 15. In the contact hole 15a of the field oxide film 15, the entire area of the active region 10 (that is, the n - type drift region 12 and the p-type region 13) and the inner portion of the FLR21 in the edge termination region 20 are exposed.

[0043] A front surface electrode 14 is provided on the entire front surface of the semiconductor substrate 30 inside the contact hole 15a of the field oxide film 15. The front surface electrode 14 functions as an anode electrode. The front surface electrode 14 may extend on the field oxide film 15. The front surface electrode 14 has a two-layer structure formed by sequentially laminating a titanium (Ti) film 31 and an aluminum (Al) alloy film (a metal film containing aluminum) 32.

[0044] A contact metal (for example, a nickel silicide (NixSiy) film, where x and y are arbitrary integers) that forms a low-resistance ohmic junction with the semiconductor substrate 30 by a silicide reaction with the semiconductor substrate 30 is not provided between the front surface electrode 14 and the front surface of the semiconductor substrate 30. Therefore, the titanium film 31 contacts the entire front surface of the semiconductor substrate 30 inside the contact hole 15a of the field oxide film 15 and contacts all of the n - type drift region 12, the p-type region 13, and the FLR21.

[0045] The junction portion of the titanium film 31 with the n - type drift region 12 is the n -It is a Schottky electrode that forms a Schottky junction with the N-type drift region 12. The junction portions of the titanium film 31 with the p-type region 13 and the FLR21 are ohmic electrodes that form ohmic junctions with the p-type region 13 and the FLR21. The junction portions of the titanium film 31 with the p-type region 13 and the FLR21 are not silicided.

[0046] The higher the effective majority carrier concentration of the p-type region 13, the lower the ohmic contact resistance between the titanium film 31 and the p-type region 13. The effective majority carrier concentration of the p-type region 13 is adjusted by the activation annealing in step S3 described later, and is higher than the effective majority carrier concentration of the p-type region constituting the JBS structure of the conventional SiC-SBD that does not provide a contact metal such as a nickel silicide film.

[0047] Therefore, the ohmic junction between the titanium film 31 and the p-type region 13 has a lower resistance compared to the ohmic junction between the titanium film of the conventional SiC-SBD that does not provide a contact metal such as a nickel silicide film and the p-type region constituting the JBS structure. By not forming a contact metal such as a nickel silicide film or a p-type contact region as in Patent Document 1, cost reduction and simplification of the manufacturing process can be achieved. + By not forming a p-type contact region, cost reduction and simplification of the manufacturing process can be achieved.

[0048] Specifically, the contact resistance between the titanium film 31 and the p-type region 13 is, for example, 5×10 -4 Ω·cm 2 or more and 8×10 -3 Ω·cm 2 or less. The lower limit value of the contact resistance between the titanium film 31 and the p-type region 13 is the limit value achievable by the activation annealing in step S3 described later. When the contact resistance between the titanium film 31 and the p-type region 13 becomes higher than the upper limit value, it is difficult to realize the effect (improvement of surge current withstand) of the present embodiment.

[0049] Preferably, the contact resistance between the titanium film 31 and the p-type region 13 is, for example, 3×10 -3 Ω·cm 2 or more and 7×10-3 Ω·cm 2 It is preferably within the following range. FLR21 may be formed simultaneously with the p-type region 13 so that the contact resistance between the titanium film 31 and FLR21 is substantially the same as the contact resistance between the titanium film 31 and the p-type region 13. Substantially the same resistance value means the same resistance value within a range including the allowable error due to process variations.

[0050] The aluminum alloy film 32 covers the entire surface of the titanium film 31 and is electrically connected to the n-type drift region 12, the p-type region 13, and FLR21 through the titanium film 31. The aluminum alloy film 32 may extend outside the titanium film 31 on the field oxide film 15. The aluminum alloy film 32 is, for example, an aluminum silicon (AlSi) film. Instead of the aluminum alloy film 32, an aluminum film may be provided. - On the outermost surface of the front surface of the semiconductor substrate 30, a passivation film 18 made of, for example, polyimide (PI: Polyimide) is provided. The passivation film 18 is a protective film that covers the front surface of the semiconductor substrate 30 and protects the front surface electrode 14 and the field oxide film 15. An opening 18a for exposing a part of the aluminum alloy film 32 is provided in the passivation film 18 in the active region 10.

[0051] On the outermost surface of the front surface of the semiconductor substrate 30, a passivation film 18 made of, for example, polyimide (PI: Polyimide) is provided. The passivation film 18 is a protective film that covers the front surface of the semiconductor substrate 30 and protects the front surface electrode 14 and the field oxide film 15. An opening 18a for exposing a part of the aluminum alloy film 32 is provided in the passivation film 18 in the active region 10.

[0052] The portion of the aluminum alloy film 32 exposed in the opening 18a of the passivation film 18 functions as a bonding pad 41 (anode pad: see FIG. 2). On the entire back surface of the back surface of the semiconductor substrate 30 (the back surface of the n-type starting substrate 11), a back surface electrode (second electrode) 19 is provided. The back surface electrode 19 forms an ohmic contact with the n-type starting substrate 11 and is electrically connected to the n-type starting substrate 11. The back surface electrode 19 functions as a cathode electrode. + On the entire back surface of the back surface of the semiconductor substrate 30 (the back surface of the n-type starting substrate 11), a back surface electrode (second electrode) 19 is provided. The back surface electrode 19 forms an ohmic contact with the n-type starting substrate 11 and is electrically connected to the n-type starting substrate 11. The back surface electrode 19 functions as a cathode electrode. + type starting substrate 11 and is electrically connected to the n-type starting substrate 11. The back surface electrode 19 functions as a cathode electrode. + type starting substrate 11 and is electrically connected to the n-type starting substrate 11. The back surface electrode 19 functions as a cathode electrode.

[0053] The operation of the silicon carbide semiconductor device 40 according to the embodiment will be described. When the forward current flowing through the silicon carbide semiconductor device 40 (SiC-SBD) according to the embodiment is below the rated value, the forward current flows only through the path from the front surface electrode 14 (anode electrode) through the Schottky junction between the front surface electrode 14 and the n - -type drift region 12 to the back surface electrode 19 (cathode electrode), and no current flows through the p-type region 13 constituting the JBS structure.

[0054] On the other hand, when the forward current flowing through the silicon carbide semiconductor device 40 according to the embodiment is a large current (surge current) exceeding the rated value flowing during surge application due to lightning strike or the like, the entire surge current cannot be borne only by the above path through the Schottky junction between the front surface electrode 14 and the n - -type drift region 12, and a surge current also flows into the p-type region 13 constituting the JBS structure from the front surface electrode 14.

[0055] Using the surge current flowing into this p-type region 13 as the base current, bipolar operation occurs at the pn junction between the p-type region 13 and the n - -type drift region 12, and a forward current also flows through the parasitic diode formed at the pn junction. The timing at which the surge current flows into the p-type region 13 is determined by the contact resistance value between the p-type region 13 and the front surface electrode 14.

[0056] In the present embodiment, by performing activation annealing in step S3 (see FIG. 5) described later, contact metals such as nickel silicide films and p + -type contact regions as in the above Patent Document 1 are not provided between the titanium film 31 and the p-type region 13, and the contact resistance between the p-type region 13 and the front surface electrode 14 can be reduced to a predetermined value as compared with a conventional SiC-SBD without providing a contact metal such as a nickel silicide film.

[0057] As a result, compared with a conventional SiC-SBD without a contact metal such as a nickel silicide film, a surge current more easily flows from the front surface electrode 14 to the p-type region 13, and between the p-type region 13 and the n -It is easy to operate in bipolar mode at the pn junction with the type drift region 12. Therefore, compared with a conventional SiC-SBD that does not provide a contact metal such as a nickel silicide film, the surge current is less likely to concentrate locally.

[0058] Next, a method for manufacturing the silicon carbide semiconductor device 40 according to the embodiment will be described. FIG. 5 is a flowchart showing an outline of the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIGS. 6 to 10 are cross-sectional views showing the states during the manufacturing of the silicon carbide semiconductor device according to the embodiment. First, as shown in FIG. 6, as the n + type starting substrate (starting wafer) 11, for example, a silicon carbide four-layer periodic hexagonal crystal (4H-SiC) substrate doped with nitrogen (N) at about 5×10 18 / cm 3 is prepared.

[0059] n + The front surface of the type starting substrate 11 may have an off-angle of about 4° with respect to the (0001) plane, for example. Next, on the front surface of the n + type starting substrate 11, an n - type epitaxial layer doped with nitrogen at about 1.0×10 16 / cm 3 to 5.0×10 16 / cm 3 is grown to form the n - type drift region 12. In FIGS. 4, 8 to 10, the thicknesses of these layers are shown in a simplified manner. The thickness of the n + type starting substrate 11 serving as the n + type cathode region is, for example, about 350 μm, and the thickness of the n - type epitaxial layer serving as the n - type drift region 12 may be, for example, about 6 μm.

[0060] Through the steps up to here, on the front surface of the n + type starting substrate 11 made of silicon carbide, an n - type drift region 12 is formed as an n -A semiconductor substrate (semiconductor wafer: SiC wafer) 30 with a stacked epitaxial layer is fabricated (step S1: first step). As described above, the semiconductor substrate 30 has a front surface on the main surface side of the n - type drift region 12 and a back surface on the main surface side of the n + type starting substrate 11. In the process of step S1, as described above, the n + type starting substrate 11 may be prepared to fabricate the semiconductor substrate 30, or the semiconductor substrate 30 itself may be purchased.

[0061] Next, as shown in FIG. 7, by photolithography and first ion implantation of a p-type impurity such as aluminum, in the active region 10 (see FIGS. 1 and 4), on the surface region of the front surface of the semiconductor substrate 30 (n - type drift region 12 becomes the surface region of the n - type epitaxial layer), one or more p-type regions 13 constituting the JBS structure and the FLR21 are selectively formed respectively (step S2 (part 1): second step). Thereby, a pn junction is formed between the p-type region 13 and the n - type drift region 12.

[0062] In FIG. 7, for simplicity, the p-type regions 13 are illustrated with a smaller number (here, three) than in FIG. 1 (the same applies to FIGS. 8 to 10). The plurality of p-type regions 13 are arranged at equal intervals in a direction parallel to the front surface of the semiconductor substrate 30. The first ion implantation is performed, for example, while heating the semiconductor substrate 30 at a temperature of about 500 °C. The first ion implantation conditions are, for example, a doping concentration of 3×10 19 / cm 3 or more and 5×10 20 / cm 3 or less, and an acceleration energy of about 30 keV. The p-type region 13 and the FLR21 may be formed simultaneously.

[0063] Next, as shown in FIG. 8, the process of taking photolithography and second ion implantation of impurities as a set is repeated under different conditions, and in the edge termination region 20 (see FIG. 4), on the surface region of the front surface of the semiconductor substrate 30, a p-type region (p -p-type region 22 and p -- -type region 23), and n + -type channel stopper region 24 are selectively formed respectively (Step S2 (Part 2)). p - -type region 22, p -- -type region 23 and n + The formation order of the -type channel stopper region 24 can be changed variously.

[0064] Next, as shown in FIG. 9, after covering and protecting the entire front surface of the semiconductor substrate 30 with, for example, a carbon (C) protective film 50, a heat treatment (activation annealing) for activating the first and second ion-implanted impurities is performed (Step S3: Third step). The activation annealing in Step S3 is, for example, inserting the semiconductor substrate 30 into the processing furnace of the heat treatment apparatus, evacuating until the pressure in the processing furnace becomes about 1×10 -2 Pa or less, and then performing the process with argon (Ar) gas introduced into the processing furnace.

[0065] The peripheral temperature of the semiconductor substrate 30 in the furnace or the temperature of the semiconductor substrate 30 itself (hereinafter referred to as the activation annealing temperature) during the activation annealing in Step S3 is, for example, about 1700°C or higher and about 1900°C or lower, which is the maximum temperature achievable with an annealing apparatus for a large-area wafer with a diameter of about 6 inches, and preferably about 1800°C or lower. The processing time of the activation annealing in Step S3 is, for example, more than 20 minutes and about 1 hour or less, and preferably about 30 minutes or more and 40 minutes or less.

[0066] By setting the temperature and processing time of the activation annealing in Step S3 to the above conditions, the activation rate of the p-type region 13 increases, and the contact resistance between the titanium film 31 and the p-type region 13 can be made within the predetermined range described above. If the processing time of the activation annealing in Step S3 exceeds 1 hour, the increase in the activation rate of the p-type region 13 becomes small, and the effect of improving the characteristics saturates. The higher the temperature of the activation annealing in Step S3, the shorter the processing time of the activation annealing can be.

[0067] The activation rate of the p-type region 13 by the activation annealing in step S3 is, for example, about 70% or more and 80% or less. The activation rate of the p-type region 13 by the activation annealing in step S3 increases as the processing time of the activation annealing becomes longer, and can be increased to, for example, about 80% or more and 90% or less. The higher the activation rate of the p-type region 13 is by the activation annealing in step S3, the lower the contact resistance between the titanium film 31 and the p-type region 13 can be.

[0068] Next, as shown in FIG. 10, for example, using an ashing apparatus, the carbon protective film 50 is removed by ashing. For example, a reactive ion etching (RIE) apparatus is used as the ashing apparatus. After making the inside of the processing chamber of the RIE apparatus an oxygen (O 2 ) gas atmosphere at a pressure of about 6 Pa, about 500 W of high-frequency (RF: Radio Frequency) power is applied to form a plasma, and the carbon protective film 50 is removed by ashing for about 5 minutes in the oxygen gas atmosphere.

[0069] Next, for example, by a thermal oxidation method and a chemical vapor deposition (CVD) method, a field oxide film 15 is formed by sequentially laminating a thermal oxide film 16 and a deposited oxide film 17 (see FIG. 4) on the entire front surface of the semiconductor substrate 30 (step S4). Next, the field oxide film 15 is selectively removed by photolithography and etching to form a contact hole 15a that exposes the entire active region 10 and the inner portion of the FLR 21 in the edge termination region 20 (step S5).

[0070] Next, a titanium film 31 is formed on the entire surface from the surface of the field oxide film 15 to the front surface of the semiconductor substrate 30 in the contact hole 15a by a physical vapor deposition method (PVD: Physical Vapor Deposition) such as sputtering. Next, the titanium film 31 is left only in the contact hole 15a of the field oxide film 15 by photolithography and etching (step S6: fourth step). The titanium film 31 may extend on the surface of the field oxide film 15.

[0071] Next, the titanium film 31 is sintered by heat treatment at a temperature of about 500° C. for about 10 minutes. By this heat treatment, a Schottky junction between the titanium film 31 and the n - type drift region 12 is formed, and an ohmic junction between the titanium film 31 and the p-type region 13 is formed (step S7). The thickness of the titanium film 31 may be, for example, about 100 nm. Next, an aluminum alloy film 32 having a thickness of about 5 μm, for example, is formed on the titanium film 31 by a physical vapor deposition method such as sputtering (step S8).

[0072] Next, the semiconductor substrate 30 is ground from the back side to make it thinner to the position of the product thickness used as the silicon carbide semiconductor device 40 (wafer thinning). Next, a back electrode 19 made of nickel or titanium is formed on the entire back surface (the back surface of the n + type starting substrate 11) of the semiconductor substrate 30 by a physical vapor deposition method such as sputtering (step S9: fifth step). The back electrode 19 may be sintered by laser annealing or the like. Thereafter, the semiconductor wafer (semiconductor substrate 30) is diced (cut) into individual chips (step S10), and the silicon carbide semiconductor device 40 shown in FIGS. 1 and 4 is completed.

[0073] As described above, according to the embodiment, after ion implantation for forming a p-type region constituting the JBS structure of the SiC-SBD, activation annealing is performed at a temperature of 1700 °C or higher and 1900 °C or lower and for a processing time exceeding 20 minutes. Thereby, without providing a contact metal such as a nickel silicide film formed by a silicide reaction with the p-type region between the titanium film of the bottom layer of the front surface electrode and the p-type region constituting the JBS structure, the contact resistance between the titanium film and the p-type region can be, for example, 5×10 -4 Ω·cm 2 or more and 8×10 -3 Ω·cm 2 or less.

[0074] As a result, even if the forward current flowing through the SiC-SBD is a large current (surge current) exceeding the rating flowing during surge application due to lightning strike or the like, current easily flows through the p-type region constituting the JBS structure, and bipolar operation is easy at the pn junction between the p-type region and the n - -type drift region. Therefore, a forward current can flow without delay even in the parasitic diode formed by the pn junction between the p-type region and the n - -type drift region, so that the surge current withstand can be improved and element breakdown due to heat generation caused by a large current does not occur. Thereby, the reliability of the SiC-SBD can be improved.

[0075] Also, according to the embodiment, since it is not necessary to provide a contact metal such as a nickel silicide film between the titanium film of the bottom layer of the front surface electrode and the p-type region constituting the JBS structure, the cost can be reduced.

[0076] (Experimental Example) The current-voltage characteristics (I-V characteristics) of the silicon carbide semiconductor device 40 according to the above-described embodiment were verified. FIG. 11 is a chart showing the results of measuring the contact resistance between the front surface electrode of Experimental Example 1 and the p-type region constituting the JBS structure. FIG. 12 is a characteristic diagram showing the current-voltage characteristics of Experimental Examples 1 to 4. FIG. 11 shows the results of measuring the contact resistance between the titanium film 31 and the p-type region 13 of an SiC-SBD (hereinafter referred to as Experimental Example 1) manufactured according to the manufacturing method of the silicon carbide semiconductor device 40 according to the above-described embodiment (see FIG. 5).

[0077] Each sample of Experimental Example 1 has different activation annealing conditions in step S3 of FIG. 5. FIG. 11 shows the doping concentration [ / cm 3 of the p-type region 13, the acceleration energy [keV] of the first ion implantation for forming the p-type region 13, the heating temperature of the semiconductor substrate 30 during the first ion implantation (implant temperature [°C]), the temperature (activation temperature [°C]) and treatment time (activation time [minute]) of the activation annealing in step S3, the presence or absence of contact metal (none), and the contact resistance [Ω·cm 2 between the titanium film 31 and the p-type region 13.

[0078] From the results shown in FIG. 11, only in Sample 3 in which the activation annealing in step S3 of FIG. 5 described above was performed within a predetermined condition range (activation temperature: about 1700 °C or more and 1900 °C or less, activation time: more than 20 minutes), even without providing a contact metal such as a nickel silicide film or a p + -type contact region as in Patent Document 1 between the titanium film 31 and the p-type region 13, the contact resistance between the titanium film 31 and the p-type region 13 can be within a predetermined range (5×10 -4 Ω·cm 2 or more and 8×10 -3 Ω·cm 2 or less). It was confirmed that this can be achieved.

[0079] Therefore, the results of measuring the current-voltage characteristics of Sample 3 in Experimental Example 1 are shown in FIG. 12. The horizontal axis in FIG. 12 represents voltage, and the vertical axis represents current density. In Sample 3 of Experimental Example 1, the temperature (activation temperature) and treatment time (activation time) of the activation annealing in Step S3 of FIG. 5 are 1700° C. and 30 minutes, respectively (see FIG. 11). FIG. 12 also shows the current-voltage characteristics of Experimental Examples 2 to 4. The differences between Experimental Examples 2 to 4 and Sample 3 of Experimental Example 1 are that the treatment times of the activation annealing in Step S3 of FIG. 5 are 20 minutes, 10 minutes, and 5 minutes, respectively.

[0080] From the results shown in FIG. 12, in Experimental Examples 2 to 4, when a high voltage is applied, the increase rate of the current density with respect to the voltage increase becomes small and reaches a saturated state B, and it has been confirmed that heat is generated in this saturated state B and destruction occurs. The reason why the current-voltage characteristics of Experimental Examples 2 to 4 reach the saturated state B when a high voltage is applied is that the contact resistance between the titanium film 31 and the p-type region 13 is a high resistance outside the above-mentioned predetermined range (see Samples 1 and 2 in Example 1 of FIG. 11), and it is difficult for current to flow from the front surface electrode 14 to the p-type region 13. experiment Since it is difficult for current to flow from the front surface electrode 14 to the p-type region 13, bipolar operation is difficult at the pn junction between the p-type region 13 and the n-type drift region 12, and a large current locally concentrates, generating heat and leading to device destruction. Although not shown in the figure, due to the bipolar operation at the pn junction due to the subsequent voltage increase, on the high voltage side beyond the saturated state B, the increase rate of the current density with respect to the voltage increase becomes larger than that in the saturated state B, so the concentration of the local large current is alleviated, but most of them generate heat in the saturated state B and lead to device destruction.

[0081] Since it is difficult for current to flow from the front surface electrode 14 to the p-type region 13, bipolar operation is difficult at the pn junction between the p-type region 13 and the n - type drift region 12, and a large current locally concentrates, generating heat and leading to device destruction. Although not shown in the figure, due to the bipolar operation at the pn junction due to the subsequent voltage increase, on the high voltage side beyond the saturated state B, the increase rate of the current density with respect to the voltage increase becomes larger than that in the saturated state B, so the concentration of the local large current is alleviated, but most of them generate heat in the saturated state B and lead to device destruction.

[0082] On the other hand, in Sample 3 of Experimental Example 1, it was confirmed that the current-voltage characteristics do not reach the saturated state B even when a high voltage is applied, and device destruction does not occur. The reason is that the contact resistance between the titanium film 31 and the p-type region 13 is a low resistance within the above-mentioned predetermined range, and bipolar operation is easy at the pn junction between the p-type region 13 and the n - type drift region 12, and it is easy for bipolar operation to occur at the pn junction between the p-type region 13 and the n -This is because a forward current flows without delay even in the parasitic diode formed by the pn junction with the n-type drift region 12, and the concentration of a large current locally is suppressed.

[0083] As described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention, and it is applicable to a SiC-SBD in which p-type regions constituting a JBS structure are arranged in a predetermined pattern. Further, in the above-described embodiments, a structure is adopted in which a contact metal such as a nickel silicide film is not provided between the front surface electrode and the p-type region constituting the JBS structure, but the present invention is also applicable to a SiC-SBD provided with this contact metal. By providing a contact metal between the front surface electrode and the p-type region constituting the JBS structure, the contact resistance between the front surface electrode and the p-type region constituting the JBS structure can be further reduced.

Industrial Applicability

[0084] As described above, the silicon carbide semiconductor device and the method for manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices, power supply devices such as various industrial machines, and the like.

Explanation of Signs

[0085] 10 Active region 11 n + -type starting substrate 12 n - -type drift region 13 p-type region constituting JBS structure 14 Front surface electrode 15 Field oxide film 15a Contact hole of field oxide film 16 Thermal oxide film 17 Deposited oxide film 18 Passivation film 18a Opening of passivation film 19 Back surface electrode ​​21 Field Limiting Ring (FLR) 22 p-type region forming the JTE structure - 23 p-type region forming the JTE structure -- 24 n-type + channel stopper region 30 Semiconductor substrate 31 Titanium film 32 Aluminum alloy film 40 Silicon carbide semiconductor device 41 Bonding pad 42 Junction of the bonding pad and the wire 50 Carbon protective film​​

Claims

1. A first step of forming a first conductivity type region forming a first main surface of the semiconductor substrate inside a semiconductor substrate made of silicon carbide; A second step of selectively forming one or more second conductivity type regions in a surface region of the first main surface of the semiconductor substrate by ion implantation of second conductivity type impurities to form a pn junction between the second conductivity type region and the first conductivity type region; A third step of activating the second conductivity type impurities by heat treatment; After the third step, a titanium film is formed as a first electrode on the first main surface of the semiconductor substrate, a Schottky junction between the titanium film and the first conductivity type region is formed, and an ohmic junction between the titanium film and the second conductivity type region is formed. A fourth step; A fifth step of forming a second electrode on a second main surface of the semiconductor substrate; Including In the third step, the heat treatment is performed at a temperature of 1700 ° C or higher and 1900 ° C or lower for a treatment time exceeding 20 minutes. A method for manufacturing a silicon carbide semiconductor device, characterized in that no contact metal due to a silicide reaction with the second conductivity type region is formed between the first main surface of the semiconductor substrate and the first electrode.

2. The contact resistance between the titanium film and the second conductivity type region is set to be within a range of 5×10 -4 Ω·cm 2 or more and 8×10 -3 Ω·cm 2 or less. A method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized by this.

3. The contact resistance between the titanium film and the second conductivity type region is 3×10 -3 Ω·cm 2 or more and 7×10 -3 Ω·cm 2 The method for manufacturing a silicon carbide semiconductor device according to claim 2, characterized in that the range is within the following range.

4. In the third step, the activation rate of the second conductivity type impurities is 70% or more and 90% or less. A method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 3.

5. In the second step, the doping concentration of the second conductivity type region is set to be 3×10 19 / cm 3 or more and 5×10 20 / cm 3 or less. The manufacturing method of the silicon carbide semiconductor device according to any one of claims 1 to 4, characterized by this.

6. In the second step, a plurality of the second conductivity type regions are formed in a matrix shape when viewed from the first main surface side of the semiconductor substrate, or in a stripe shape extending parallel to the first main surface of the semiconductor substrate. A method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 5.

7. In the second step, all of the second conductivity type regions are connected to each other at a predetermined location. A method for manufacturing a silicon carbide semiconductor device according to claim 6.

8. In the second step, a plurality of the second conductivity type regions extending in a stripe shape parallel to the first main surface of the semiconductor substrate and connected to each other at ends in the longitudinal direction are formed. A method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 5.

9. Provided inside a semiconductor substrate made of silicon carbide, a first conductivity type region forming a first main surface of the semiconductor substrate, and Selectively provided in contact with the first conductivity type region between the first main surface of the semiconductor substrate and the first conductivity type region, and a second conductivity type region forming the first main surface of the semiconductor substrate. A first electrode provided on a first main surface of the semiconductor substrate, in contact with the first conductivity type region to form a Schottky junction with the first conductivity type region, and in contact with the second conductivity type region to form an ohmic junction with the second conductivity type region, the first electrode including a titanium film; A second electrode provided on a second main surface of the semiconductor substrate; Comprising; The contact resistance between the titanium film and the second conductivity type region is 5×10 -4 Ω·cm 2 or more and 8×10 -3 Ω·cm 2 or less, and A silicon carbide semiconductor device, characterized in that no contact metal due to a silicide reaction with the second conductivity type region is provided between the first main surface of the semiconductor substrate and the first electrode.

10. The contact resistance between the titanium film and the second conductivity type region is 3×10 -3 Ω·cm 2 or more and 7×10 -3 Ω·cm 2 or less, and the silicon carbide semiconductor device according to claim 9 is characterized by this.

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