Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device having a structure which can suppress warpage of a wafer while configuring a semiconductor layer constituting a deep layer by an ion implantation layer.SOLUTION: A p-type deep layer 5, a p-type deep layer 30, and a p-type guard ring 21 are formed by ion implantation. Not only the p-type deep layer 5 and the p-type guard ring 21 but also the p-type deep layer 30 is linearly configured. In this way, linearly configuring the p-type deep layer 30 makes a total value of occupancy of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 40% or lower. This makes it possible to suppress the warpage of a wafer while configuring the p-type layer 30 by ion implantation.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and is particularly suitable for application to a silicon carbide (hereinafter referred to as SiC) semiconductor device.

Background Art

[0002] Conventionally, in order to reduce the on-resistance of a semiconductor switching element such as a MOSFET by adopting a trench gate structure, it is necessary to relax the electric field at the bottom of the trench in the trench gate structure in order to suppress the application of a high electric field to the gate insulating film. For this reason, for example, in Patent Document 1, in order to relax the electric field at the bottom of the trench, a deep layer is formed by high-acceleration ion implantation on both sides of the trench gate structure. Due to this deep layer, the rise of the equipotential line is suppressed, and the electric field at the bottom of the trench is relaxed, thereby suppressing the application of a high electric field to the gate insulating film. In addition, an outer peripheral region surrounding the cell region is provided with a guard ring portion, and a deep layer is provided over the entire area of the connecting portion located between the cell region and the guard ring portion. As a result, the equipotential line extends from the cell region to the connecting portion and further to the guard ring portion and is terminated at the guard ring portion, so that a high breakdown voltage can be achieved.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, when forming a deep layer by high-acceleration ion implantation as in Patent Document 1, warping of the wafer that depends on the dose amount and acceleration occurs during the process, causing problems associated with wafer warping such as conveyance errors, substrate adsorption errors, and reduction in photoresolution.

[0005] On the other hand, when ion implantation is performed, the wafer warpage can be reduced by performing activation annealing and the like each time. However, stacking defects occur in the ion implantation region along with the relaxation process, leading to an increase in drain leakage, an increase in the number of processes, that is, an increase in manufacturing cost.

[0006] Also, as a countermeasure against wafer warpage, there are measures such as ion implantation on the back surface of the wafer. However, an increase in the number of processes and unexpected particle adhesion due to surface adsorption occur, resulting in a decrease in yield due to pattern collapse.

[0007] Furthermore, a deep layer can be formed by embedding a p-type epitaxial layer in the trench, but it is difficult to control the concentration of the deep layer and perform planarization processing on the surface.

[0008] In view of the above points, an object of the present invention is to provide a semiconductor device having a structure capable of suppressing wafer warpage while forming a semiconductor layer constituting a deep layer with an ion implantation layer, and a method for manufacturing the same.

Means for Solving the Problems

[0009] To achieve the above object, claim 1、2、4、5、10、11The invention described in is a semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed in a chip (Ch), a guard ring portion (RG) surrounding the outer periphery of the cell region, and an outer peripheral region (RO) including a connecting portion (RJ) located between the guard ring portion and the cell region, the semiconductor device having a substrate (1, 101) of a first or second conductivity type, and a first conductivity type drift layer (2, 50, 60, 102) formed on the front surface side of the substrate having a front surface and a back surface and having a lower impurity concentration than the substrate. The cell region has a second conductivity type layer (5, 5a, 51, 103) formed in the drift layer and including a portion formed in a stripe shape with one direction as the longitudinal direction, a first electrode (9, 106) electrically connected to the second conductivity type layer, and a second electrode (11, 107) formed on the back surface side of the substrate, and is provided with a vertical semiconductor element for flowing a current between the first electrode and the second electrode. The connecting portion is also provided with a second conductivity type layer (31, 33 to 35, 71) formed in a line shape in the drift layer. Further, the guard ring portion or the guard ring portion and the connecting portion are provided with a second conductivity type ring (21, 32, 72, 104, 105) formed in the drift layer and having a plurality of line-shaped frame shapes surrounding the cell region, and at least a part located on the outer peripheral side constituting a guard ring (21, 104). And the second conductivity type layer and the second conductivity type ring are constituted by an ion implantation layer, and the ratio occupied by the second conductivity type layer and the second conductivity type ring with respect to the total area of the chip is 40% or less.

[0010] Thus, the second conductivity type layer and the second conductivity type ring are formed by ion implantation. Not only the second conductivity type layer in the cell region and the second conductivity type ring in the guard ring portion, but also the second conductivity type layer in the connecting portion is configured in a line shape. By configuring the second conductivity type layer in the connecting portion in a line shape in this way, the total value of the occupancy rates of the second conductivity type layer and the second conductivity type ring in the chip is made 40% or less. Thereby, while configuring the semiconductor layer constituting the second conductivity type layer in the connecting portion, that is, the deep layer, by ion implantation, it becomes possible to suppress wafer warpage.

[0011] Claim 15 or 16The semiconductor device described in has a cell region (RC) in which a semiconductor element (100) is formed in a chip (Ch), a guard ring portion (RG) surrounding the outer periphery of the cell region, and an outer peripheral region (RO) including a connecting portion (RJ) located between the guard ring portion and the cell region. A method for manufacturing a semiconductor device includes forming a first conductivity type drift layer (2, 50, 60, 102) made of a first conductivity type semiconductor having a lower impurity concentration than the substrate on a substrate (1, 101) composed of a semiconductor of a first or second conductivity type having a front surface and a back surface; forming a second conductivity type layer (5, 5a, 51, 103) including a stripe-shaped portion having one direction as a longitudinal direction in the cell region by ion-implanting a second conductivity type impurity into the drift layer, and also forming a second conductivity type layer (31, 33 - 35, 71) formed in a line shape in the connecting portion; further forming a second conductivity type ring (21, 32, 72, 104, 105) having a plurality of line-shaped frame shapes surrounding the cell region, and at least a part located on the outer peripheral side constituting a guard ring (21, 104) in the guard ring portion or the guard ring portion and the connecting portion; forming a first electrode (9, 106) electrically connected to the second conductivity type layer in the cell region; and forming a second electrode (11, 107) on the back surface side of the substrate. By forming the second conductivity type layer and the second conductivity type ring, the ratio occupied by the second conductivity type layer and the second conductivity type ring with respect to the total area of the chip is set to 40% or less.

[0012] In this way, the second conductivity type layer and the second conductivity type ring are formed by ion implantation. And not only the second conductivity type layer in the cell region and the second conductivity type ring in the guard ring portion but also the second conductivity type layer in the connecting portion is formed in a line shape. By configuring the second conductivity type layer in the connecting portion in a line shape like this, the total value of the occupation ratio of the second conductivity type layer and the second conductivity type ring in the chip is made 40% or less. Thereby, while configuring the semiconductor layer constituting the second conductivity type layer in the connecting portion, that is, the deep layer, by ion implantation, it becomes possible to suppress wafer warpage.

[0013] Note that the reference numerals in parentheses for each of the above means indicate an example of the correspondence relationship with the specific means described in the embodiments described later.

Brief Explanation of Drawings

[0014]

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Embodiments for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals for description.

[0016] (First Embodiment) The first embodiment will be described. Here, a SiC semiconductor device in which an inversion-type MOSFET having a trench gate structure is formed as a semiconductor element will be described as an example.

[0017] FIG. 1 shows a top layout of a chip CH of a SiC semiconductor device in which a MOSFET 100 having a trench gate structure is formed. The SiC semiconductor device shown in FIG. 1 has a configuration including a cell region RC in which the MOSFET 100 is formed and an outer peripheral region RO surrounding the cell region RC. The outer peripheral region RO has a configuration including a guard ring portion RG and a connecting portion RJ disposed inside the guard ring portion RG, that is, between the cell region RC and the guard ring portion RG. Note that although FIG. 1 is not a cross-sectional view, hatching is partially shown for ease of viewing.

[0018] As shown in FIG. 2, the SiC semiconductor device is formed using an n-type substrate 1 made of SiC. + An n-type layer 2 corresponding to a low-concentration layer made of SiC and a p-type base region 3 are formed on the main surface of the n-type substrate 1 by epitaxial growth or the like. Further, an n-type source region 4 is formed in the surface layer portion of the p-type base region 3. + An n-type layer 2 corresponding to a low-concentration layer made of SiC and a p-type base region 3 are formed on the main surface of the n-type substrate 1 by epitaxial growth or the like. Further, an n-type source region 4 is formed in the surface layer portion of the p-type base region 3. - An n-type layer 2 corresponding to a low-concentration layer made of SiC and a p-type base region 3 are formed on the main surface of the n-type substrate 1 by epitaxial growth or the like. Further, an n-type source region 4 is formed in the surface layer portion of the p-type base region 3. + An n-type layer 2 corresponding to a low-concentration layer made of SiC and a p-type base region 3 are formed on the main surface of the n-type substrate 1 by epitaxial growth or the like. Further, an n-type source region 4 is formed in the surface layer portion of the p-type base region 3.

[0019] n + The n-type substrate 1 has, for example, an n-type impurity concentration of 1.0×10 19 / cm 3 and is an off-substrate having a surface of (0001)Si plane and an off direction of <11-20> direction. The n-type layer 2 has a lower impurity concentration than the n-type substrate 1 and has, for example, an n-type impurity concentration of 5.0×10 - n + ~2.0×10 15 ~2.0×10 16 / cm 3 In the case of this embodiment, this n-type layer 2 constitutes a drift layer. - In the case of this embodiment, this n-type layer 2 constitutes a drift layer.

[0020] Also, the p-type base region 3 is a portion where a channel region is formed, and has a p-type impurity concentration of, for example, 2.0×1017 / cm 3 is set to a certain level and has a thickness of 300 nm. In the surface layer of the p-type base region 3, that is, in the n of each adjacent cell in the MOSFET 100 + type source region 4, a p-type contact region 3a and a p-type hole extraction layer 3b with a high concentration of p-type impurities are partially formed. The n + type source region 4 has a higher impurity concentration than the n - type layer 2, and the n-type impurity concentration in the surface layer is, for example, 2.5×10 18 ~1.0×10 19 / cm 3 and is configured to have a thickness of about 0.5 μm.

[0021] In the cell region RC, the p-type base region 3 and the n + type source region 4 are left on the surface side of the n-type substrate 1. In the connection portion RJ, the p-type base region 3 including the p-type hole extraction layer 3b is left on the surface side of the n + type substrate 1. Further, in the guard ring portion RG, a recess 20 is formed so as to reach the n + type layer 2 through the p-type base region 3. By adopting such a structure, a mesa portion RM in which the cell region RC and the connection portion RJ protrude from the guard ring portion RG is formed. Note that the portion surrounded by the broken line in FIG. 1 indicates the mesa portion RM, and the portion with the broken line hatching inside is the connection portion RJ. - type layer 2 through the p-type base region 3. By adopting such a structure, a mesa portion RM in which the cell region RC and the connection portion RJ protrude from the guard ring portion RG is formed. Note that the portion surrounded by the broken line in FIG. 1 indicates the mesa portion RM, and the portion with the broken line hatching inside is the connection portion RJ.

[0022] Also, in the cell region RC, a p-type deep layer 5 having a higher p-type impurity concentration than the p-type base region 3 is formed in the surface layer of the n - type layer 2. The p-type deep layer 5 constitutes at least a part of the second conductivity type layer. The p-type deep layer 5 is formed from a position at a predetermined depth of the n - type layer 2 to the surface, and is formed by ion-implanting p-type impurities into the n - type layer 2.

[0023] The p-type deep layer 5 is the n -A plurality of them are arranged at equal intervals within the p-type layer 2, and as shown in FIG. 1, they have linear portions 5a arranged in a striped pattern that are spaced apart from each other without intersections. Also, in the case of this embodiment, the p-type deep layer 5 also has intersection portions 5b extending in a direction intersecting the linear portions 5a, and the intersection portions 5b are arranged at both ends of each linear portion 5a so that the two are connected. In other words, the p-type deep layer 5 forms a rectangular shape surrounding the outer periphery of the cell region RC by the outermost portion among the plurality of linear portions 5a and the intersection portions 5b, and inside that, the remaining linear portions 5a are arranged in a plurality of stripes. The above-described p-type base region 3 and n + type source region 4 are formed on this p-type deep layer 5.

[0024] In this embodiment, the p-type deep layer 5 is formed with the same impurity concentration, the same width, and the same depth. For example, the p-type impurity concentration is 1.0×10 17 ~1.0×10 19 / cm 3 , the width is 0.4 to 1.0 μm, and the depth is about 2.0 μm. Also, the interval DA1 between the linear portions 5a of the p-type deep layer 5 is set to 0.6 to 1.5 μm. And at the intersection portion 5b of the p-type deep layer 5, the linear portion 31 of the p-type deep layer 30 of the connecting portion RJ described later is connected.

[0025] The extending direction of the p-type deep layer 5 is arbitrary, but in this embodiment, it is the <11-20> direction same as the off direction.

[0026] Note that the intersection portion 5b of the p-type deep layer 5 is not essential, and the linear portions 5a of the p-type deep layer 5 and the p-type deep layer 30 of the connecting portion RJ do not have to be connected. Here, the interval DA1 between the linear portions 5a of the p-type deep layer 5 is made different from the interval DA2 of the linear portion 31 of the p-type deep layer 30, but the interval DA1 and the interval DA2 may be the same, and a structure may be adopted in which each linear portion 5a and each linear portion 31 are connected.

[0027] Also, a p-type base region 3 and an n + type source region 4 penetrate through to reach the n - type layer 2, and a plurality of gate trenches 6, for example, having a width of 0.8 μm and a depth of 1.0 μm, are formed so as to be shallower than the p-type deep layer 5. The above-described p-type base region 3 and n + type source region 4 are arranged so as to be in contact with the side surfaces of each of the plurality of gate trenches 6. Each gate trench 6 is formed in a linear layout with the horizontal direction in the plane of FIG. 2 as the width direction, the vertical direction in the plane of the paper as the longitudinal direction, and the up-down direction in the plane of the paper as the depth direction. Also, as shown in FIG. 1, the plurality of gate trenches 6 are arranged so as to be sandwiched between the respective linear portions 5a of the p-type deep layer 5, and are formed in a stripe shape by being arranged in parallel at equal intervals.

[0028] Furthermore, a portion of the p-type base region 3 located on the side surface of the gate trench 6 is used as a channel region that connects between the n + type source region 4 and the n - type layer 2 during the operation of the MOSFET 100, and a gate insulating film 7 is formed on the inner wall surface of the gate trench 6 including the channel region. A gate electrode 8 made of doped Poly-Si is formed on the surface of the gate insulating film 7, and the gate trench 6 is filled with these gate insulating film 7 and gate electrode 8. Thereby, a trench gate structure having one direction as the longitudinal direction is configured. The above-described p-type deep layer 5 is formed along the same direction as the longitudinal direction of the trench gate structure on both sides of this trench gate structure. In FIG. 1, the number of the trench gate structure and the p-type deep layer 5 is reduced for easy viewing of the figure, but actually, a large number of similar structures are arranged.

[0029] Also, on the opposite side of the n + type substrate 1 with the n - type layer 2 interposed therebetween, specifically, on the n +On the surfaces of the n-type source region 4, the p-type base region 3, and the gate electrode 8, a source electrode 9 corresponding to the first electrode and a gate wiring layer (not shown) are formed via an interlayer insulating film 10. The source electrode 9 and the gate wiring layer are composed of a plurality of metals, for example, Ni / Al, etc. And among the plurality of metals, at least the part in contact with the n-type SiC, specifically the n + type source region 4 is composed of a metal capable of forming an ohmic contact with n-type SiC. Also, among the plurality of metals, at least the part in contact with the p-type SiC, specifically the p-type contact region 3a and the p-type hole extraction layer 3b, is composed of a metal capable of forming an ohmic contact with p-type SiC. Note that these source electrode 9 and gate wiring layer are electrically insulated by being separated on the interlayer insulating film 10. And through the contact holes formed in the interlayer insulating film 10, the source electrode 9 is electrically contacted with the n + type source region 4 and the p-type contact region 3a, etc., and the gate wiring layer is electrically contacted with the gate electrode 8.

[0030] Furthermore, on the back side of the n + type substrate 1, a drain electrode 11 corresponding to the second electrode electrically connected to the n + type substrate 1 is formed. With such a structure, an n-channel type inversion-mode trench gate structure MOSFET 100 is configured. And by arranging a plurality of such MOSFETs 100, a cell region RC is configured.

[0031] On the other hand, in the guard ring portion RG, as described above, a recess 20 is formed so as to penetrate the p-type base region 3 and reach the n - type layer 2. Therefore, at a position away from the cell region RC, the n + type source region 4 and the p-type base region 3 are removed, and the n - type layer 2 is exposed. And in the thickness direction of the n + type substrate 1, a cell region RC and a part of the connection portion RJ located inside the recess 20 form a mesa portion RM protruding in an island shape.

[0032] Also, n located below the concave portion 20 - On the surface layer portion of the n-type layer 2, a plurality of p-type guard rings 21 are provided so as to surround the cell region RC and the connection portion RJ. The p-type guard ring 21 constitutes at least a part of the second conductivity type ring. In the case of the present embodiment, as shown in FIG. 1, the p-type guard ring 21 has a rectangular shape with rounded corners, but may be formed in other frame shapes such as a circular shape. The p-type guard ring 21 is formed from the surface of the n - type layer 2 to a position at a predetermined depth, but may be formed away from the surface of the n - type layer 2. The p-type guard ring 21 is formed by ion-implanting p-type impurities into the n - type layer 2.

[0033] In the present embodiment, the p-type guard ring 21 has the same configuration as the above-described p-type deep layer 5. The p-type guard ring 21 is different from the linearly formed p-type deep layer 5 in that the upper surface shape is a line shape of a frame shape surrounding the cell region RC and the connection portion RJ, but the others are the same. That is, the p-type guard ring 21 has the same impurity concentration and the same width as the p-type deep layer 5. Regarding the interval DA3 between the p-type guard rings 21, it may be equally spaced, but in order to relieve the electric field concentration on the cell region RC side and make the equipotential lines go more toward the outer peripheral side, the interval DA3 of the p-type guard rings 21 is made narrower on the cell region RC side and larger toward the outer peripheral side. The interval DA3in of the portion of the interval DA3 of the p-type guard ring 21 located within a predetermined range from the boundary position of the mesa portion RM is made narrower than the interval DA1 of the linear portion 5a of the p-type deep layer 5 and the interval DA2 of the linear portion 31 of the p-type deep layer 30 described later. Also, the widest portion located at the outermost periphery of the interval DA3, that is, the interval DA3out between the outermost p-type guard ring 21 and the one inside it is made wider than the interval DA1 and the interval DA2.

[0034] Although not shown in the drawings, an EQR structure is provided on the outer periphery of the p-type guard ring 21 as needed, thereby forming a guard ring portion RG having an outer peripheral pressure-resistant structure surrounding the cell region RC.

[0035] Furthermore, the portion from the cell region RC to the guard ring portion RG is defined as a connecting portion RJ. In the connecting portion RJ, a p-type deep layer 30 is formed in the surface layer portion of the n - type layer 2. The p-type deep layer 30 is in contact with the p-type base region 3 and is fixed to the source potential. In the case of this embodiment, as shown by the broken-line hatching in FIG. 1, the connecting portion RJ is formed so as to surround the cell region RC. Further, a plurality of p-type guard rings 21 having a rectangular shape with rounded corners are formed so as to surround the outside of the connecting portion RJ.

[0036] The p-type deep layer 30 is configured to have a linear portion 31 arranged in a stripe shape with a plurality of them arranged in parallel with the p-type deep layer 5 formed in the cell region RC, and a frame portion 32 formed by arranging one or more of them so as to surround the p-type deep layer 5 and the linear portion 31. The linear portion 31 of the p-type deep layer 30 constitutes a part of the second conductivity type layer, and the frame portion 32 constitutes a part of the second conductivity type ring.

[0037] The linear portion 31 is formed in the region between the cell region RC and the frame portion 32. In this region, n -If a p-type layer is not formed in the type layer 2, a location where equipotential lines rise excessively will occur. Therefore, it is formed so that such a location does not occur. In the direction perpendicular to the longitudinal direction of the linear portion 5a of the p-type deep layer 5, a plurality of linear portions 31 are arranged in parallel with the linear portion 5a between the cell region RC and the frame-shaped portion 32. Also, in the longitudinal direction of the linear portion 5a, a plurality of linear portions 31 are formed to extend in the same direction as the linear portion 5a between the cell region RC and the frame-shaped portion 32. And the tip of each linear portion 5a is connected to the intersection portion 5b of the p-type deep layer 5 or the portion located on the innermost peripheral side of the frame-shaped portion 32. In this way, the linear portion 31 is arranged between the cell region RC and the frame-shaped portion 32. The tip of the linear portion 31 may be separated without being connected to the intersection portion 5b or the frame-shaped portion 32, but in that case, it is preferable that the distance between them is the same as or smaller than the interval DA1 between the linear portions 5a of the p-type deep layer 5.

[0038] The frame-shaped portion 32 has a rectangular shape with rounded corners and surrounds the cell region RC and the periphery of the linear portion 31. Specifically, the frame-shaped portion 32 is arranged concentrically with the p-type guard ring 21. In this embodiment, a plurality of frame-shaped portions 32 are provided.

[0039] Each p-type deep layer 30 composed of these linear portions 31 and the frame-shaped portion 32 is formed by ion implantation from the surface of the n - type layer 2 to a position at a predetermined depth.

[0040] In the case of this embodiment, the width of the linear portion 31 of the p-type deep layer 30 is set to 0.4 to 1.0 μm, which is the same as the width of the p-type deep layer 5. The interval DA2 between the linear portions 31 may be the same as the interval DA1 between the linear portions 5a of the p-type deep layer 5, but here it is made narrower than the interval DA1.

[0041] The frame-shaped portion 32 is formed from the inner peripheral side to the outer peripheral side of the mesa portion RM and has the same width as the p-type deep layer 5. Also, the intervals DA4 of the frame-shaped portions 32 may all have the same width or may be different. Preferably, the interval DA4 of the frame-shaped portions 32 is equal to or less than the interval DA1 between the linear portions 5a of the p-type deep layer 5 in the cell region RC. More preferably, the interval DA4out of the portions of the interval DA4 of the frame-shaped portions 32 that are located within a predetermined range from the boundary position of the mesa portion RM is made narrower than the interval DA2 between the linear portions 31 in the p-type deep layer 30.

[0042] Here, the interval DA3in of the p-type guard ring 21 and the interval DA4out of the frame-shaped portion 32 that are located within a predetermined range from the boundary position of the mesa portion RM are made narrower than the interval DA2 between the linear portions 31 in the p-type deep layer 30. This is to cope with mask misalignment when forming the recess 20 for forming the mesa portion RM.

[0043] When mask misalignment occurs, the formation position of the inner peripheral end of the recess 20 is shifted. For example, in the structure of FIG. 1, assume that mask misalignment occurs and the formation position of the inner peripheral end of the recess 20 is shifted to the right side of the paper surface. In this case, a part of the frame-shaped portion 32 is formed within the recess 20 outside the mesa portion RM on the left side of the paper surface, and a part of the p-type guard ring 21 is formed not within the recess 20 but within the mesa portion RM on the right side of the paper surface. With such a structure, since a part of the frame-shaped portion 32 has the same structure as the guard ring, it is preferable that the width and interval are the same as those on the inner peripheral side of the p-type guard ring 21. Therefore, as in the present embodiment, for the portions located within a predetermined range from the boundary position of the mesa portion RM, the interval DA4out of the frame-shaped portion 32 and the interval DA3in of the p-type guard ring 21 are made narrower than the interval DA1. Preferably, the frame-shaped portion 32 and the p-type guard ring 21 are made to have the same width and interval. By doing so, it is possible to cope with mask misalignment.

[0044] Here, the frame-shaped portion 32 has been described separately from the p-type guard ring 21. However, it can be said that the frame-shaped portion 32 and the p-type guard ring 21 constitute a plurality of concentric frame-shaped p-type rings. That is, it can be said that the portion of the p-type ring disposed on the inner peripheral side of the concave portion 20 constitutes the frame-shaped portion 32, and the portion formed within the concave portion 20 constitutes the p-type guard ring 21.

[0045] Also, a p-type base region 3 is formed at the connection portion RJ. And, a p-type hole extraction layer 3b is formed on the p-type base region 3. The source electrode 9 is formed up to the upper part of the p-type hole extraction layer 3b, and the p-type base region 3 and the p-type deep layer 30 are connected through the p-type hole extraction layer 3b. The p-type hole extraction layer 3b is formed so as to surround the cell region RC at the connection portion RJ. Here, the p-type hole extraction layer 3b is formed so as to surround the entire circumference of the cell region RC once. However, it may be formed by dividing it into a plurality of parts and arranging them at equal intervals over the entire circumference. By providing this p-type hole extraction layer 3b, when avalanche breakdown occurs in the cell region RC, or when avalanche breakdown occurs in the guard ring portion RG or the connection portion RJ, holes generated in the outer peripheral region can be extracted to the source electrode 9. For this reason, it is possible to restrict the flow of holes into the cell region RC side, and it becomes possible to suppress element breakdown.

[0046] Also, an interlayer insulating film 10 is formed on the surface of the p-type hole extraction layer 3b. Although not shown, the gate pad connected to the gate wiring layer is formed at a location different from the location where the source electrode 9 is disposed in the interlayer insulating film 10 at the connection portion RJ.

[0047] With the above structure, the SiC semiconductor device according to this embodiment is configured. When the MOSFET 100 is turned on, the SiC semiconductor device configured in this way forms a channel region on the surface portion of the p-type base region 3 located on the side surface of the gate trench 6 by controlling the voltage applied to the gate electrode 8. As a result, the n + type source region 4, the channel region, and the n -A current is passed between the source electrode 9 and the drain electrode 11 through the type layer 2.

[0048] Also, when the MOSFET 100 is off, even if a high voltage is applied, the entry of the electric field to the bottom of the gate trench is suppressed by the p-type deep layer 5 and the p-type deep layer 30 formed to a position deeper than the trench gate structure. For this reason, the electric field concentration at the bottom of the gate trench is alleviated. Thereby, the breakdown of the gate insulating film 7 is prevented.

[0049] Furthermore, at the connection part RJ, the rise of the equipotential line is suppressed, and the equipotential line is made to go toward the guard ring part RG side. Then, in the guard ring part RG, the equipotential line is gradually terminated in the outer peripheral direction by the p-type guard ring 21, and a desired withstand voltage can be obtained also in the guard ring part RG.

[0050] Here, regarding the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21, the width of each part, the intervals DA1 to DA4, etc. are as described above. Thereby, the ratio occupied by the p-type layer deeply implanted by ion implantation with respect to the entire area of the chip constituting the SiC semiconductor device, that is, the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21, is made 40% or less.

[0051] When the p-type layer is formed by ion implantation, warpage occurs in the wafer for forming the SiC semiconductor device depending on the dose amount and acceleration during the process, so problems associated with wafer warpage such as transfer errors, substrate adsorption errors, and reduction in photo resolution occur.

[0052] Therefore, while achieving the effect of suppressing the entry of the electric field to the bottom of the gate trench and the effect of obtaining a desired withstand voltage in the guard ring part RG, it is required to minimize the wafer warpage.

[0053] Specifically, the relationship between the acceleration voltage of ion implantation and the wafer warp is shown as in Figure 3. Also, the relationship between the integrated dose amount of ion implantation and the wafer warp is shown as in Figure 4. Regarding the relationship between the acceleration voltage of ion implantation and the warp of the wafer, a 350-μm-thick substrate was used, and a p-type layer with a depth similar to that of the p-type deep layer 5 was formed using Al as a p-type impurity. The ion implantation was investigated for the case of performing ion implantation on the front surface side and the back surface side of the SiC substrate, respectively. The dose amount at this time was fixed at 8×10 14 cm -2 . Also, regarding the relationship between the dose amount of ion implantation and the wafer warp, a constant acceleration voltage of 150 keV was used, and a p-type layer with a depth similar to that of the p-type deep layer 5 was formed on the surface of the SiC substrate using Al as a p-type impurity. The difference in height between the outer edge and the center of the substrate was measured as the warp amount.

[0054] As can be seen from Figure 3, the wafer warp is proportional to the acceleration voltage of ion implantation, and the larger the acceleration voltage, the larger the wafer warp. Also, as can be seen from Figure 4, the wafer warp is proportional to the dose amount of ion implantation, and the larger the dose amount, the larger the wafer warp.

[0055] Therefore, if the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are to be formed to a deep position at a high acceleration voltage, it is required to reduce the dose amount during ion implantation. To achieve this, it is not preferable to have a structure with deep layers throughout the joint part as in Patent Document 1, and it is necessary to limit the formation ranges of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 as in this embodiment.

[0056] Therefore, in the present embodiment, the p-type deep layer 30 formed in the connection portion RJ is configured by a linear straight portion 31 and a frame-shaped portion 32, and is not formed over the entire area of the connection portion RJ. However, when the p-type deep layer 30 is not formed over the entire area of the connection portion RJ, if the interval DA2 between the linear portions 31 is wide, as shown in FIG. 5A, the equipotential line will bulge, which may reduce the breakdown voltage. Specifically, when the p-type layers are arranged in stripes and the relationship between the interval DA2 and the breakdown voltage is examined, the results shown in FIG. 5B are obtained. It is confirmed that in order to obtain a breakdown voltage with an interval DA2 of about 1800 [V], the interval DA2 is preferably 1.5 μm or less. For this reason, the interval DA2 between the linear portions 31 in the p-type deep layer 30 is set to 1.5 μm or less.

[0057] On the other hand, from the perspective of the breakdown voltage, it is sufficient if the interval DA2 is 1.5 μm or less. However, if the interval DA2 is too narrow, the remaining width of the photomask used when ion-implanting the p-type deep layer 30 becomes narrow, and there is a possibility that patterning cannot be performed well. For this reason, the interval DA2 is set to 0.6 μm or more.

[0058] Here, the interval DA2 between the linear portions 31 in the p-type deep layer 30 has been described. The same applies to the interval DA1 between the p-type deep layers 5 in the cell region RC. It is preferable that the interval DA1 is 0.6 to 1.5 μm. Also, it is preferable that the intervals DA3in and DA4out are 0.6 to 1.5 μm, and it is more preferable to make them smaller than the intervals DA1 and DA2 so as to cope with mask misalignment.

[0059] Also, the closer the intervals DA1 and DA2 are, the higher the withstand voltage can be improved. However, accordingly, the formation ratios of the p-type deep layer 5 and the p-type deep layer 30 increase, and the dose amount during ion implantation increases. Therefore, while reducing the intervals DA1 and DA2, it is necessary to ensure that the dose amount during ion implantation does not become excessive. Furthermore, not only the intervals DA1 and DA2 but also the widths of the p-type deep layer 5 and the p-type deep layer 30 affect the dose amount of ion implantation. And since the widths of the p-type deep layer 5 and the p-type deep layer 30 are factors contributing to a decrease in withstand voltage and an increase in the feedback capacitance Crss, it is necessary to set the dose amount of ion implantation so that the feedback capacitance Crss can be suppressed while ensuring the withstand voltage and the wafer warpage can be suppressed.

[0060] FIG. 6A shows the change in the strength of the electric field applied near the bottom of the gate trench 6 when the width of the linear portion 31 in the p-type deep layer 5 is changed in the cell region RC. The same result was obtained when the interval between the linear portions 31 was widened while keeping the width of the linear portion 31 constant. Although the electric field in the cell region RC is shown here, the same applies to the connecting portion RJ. As shown in this figure, when the widths of the p-type deep layer 5 and the p-type deep layer 30 become narrower, equipotential lines are more likely to enter the p-type deep layer 5 and the p-type deep layer 30 as described above. For this reason, the rise of the equipotential lines between the p-type deep layer 5 and the p-type deep layer 30 becomes large, leading to a decrease in withstand voltage. In particular, in the cell region RC, a high electric field is applied to the bottom of the gate trench 6, and the gate insulating film 7 may be broken down.

[0061] FIG. 6B shows the change in the feedback capacitance Crss when the interval between the linear portions 31 in the p-type deep layer 30 is kept constant and the width of the linear portion 31 is changed. Specifically, with the measured value n = 3, the width of the linear portion 31 was changed, and the feedback capacitance Crss when 450 [V] was applied to the drain side was measured, and the result of curve fitting of the average value is shown. The same result was obtained when the interval between the linear portions 31 was widened while keeping the width of the linear portion 31 constant.

[0062] When the reverse recovery capacitance Crss increases, the switching loss increases. Therefore, it is necessary to limit the width of the p-type deep layer 30 to a certain extent. When the width of the p-type deep layer 30 is narrow, a depletion layer is generated at the PN junction between the p-type deep layer 30 and the n - type layer 2, and equipotential lines enter the p-type deep layer 30. For this reason, if the width of the p-type deep layer 30 is too narrow, the reverse recovery capacitance Crss will increase further.

[0063] Considering the switching loss, it is preferable that the reverse recovery capacitance Crss is 60 [pF] or less. Considering the breakdown voltage, it is preferable that the electric field strength applied between the p-type deep layer 5 and the p-type deep layer 30 is 4 [MV / cm] or less. In order to satisfy these conditions, in the present embodiment, the widths of the p-type deep layer 5 and the p-type deep layer 30 are set to 0.4 μm or more.

[0064] Also, for the p-type deep layer 5 and the p-type deep layer 30, if the width is increased, the above conditions can be satisfied. However, when the width exceeds a certain level, even if the width is increased, the effect of suppressing the reverse recovery capacitance Crss and ensuring the breakdown voltage does not improve much. Conversely, increasing the width of the p-type deep layer 5 or the p-type deep layer 30 means that the dose amount of the p-type impurity increases when ion-implanting, which affects the wafer warpage. Therefore, it is better to limit the widths of the p-type deep layer 5 and the p-type deep layer 30 to 1.5 μm or less, preferably 1.0 μm or less, at which the effect of suppressing the reverse recovery capacitance Crss and ensuring the breakdown voltage almost levels off.

[0065] When the widths of the p-type deep layer 5 and the p-type deep layer 30 are set to 0.4 to 1.5 μm, it is necessary to set the intervals between the p-type deep layer 5 and the p-type deep layer 30 so that the dose amount during ion implantation can suppress the wafer warp to a predetermined value or less. For this reason, based on the results shown in FIG. 4, the intervals DA1 and DA2 are set to 0.6 to 1.5 μm. As described above, the interval DA1 and the interval DA2 can be made the same. However, unlike the interval DA1 in which the trench gate structure is sandwiched, since the trench gate structure is not sandwiched in the interval DA2, it is more preferable to make it smaller than the interval DA1.

[0066] Here, the intervals DA1 and DA2 have been described. However, the same can be said for the intervals DA4, DA4out of the frame-shaped portion 32 and the interval DA3in of the portion located in a predetermined range from the boundary position of the mesa portion RM of the p-type guard ring 21. Also, the same can be said for the width of the p-type guard ring 21 as that of the p-type deep layer 5 and the p-type deep layer 30. Furthermore, due to the concentration of equipotential lines in the vicinity of the mesa portion RM in terms of structure, in order to suppress the rise of the equipotential lines in the mesa portion RM, it is better to make the intervals DA4out and DA3in in a predetermined range from the boundary portion of the mesa portion RM smaller than the intervals DA1 and DA2.

[0067] In this way, the intervals DA1 to DA4 and the widths of the p-type deep layers 5 and 30 are defined. FIG. 7 shows the area ratios occupied by the cell region RC, the connection part RJ, and the guard ring part RG in a 5 mm□ chip in which the SiC semiconductor device is formed, and the occupancy ratios of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 among them. Here, as an example, a case is cited where the cell region RC occupies 60%, the connection part RJ occupies 30%, and the guard ring part RG occupies 10% with respect to the chip area. As a comparative example, a case where the p-type deep layer 30 is formed over the entire area of the connection part RJ and a case where the p-type deep layer 30 is composed of the linear part 31 and the frame-shaped part 32 as in the present embodiment are examined. Also, the widths of the p-type deep layer 5 and the p-type deep layer 30 are set to 1.0 μm, the intervals DA1 to DA3 are set to 0.6 μm, the width of the p-type guard ring 21 is set to 1.0 μm, and the interval DA4 is set to 0.6 to 1.5 μm so as to become wider as it is farther from the cell region RC.

[0068] As shown in this figure, in the comparative example where the p-type deep layer 30 is formed over the entire area of the connection part RJ, the occupancy ratio of the p-type deep layer 30 in the connection part RJ becomes 100%. Therefore, the occupancy ratio of the p-type deep layer 30 in the chip becomes 30%, which is the same as the area ratio occupied by the connection part RJ in the chip. And in the cell region RC, the occupancy ratio of the p-type deep layer 5 in the chip was 24%, and in the guard ring part RG, the occupancy ratio of the p-type guard ring 21 in the chip was 3%. Therefore, the total value of the occupancy ratios of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip became 57%.

[0069] On the other hand, when the p-type deep layer 30 is configured by the linear part 31 and the frame-shaped part 32 as in this embodiment, the proportion of the p-type deep layer 30 in the connecting part RJ becomes 40%. Therefore, the proportion of the p-type deep layer 30 in the chip becomes 12%. Also, in the cell region RC, the proportion of the p-type deep layer 5 in the chip remains 24%, and in the guard ring part RG, the proportion of the p-type guard ring 21 in the chip remains 3%. Therefore, the total value TV of the occupancy rates of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip becomes 39%.

[0070] In this way, by making the p-type deep layer 30 line-shaped such as the linear part 31 and the frame-shaped part 32, the occupancy rates of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip can be decreased. Here, the widths of the p-type deep layer 5 and the p-type deep layer 30 are set to 1.0 μm, and the intervals DA1 to DA3 are set to 0.6 μm. Therefore, compared with the case of making the widths narrower and the intervals DA1 to DA3 wider than this, the occupancy rates of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip are high. If the width of the p-type deep layer 30 is made smaller than 1.0 μm or the intervals DA1 to DA3 are made larger than 0.6 μm, the total value TV can be made smaller and can be at least 40% or less. Thereby, it becomes possible to suppress the total value TV of the occupancy rates of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip, that is, to reduce the dose amount during ion implantation, and it becomes possible to suppress wafer warping.

[0071] As described above, in this embodiment, by configuring the p-type deep layer 30 in a line shape, the total value TV of the occupancy rates of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip is made 40% or less. Thereby, it becomes possible to suppress wafer warping while forming the p-type deep layer 30 by ion implantation.

[0072] In addition, in this embodiment, the following effects can also be achieved.

[0073] (1) As described above, the widths of the p-type deep layer 5 and the p-type deep layer 30 are set to 0.4 to 1.0 μm, and the intervals DA1 between the p-type deep layers 5, the interval DA2 of the linear portion 31, and the interval DA4 of the frame-shaped portion 32 are set to 0.6 to 1.5 μm. Therefore, an increase in the feedback capacitance Crss can be suppressed. In addition, it is possible to suppress the rise of equipotential lines between the p-type deep layer 5 and the p-type deep layer 30, suppress the application of a high electric field to the bottom of the gate trench 6, and ensure the breakdown voltage of the SiC semiconductor device. Further, by setting the widths of the p-type deep layer 5 and the p-type deep layer 30 and the intervals DA1, DA2, and DA4 in this way, the occupied area of the p-type deep layer 5 and the p-type deep layer 30 in the chip can be reduced, and the dose amount during ion implantation can be further reduced. Therefore, it is possible to further reduce the wafer warp.

[0074] In this case, it is preferable that the intervals DA1 to DA4 are set to be equal to or greater than the widths of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21. By doing so, the ratio of the occupied area of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip, where the total value TV is 40% or less, can be achieved without degrading functions such as the breakdown voltage.

[0075] (2) Also, when the sizes of the respective intervals are such that interval DA3out > interval DA1 > interval DA2 > interval DA3in and interval DA4out, a breakdown can be caused throughout the cell region RC. Thereby, even if a high voltage due to a load surge or the like is applied to the SiC semiconductor device, element breakdown can be prevented.

[0076] (3) Further, in this embodiment, the p-type deep layer 5 in the cell region RC is provided with an intersection portion 5b, and is connected to the linear portion 31 in the p-type deep layer 30 of the linear portion 5a and the connecting portion RJ. Also, the portion located on the innermost peripheral side of the frame-shaped portion 32 is connected to the linear portion 31.

[0077] By adopting such a structure, in the top view shown in FIG. 1, the gap between the p-type deep layer 5 and the p-type deep layer 30, that is, the area of the portion where the p-type deep layer 5 and the p-type deep layer 30 are not arranged can be reduced. Therefore, it becomes possible to further suppress the rise of the equipotential line, and it becomes possible to ensure a high breakdown voltage.

[0078] Note that instead of forming the p-type deep layer 5 and the p-type deep layer 30 by an ion implantation layer, it is also conceivable to form trenches on the surface of the n - type layer 2 and embed the trenches with a p-type layer. However, in addition to the difficulty of embedding the trenches with a p-type layer itself, dents will occur in the p-type layer at the positions where the linear portions intersect or are connected. On the other hand, when the p-type deep layer 5 and the p-type deep layer 30 are formed by an ion implantation layer, no dents will occur in the p-type layer even at the positions where the linear portions intersect or are connected. Therefore, the flatness of the wafer surface can be ensured.

[0079] Subsequently, a method for manufacturing the SiC semiconductor device according to the present embodiment will be described with reference to FIGS. 8A to 8H.

[0080] [Step shown in FIG. 8A] First, as a semiconductor substrate, a semiconductor substrate obtained by epitaxially growing an n + type layer 2 made of SiC on the main surface of the n - type substrate 1 is prepared. At this time, the semiconductor substrate may be prepared by epitaxially growing the n + type layer 2 on the main surface of the n - type substrate 1, or a so-called epi-substrate in which the n + type layer 2 has been epitaxially grown on the main surface of the n - type substrate 1 in advance may be prepared as the semiconductor substrate.

[0081] [Step shown in FIG. 8B] Next, the n -Place a mask (not shown) on the p-type layer 2, and open the mask in the regions where the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are to be formed. Then, ion-implant p-type impurities using the mask. At this time, adjust the range of the ion implantation so that the p-type impurities are implanted to a position at a predetermined depth from the surface of the n - type layer 2. Thereby, the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are formed. Then, remove the mask.

[0082] Here, the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are formed at once, but they may be formed in multiple portions. In that case, for example, the p-type deep layer 5 and the p-type deep layer 30 may be formed separately into upper and lower portions, and the lower portion may have a different width, such as being wider than the upper portion.

[0083] [Process shown in FIG. 8C] Epitaxially grow the p-type base region 3 and the n - type layer 2, including over the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21, and then sequentially grow the n + type source region 4.

[0084] [Process shown in FIG. 8D] n + After placing a mask (not shown) on the n-type source region 4, open the regions of the mask where the p-type contact region 3a and the p-type hole extraction layer 3b are to be formed. Then, form the p-type contact region 3a and the p-type hole extraction layer 3b by ion-implanting p-type impurities using the mask. Then, remove the mask.

[0085] Here, the n + type source region 4 is epitaxially grown, and the p-type contact region 3a and the p-type hole extraction layer 3b are formed by ion implantation, but it is not limited to this. For example, the n +The n-type source region 4, the p-type contact region 3a, and the p-type hole extraction layer 3b may all be formed by ion implantation into the p-type base region 3. Further, epitaxial growth is performed so that the impurity concentration in the surface layer portion of the p-type base region 3 becomes high to form the p-type contact region 3a and the p-type hole extraction layer 3b, and n-type impurities are ion-implanted into the p-type base region 3 to form the n + type source region 4.

[0086] 〔Steps shown in FIG. 8E〕 n + After forming a mask (not shown) on the n-type source region 4, the p-type base region 3, etc., the planned formation regions of the gate trench 6 and the recess 20 in the mask are opened. Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using the mask to simultaneously form the gate trench 6 and the recess 20 having a depth deeper than the upper surface of the n - type layer 2.

[0087] Here, the gate trench 6 and the recess 20 are formed simultaneously, but they can also be formed separately. In that case, since the gate trench 6 and the recess 20 can have different depths, it is also possible to design each of them to an optimal depth.

[0088] 〔Steps shown in FIG. 8F〕 After removing the mask, for example, by depositing an oxide film, the gate insulating film 7 is formed, and the inner wall surface of the gate trench 6 and the surface of the n + type source region 4 are covered by the gate insulating film 7. Then, after depositing Poly-Si doped with p-type impurities or n-type impurities and etching it back, the gate electrode 8 is formed by leaving Poly-Si in at least the gate trench 6. Thereby, a trench gate structure is configured.

[0089] 〔Steps shown in FIG. 8G〕 A interlayer insulating film 10 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 8 and the gate insulating film 7. Then, after forming a mask (not shown) on the surface of the interlayer insulating film 10, the portion of the mask located between each gate electrode 8, that is, the portion corresponding to the p-type contact region 3a and its vicinity are opened. At the same time, the portion of the mask corresponding to the p-type hole extraction layer 3b is also opened. After that, by patterning the interlayer insulating film 10 using the mask, contact holes for exposing the p-type contact region 3a and the n + type source region 4 and contact holes for exposing the p-type hole extraction layer 3b are formed.

[0090] 〔Step shown in FIG. 8H〕 An electrode material composed of, for example, a laminated structure of a plurality of metals is formed on the surface of the interlayer insulating film 10. Then, by patterning the electrode material, a source electrode 9 and a gate wiring (not shown) are formed.

[0091] Although the subsequent steps are not shown, by performing steps such as forming a drain electrode 11 on the back side of the n + type substrate 1, the SiC semiconductor device according to the present embodiment is completed.

[0092] As described above, the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are formed by ion implantation. However, not only the p-type deep layer 5 and the p-type guard ring 21 but also the p-type deep layer 30 are configured in a line shape. And by configuring the p-type deep layer 30 in a line shape, the total value TV of the occupancy rates of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip is made 40% or less. Thereby, it becomes possible to suppress wafer warpage while forming the p-type deep layer 30 by ion implantation.

[0093] (Modification of the First Embodiment) The layout of the p-type deep layer 5 and the p-type deep layer 30 may be changed with respect to the first embodiment.

[0094] For example, as shown in FIG. 9, the p-type deep layer 5 may be composed of only a stripe-shaped portion formed by a linear portion 5a. Also, as shown in FIG. 10, the inner portion of the frame-shaped portion 32 of the p-type deep layer 30 may be a lattice-shaped portion 33 formed by the intersection of stripes extending in two directions. Specifically, a lattice-shaped portion 33 can be formed with a structure in which one stripe is parallel to the linear portion 5a in the p-type deep layer 5 and the other stripe is orthogonal to the linear portion 5a. Further, as shown in FIG. 11, the inner portion of the frame-shaped portion 32 of the p-type deep layer 30 may be a mesh-shaped portion 34 in which stripes extending in different two directions intersect each other and are inclined with respect to the linear portion 5a. Furthermore, as shown in FIG. 12, the inner portion of the frame-shaped portion 32 of the p-type deep layer 30 may be a dot-shaped portion 35 in which a plurality of dots are arranged linearly with the same direction as the linear portion 5a in the p-type deep layer 5 as the longitudinal direction. Here, the case where oval dots are arranged in a dot line shape with the longitudinal direction being the same direction as the direction in which the dot-shaped portion 35 is linearly arranged is illustrated, but each dot may be formed in other shapes such as a circular shape or a square shape. In the case of the structures shown in FIGS. 10 to 12, the lattice-shaped portion 33, the mesh-shaped portion 34, and the dot-shaped portion 35 each constitute a part of the second conductivity type layer.

[0095] Also in these cases, it is preferable to set the interval DA2 of the p-type deep layer 30 at the connecting portion RJ so that the relationship of interval DA3out > interval DA1 > interval DA2 > interval DA3in, DA4out holds. In the case of the structures of FIGS. 10 and 11, the interval between each stripe extending in two directions that constitutes the lattice-shaped portion 33 and the mesh-shaped portion 34 corresponds to the interval DA2. In the case of the structure of FIG. 12, the interval between adjacent dot lines and the interval between adjacent dots on the same dot line correspond to the interval DA2.

[0096] (Second Embodiment) A second embodiment will be described. This embodiment is different from the first embodiment in that the breakdown voltage structure using the p-type layer is changed, and other aspects are the same as those of the first embodiment, so the differences from the first embodiment will be mainly described.

[0097] 13, in this embodiment, in the cell region RC, an n-type first current spreading layer 50 and a p-type deep layer 51 are provided below the p-type deep layer 5, and a second current spreading layer 60 is provided between the p-type deep layers 5. The p-type deep layer 51 corresponds to the first deep layer and constitutes at least a part of the second conductive type layer. In addition, the p-type deep layer 5 disposed on the p-type deep layer 51 corresponds to the second deep layer.

[0098] Specifically, n - A first current spreading layer 50 and a p-type deep layer 51 are formed on the n-type layer 2. The first current spreading layer 50 has a depth of 0.3 to 1.5 μm. The p-type deep layer 51 is shallower than the first current spreading layer 50, but has a depth of approximately the same 0.3 to 1.4 μm. In other words, the p-type deep layer 51 is formed so that its bottom is located within the first current spreading layer 50, and - The first current spreading layer 50 is formed at a depth such that it is located between the first and second layers 2. Note that, although a part of the first current spreading layer 50 is arranged at the bottom of the p-type deep layer 51 here, the first current spreading layer 50 and the p-type deep layer 51 may be at the same depth.

[0099] The first current spreading layer 50 and the p-type deep layer 51 are each extended in one direction so as to form a stripe shape in which a plurality of lines are alternately arranged, and are arranged at equal intervals along the perpendicular direction. In the present embodiment, the stripe-shaped portion of the first current spreading layer 50 and the p-type deep layer 51 are extended in a direction intersecting the longitudinal direction of the trench gate structure.

[0100] The spacing between the lines of the striped portion of the first current spreading layer 50 is, for example, 0.6 to 1.5 μm, and the n-type impurity concentration is, for example, 5.0×1016 ~2.0×10 18 / cm 3 is set. The width of each p-type deep layer 51 is, for example, 0.4 to 1.0 μm, and the p-type impurity concentration is, for example, 3.0×10 17 ~1.0×10 18 / cm 3 is set. Regarding the interval DB1 between each p-type deep layer 51, that is, the width of each line of the striped portion in the first current dispersion layer 50, it is made different from the interval DB2 of the linear portion 71 of the p-type deep layer 70 provided in the joint portion RJ described later, but it may be the same. Here, the interval DB1 is set to be equal to or greater than the interval DB2.

[0101] Regarding the first current dispersion layer 50, a concave portion is formed in the surface layer portion of the n - type layer 2, and after epitaxially growing the n-type layer, it is flattened, or it is formed by ion-implanting n-type impurities into the surface layer portion of the n - type layer 2. When the first current dispersion layer 50 is formed by ion implantation, since n-type impurities are implanted into the n - type layer 2, the dose amount becomes sufficiently smaller than when ion-implanting p-type impurities for forming the p-type deep layer 5 or the like. Therefore, wafer warping hardly occurs. Also, regarding the p-type deep layer 51, it is formed by ion-implanting p-type impurities. Therefore, regarding the p-type deep layer 51, the width and the dose amount are set in consideration of wafer warping. Also, regarding the p-type deep layer 51, the interval is set to be 0.6 μm or more so that the remaining width of the photomask during ion implantation does not become too narrow.

[0102] The second current dispersion layer 60 is formed on the first current dispersion layer 50 and the p-type deep layer 51 together with the p-type deep layer 5. In the first embodiment, the space between the p-type deep layers 5 is the n - type layer 2, but in this embodiment, it is the second current dispersion layer 60. The second current dispersion layer 60 may have the same n-type impurity concentration as the n - type layer 2, but in order to have a lower resistance and enable the current to be dispersed over a wider range, the n -It is preferably higher than the type layer 2. Here, the n-type impurity concentration of the second current dispersion layer 60 is, for example, 1.0×10 16 ~5.0×10 17 / cm 3 and is set to such. Also, the thickness of the second current dispersion layer 60 is, for example, set to 0.5 to 2 μm. By ion-implanting p-type impurities into this second current dispersion layer 60, a p-type deep layer 5 is formed. And the p-type deep layer 5 is formed at a depth equal to or greater than the depth of the second current dispersion layer 60 and is in a state connected to the p-type deep layer 51.

[0103] In addition, in the present embodiment, in addition to the n - type layer 2, the first current dispersion layer 50 and the second current dispersion layer 60 form a part of the drift layer. The second current dispersion layer 60 is formed at a position corresponding to the trench gate structure and extends in a direction orthogonal to the first current dispersion layer 50, that is, in the same direction as the longitudinal direction of the trench gate structure.

[0104] In the guard ring portion RG, the second current dispersion layer 60 formed in the cell region RC remains on the surface of the n - type layer 2. Also, a recess 20 is formed so as to penetrate the p-type base region 3 and reach the second current dispersion layer 60. And a p-type guard ring 21 is formed on the surface layer portion of the n - type layer 2. Here, the p-type guard ring 21 is arranged away from the bottom surface of the recess 20, but it may also be formed in contact with the bottom surface of the recess 20.

[0105] The p-type guard ring 21 is formed so as to surround the cell region RC and the connection part RJ, and a plurality of them are arranged concentrically and have the layout of the first embodiment. The p-type guard ring 21 has the same width and impurity concentration as the above-described p-type deep layer 51. Regarding the interval DB3 between the p-type guard rings 21, it may be equally spaced, but in order to relieve the electric field concentration on the cell region RC side and make the equipotential lines go more toward the outer peripheral side, the interval DB3 of the p-type guard rings 21 is made narrower on the cell region RC side and larger toward the outer peripheral side. The interval DB3in of the portion of the interval DB3 of the p-type guard rings 21 that is located within a predetermined range from the boundary position of the mesa portion RM is made narrower than the interval DB1 between the p-type deep layers 51 in the cell region RC and the interval DB2 of the linear portion 71 of the p-type deep layer 70 in the connection part RJ. Also, the widest portion of the interval DB3, that is, the interval DB3out between the outermost p-type guard ring 21 and the one adjacent to it is made wider than the interval DB1 and the interval DB2.

[0106] Also, in the connection part RJ, - a p-type deep layer 5 and a second current dispersion layer 60 are formed on the surface of the n-type layer 2, and further, a p-type base region 3 is also formed thereon. Also, - a p-type deep layer 70 is formed in the surface layer portion of the n-type layer 2.

[0107] Although only a cross-section is shown in Fig. 13, the p-type deep layer 70 is configured to have a linear portion 71 and a frame-shaped portion 72. The linear portion 71 of the p-type deep layer 70 constitutes a part of the second conductivity type layer, and the frame-shaped portion 72 constitutes a part of the second conductivity type ring. When viewing the SiC semiconductor device from above, the linear portion 71 is arranged in parallel with the p-type deep layer 51 and is provided with one or more. When a plurality of linear portions 71 are provided, the layout is such that the interval DB2 between the respective linear portions 71 is equal to or less than the interval DB1 of the p-type deep layer 51. Also, when viewing the SiC semiconductor device from above, the frame-shaped portion 72 is arranged so as to surround the cell region RC and the linear portion 71, and is configured in a rectangular frame shape with rounded corners. The frame-shaped portion 72 is arranged concentrically with the p-type guard ring 21, and a plurality of them are provided in this embodiment.

[0108] The width of the p-type deep layer 70 is the same as that of the p-type deep layer 51. The interval DB2 between the linear portions 71 may be the same as the interval DB1 of the linear portion 5a of the p-type deep layer 5, but here it is made narrower than the interval DB1. Also, the intervals DB4 of the frame-shaped portion 72 may all be the same width, or may be different. The interval DB4 of the frame-shaped portion 72 is preferably equal to or less than the interval DB1 of the p-type deep layer 51 in the cell region RC. In particular, it is more preferable that the interval DB4out of the portion of the interval DB4 of the frame-shaped portion 72 located within a predetermined range from the boundary position of the mesa portion RM is made narrower than the interval DB2 between the linear portions 71 in the p-type deep layer 70.

[0109] Also, regarding the interval DB3in of the p-type guard ring 21 and the interval DB4out of the frame-shaped portion 72 located within a predetermined range from the boundary position of the mesa portion RM, they are made narrower than the interval DB2 between the linear portions 71 in the p-type deep layer 70. Thereby, similar to the first embodiment, it becomes possible to cope with mask misalignment when forming the recess 20 for forming the mesa portion RM.

[0110] Here, the p-type deep layer 70 is provided with the linear portion 71 and the frame portion 72, but it may be configured with only one of them. The number of linear portions 71 and frame portions 72 can also be set arbitrarily. Furthermore, the inner portion of the frame portion 72 may be laid out in a manner similar to the lattice portion 33, mesh portion 34, or dot-shaped portion 35 shown in the modified example of the first embodiment.

[0111] The SiC semiconductor device of this embodiment is configured as described above. In the SiC semiconductor device configured as described above, the proportion of the p-type layers deeply implanted by ion implantation, that is, the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21, to the total area of ​​the chip constituting the SiC semiconductor device is set to 40% or less. This makes it possible to reduce the dose during ion implantation, and suppress wafer warpage.

[0112] The width of the p-type deep layer 5 is set to 0.4 to 1.0 μm, similarly to the first embodiment. In this manner, by limiting the implantation range of the p-type deep layer 5 disposed above the p-type deep layer 51, wafer warpage can be further suppressed.

[0113] Next, a method for manufacturing the SiC semiconductor device of this embodiment will be described. The method for manufacturing the SiC semiconductor device of this embodiment is generally similar to that of the first embodiment, except for the steps of forming the first current spreading layer 50, the p-type deep layer 51, the p-type deep layer 70, the p-type guard ring 21, the second current spreading layer 60, and the p-type deep layer 5. Therefore, the steps other than these manufacturing steps will be described with reference to the manufacturing steps described in the first embodiment.

[0114] First, similarly to the process shown in FIG. 8A described in the first embodiment, a semiconductor substrate having n + A n-type substrate 1 is formed on the main surface of the n-type substrate 1. - A mold layer 2 is prepared by epitaxial growth. Then, the steps shown in Figs. 14A to 14C are carried out.

[0115] [Process shown in FIG. 14A] n - After placing a mask (not shown) with an opening at the planned formation area of the first current dispersion layer 50 on the n-type layer 2, the first current dispersion layer 50 is formed by ion-implanting n-type impurities. Note that the first current dispersion layer 50 may be formed by selective epitaxial growth instead of ion implantation. For example, n - After partially etching the n-type layer 2 to form a trench at the planned formation position of the first current dispersion layer 50, the n-type layer may be epitaxially grown and then planarized to form the first current dispersion layer 50.

[0116] [Process shown in FIG. 14B] Subsequently, after placing a mask (not shown) with openings at the planned formation positions of the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21 on the n-type layer 2 including the first current dispersion layer 50, p-type impurities are ion-implanted. Thereby, the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21 are formed. -

[0117] [Process shown in FIG. 14C] Furthermore, the second current dispersion layer 60 is epitaxially grown on the n-type layer 2 including the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21. Then, after placing a mask (not shown) with an opening at the planned formation position of the p-type deep layer 5, p-type impurities are ion-implanted. Thereby, the p-type deep layer 5 that penetrates the second current dispersion layer 60 and is connected to the p-type deep layer 51 and the p-type deep layer 70 is formed. -

[0118] Although the subsequent processes are not shown, the SiC semiconductor device of this embodiment can be manufactured by performing the same manufacturing processes as those from FIG. 8D onward described in the first embodiment.

[0119] Thus, in the case of this embodiment, in the cell region RC, the p-type deep layer 51, in the connection part RJ, the p-type deep layer 70, and in the guard ring part RG, the p-type guard ring 21 are respectively n - ​​It is provided in the surface layer portion of the p-type layer 2, and these are simultaneously formed by ion implantation. Then, the ratio of the p-type layer, that is, the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21 that are deeply implanted by ion implantation with respect to the total area of the chip constituting the SiC semiconductor device is set to 40% or less. As a result, it becomes possible to reduce the dose amount during ion implantation, and it becomes possible to suppress wafer warpage.

[0120] (Third Embodiment) The third embodiment will be described. This embodiment is provided with a junction barrier schottky diode (hereinafter referred to as JBS) instead of a vertical MOSFET as a power element with respect to the first embodiment. Since the other parts are the same as those of the first embodiment, only the parts different from the first embodiment will be described.

[0121] As shown in FIGS. 15 and 16, an n- + type drift layer 102 is formed on the n- - type substrate 101. And in the cell region RC, a p-type deep layer 103 that is striped with respect to the n- - type drift layer 102 is formed, and a p-type guard ring 104 is formed in the guard ring portion RG that surrounds the periphery thereof. Also, a p-type connecting layer 105 is formed at the connecting portion RJ between the cell region RC and the guard ring portion RG.

[0122] The p-type deep layer 103 constitutes at least a part of the second conductivity type layer, and the n- -A plurality of them are arranged at equal intervals in the p-type drift layer 102 to form a stripe shape. The p-type guard ring 104 constitutes at least a part of the second conductivity type ring, and a plurality of square-shaped ones with rounded corners are arranged concentrically. The p-type connecting layer 105 has a configuration in which a plurality of frame-shaped ones surrounding the periphery of the p-type deep layer 103 formed in the cell region are arranged side by side. Here, the p-type connecting layer 105 is entirely composed of a frame-shaped portion, but a linear portion may be provided inside the frame-shaped portion. The linear portion of the p-type connecting layer 105 constitutes a part of the second conductivity type layer, and the frame-shaped portion constitutes a part of the second conductivity type ring. These p-type deep layer 103, p-type guard ring 104, and p-type connecting layer 105 are formed by ion implanting p-type impurities into the n - type drift layer 102.

[0123] Also, in the cell region RC and the connecting portion RJ, a Schottky electrode 106 corresponding to the first electrode in contact with the surfaces of the n - type drift layer 102, p-type deep layer 103, and p-type connecting layer 105 is formed. That is, in the case of this embodiment, a plurality of p-type rings made of a linear frame-shaped p-type layer surrounding the cell region RC are provided, and the Schottky electrode 106 is arranged so as to cover a part of the inner peripheral side thereof. Among these plurality of p-type rings, the one in contact with the Schottky electrode 106 is called the p-type connecting layer 105. Also, among the plurality of p-type layers, the one not in contact with the Schottky electrode 106 and located outside it and where the n - type drift layer 102 is exposed is called the p-type guard ring 104. And the portion where the Schottky electrode 106 is formed becomes the Schottky electrode portion RS composed of the cell region RC and the connecting portion RJ.

[0124] Furthermore, on the back surface side of the n + type substrate 101, an ohmic electrode 107 corresponding to the second electrode is formed. In this way, the SiC semiconductor device of this embodiment is configured.

[0125] In such a configuration, the p-type deep layer 103, the p-type guard ring 104, and the p-type connecting layer 105 are, for example, set to have a width of 0.4 to 1 μm. These may be formed with the same width or different widths. Also, these are, for example, set to have a depth of about 2 μm. These depths may be different, but here they are set to the same depth. Further, the intervals DC1 to DC4 between these are, for example, set to 0.6 to 1.5 μm. These intervals DC1 to DC4 may be the same, but here they are made different. Specifically, the interval DC2 of the p-type connecting layer 105 at the connection part RJ is made narrower than the interval DC1 of the p-type deep layer 103 in the cell region RC. In the case of this embodiment, the p-type connecting layer 105 is composed only of the frame-shaped part. If the interval between the parts formed as the frame-shaped part in the interval DC2 is set as the interval DC4, the interval DC4out of the part located in a predetermined range from the boundary position of the Schottky electrode part RS among the interval DC4 is made the narrowest. Also, regarding the interval DC3 of the p-type guard ring 104, it may be equally spaced, but in order to relieve the electric field concentration on the cell region RC side and make the equipotential lines go more toward the outer peripheral side, it is made narrower on the cell region RC side and larger toward the outer peripheral side. The interval DC3in of the part of the interval DC3 of the p-type guard ring 104 located in a predetermined range from the boundary position of the Schottky electrode part RS is made narrower than the interval DC1 of the p-type deep layer 103 in the cell region RC and is made to be about the same as the interval DC4out. Also, the widest part of the interval DC3, that is, the interval DC3out between the outermost p-type guard ring 104 and the one inside it is made wider than the interval DC1 and the interval DC2.

[0126] Thus, also in the SiC semiconductor device including the JBS as a power device, the widths and intervals of the p-type connecting layer 105 and the p-type guard ring 104 are made the same as those in the first embodiment.

[0127] That is, the interval DC2 of the p-type connecting layer 105 is basically set to be equal to or less than the interval DC1 of the p-type deep layer 103, and the interval DC2 is further reduced on the outer edge side of the Schottky electrode portion RS. Also, the interval DC3 between the p-type guard rings 104 gradually increases toward the outer peripheral side. And on the outermost peripheral side, the interval DC3out between the p-type guard rings 104 is made larger than the interval DC1 between the p-type deep layers 103. Thereby, the ratio occupied by the p-type layer that is deeply implanted by ion implantation with respect to the entire area of the chip constituting the SiC semiconductor device, that is, the p-type deep layer 103, the p-type connecting layer 105, and the p-type guard rings 104, is made 40% or less.

[0128] The SiC semiconductor device having such a structure is formed, for example, as follows. First, an n + -type drift layer 102 is epitaxially grown on the n - -type substrate 101. After that, a mask (not shown) is disposed on the surface of the n - -type drift layer 102. Then, p-type impurities are ion-implanted from above the mask to form the p-type deep layer 103, the p-type guard rings 104, and the p-type connecting layer 105. After that, an electrode material is deposited on the n - -type drift layer 102 including the p-type deep layer 103, the p-type guard rings 104, and the p-type connecting layer 105, and then this is patterned to form the Schottky electrode 106. Finally, an ohmic electrode 107 is formed on the back surface side of the n + -type substrate 101, and thus the SiC semiconductor device of the present embodiment is completed.

[0129] In the manufacture of such a SiC semiconductor device, the p-type deep layer 103, the p-type guard rings 104, and the p-type connecting layer 105 are formed by ion implantation. However, since the p-type deep layer 103, the p-type guard rings 104, and the p-type connecting layer 105 are configured as described above, the SiC semiconductor device of the present embodiment can also obtain the same effects as those of the first embodiment.

[0130] (Other embodiments) The present invention is not limited to the above-described embodiments, and can be appropriately modified within the scope described in the claims.

[0131] For example, in each of the above embodiments, although a p-type impurity is ion-implanted from the surface of the n - -type layer 2 to form a p-type deep layer 5 or the like, the p-type impurity may also be ion-implanted from the surface of the p-type base region 3 or the surface of the n + -type source region 4 or the like. However, in that case, ion implantation with a higher acceleration voltage will be performed, and the influence of wafer warpage will increase. Therefore, considering the influence of wafer warpage, the allowable range of the dose amount and width of the p-type deep layer 5 or the like can be narrower than the case where a p-type impurity is ion-implanted from the surface of the n - -type layer 2 to form a p-type deep layer 5 or the like.

[0132] Also, in each of the above embodiments, MOSFET100 and JBS are cited as examples of semiconductor elements provided in the cell region RC of the SiC semiconductor device. However, even if other semiconductor elements are formed, as long as it has a cell region RC and an outer peripheral region RO, and a p-type deep layer is formed at the joint RJ of the outer peripheral region RO, it is acceptable. Examples of such semiconductor elements include IGBTs and the like. Also, in each of the above embodiments, an n-channel type MOSFET100 with the first conductivity type being n-type and the second conductivity type being p-type was cited as an example for explanation, but it may also be a p-channel type MOSFET100 with the conductivity types of each component inverted. Also, it is not limited to an element with a trench gate structure, and a planar type element may also be acceptable. Note that for an IGBT, it only requires changing the conductivity type of the n + -type substrate 1 from n-type to p-type, and the other structures and manufacturing methods are the same as those in each of the above embodiments.

[0133] Also, in the first embodiment, the widths of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are the same, but they may be different. In the second embodiment, the widths of the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21 are the same, but they may be different. In the third embodiment, the widths of the p-type deep layer 103, the p-type guard ring 104, and the p-type connecting layer 105 are the same, but they may be different. Further, in the first to third embodiments, the widths of the respective p-type guard rings 21 and p-type guard rings 104 are the same, but the widths of the respective p-type guard rings 21 may have a structure that becomes wider toward the outer periphery.

[0134] Also, in each of the above embodiments, the case where SiC is used as the semiconductor material has been described, but the present invention can also be applied to semiconductor devices using other semiconductor materials such as Si.

[0135] Note that when indicating the crystal orientation, a bar (-) should originally be attached above the desired number. However, due to the expression limitations based on the electronic application, in this specification, a bar is attached in front of the desired number.

Explanation of Reference Numerals

[0136] 1 n + -type substrate 2 n - -type layer 3 p-type base region 4 n + -type source region 5, 30 p-type deep layer 8 gate electrode 9 source electrode 10 interlayer insulating film 21 p-type guard ring

Claims

1. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connection portion (RJ) located between the guard ring portion and the cell region, a substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, in the cell region, a second conductivity type layer (5, 5a, 51, 103) formed in the drift layer and including a portion formed in a stripe shape with one direction as the longitudinal direction, a first electrode (9, 106) electrically connected to the second conductivity type layer, a second electrode (11, 107) formed on the back surface side of the substrate, and having, a vertical semiconductor element for flowing a current between the first electrode and the second electrode, also in the connection portion, the drift layer is provided with a second conductivity type layer (31, 33 to 35, 71) formed in a line shape, in the guard ring portion or the guard ring portion and the connection portion, a second conductivity type ring (21, 32, 72, 104, 105) formed in the drift layer and having a plurality of line-shaped frame shapes surrounding the cell region, and at least a part located on the outer peripheral side constituting a guard ring (21, 104), the second conductivity type layer and the second conductivity type ring are constituted by an ion implantation layer, and the ratio occupied by the second conductivity type layer and the second conductivity type ring with respect to the total area of the chip is 40% or less, the second conductivity type layer provided in the connection portion includes a lattice-shaped portion (33) having a structure in which stripes extending in a direction along the longitudinal direction of the second conductivity type layer provided in the cell region and in a direction intersecting the longitudinal direction are orthogonal, a semiconductor device.

2. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connection portion (RJ) located between the guard ring portion and the cell region, A substrate (1, 101) of the first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of the first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, In the cell region, A second conductivity type layer (5, 5a, 51, 103) formed in the drift layer and including a portion formed in a stripe shape with one direction as the longitudinal direction, A first electrode (9, 106) electrically connected to the second conductivity type layer, A second electrode (11, 107) formed on the back surface side of the substrate, A vertical semiconductor element for flowing a current between the first electrode and the second electrode is provided, Also in the connecting portion, The drift layer is provided with a second conductivity type layer (31, 33 - 35, 71) formed in a line shape, In the guard ring portion or the guard ring portion and the connecting portion, A second conductivity type ring (21, 32, 72, 104, 105) formed in the drift layer and having a plurality of line-shaped frame shapes surrounding the cell region, and at least a part located on the outer peripheral side constituting a guard ring (21, 104) is provided, The second conductivity type layer and the second conductivity type ring are constituted by an ion implantation layer, and the ratio occupied by the second conductivity type layer and the second conductivity type ring with respect to the total area of the chip is 40% or less, The second conductivity type layer provided in the connecting portion includes a mesh-shaped portion (34) in which stripes extending in different two directions intersect each other and are inclined with respect to the second conductivity type layer provided in the cell region, A semiconductor device.

3. The second conductivity type ring is disposed in the guard ring portion and the connecting portion, A mesa portion (RM) in which the cell region and the connecting portion protrude more than the guard ring portion is formed, The distance (DA3, DB3) between the guard rings is increased as going from the inner peripheral side to the outer peripheral side, Let the distance between the second conductivity type layers disposed in the cell region be a first distance (DA1, DB1), the distance between the second conductivity type layers in the connecting portion be a second distance (DA2, DB2), the distance between the guard rings be a third distance (DA3, DB3), and the distance between the second conductivity type rings in the connecting portion be a fourth distance (DA4, DB4), The relationship is such that the intervals (DA3out, DB3out) of the widest portions located on the outermost periphery among the third intervals > the first interval > the second interval > the intervals (DA3in, DB3in, DA4out, DB4out) of the portions located within a predetermined range from the boundary position of the mesa portion among the third interval and the fourth interval, for the semiconductor device according to claim 1 or 2.

4. A semiconductor device having a cell region (RC) in which semiconductor elements (100) are formed within a chip (Ch), a guard ring portion (RG) surrounding the outer periphery of the cell region, and an outer peripheral region (RO) including a connecting portion (RJ) located between the guard ring portion and the cell region, a substrate (1, 101) of the first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of the first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, In the cell region, a second conductivity type layer (5, 5a, 51, 103) formed in the drift layer and including portions formed in a stripe shape with one direction as the longitudinal direction, a first electrode (9, 106) electrically connected to the second conductivity type layer, a second electrode (11, 107) formed on the back surface side of the substrate, a vertical semiconductor element for flowing a current between the first electrode and the second electrode is provided, Also in the connecting portion, the drift layer is provided with a second conductivity type layer (31, 33 - 35, 71) formed in a line shape, In the guard ring portion or the guard ring portion and the connecting portion, a second conductivity type ring (21, 32, 72, 104, 105) is provided, which is formed in the drift layer and has a plurality of line-shaped frame shapes surrounding the cell region, and at least a part located on the outer peripheral side constitutes a guard ring (21, 104), the second conductivity type layer and the second conductivity type ring are constituted by an ion implantation layer, and the proportion occupied by the second conductivity type layer and the second conductivity type ring with respect to the total area of the chip is 40% or less, the second conductivity type layer provided in the connecting portion includes a linear portion (31) having the same longitudinal direction as the longitudinal direction of the second conductivity type layer provided in the cell region, the second conductivity type ring is disposed in the guard ring portion and the connecting portion, a mesa portion (RM) is formed in which the cell region and the connecting portion protrude more than the guard ring portion, The guard rings are arranged such that the distance (DA3, DB3) between the guard rings increases from the inner peripheral side to the outer peripheral side. Let the distance between the second conductivity type layers arranged in the cell region be a first distance (DA1, DB1), the distance between the second conductivity type layers in the connecting portion be a second distance (DA2, DB2), the distance between the guard rings be a third distance (DA3, DB3), and the distance between the second conductivity type rings in the connecting portion be a fourth distance (DA4, DB4). A semiconductor device, wherein the distance (DA3out, DB3out) of the widest portion located at the outermost periphery among the third distances > the first distance > the second distance > the distances (DA3in, DB3in, DA4out, DB4out) of the portions located within a predetermined range from the boundary position of the mesa portion among the third distance and the fourth distance.

5. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed in a chip (Ch), a guard ring portion (RG) surrounding the outer periphery of the cell region, and an outer peripheral region (RO) including a connecting portion (RJ) located between the guard ring portion and the cell region. A first or second conductivity type substrate (1, 101) having a front surface and a back surface, and a first conductivity type drift layer (2, 50, 60, 102) formed on the front surface side of the substrate and having a lower impurity concentration than the substrate. In the cell region, A second conductivity type layer (5, 5a, 51, 103) formed in the drift layer and including a portion formed in a stripe shape with one direction as the longitudinal direction. A first electrode (9, 106) electrically connected to the second conductivity type layer. A second electrode (11, 107) formed on the back surface side of the substrate. The semiconductor device is provided with a vertical semiconductor element that allows a current to flow between the first electrode and the second electrode. In the connecting portion as well, The drift layer is provided with a second conductivity type layer (31, 33 - 35, 71) formed in a line shape. In the guard ring portion or the guard ring portion and the connecting portion, A second conductivity type ring (21, 32, 72, 104, 105) is provided, which is formed in the drift layer, has a plurality of line-shaped frame shapes surrounding the cell region, and at least a part located on the outer peripheral side constitutes a guard ring (21, 104). The second conductivity type layer and the second conductivity type ring are constituted by an ion implantation layer, and the ratio occupied by the second conductivity type layer and the second conductivity type ring with respect to the total area of the chip is 40% or less. The second conductivity type layer provided in the connecting portion includes a dot-shaped portion (35) having a dot line structure in which a plurality of dots are arranged linearly with the same longitudinal direction as the longitudinal direction of the second conductivity type layer provided in the cell region. The second conductivity type ring is disposed in the guard ring portion and the connecting portion. A mesa portion (RM) is formed in which the cell region and the connecting portion protrude more than the guard ring portion. In the guard ring, the distance (DA3, DB3) between the guard rings increases from the inner peripheral side to the outer peripheral side. Taking the distance between the second conductivity type layers disposed in the cell region as the first distance (DA1, DB1), the distance between the second conductivity type layers in the connecting portion as the second distance (DA2, DB2), the distance between the guard rings as the third distance (DA3, DB3), and the distance between the second conductivity type rings in the connecting portion as the fourth distance (DA4, DB4). A semiconductor device having a relationship of the distance (DA3out, DB3out) of the widest portion located at the outermost periphery among the third distances > the first distance > the second distance > the distances (DA3in, DB3in, DA4out, DB4out) in the portion located within a predetermined range from the boundary position of the mesa portion among the third distance and the fourth distance.

6. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor element is any one of a trench gate structure or a planar type MOSFET or IGBT.

7. The semiconductor element is a MOSFET (100) having a trench gate structure. The MOSFET is a second conductivity type base region (3) formed on the drift layer; a first conductivity type source region (4) formed on the base region and having a higher first conductivity type impurity concentration than the drift layer; a gate insulating film (7) covering the inner wall surface of the gate trench and a gate electrode (8) disposed on the gate insulating film in a gate trench (6) formed deeper from the surface of the source region than the base region, and the trench gate structure formed with one direction as the longitudinal direction. An interlayer insulating film (10) that covers the gate electrode and the gate insulating film and in which a contact hole is formed; A source electrode (9) corresponding to the first electrode that is electrically connected to the source region and the base region through the contact hole; A drain electrode (11) corresponding to the second electrode formed on the back surface side of the substrate, the semiconductor device according to any one of claims 1 to 5, comprising:

8. The drift layer includes: A low-concentration layer (2) having a lower impurity concentration than the substrate; A first current dispersion layer (50) of a first conductivity type formed on the surface layer portion of the low-concentration layer in the cell region; A second current dispersion layer (60) of a first conductivity type formed on the low-concentration layer including the first current dispersion layer and connected to the first current dispersion layer; In the first current dispersion layer, a first deep layer (51) that constitutes the second conductivity type layer in the cell region is formed with a longitudinal direction intersecting the longitudinal direction of the trench gate structure; In the second current dispersion layer, a second deep layer (5) of a second conductivity type is formed with a longitudinal direction in the same direction as the longitudinal direction of the trench gate structure, disposed on both sides of the trench gate structure, and connected to the first deep layer; The semiconductor device according to claim 7, wherein the second deep layer also has a width of 0.4 to 1.0 μm.

9. The second conductivity type ring is disposed in the guard ring portion and the connecting portion; The cell region and the connecting portion constitute a Schottky electrode portion (RS) in which a Schottky electrode (106) is disposed as the first electrode; The guard rings are spaced apart from each other (DC3) such that the distance between the guard rings increases from the inner peripheral side to the outer peripheral side; Let the distance between the second conductivity type layers disposed in the cell region be a first distance (DC1), the distance between the second conductivity type layers in the connecting portion be a second distance (DC2), the distance between the guard rings be a third distance (DC3), and the distance between the second conductivity type rings in the connecting portion be a fourth distance (DC2, DC4); The semiconductor device according to claim 1 or 2, wherein the distance (DC3out) of the widest portion located at the outermost periphery of the third distance > the first distance > the second distance > the distance (DC3in, DC4out) of the portion located within a predetermined range from the boundary position of the Schottky electrode portion among the third distance and the fourth distance.

10. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connecting portion (RJ) located between the guard ring portion and the cell region, a substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, in the cell region, a second conductivity type layer (5, 5a, 51, 103) formed in the drift layer and including a portion formed in a stripe shape with one direction as the longitudinal direction, a first electrode (9, 106) electrically connected to the second conductivity type layer, a second electrode (11, 107) formed on the back surface side of the substrate, and having, a vertical semiconductor element for flowing a current between the first electrode and the second electrode is provided, also in the connecting portion, the drift layer is provided with a second conductivity type layer (31, 33 to 35, 71) formed in a line shape, in the guard ring portion or the guard ring portion and the connecting portion, a second conductivity type ring (21, 32, 72, 104, 105) formed in the drift layer and having a plurality of line-shaped frame shapes surrounding the cell region, and at least a part located on the outer peripheral side constituting a guard ring (21, 104) is provided, the second conductivity type layer and the second conductivity type ring are constituted by an ion implantation layer, and the ratio occupied by the second conductivity type layer and the second conductivity type ring with respect to the total area of the chip is 40% or less, the second conductivity type layer provided in the connecting portion includes a linear portion (31) having the same longitudinal direction as the longitudinal direction of the second conductivity type layer provided in the cell region, the second conductivity type ring is disposed in the guard ring portion and the connecting portion, the cell region and the connecting portion constitute a Schottky electrode portion (RS) in which a Schottky electrode (106) is disposed as the first electrode, the guard rings are spaced apart from each other (DC3) such that the distance between the guard rings increases from the inner peripheral side to the outer peripheral side, The interval between the second conductivity type layers disposed in the cell region is defined as a first interval (DC1), the interval between the second conductivity type layers in the connecting portion is defined as a second interval (DC2), the interval of the guard ring is defined as a third interval (DC3), and the interval between the second conductivity type rings in the connecting portion is defined as a fourth interval (DC2, DC4). A semiconductor device, in which the interval (DC3out) of the widest portion located at the outermost periphery among the third intervals > the first interval > the second interval > the intervals (DC3in, DC4out) of the portions located in a predetermined range from the boundary position of the Schottky electrode portion among the third interval and the fourth interval.

11. A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed in a chip (Ch), a guard ring portion (RG) surrounding the outer periphery of the cell region, and an outer peripheral region (RO) including a connecting portion (RJ) located between the guard ring portion and the cell region. A substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate. In the cell region, A second conductivity type layer (5, 5a, 51, 103) formed in the drift layer and including a portion formed in a stripe shape with one direction as the longitudinal direction. A first electrode (9, 106) electrically connected to the second conductivity type layer. A second electrode (11, 107) formed on the back surface side of the substrate. A vertical semiconductor element for flowing a current between the first electrode and the second electrode is provided. Also in the connecting portion, The drift layer is provided with a second conductivity type layer (31, 33 to 35, 71) formed in a line shape. In the guard ring portion or the guard ring portion and the connecting portion, A second conductivity type ring (21, 32, 72, 104, 105) is provided, which is formed in the drift layer and has a plurality of line-shaped frame shapes surrounding the cell region, and at least a part located on the outer peripheral side constitutes a guard ring (21, 104). The second conductivity type layer and the second conductivity type ring are constituted by an ion implantation layer, and the ratio occupied by the second conductivity type layer and the second conductivity type ring with respect to the total area of the chip is 40% or less. The second conductivity type layer provided in the connecting portion includes a dot-shaped portion (35) having a dot line structure in which a plurality of dots are arranged linearly with the longitudinal direction being the same as the longitudinal direction of the second conductivity type layer provided in the cell region, The second conductivity type ring is disposed in the guard ring portion and the connecting portion, The cell region and the connecting portion constitute a Schottky electrode portion (RS) in which a Schottky electrode (106) is disposed as the first electrode, The guard rings are arranged such that the distance (DC3) between the guard rings increases from the inner peripheral side to the outer peripheral side, Let the distance between the second conductivity type layers disposed in the cell region be a first distance (DC1), the distance between the second conductivity type layers in the connecting portion be a second distance (DC2), the distance between the guard rings be a third distance (DC3), and the distance between the second conductivity type rings in the connecting portion be a fourth distance (DC2, DC4), A semiconductor device in which the distance (DC3out) of the widest portion located at the outermost periphery of the third distance > the first distance > the second distance > the distance (DC3in, DC4out) of the portion located within a predetermined range from the boundary position of the Schottky electrode portion among the third distance and the fourth distance.

12. The width of the second conductivity type layer and the second conductivity type ring is 0.4 to 1.0 μm, and the distance (DA1, DA2, DC1, DB1, DB2, DC2) between the second conductivity type layers and the distance (DA3, DA4, DB3, DB4, DC3, DC4) between the second conductivity type rings are 0.6 to 1.5 μm. The semiconductor device according to any one of claims 1 to 11.

13. The distance between the second conductivity type layers and the distance between the second conductivity type rings are equal to or greater than the width of the second conductivity type layer and the second conductivity type ring. The semiconductor device according to any one of claims 1 to 12.

14. The semiconductor device according to any one of claims 1 to 13, wherein the innermost one of the second conductivity type layer and the second conductivity type ring is connected.

15. A method for manufacturing a semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed in a chip (Ch), a guard ring portion (RG) surrounding the outer periphery of the cell region, and an outer peripheral region (RO) including a connecting portion (RJ) located between the guard ring portion and the cell region, On a substrate (1) composed of a semiconductor of the first or second conductivity type having a front surface and a back surface, a first conductivity type drift layer (2) made of a semiconductor of the first conductivity type having a lower impurity concentration than the substrate is formed. By ion-implanting a second conductivity type impurity into the drift layer, a second conductivity type layer (5, 5a) including a stripe-shaped portion having one direction as the longitudinal direction is formed in the cell region, and in the connecting portion, a lattice-shaped portion (33) having a structure in which stripes extending in the direction along the longitudinal direction of the second conductivity type layer provided in the cell region and in the direction intersecting the longitudinal direction are orthogonal to each other is formed. A second conductivity type layer formed in a line shape including the second conductivity type layer is formed, and further, a second conductivity type ring (21, 32) having a plurality of linear frame shapes surrounding the cell region and at least a part of which is located on the outer peripheral side and constitutes a guard ring (21) is formed in the guard ring portion or the guard ring portion and the connecting portion. In the cell region, a first electrode (9) electrically connected to the second conductivity type layer is formed. Forming a second electrode (11) on the back surface side of the substrate. A method for manufacturing a semiconductor device, wherein by forming the second conductivity type layer and the second conductivity type ring, the ratio occupied by the second conductivity type layer and the second conductivity type ring with respect to the total area of the chip is 40% or less.

16. A method for manufacturing a semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed in a chip (Ch), a guard ring portion (RG) surrounding the outer periphery of the cell region, and an outer peripheral region (RO) including a connecting portion (RJ) located between the guard ring portion and the cell region. On a substrate (1) composed of a semiconductor of the first or second conductivity type having a front surface and a back surface, a first conductivity type drift layer (2) made of a semiconductor of the first conductivity type having a lower impurity concentration than the substrate is formed. By ion-implanting second-conductivity-type impurities into the drift layer, a second-conductivity-type layer (5, 5a) including a stripe-shaped portion having one direction as the longitudinal direction is formed in the cell region, and in the connecting portion, stripes extending in two different directions intersect each other, and a line-shaped second-conductivity-type layer including a mesh-shaped portion (34) having a structure inclined with respect to the second-conductivity-type layer provided in the cell region is formed. Further, a second-conductivity-type ring (21, 32) having a plurality of line-shaped frame shapes surrounding the cell region and at least a part of the outer peripheral side constituting a guard ring (21) is formed in the guard ring portion or the guard ring portion and the connecting portion. In the cell region, a first electrode (9) electrically connected to the second-conductivity-type layer is formed. Forming a second electrode (11) on the back surface side of the substrate. A method of manufacturing a semiconductor device, wherein by forming the second-conductivity-type layer and the second-conductivity-type ring, the ratio occupied by the second-conductivity-type layer and the second-conductivity-type ring with respect to the total area of the chip is 40% or less.

17. Forming a base region (3) made of a second-conductivity-type semiconductor on the drift layer. Forming a source region (4) made of a first-conductivity-type semiconductor having a higher first-conductivity-type impurity concentration than the drift layer on the base region. In the cell region, after forming a gate trench (6) that penetrates the base region from the surface of the source region and reaches the drift layer, forming a gate insulating film (7) in the gate trench and forming a gate electrode (8) on the gate insulating film to form a trench gate structure having one direction as the longitudinal direction. In the outer peripheral region, forming a recess (20) that penetrates the source region and the base region and reaches the drift layer. Forming an interlayer insulating film (10) that covers the trench gate structure, the source region, and the base region and covers the inside of the recess. In the cell region, after forming a contact hole in the interlayer insulating film, forming a source electrode (9) electrically connected to the source region and the base region through the contact hole. The method of manufacturing a semiconductor device according to claim 15 or 16, including forming a drain electrode (11) on the back surface side of the substrate.

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